drivers/dma/dw_dmac.c

   1 /*
   2  * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
   3  * AVR32 systems.)
   4  *
   5  * Copyright (C) 2007-2008 Atmel Corporation
   6  * Copyright (C) 2010-2011 ST Microelectronics
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/mm.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/slab.h>
  23
  24 #include "dw_dmac_regs.h"
  25 #include "dmaengine.h"
  26
  27 /*
  28  * This supports the Synopsys "DesignWare AHB Central DMA Controller",
  29  * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all
  30  * of which use ARM any more).  See the "Databook" from Synopsys for
  31  * information beyond what licensees probably provide.
  32  *
  33  * The driver has currently been tested only with the Atmel AT32AP7000,
  34  * which does not support descriptor writeback.
  35  */
  36
  37 #define DWC_DEFAULT_CTLLO(private) ({                           \
  38                 struct dw_dma_slave *__slave = (private);       \
  39                 int dms = __slave ? __slave->dst_master : 0;    \
  40                 int sms = __slave ? __slave->src_master : 1;    \
  41                 u8 smsize = __slave ? __slave->src_msize : DW_DMA_MSIZE_16; \
  42                 u8 dmsize = __slave ? __slave->dst_msize : DW_DMA_MSIZE_16; \
  43                                                                 \
  44                 (DWC_CTLL_DST_MSIZE(dmsize)                     \
  45                  | DWC_CTLL_SRC_MSIZE(smsize)                   \
  46                  | DWC_CTLL_LLP_D_EN                            \
  47                  | DWC_CTLL_LLP_S_EN                            \
  48                  | DWC_CTLL_DMS(dms)                            \
  49                  | DWC_CTLL_SMS(sms));                          \
  50         })
  51
  52 /*
  53  * This is configuration-dependent and usually a funny size like 4095.
  54  *
  55  * Note that this is a transfer count, i.e. if we transfer 32-bit
  56  * words, we can do 16380 bytes per descriptor.
  57  *
  58  * This parameter is also system-specific.
  59  */
  60 #define DWC_MAX_COUNT   4095U
  61
  62 /*
  63  * Number of descriptors to allocate for each channel. This should be
  64  * made configurable somehow; preferably, the clients (at least the
  65  * ones using slave transfers) should be able to give us a hint.
  66  */
  67 #define NR_DESCS_PER_CHANNEL    64
  68
  69 /*----------------------------------------------------------------------*/
  70
  71 /*
  72  * Because we're not relying on writeback from the controller (it may not
  73  * even be configured into the core!) we don't need to use dma_pool.  These
  74  * descriptors -- and associated data -- are cacheable.  We do need to make
  75  * sure their dcache entries are written back before handing them off to
  76  * the controller, though.
  77  */
  78
  79 static struct device *chan2dev(struct dma_chan *chan)
  80 {
  81         return &chan->dev->device;
  82 }
  83 static struct device *chan2parent(struct dma_chan *chan)
  84 {
  85         return chan->dev->device.parent;
  86 }
  87
  88 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc)
  89 {
  90         return list_entry(dwc->active_list.next, struct dw_desc, desc_node);
  91 }
  92
  93 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
  94 {
  95         struct dw_desc *desc, *_desc;
  96         struct dw_desc *ret = NULL;
  97         unsigned int i = 0;
  98         unsigned long flags;
  99
 100         spin_lock_irqsave(&dwc->lock, flags);
 101         list_for_each_entry_safe(desc, _desc, &dwc->free_list, desc_node) {
 102                 if (async_tx_test_ack(&desc->txd)) {
 103                         list_del(&desc->desc_node);
 104                         ret = desc;
 105                         break;
 106                 }
 107                 dev_dbg(chan2dev(&dwc->chan), "desc %p not ACKed\n", desc);
 108                 i++;
 109         }
 110         spin_unlock_irqrestore(&dwc->lock, flags);
 111
 112         dev_vdbg(chan2dev(&dwc->chan), "scanned %u descriptors on freelist\n", i);
 113
 114         return ret;
 115 }
 116
 117 static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
 118 {
 119         struct dw_desc  *child;
 120
 121         list_for_each_entry(child, &desc->tx_list, desc_node)
 122                 dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 123                                 child->txd.phys, sizeof(child->lli),
 124                                 DMA_TO_DEVICE);
 125         dma_sync_single_for_cpu(chan2parent(&dwc->chan),
 126                         desc->txd.phys, sizeof(desc->lli),
 127                         DMA_TO_DEVICE);
 128 }
 129
 130 /*
 131  * Move a descriptor, including any children, to the free list.
 132  * `desc' must not be on any lists.
 133  */
 134 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
 135 {
 136         unsigned long flags;
 137
 138         if (desc) {
 139                 struct dw_desc *child;
 140
 141                 dwc_sync_desc_for_cpu(dwc, desc);
 142
 143                 spin_lock_irqsave(&dwc->lock, flags);
 144                 list_for_each_entry(child, &desc->tx_list, desc_node)
 145                         dev_vdbg(chan2dev(&dwc->chan),
 146                                         "moving child desc %p to freelist\n",
 147                                         child);
 148                 list_splice_init(&desc->tx_list, &dwc->free_list);
 149                 dev_vdbg(chan2dev(&dwc->chan), "moving desc %p to freelist\n", desc);
 150                 list_add(&desc->desc_node, &dwc->free_list);
 151                 spin_unlock_irqrestore(&dwc->lock, flags);
 152         }
 153 }
 154
 155 /* Called with dwc->lock held and bh disabled */
 156 static dma_cookie_t
 157 dwc_assign_cookie(struct dw_dma_chan *dwc, struct dw_desc *desc)
 158 {
 159         dma_cookie_t cookie = dwc->chan.cookie;
 160
 161         if (++cookie < 0)
 162                 cookie = 1;
 163
 164         dwc->chan.cookie = cookie;
 165         desc->txd.cookie = cookie;
 166
 167         return cookie;
 168 }
 169
 170 /*----------------------------------------------------------------------*/
 171
 172 /* Called with dwc->lock held and bh disabled */
 173 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first)
 174 {
 175         struct dw_dma   *dw = to_dw_dma(dwc->chan.device);
 176
 177         /* ASSERT:  channel is idle */
 178         if (dma_readl(dw, CH_EN) & dwc->mask) {
 179                 dev_err(chan2dev(&dwc->chan),
 180                         "BUG: Attempted to start non-idle channel\n");
 181                 dev_err(chan2dev(&dwc->chan),
 182                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 183                         channel_readl(dwc, SAR),
 184                         channel_readl(dwc, DAR),
 185                         channel_readl(dwc, LLP),
 186                         channel_readl(dwc, CTL_HI),
 187                         channel_readl(dwc, CTL_LO));
 188
 189                 /* The tasklet will hopefully advance the queue... */
 190                 return;
 191         }
 192
 193         channel_writel(dwc, LLP, first->txd.phys);
 194         channel_writel(dwc, CTL_LO,
 195                         DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
 196         channel_writel(dwc, CTL_HI, 0);
 197         channel_set_bit(dw, CH_EN, dwc->mask);
 198 }
 199
 200 /*----------------------------------------------------------------------*/
 201
 202 static void
 203 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
 204                 bool callback_required)
 205 {
 206         dma_async_tx_callback           callback = NULL;
 207         void                            *param = NULL;
 208         struct dma_async_tx_descriptor  *txd = &desc->txd;
 209         struct dw_desc                  *child;
 210         unsigned long                   flags;
 211
 212         dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie);
 213
 214         spin_lock_irqsave(&dwc->lock, flags);
 215         dwc->chan.completed_cookie = txd->cookie;
 216         if (callback_required) {
 217                 callback = txd->callback;
 218                 param = txd->callback_param;
 219         }
 220
 221         dwc_sync_desc_for_cpu(dwc, desc);
 222
 223         /* async_tx_ack */
 224         list_for_each_entry(child, &desc->tx_list, desc_node)
 225                 async_tx_ack(&child->txd);
 226         async_tx_ack(&desc->txd);
 227
 228         list_splice_init(&desc->tx_list, &dwc->free_list);
 229         list_move(&desc->desc_node, &dwc->free_list);
 230
 231         if (!dwc->chan.private) {
 232                 struct device *parent = chan2parent(&dwc->chan);
 233                 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
 234                         if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
 235                                 dma_unmap_single(parent, desc->lli.dar,
 236                                                 desc->len, DMA_FROM_DEVICE);
 237                         else
 238                                 dma_unmap_page(parent, desc->lli.dar,
 239                                                 desc->len, DMA_FROM_DEVICE);
 240                 }
 241                 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
 242                         if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
 243                                 dma_unmap_single(parent, desc->lli.sar,
 244                                                 desc->len, DMA_TO_DEVICE);
 245                         else
 246                                 dma_unmap_page(parent, desc->lli.sar,
 247                                                 desc->len, DMA_TO_DEVICE);
 248                 }
 249         }
 250
 251         spin_unlock_irqrestore(&dwc->lock, flags);
 252
 253         if (callback_required && callback)
 254                 callback(param);
 255 }
 256
 257 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc)
 258 {
 259         struct dw_desc *desc, *_desc;
 260         LIST_HEAD(list);
 261         unsigned long flags;
 262
 263         spin_lock_irqsave(&dwc->lock, flags);
 264         if (dma_readl(dw, CH_EN) & dwc->mask) {
 265                 dev_err(chan2dev(&dwc->chan),
 266                         "BUG: XFER bit set, but channel not idle!\n");
 267
 268                 /* Try to continue after resetting the channel... */
 269                 channel_clear_bit(dw, CH_EN, dwc->mask);
 270                 while (dma_readl(dw, CH_EN) & dwc->mask)
 271                         cpu_relax();
 272         }
 273
 274         /*
 275          * Submit queued descriptors ASAP, i.e. before we go through
 276          * the completed ones.
 277          */
 278         list_splice_init(&dwc->active_list, &list);
 279         if (!list_empty(&dwc->queue)) {
 280                 list_move(dwc->queue.next, &dwc->active_list);
 281                 dwc_dostart(dwc, dwc_first_active(dwc));
 282         }
 283
 284         spin_unlock_irqrestore(&dwc->lock, flags);
 285
 286         list_for_each_entry_safe(desc, _desc, &list, desc_node)
 287                 dwc_descriptor_complete(dwc, desc, true);
 288 }
 289
 290 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc)
 291 {
 292         dma_addr_t llp;
 293         struct dw_desc *desc, *_desc;
 294         struct dw_desc *child;
 295         u32 status_xfer;
 296         unsigned long flags;
 297
 298         spin_lock_irqsave(&dwc->lock, flags);
 299         /*
 300          * Clear block interrupt flag before scanning so that we don't
 301          * miss any, and read LLP before RAW_XFER to ensure it is
 302          * valid if we decide to scan the list.
 303          */
 304         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 305         llp = channel_readl(dwc, LLP);
 306         status_xfer = dma_readl(dw, RAW.XFER);
 307
 308         if (status_xfer & dwc->mask) {
 309                 /* Everything we've submitted is done */
 310                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 311                 spin_unlock_irqrestore(&dwc->lock, flags);
 312
 313                 dwc_complete_all(dw, dwc);
 314                 return;
 315         }
 316
 317         if (list_empty(&dwc->active_list)) {
 318                 spin_unlock_irqrestore(&dwc->lock, flags);
 319                 return;
 320         }
 321
 322         dev_vdbg(chan2dev(&dwc->chan), "scan_descriptors: llp=0x%x\n", llp);
 323
 324         list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) {
 325                 /* check first descriptors addr */
 326                 if (desc->txd.phys == llp) {
 327                         spin_unlock_irqrestore(&dwc->lock, flags);
 328                         return;
 329                 }
 330
 331                 /* check first descriptors llp */
 332                 if (desc->lli.llp == llp) {
 333                         /* This one is currently in progress */
 334                         spin_unlock_irqrestore(&dwc->lock, flags);
 335                         return;
 336                 }
 337
 338                 list_for_each_entry(child, &desc->tx_list, desc_node)
 339                         if (child->lli.llp == llp) {
 340                                 /* Currently in progress */
 341                                 spin_unlock_irqrestore(&dwc->lock, flags);
 342                                 return;
 343                         }
 344
 345                 /*
 346                  * No descriptors so far seem to be in progress, i.e.
 347                  * this one must be done.
 348                  */
 349                 spin_unlock_irqrestore(&dwc->lock, flags);
 350                 dwc_descriptor_complete(dwc, desc, true);
 351                 spin_lock_irqsave(&dwc->lock, flags);
 352         }
 353
 354         dev_err(chan2dev(&dwc->chan),
 355                 "BUG: All descriptors done, but channel not idle!\n");
 356
 357         /* Try to continue after resetting the channel... */
 358         channel_clear_bit(dw, CH_EN, dwc->mask);
 359         while (dma_readl(dw, CH_EN) & dwc->mask)
 360                 cpu_relax();
 361
 362         if (!list_empty(&dwc->queue)) {
 363                 list_move(dwc->queue.next, &dwc->active_list);
 364                 dwc_dostart(dwc, dwc_first_active(dwc));
 365         }
 366         spin_unlock_irqrestore(&dwc->lock, flags);
 367 }
 368
 369 static void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_lli *lli)
 370 {
 371         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 372                         "  desc: s0x%x d0x%x l0x%x c0x%x:%x\n",
 373                         lli->sar, lli->dar, lli->llp,
 374                         lli->ctlhi, lli->ctllo);
 375 }
 376
 377 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc)
 378 {
 379         struct dw_desc *bad_desc;
 380         struct dw_desc *child;
 381         unsigned long flags;
 382
 383         dwc_scan_descriptors(dw, dwc);
 384
 385         spin_lock_irqsave(&dwc->lock, flags);
 386
 387         /*
 388          * The descriptor currently at the head of the active list is
 389          * borked. Since we don't have any way to report errors, we'll
 390          * just have to scream loudly and try to carry on.
 391          */
 392         bad_desc = dwc_first_active(dwc);
 393         list_del_init(&bad_desc->desc_node);
 394         list_move(dwc->queue.next, dwc->active_list.prev);
 395
 396         /* Clear the error flag and try to restart the controller */
 397         dma_writel(dw, CLEAR.ERROR, dwc->mask);
 398         if (!list_empty(&dwc->active_list))
 399                 dwc_dostart(dwc, dwc_first_active(dwc));
 400
 401         /*
 402          * KERN_CRITICAL may seem harsh, but since this only happens
 403          * when someone submits a bad physical address in a
 404          * descriptor, we should consider ourselves lucky that the
 405          * controller flagged an error instead of scribbling over
 406          * random memory locations.
 407          */
 408         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 409                         "Bad descriptor submitted for DMA!\n");
 410         dev_printk(KERN_CRIT, chan2dev(&dwc->chan),
 411                         "  cookie: %d\n", bad_desc->txd.cookie);
 412         dwc_dump_lli(dwc, &bad_desc->lli);
 413         list_for_each_entry(child, &bad_desc->tx_list, desc_node)
 414                 dwc_dump_lli(dwc, &child->lli);
 415
 416         spin_unlock_irqrestore(&dwc->lock, flags);
 417
 418         /* Pretend the descriptor completed successfully */
 419         dwc_descriptor_complete(dwc, bad_desc, true);
 420 }
 421
 422 /* --------------------- Cyclic DMA API extensions -------------------- */
 423
 424 inline dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan)
 425 {
 426         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 427         return channel_readl(dwc, SAR);
 428 }
 429 EXPORT_SYMBOL(dw_dma_get_src_addr);
 430
 431 inline dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan)
 432 {
 433         struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 434         return channel_readl(dwc, DAR);
 435 }
 436 EXPORT_SYMBOL(dw_dma_get_dst_addr);
 437
 438 /* called with dwc->lock held and all DMAC interrupts disabled */
 439 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc,
 440                 u32 status_block, u32 status_err, u32 status_xfer)
 441 {
 442         unsigned long flags;
 443
 444         if (status_block & dwc->mask) {
 445                 void (*callback)(void *param);
 446                 void *callback_param;
 447
 448                 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n",
 449                                 channel_readl(dwc, LLP));
 450                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 451
 452                 callback = dwc->cdesc->period_callback;
 453                 callback_param = dwc->cdesc->period_callback_param;
 454
 455                 if (callback)
 456                         callback(callback_param);
 457         }
 458
 459         /*
 460          * Error and transfer complete are highly unlikely, and will most
 461          * likely be due to a configuration error by the user.
 462          */
 463         if (unlikely(status_err & dwc->mask) ||
 464                         unlikely(status_xfer & dwc->mask)) {
 465                 int i;
 466
 467                 dev_err(chan2dev(&dwc->chan), "cyclic DMA unexpected %s "
 468                                 "interrupt, stopping DMA transfer\n",
 469                                 status_xfer ? "xfer" : "error");
 470
 471                 spin_lock_irqsave(&dwc->lock, flags);
 472
 473                 dev_err(chan2dev(&dwc->chan),
 474                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
 475                         channel_readl(dwc, SAR),
 476                         channel_readl(dwc, DAR),
 477                         channel_readl(dwc, LLP),
 478                         channel_readl(dwc, CTL_HI),
 479                         channel_readl(dwc, CTL_LO));
 480
 481                 channel_clear_bit(dw, CH_EN, dwc->mask);
 482                 while (dma_readl(dw, CH_EN) & dwc->mask)
 483                         cpu_relax();
 484
 485                 /* make sure DMA does not restart by loading a new list */
 486                 channel_writel(dwc, LLP, 0);
 487                 channel_writel(dwc, CTL_LO, 0);
 488                 channel_writel(dwc, CTL_HI, 0);
 489
 490                 dma_writel(dw, CLEAR.BLOCK, dwc->mask);
 491                 dma_writel(dw, CLEAR.ERROR, dwc->mask);
 492                 dma_writel(dw, CLEAR.XFER, dwc->mask);
 493
 494                 for (i = 0; i < dwc->cdesc->periods; i++)
 495                         dwc_dump_lli(dwc, &dwc->cdesc->desc[i]->lli);
 496
 497                 spin_unlock_irqrestore(&dwc->lock, flags);
 498         }
 499 }
 500
 501 /* ------------------------------------------------------------------------- */
 502
 503 static void dw_dma_tasklet(unsigned long data)
 504 {
 505         struct dw_dma *dw = (struct dw_dma *)data;
 506         struct dw_dma_chan *dwc;
 507         u32 status_block;
 508         u32 status_xfer;
 509         u32 status_err;
 510         int i;
 511
 512         status_block = dma_readl(dw, RAW.BLOCK);
 513         status_xfer = dma_readl(dw, RAW.XFER);
 514         status_err = dma_readl(dw, RAW.ERROR);
 515
 516         dev_vdbg(dw->dma.dev, "tasklet: status_block=%x status_err=%x\n",
 517                         status_block, status_err);
 518
 519         for (i = 0; i < dw->dma.chancnt; i++) {
 520                 dwc = &dw->chan[i];
 521                 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags))
 522                         dwc_handle_cyclic(dw, dwc, status_block, status_err,
 523                                         status_xfer);
 524                 else if (status_err & (1 << i))
 525                         dwc_handle_error(dw, dwc);
 526                 else if ((status_block | status_xfer) & (1 << i))
 527                         dwc_scan_descriptors(dw, dwc);
 528         }
 529
 530         /*
 531          * Re-enable interrupts. Block Complete interrupts are only
 532          * enabled if the INT_EN bit in the descriptor is set. This
 533          * will trigger a scan before the whole list is done.
 534          */
 535         channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
 536         channel_set_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 537         channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask);
 538 }
 539
 540 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id)
 541 {
 542         struct dw_dma *dw = dev_id;
 543         u32 status;
 544
 545         dev_vdbg(dw->dma.dev, "interrupt: status=0x%x\n",
 546                         dma_readl(dw, STATUS_INT));
 547
 548         /*
 549          * Just disable the interrupts. We'll turn them back on in the
 550          * softirq handler.
 551          */
 552         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
 553         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
 554         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
 555
 556         status = dma_readl(dw, STATUS_INT);
 557         if (status) {
 558                 dev_err(dw->dma.dev,
 559                         "BUG: Unexpected interrupts pending: 0x%x\n",
 560                         status);
 561
 562                 /* Try to recover */
 563                 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
 564                 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1);
 565                 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1);
 566                 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1);
 567                 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1);
 568         }
 569
 570         tasklet_schedule(&dw->tasklet);
 571
 572         return IRQ_HANDLED;
 573 }
 574
 575 /*----------------------------------------------------------------------*/
 576
 577 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx)
 578 {
 579         struct dw_desc          *desc = txd_to_dw_desc(tx);
 580         struct dw_dma_chan      *dwc = to_dw_dma_chan(tx->chan);
 581         dma_cookie_t            cookie;
 582         unsigned long           flags;
 583
 584         spin_lock_irqsave(&dwc->lock, flags);
 585         cookie = dwc_assign_cookie(dwc, desc);
 586
 587         /*
 588          * REVISIT: We should attempt to chain as many descriptors as
 589          * possible, perhaps even appending to those already submitted
 590          * for DMA. But this is hard to do in a race-free manner.
 591          */
 592         if (list_empty(&dwc->active_list)) {
 593                 dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n",
 594                                 desc->txd.cookie);
 595                 list_add_tail(&desc->desc_node, &dwc->active_list);
 596                 dwc_dostart(dwc, dwc_first_active(dwc));
 597         } else {
 598                 dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n",
 599                                 desc->txd.cookie);
 600
 601                 list_add_tail(&desc->desc_node, &dwc->queue);
 602         }
 603
 604         spin_unlock_irqrestore(&dwc->lock, flags);
 605
 606         return cookie;
 607 }
 608
 609 static struct dma_async_tx_descriptor *
 610 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
 611                 size_t len, unsigned long flags)
 612 {
 613         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 614         struct dw_desc          *desc;
 615         struct dw_desc          *first;
 616         struct dw_desc          *prev;
 617         size_t                  xfer_count;
 618         size_t                  offset;
 619         unsigned int            src_width;
 620         unsigned int            dst_width;
 621         u32                     ctllo;
 622
 623         dev_vdbg(chan2dev(chan), "prep_dma_memcpy d0x%x s0x%x l0x%zx f0x%lx\n",
 624                         dest, src, len, flags);
 625
 626         if (unlikely(!len)) {
 627                 dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n");
 628                 return NULL;
 629         }
 630
 631         /*
 632          * We can be a lot more clever here, but this should take care
 633          * of the most common optimization.
 634          */
 635         if (!((src | dest  | len) & 7))
 636                 src_width = dst_width = 3;
 637         else if (!((src | dest  | len) & 3))
 638                 src_width = dst_width = 2;
 639         else if (!((src | dest | len) & 1))
 640                 src_width = dst_width = 1;
 641         else
 642                 src_width = dst_width = 0;
 643
 644         ctllo = DWC_DEFAULT_CTLLO(chan->private)
 645                         | DWC_CTLL_DST_WIDTH(dst_width)
 646                         | DWC_CTLL_SRC_WIDTH(src_width)
 647                         | DWC_CTLL_DST_INC
 648                         | DWC_CTLL_SRC_INC
 649                         | DWC_CTLL_FC_M2M;
 650         prev = first = NULL;
 651
 652         for (offset = 0; offset < len; offset += xfer_count << src_width) {
 653                 xfer_count = min_t(size_t, (len - offset) >> src_width,
 654                                 DWC_MAX_COUNT);
 655
 656                 desc = dwc_desc_get(dwc);
 657                 if (!desc)
 658                         goto err_desc_get;
 659
 660                 desc->lli.sar = src + offset;
 661                 desc->lli.dar = dest + offset;
 662                 desc->lli.ctllo = ctllo;
 663                 desc->lli.ctlhi = xfer_count;
 664
 665                 if (!first) {
 666                         first = desc;
 667                 } else {
 668                         prev->lli.llp = desc->txd.phys;
 669                         dma_sync_single_for_device(chan2parent(chan),
 670                                         prev->txd.phys, sizeof(prev->lli),
 671                                         DMA_TO_DEVICE);
 672                         list_add_tail(&desc->desc_node,
 673                                         &first->tx_list);
 674                 }
 675                 prev = desc;
 676         }
 677
 678
 679         if (flags & DMA_PREP_INTERRUPT)
 680                 /* Trigger interrupt after last block */
 681                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 682
 683         prev->lli.llp = 0;
 684         dma_sync_single_for_device(chan2parent(chan),
 685                         prev->txd.phys, sizeof(prev->lli),
 686                         DMA_TO_DEVICE);
 687
 688         first->txd.flags = flags;
 689         first->len = len;
 690
 691         return &first->txd;
 692
 693 err_desc_get:
 694         dwc_desc_put(dwc, first);
 695         return NULL;
 696 }
 697
 698 static struct dma_async_tx_descriptor *
 699 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 700                 unsigned int sg_len, enum dma_data_direction direction,
 701                 unsigned long flags)
 702 {
 703         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 704         struct dw_dma_slave     *dws = chan->private;
 705         struct dw_desc          *prev;
 706         struct dw_desc          *first;
 707         u32                     ctllo;
 708         dma_addr_t              reg;
 709         unsigned int            reg_width;
 710         unsigned int            mem_width;
 711         unsigned int            i;
 712         struct scatterlist      *sg;
 713         size_t                  total_len = 0;
 714
 715         dev_vdbg(chan2dev(chan), "prep_dma_slave\n");
 716
 717         if (unlikely(!dws || !sg_len))
 718                 return NULL;
 719
 720         reg_width = dws->reg_width;
 721         prev = first = NULL;
 722
 723         switch (direction) {
 724         case DMA_TO_DEVICE:
 725                 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
 726                                 | DWC_CTLL_DST_WIDTH(reg_width)
 727                                 | DWC_CTLL_DST_FIX
 728                                 | DWC_CTLL_SRC_INC
 729                                 | DWC_CTLL_FC(dws->fc));
 730                 reg = dws->tx_reg;
 731                 for_each_sg(sgl, sg, sg_len, i) {
 732                         struct dw_desc  *desc;
 733                         u32             len, dlen, mem;
 734
 735                         mem = sg_phys(sg);
 736                         len = sg_dma_len(sg);
 737                         mem_width = 2;
 738                         if (unlikely(mem & 3 || len & 3))
 739                                 mem_width = 0;
 740
 741 slave_sg_todev_fill_desc:
 742                         desc = dwc_desc_get(dwc);
 743                         if (!desc) {
 744                                 dev_err(chan2dev(chan),
 745                                         "not enough descriptors available\n");
 746                                 goto err_desc_get;
 747                         }
 748
 749                         desc->lli.sar = mem;
 750                         desc->lli.dar = reg;
 751                         desc->lli.ctllo = ctllo | DWC_CTLL_SRC_WIDTH(mem_width);
 752                         if ((len >> mem_width) > DWC_MAX_COUNT) {
 753                                 dlen = DWC_MAX_COUNT << mem_width;
 754                                 mem += dlen;
 755                                 len -= dlen;
 756                         } else {
 757                                 dlen = len;
 758                                 len = 0;
 759                         }
 760
 761                         desc->lli.ctlhi = dlen >> mem_width;
 762
 763                         if (!first) {
 764                                 first = desc;
 765                         } else {
 766                                 prev->lli.llp = desc->txd.phys;
 767                                 dma_sync_single_for_device(chan2parent(chan),
 768                                                 prev->txd.phys,
 769                                                 sizeof(prev->lli),
 770                                                 DMA_TO_DEVICE);
 771                                 list_add_tail(&desc->desc_node,
 772                                                 &first->tx_list);
 773                         }
 774                         prev = desc;
 775                         total_len += dlen;
 776
 777                         if (len)
 778                                 goto slave_sg_todev_fill_desc;
 779                 }
 780                 break;
 781         case DMA_FROM_DEVICE:
 782                 ctllo = (DWC_DEFAULT_CTLLO(chan->private)
 783                                 | DWC_CTLL_SRC_WIDTH(reg_width)
 784                                 | DWC_CTLL_DST_INC
 785                                 | DWC_CTLL_SRC_FIX
 786                                 | DWC_CTLL_FC(dws->fc));
 787
 788                 reg = dws->rx_reg;
 789                 for_each_sg(sgl, sg, sg_len, i) {
 790                         struct dw_desc  *desc;
 791                         u32             len, dlen, mem;
 792
 793                         mem = sg_phys(sg);
 794                         len = sg_dma_len(sg);
 795                         mem_width = 2;
 796                         if (unlikely(mem & 3 || len & 3))
 797                                 mem_width = 0;
 798
 799 slave_sg_fromdev_fill_desc:
 800                         desc = dwc_desc_get(dwc);
 801                         if (!desc) {
 802                                 dev_err(chan2dev(chan),
 803                                                 "not enough descriptors available\n");
 804                                 goto err_desc_get;
 805                         }
 806
 807                         desc->lli.sar = reg;
 808                         desc->lli.dar = mem;
 809                         desc->lli.ctllo = ctllo | DWC_CTLL_DST_WIDTH(mem_width);
 810                         if ((len >> reg_width) > DWC_MAX_COUNT) {
 811                                 dlen = DWC_MAX_COUNT << reg_width;
 812                                 mem += dlen;
 813                                 len -= dlen;
 814                         } else {
 815                                 dlen = len;
 816                                 len = 0;
 817                         }
 818                         desc->lli.ctlhi = dlen >> reg_width;
 819
 820                         if (!first) {
 821                                 first = desc;
 822                         } else {
 823                                 prev->lli.llp = desc->txd.phys;
 824                                 dma_sync_single_for_device(chan2parent(chan),
 825                                                 prev->txd.phys,
 826                                                 sizeof(prev->lli),
 827                                                 DMA_TO_DEVICE);
 828                                 list_add_tail(&desc->desc_node,
 829                                                 &first->tx_list);
 830                         }
 831                         prev = desc;
 832                         total_len += dlen;
 833
 834                         if (len)
 835                                 goto slave_sg_fromdev_fill_desc;
 836                 }
 837                 break;
 838         default:
 839                 return NULL;
 840         }
 841
 842         if (flags & DMA_PREP_INTERRUPT)
 843                 /* Trigger interrupt after last block */
 844                 prev->lli.ctllo |= DWC_CTLL_INT_EN;
 845
 846         prev->lli.llp = 0;
 847         dma_sync_single_for_device(chan2parent(chan),
 848                         prev->txd.phys, sizeof(prev->lli),
 849                         DMA_TO_DEVICE);
 850
 851         first->len = total_len;
 852
 853         return &first->txd;
 854
 855 err_desc_get:
 856         dwc_desc_put(dwc, first);
 857         return NULL;
 858 }
 859
 860 static int dwc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 861                        unsigned long arg)
 862 {
 863         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 864         struct dw_dma           *dw = to_dw_dma(chan->device);
 865         struct dw_desc          *desc, *_desc;
 866         unsigned long           flags;
 867         u32                     cfglo;
 868         LIST_HEAD(list);
 869
 870         if (cmd == DMA_PAUSE) {
 871                 spin_lock_irqsave(&dwc->lock, flags);
 872
 873                 cfglo = channel_readl(dwc, CFG_LO);
 874                 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
 875                 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY))
 876                         cpu_relax();
 877
 878                 dwc->paused = true;
 879                 spin_unlock_irqrestore(&dwc->lock, flags);
 880         } else if (cmd == DMA_RESUME) {
 881                 if (!dwc->paused)
 882                         return 0;
 883
 884                 spin_lock_irqsave(&dwc->lock, flags);
 885
 886                 cfglo = channel_readl(dwc, CFG_LO);
 887                 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
 888                 dwc->paused = false;
 889
 890                 spin_unlock_irqrestore(&dwc->lock, flags);
 891         } else if (cmd == DMA_TERMINATE_ALL) {
 892                 spin_lock_irqsave(&dwc->lock, flags);
 893
 894                 channel_clear_bit(dw, CH_EN, dwc->mask);
 895                 while (dma_readl(dw, CH_EN) & dwc->mask)
 896                         cpu_relax();
 897
 898                 dwc->paused = false;
 899
 900                 /* active_list entries will end up before queued entries */
 901                 list_splice_init(&dwc->queue, &list);
 902                 list_splice_init(&dwc->active_list, &list);
 903
 904                 spin_unlock_irqrestore(&dwc->lock, flags);
 905
 906                 /* Flush all pending and queued descriptors */
 907                 list_for_each_entry_safe(desc, _desc, &list, desc_node)
 908                         dwc_descriptor_complete(dwc, desc, false);
 909         } else
 910                 return -ENXIO;
 911
 912         return 0;
 913 }
 914
 915 static enum dma_status
 916 dwc_tx_status(struct dma_chan *chan,
 917               dma_cookie_t cookie,
 918               struct dma_tx_state *txstate)
 919 {
 920         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 921         dma_cookie_t            last_used;
 922         dma_cookie_t            last_complete;
 923         int                     ret;
 924
 925         last_complete = chan->completed_cookie;
 926         last_used = chan->cookie;
 927
 928         ret = dma_async_is_complete(cookie, last_complete, last_used);
 929         if (ret != DMA_SUCCESS) {
 930                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 931
 932                 last_complete = chan->completed_cookie;
 933                 last_used = chan->cookie;
 934
 935                 ret = dma_async_is_complete(cookie, last_complete, last_used);
 936         }
 937
 938         if (ret != DMA_SUCCESS)
 939                 dma_set_tx_state(txstate, last_complete, last_used,
 940                                 dwc_first_active(dwc)->len);
 941         else
 942                 dma_set_tx_state(txstate, last_complete, last_used, 0);
 943
 944         if (dwc->paused)
 945                 return DMA_PAUSED;
 946
 947         return ret;
 948 }
 949
 950 static void dwc_issue_pending(struct dma_chan *chan)
 951 {
 952         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 953
 954         if (!list_empty(&dwc->queue))
 955                 dwc_scan_descriptors(to_dw_dma(chan->device), dwc);
 956 }
 957
 958 static int dwc_alloc_chan_resources(struct dma_chan *chan)
 959 {
 960         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
 961         struct dw_dma           *dw = to_dw_dma(chan->device);
 962         struct dw_desc          *desc;
 963         struct dw_dma_slave     *dws;
 964         int                     i;
 965         u32                     cfghi;
 966         u32                     cfglo;
 967         unsigned long           flags;
 968
 969         dev_vdbg(chan2dev(chan), "alloc_chan_resources\n");
 970
 971         /* ASSERT:  channel is idle */
 972         if (dma_readl(dw, CH_EN) & dwc->mask) {
 973                 dev_dbg(chan2dev(chan), "DMA channel not idle?\n");
 974                 return -EIO;
 975         }
 976
 977         chan->completed_cookie = chan->cookie = 1;
 978
 979         cfghi = DWC_CFGH_FIFO_MODE;
 980         cfglo = 0;
 981
 982         dws = chan->private;
 983         if (dws) {
 984                 /*
 985                  * We need controller-specific data to set up slave
 986                  * transfers.
 987                  */
 988                 BUG_ON(!dws->dma_dev || dws->dma_dev != dw->dma.dev);
 989
 990                 cfghi = dws->cfg_hi;
 991                 cfglo = dws->cfg_lo & ~DWC_CFGL_CH_PRIOR_MASK;
 992         }
 993
 994         cfglo |= DWC_CFGL_CH_PRIOR(dwc->priority);
 995
 996         channel_writel(dwc, CFG_LO, cfglo);
 997         channel_writel(dwc, CFG_HI, cfghi);
 998
 999         /*
1000          * NOTE: some controllers may have additional features that we
1001          * need to initialize here, like "scatter-gather" (which
1002          * doesn't mean what you think it means), and status writeback.
1003          */
1004
1005         spin_lock_irqsave(&dwc->lock, flags);
1006         i = dwc->descs_allocated;
1007         while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
1008                 spin_unlock_irqrestore(&dwc->lock, flags);
1009
1010                 desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
1011                 if (!desc) {
1012                         dev_info(chan2dev(chan),
1013                                 "only allocated %d descriptors\n", i);
1014                         spin_lock_irqsave(&dwc->lock, flags);
1015                         break;
1016                 }
1017
1018                 INIT_LIST_HEAD(&desc->tx_list);
1019                 dma_async_tx_descriptor_init(&desc->txd, chan);
1020                 desc->txd.tx_submit = dwc_tx_submit;
1021                 desc->txd.flags = DMA_CTRL_ACK;
1022                 desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
1023                                 sizeof(desc->lli), DMA_TO_DEVICE);
1024                 dwc_desc_put(dwc, desc);
1025
1026                 spin_lock_irqsave(&dwc->lock, flags);
1027                 i = ++dwc->descs_allocated;
1028         }
1029
1030         /* Enable interrupts */
1031         channel_set_bit(dw, MASK.XFER, dwc->mask);
1032         channel_set_bit(dw, MASK.BLOCK, dwc->mask);
1033         channel_set_bit(dw, MASK.ERROR, dwc->mask);
1034
1035         spin_unlock_irqrestore(&dwc->lock, flags);
1036
1037         dev_dbg(chan2dev(chan),
1038                 "alloc_chan_resources allocated %d descriptors\n", i);
1039
1040         return i;
1041 }
1042
1043 static void dwc_free_chan_resources(struct dma_chan *chan)
1044 {
1045         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1046         struct dw_dma           *dw = to_dw_dma(chan->device);
1047         struct dw_desc          *desc, *_desc;
1048         unsigned long           flags;
1049         LIST_HEAD(list);
1050
1051         dev_dbg(chan2dev(chan), "free_chan_resources (descs allocated=%u)\n",
1052                         dwc->descs_allocated);
1053
1054         /* ASSERT:  channel is idle */
1055         BUG_ON(!list_empty(&dwc->active_list));
1056         BUG_ON(!list_empty(&dwc->queue));
1057         BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask);
1058
1059         spin_lock_irqsave(&dwc->lock, flags);
1060         list_splice_init(&dwc->free_list, &list);
1061         dwc->descs_allocated = 0;
1062
1063         /* Disable interrupts */
1064         channel_clear_bit(dw, MASK.XFER, dwc->mask);
1065         channel_clear_bit(dw, MASK.BLOCK, dwc->mask);
1066         channel_clear_bit(dw, MASK.ERROR, dwc->mask);
1067
1068         spin_unlock_irqrestore(&dwc->lock, flags);
1069
1070         list_for_each_entry_safe(desc, _desc, &list, desc_node) {
1071                 dev_vdbg(chan2dev(chan), "  freeing descriptor %p\n", desc);
1072                 dma_unmap_single(chan2parent(chan), desc->txd.phys,
1073                                 sizeof(desc->lli), DMA_TO_DEVICE);
1074                 kfree(desc);
1075         }
1076
1077         dev_vdbg(chan2dev(chan), "free_chan_resources done\n");
1078 }
1079
1080 /* --------------------- Cyclic DMA API extensions -------------------- */
1081
1082 /**
1083  * dw_dma_cyclic_start - start the cyclic DMA transfer
1084  * @chan: the DMA channel to start
1085  *
1086  * Must be called with soft interrupts disabled. Returns zero on success or
1087  * -errno on failure.
1088  */
1089 int dw_dma_cyclic_start(struct dma_chan *chan)
1090 {
1091         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1092         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1093         unsigned long           flags;
1094
1095         if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) {
1096                 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n");
1097                 return -ENODEV;
1098         }
1099
1100         spin_lock_irqsave(&dwc->lock, flags);
1101
1102         /* assert channel is idle */
1103         if (dma_readl(dw, CH_EN) & dwc->mask) {
1104                 dev_err(chan2dev(&dwc->chan),
1105                         "BUG: Attempted to start non-idle channel\n");
1106                 dev_err(chan2dev(&dwc->chan),
1107                         "  SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n",
1108                         channel_readl(dwc, SAR),
1109                         channel_readl(dwc, DAR),
1110                         channel_readl(dwc, LLP),
1111                         channel_readl(dwc, CTL_HI),
1112                         channel_readl(dwc, CTL_LO));
1113                 spin_unlock_irqrestore(&dwc->lock, flags);
1114                 return -EBUSY;
1115         }
1116
1117         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1118         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1119         dma_writel(dw, CLEAR.XFER, dwc->mask);
1120
1121         /* setup DMAC channel registers */
1122         channel_writel(dwc, LLP, dwc->cdesc->desc[0]->txd.phys);
1123         channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN);
1124         channel_writel(dwc, CTL_HI, 0);
1125
1126         channel_set_bit(dw, CH_EN, dwc->mask);
1127
1128         spin_unlock_irqrestore(&dwc->lock, flags);
1129
1130         return 0;
1131 }
1132 EXPORT_SYMBOL(dw_dma_cyclic_start);
1133
1134 /**
1135  * dw_dma_cyclic_stop - stop the cyclic DMA transfer
1136  * @chan: the DMA channel to stop
1137  *
1138  * Must be called with soft interrupts disabled.
1139  */
1140 void dw_dma_cyclic_stop(struct dma_chan *chan)
1141 {
1142         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1143         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1144         unsigned long           flags;
1145
1146         spin_lock_irqsave(&dwc->lock, flags);
1147
1148         channel_clear_bit(dw, CH_EN, dwc->mask);
1149         while (dma_readl(dw, CH_EN) & dwc->mask)
1150                 cpu_relax();
1151
1152         spin_unlock_irqrestore(&dwc->lock, flags);
1153 }
1154 EXPORT_SYMBOL(dw_dma_cyclic_stop);
1155
1156 /**
1157  * dw_dma_cyclic_prep - prepare the cyclic DMA transfer
1158  * @chan: the DMA channel to prepare
1159  * @buf_addr: physical DMA address where the buffer starts
1160  * @buf_len: total number of bytes for the entire buffer
1161  * @period_len: number of bytes for each period
1162  * @direction: transfer direction, to or from device
1163  *
1164  * Must be called before trying to start the transfer. Returns a valid struct
1165  * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful.
1166  */
1167 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
1168                 dma_addr_t buf_addr, size_t buf_len, size_t period_len,
1169                 enum dma_data_direction direction)
1170 {
1171         struct dw_dma_chan              *dwc = to_dw_dma_chan(chan);
1172         struct dw_cyclic_desc           *cdesc;
1173         struct dw_cyclic_desc           *retval = NULL;
1174         struct dw_desc                  *desc;
1175         struct dw_desc                  *last = NULL;
1176         struct dw_dma_slave             *dws = chan->private;
1177         unsigned long                   was_cyclic;
1178         unsigned int                    reg_width;
1179         unsigned int                    periods;
1180         unsigned int                    i;
1181         unsigned long                   flags;
1182
1183         spin_lock_irqsave(&dwc->lock, flags);
1184         if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) {
1185                 spin_unlock_irqrestore(&dwc->lock, flags);
1186                 dev_dbg(chan2dev(&dwc->chan),
1187                                 "queue and/or active list are not empty\n");
1188                 return ERR_PTR(-EBUSY);
1189         }
1190
1191         was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1192         spin_unlock_irqrestore(&dwc->lock, flags);
1193         if (was_cyclic) {
1194                 dev_dbg(chan2dev(&dwc->chan),
1195                                 "channel already prepared for cyclic DMA\n");
1196                 return ERR_PTR(-EBUSY);
1197         }
1198
1199         retval = ERR_PTR(-EINVAL);
1200         reg_width = dws->reg_width;
1201         periods = buf_len / period_len;
1202
1203         /* Check for too big/unaligned periods and unaligned DMA buffer. */
1204         if (period_len > (DWC_MAX_COUNT << reg_width))
1205                 goto out_err;
1206         if (unlikely(period_len & ((1 << reg_width) - 1)))
1207                 goto out_err;
1208         if (unlikely(buf_addr & ((1 << reg_width) - 1)))
1209                 goto out_err;
1210         if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE))))
1211                 goto out_err;
1212
1213         retval = ERR_PTR(-ENOMEM);
1214
1215         if (periods > NR_DESCS_PER_CHANNEL)
1216                 goto out_err;
1217
1218         cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL);
1219         if (!cdesc)
1220                 goto out_err;
1221
1222         cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL);
1223         if (!cdesc->desc)
1224                 goto out_err_alloc;
1225
1226         for (i = 0; i < periods; i++) {
1227                 desc = dwc_desc_get(dwc);
1228                 if (!desc)
1229                         goto out_err_desc_get;
1230
1231                 switch (direction) {
1232                 case DMA_TO_DEVICE:
1233                         desc->lli.dar = dws->tx_reg;
1234                         desc->lli.sar = buf_addr + (period_len * i);
1235                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
1236                                         | DWC_CTLL_DST_WIDTH(reg_width)
1237                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1238                                         | DWC_CTLL_DST_FIX
1239                                         | DWC_CTLL_SRC_INC
1240                                         | DWC_CTLL_FC(dws->fc)
1241                                         | DWC_CTLL_INT_EN);
1242                         break;
1243                 case DMA_FROM_DEVICE:
1244                         desc->lli.dar = buf_addr + (period_len * i);
1245                         desc->lli.sar = dws->rx_reg;
1246                         desc->lli.ctllo = (DWC_DEFAULT_CTLLO(chan->private)
1247                                         | DWC_CTLL_SRC_WIDTH(reg_width)
1248                                         | DWC_CTLL_DST_WIDTH(reg_width)
1249                                         | DWC_CTLL_DST_INC
1250                                         | DWC_CTLL_SRC_FIX
1251                                         | DWC_CTLL_FC(dws->fc)
1252                                         | DWC_CTLL_INT_EN);
1253                         break;
1254                 default:
1255                         break;
1256                 }
1257
1258                 desc->lli.ctlhi = (period_len >> reg_width);
1259                 cdesc->desc[i] = desc;
1260
1261                 if (last) {
1262                         last->lli.llp = desc->txd.phys;
1263                         dma_sync_single_for_device(chan2parent(chan),
1264                                         last->txd.phys, sizeof(last->lli),
1265                                         DMA_TO_DEVICE);
1266                 }
1267
1268                 last = desc;
1269         }
1270
1271         /* lets make a cyclic list */
1272         last->lli.llp = cdesc->desc[0]->txd.phys;
1273         dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
1274                         sizeof(last->lli), DMA_TO_DEVICE);
1275
1276         dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%08x len %zu "
1277                         "period %zu periods %d\n", buf_addr, buf_len,
1278                         period_len, periods);
1279
1280         cdesc->periods = periods;
1281         dwc->cdesc = cdesc;
1282
1283         return cdesc;
1284
1285 out_err_desc_get:
1286         while (i--)
1287                 dwc_desc_put(dwc, cdesc->desc[i]);
1288 out_err_alloc:
1289         kfree(cdesc);
1290 out_err:
1291         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1292         return (struct dw_cyclic_desc *)retval;
1293 }
1294 EXPORT_SYMBOL(dw_dma_cyclic_prep);
1295
1296 /**
1297  * dw_dma_cyclic_free - free a prepared cyclic DMA transfer
1298  * @chan: the DMA channel to free
1299  */
1300 void dw_dma_cyclic_free(struct dma_chan *chan)
1301 {
1302         struct dw_dma_chan      *dwc = to_dw_dma_chan(chan);
1303         struct dw_dma           *dw = to_dw_dma(dwc->chan.device);
1304         struct dw_cyclic_desc   *cdesc = dwc->cdesc;
1305         int                     i;
1306         unsigned long           flags;
1307
1308         dev_dbg(chan2dev(&dwc->chan), "cyclic free\n");
1309
1310         if (!cdesc)
1311                 return;
1312
1313         spin_lock_irqsave(&dwc->lock, flags);
1314
1315         channel_clear_bit(dw, CH_EN, dwc->mask);
1316         while (dma_readl(dw, CH_EN) & dwc->mask)
1317                 cpu_relax();
1318
1319         dma_writel(dw, CLEAR.BLOCK, dwc->mask);
1320         dma_writel(dw, CLEAR.ERROR, dwc->mask);
1321         dma_writel(dw, CLEAR.XFER, dwc->mask);
1322
1323         spin_unlock_irqrestore(&dwc->lock, flags);
1324
1325         for (i = 0; i < cdesc->periods; i++)
1326                 dwc_desc_put(dwc, cdesc->desc[i]);
1327
1328         kfree(cdesc->desc);
1329         kfree(cdesc);
1330
1331         clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags);
1332 }
1333 EXPORT_SYMBOL(dw_dma_cyclic_free);
1334
1335 /*----------------------------------------------------------------------*/
1336
1337 static void dw_dma_off(struct dw_dma *dw)
1338 {
1339         dma_writel(dw, CFG, 0);
1340
1341         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1342         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1343         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1344         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1345         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1346
1347         while (dma_readl(dw, CFG) & DW_CFG_DMA_EN)
1348                 cpu_relax();
1349 }
1350
1351 static int __init dw_probe(struct platform_device *pdev)
1352 {
1353         struct dw_dma_platform_data *pdata;
1354         struct resource         *io;
1355         struct dw_dma           *dw;
1356         size_t                  size;
1357         int                     irq;
1358         int                     err;
1359         int                     i;
1360
1361         pdata = pdev->dev.platform_data;
1362         if (!pdata || pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS)
1363                 return -EINVAL;
1364
1365         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1366         if (!io)
1367                 return -EINVAL;
1368
1369         irq = platform_get_irq(pdev, 0);
1370         if (irq < 0)
1371                 return irq;
1372
1373         size = sizeof(struct dw_dma);
1374         size += pdata->nr_channels * sizeof(struct dw_dma_chan);
1375         dw = kzalloc(size, GFP_KERNEL);
1376         if (!dw)
1377                 return -ENOMEM;
1378
1379         if (!request_mem_region(io->start, DW_REGLEN, pdev->dev.driver->name)) {
1380                 err = -EBUSY;
1381                 goto err_kfree;
1382         }
1383
1384         dw->regs = ioremap(io->start, DW_REGLEN);
1385         if (!dw->regs) {
1386                 err = -ENOMEM;
1387                 goto err_release_r;
1388         }
1389
1390         dw->clk = clk_get(&pdev->dev, "hclk");
1391         if (IS_ERR(dw->clk)) {
1392                 err = PTR_ERR(dw->clk);
1393                 goto err_clk;
1394         }
1395         clk_enable(dw->clk);
1396
1397         /* force dma off, just in case */
1398         dw_dma_off(dw);
1399
1400         err = request_irq(irq, dw_dma_interrupt, 0, "dw_dmac", dw);
1401         if (err)
1402                 goto err_irq;
1403
1404         platform_set_drvdata(pdev, dw);
1405
1406         tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
1407
1408         dw->all_chan_mask = (1 << pdata->nr_channels) - 1;
1409
1410         INIT_LIST_HEAD(&dw->dma.channels);
1411         for (i = 0; i < pdata->nr_channels; i++, dw->dma.chancnt++) {
1412                 struct dw_dma_chan      *dwc = &dw->chan[i];
1413
1414                 dwc->chan.device = &dw->dma;
1415                 dwc->chan.chan_id = i;
1416                 dwc->chan.cookie = dwc->chan.completed_cookie = 1;
1417                 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING)
1418                         list_add_tail(&dwc->chan.device_node,
1419                                         &dw->dma.channels);
1420                 else
1421                         list_add(&dwc->chan.device_node, &dw->dma.channels);
1422
1423                 /* 7 is highest priority & 0 is lowest. */
1424                 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING)
1425                         dwc->priority = 7 - i;
1426                 else
1427                         dwc->priority = i;
1428
1429                 dwc->ch_regs = &__dw_regs(dw)->CHAN[i];
1430                 spin_lock_init(&dwc->lock);
1431                 dwc->mask = 1 << i;
1432
1433                 INIT_LIST_HEAD(&dwc->active_list);
1434                 INIT_LIST_HEAD(&dwc->queue);
1435                 INIT_LIST_HEAD(&dwc->free_list);
1436
1437                 channel_clear_bit(dw, CH_EN, dwc->mask);
1438         }
1439
1440         /* Clear/disable all interrupts on all channels. */
1441         dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
1442         dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask);
1443         dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask);
1444         dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask);
1445         dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask);
1446
1447         channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
1448         channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask);
1449         channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask);
1450         channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask);
1451         channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask);
1452
1453         dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
1454         dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
1455         if (pdata->is_private)
1456                 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask);
1457         dw->dma.dev = &pdev->dev;
1458         dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources;
1459         dw->dma.device_free_chan_resources = dwc_free_chan_resources;
1460
1461         dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy;
1462
1463         dw->dma.device_prep_slave_sg = dwc_prep_slave_sg;
1464         dw->dma.device_control = dwc_control;
1465
1466         dw->dma.device_tx_status = dwc_tx_status;
1467         dw->dma.device_issue_pending = dwc_issue_pending;
1468
1469         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1470
1471         printk(KERN_INFO "%s: DesignWare DMA Controller, %d channels\n",
1472                         dev_name(&pdev->dev), dw->dma.chancnt);
1473
1474         dma_async_device_register(&dw->dma);
1475
1476         return 0;
1477
1478 err_irq:
1479         clk_disable(dw->clk);
1480         clk_put(dw->clk);
1481 err_clk:
1482         iounmap(dw->regs);
1483         dw->regs = NULL;
1484 err_release_r:
1485         release_resource(io);
1486 err_kfree:
1487         kfree(dw);
1488         return err;
1489 }
1490
1491 static int __exit dw_remove(struct platform_device *pdev)
1492 {
1493         struct dw_dma           *dw = platform_get_drvdata(pdev);
1494         struct dw_dma_chan      *dwc, *_dwc;
1495         struct resource         *io;
1496
1497         dw_dma_off(dw);
1498         dma_async_device_unregister(&dw->dma);
1499
1500         free_irq(platform_get_irq(pdev, 0), dw);
1501         tasklet_kill(&dw->tasklet);
1502
1503         list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels,
1504                         chan.device_node) {
1505                 list_del(&dwc->chan.device_node);
1506                 channel_clear_bit(dw, CH_EN, dwc->mask);
1507         }
1508
1509         clk_disable(dw->clk);
1510         clk_put(dw->clk);
1511
1512         iounmap(dw->regs);
1513         dw->regs = NULL;
1514
1515         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1516         release_mem_region(io->start, DW_REGLEN);
1517
1518         kfree(dw);
1519
1520         return 0;
1521 }
1522
1523 static void dw_shutdown(struct platform_device *pdev)
1524 {
1525         struct dw_dma   *dw = platform_get_drvdata(pdev);
1526
1527         dw_dma_off(platform_get_drvdata(pdev));
1528         clk_disable(dw->clk);
1529 }
1530
1531 static int dw_suspend_noirq(struct device *dev)
1532 {
1533         struct platform_device *pdev = to_platform_device(dev);
1534         struct dw_dma   *dw = platform_get_drvdata(pdev);
1535
1536         dw_dma_off(platform_get_drvdata(pdev));
1537         clk_disable(dw->clk);
1538         return 0;
1539 }
1540
1541 static int dw_resume_noirq(struct device *dev)
1542 {
1543         struct platform_device *pdev = to_platform_device(dev);
1544         struct dw_dma   *dw = platform_get_drvdata(pdev);
1545
1546         clk_enable(dw->clk);
1547         dma_writel(dw, CFG, DW_CFG_DMA_EN);
1548         return 0;
1549 }
1550
1551 static const struct dev_pm_ops dw_dev_pm_ops = {
1552         .suspend_noirq = dw_suspend_noirq,
1553         .resume_noirq = dw_resume_noirq,
1554 };
1555
1556 static struct platform_driver dw_driver = {
1557         .remove         = __exit_p(dw_remove),
1558         .shutdown       = dw_shutdown,
1559         .driver = {
1560                 .name   = "dw_dmac",
1561                 .pm     = &dw_dev_pm_ops,
1562         },
1563 };
1564
1565 static int __init dw_init(void)
1566 {
1567         return platform_driver_probe(&dw_driver, dw_probe);
1568 }
1569 subsys_initcall(dw_init);
1570
1571 static void __exit dw_exit(void)
1572 {
1573         platform_driver_unregister(&dw_driver);
1574 }
1575 module_exit(dw_exit);
1576
1577 MODULE_LICENSE("GPL v2");
1578 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller driver");
1579 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1580 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>");