DMAENGINE: COH 901 318 fix bytesleft
[linux-2.6.git] / drivers / dma / coh901318.c
1 /*
2  * driver/dma/coh901318.c
3  *
4  * Copyright (C) 2007-2009 ST-Ericsson
5  * License terms: GNU General Public License (GPL) version 2
6  * DMA driver for COH 901 318
7  * Author: Per Friden <per.friden@stericsson.com>
8  */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/slab.h> /* kmalloc() */
15 #include <linux/dmaengine.h>
16 #include <linux/platform_device.h>
17 #include <linux/device.h>
18 #include <linux/irqreturn.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/uaccess.h>
22 #include <linux/debugfs.h>
23 #include <mach/coh901318.h>
24
25 #include "coh901318_lli.h"
26
27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
28
29 #ifdef VERBOSE_DEBUG
30 #define COH_DBG(x) ({ if (1) x; 0; })
31 #else
32 #define COH_DBG(x) ({ if (0) x; 0; })
33 #endif
34
35 struct coh901318_desc {
36         struct dma_async_tx_descriptor desc;
37         struct list_head node;
38         struct scatterlist *sg;
39         unsigned int sg_len;
40         struct coh901318_lli *lli;
41         enum dma_data_direction dir;
42         unsigned long flags;
43 };
44
45 struct coh901318_base {
46         struct device *dev;
47         void __iomem *virtbase;
48         struct coh901318_pool pool;
49         struct powersave pm;
50         struct dma_device dma_slave;
51         struct dma_device dma_memcpy;
52         struct coh901318_chan *chans;
53         struct coh901318_platform *platform;
54 };
55
56 struct coh901318_chan {
57         spinlock_t lock;
58         int allocated;
59         int completed;
60         int id;
61         int stopped;
62
63         struct work_struct free_work;
64         struct dma_chan chan;
65
66         struct tasklet_struct tasklet;
67
68         struct list_head active;
69         struct list_head queue;
70         struct list_head free;
71
72         unsigned long nbr_active_done;
73         unsigned long busy;
74
75         struct coh901318_base *base;
76 };
77
78 static void coh901318_list_print(struct coh901318_chan *cohc,
79                                  struct coh901318_lli *lli)
80 {
81         struct coh901318_lli *l = lli;
82         int i = 0;
83
84         while (l) {
85                 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
86                          ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
87                          i, l, l->control, l->src_addr, l->dst_addr,
88                          l->link_addr, l->virt_link_addr);
89                 i++;
90                 l = l->virt_link_addr;
91         }
92 }
93
94 #ifdef CONFIG_DEBUG_FS
95
96 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
97
98 static struct coh901318_base *debugfs_dma_base;
99 static struct dentry *dma_dentry;
100
101 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
102 {
103
104         file->private_data = inode->i_private;
105         return 0;
106 }
107
108 static int coh901318_debugfs_read(struct file *file, char __user *buf,
109                                   size_t count, loff_t *f_pos)
110 {
111         u64 started_channels = debugfs_dma_base->pm.started_channels;
112         int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
113         int i;
114         int ret = 0;
115         char *dev_buf;
116         char *tmp;
117         int dev_size;
118
119         dev_buf = kmalloc(4*1024, GFP_KERNEL);
120         if (dev_buf == NULL)
121                 goto err_kmalloc;
122         tmp = dev_buf;
123
124         tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
125
126         for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
127                 if (started_channels & (1 << i))
128                         tmp += sprintf(tmp, "channel %d\n", i);
129
130         tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
131         dev_size = tmp  - dev_buf;
132
133         /* No more to read if offset != 0 */
134         if (*f_pos > dev_size)
135                 goto out;
136
137         if (count > dev_size - *f_pos)
138                 count = dev_size - *f_pos;
139
140         if (copy_to_user(buf, dev_buf + *f_pos, count))
141                 ret = -EINVAL;
142         ret = count;
143         *f_pos += count;
144
145  out:
146         kfree(dev_buf);
147         return ret;
148
149  err_kmalloc:
150         return 0;
151 }
152
153 static const struct file_operations coh901318_debugfs_status_operations = {
154         .owner          = THIS_MODULE,
155         .open           = coh901318_debugfs_open,
156         .read           = coh901318_debugfs_read,
157 };
158
159
160 static int __init init_coh901318_debugfs(void)
161 {
162
163         dma_dentry = debugfs_create_dir("dma", NULL);
164
165         (void) debugfs_create_file("status",
166                                    S_IFREG | S_IRUGO,
167                                    dma_dentry, NULL,
168                                    &coh901318_debugfs_status_operations);
169         return 0;
170 }
171
172 static void __exit exit_coh901318_debugfs(void)
173 {
174         debugfs_remove_recursive(dma_dentry);
175 }
176
177 module_init(init_coh901318_debugfs);
178 module_exit(exit_coh901318_debugfs);
179 #else
180
181 #define COH901318_DEBUGFS_ASSIGN(x, y)
182
183 #endif /* CONFIG_DEBUG_FS */
184
185 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
186 {
187         return container_of(chan, struct coh901318_chan, chan);
188 }
189
190 static inline dma_addr_t
191 cohc_dev_addr(struct coh901318_chan *cohc)
192 {
193         return cohc->base->platform->chan_conf[cohc->id].dev_addr;
194 }
195
196 static inline const struct coh901318_params *
197 cohc_chan_param(struct coh901318_chan *cohc)
198 {
199         return &cohc->base->platform->chan_conf[cohc->id].param;
200 }
201
202 static inline const struct coh_dma_channel *
203 cohc_chan_conf(struct coh901318_chan *cohc)
204 {
205         return &cohc->base->platform->chan_conf[cohc->id];
206 }
207
208 static void enable_powersave(struct coh901318_chan *cohc)
209 {
210         unsigned long flags;
211         struct powersave *pm = &cohc->base->pm;
212
213         spin_lock_irqsave(&pm->lock, flags);
214
215         pm->started_channels &= ~(1ULL << cohc->id);
216
217         if (!pm->started_channels) {
218                 /* DMA no longer intends to access memory */
219                 cohc->base->platform->access_memory_state(cohc->base->dev,
220                                                           false);
221         }
222
223         spin_unlock_irqrestore(&pm->lock, flags);
224 }
225 static void disable_powersave(struct coh901318_chan *cohc)
226 {
227         unsigned long flags;
228         struct powersave *pm = &cohc->base->pm;
229
230         spin_lock_irqsave(&pm->lock, flags);
231
232         if (!pm->started_channels) {
233                 /* DMA intends to access memory */
234                 cohc->base->platform->access_memory_state(cohc->base->dev,
235                                                           true);
236         }
237
238         pm->started_channels |= (1ULL << cohc->id);
239
240         spin_unlock_irqrestore(&pm->lock, flags);
241 }
242
243 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
244 {
245         int channel = cohc->id;
246         void __iomem *virtbase = cohc->base->virtbase;
247
248         writel(control,
249                virtbase + COH901318_CX_CTRL +
250                COH901318_CX_CTRL_SPACING * channel);
251         return 0;
252 }
253
254 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
255 {
256         int channel = cohc->id;
257         void __iomem *virtbase = cohc->base->virtbase;
258
259         writel(conf,
260                virtbase + COH901318_CX_CFG +
261                COH901318_CX_CFG_SPACING*channel);
262         return 0;
263 }
264
265
266 static int coh901318_start(struct coh901318_chan *cohc)
267 {
268         u32 val;
269         int channel = cohc->id;
270         void __iomem *virtbase = cohc->base->virtbase;
271
272         disable_powersave(cohc);
273
274         val = readl(virtbase + COH901318_CX_CFG +
275                     COH901318_CX_CFG_SPACING * channel);
276
277         /* Enable channel */
278         val |= COH901318_CX_CFG_CH_ENABLE;
279         writel(val, virtbase + COH901318_CX_CFG +
280                COH901318_CX_CFG_SPACING * channel);
281
282         return 0;
283 }
284
285 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
286                                       struct coh901318_lli *lli)
287 {
288         int channel = cohc->id;
289         void __iomem *virtbase = cohc->base->virtbase;
290
291         BUG_ON(readl(virtbase + COH901318_CX_STAT +
292                      COH901318_CX_STAT_SPACING*channel) &
293                COH901318_CX_STAT_ACTIVE);
294
295         writel(lli->src_addr,
296                virtbase + COH901318_CX_SRC_ADDR +
297                COH901318_CX_SRC_ADDR_SPACING * channel);
298
299         writel(lli->dst_addr, virtbase +
300                COH901318_CX_DST_ADDR +
301                COH901318_CX_DST_ADDR_SPACING * channel);
302
303         writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
304                COH901318_CX_LNK_ADDR_SPACING * channel);
305
306         writel(lli->control, virtbase + COH901318_CX_CTRL +
307                COH901318_CX_CTRL_SPACING * channel);
308
309         return 0;
310 }
311 static dma_cookie_t
312 coh901318_assign_cookie(struct coh901318_chan *cohc,
313                         struct coh901318_desc *cohd)
314 {
315         dma_cookie_t cookie = cohc->chan.cookie;
316
317         if (++cookie < 0)
318                 cookie = 1;
319
320         cohc->chan.cookie = cookie;
321         cohd->desc.cookie = cookie;
322
323         return cookie;
324 }
325
326 static struct coh901318_desc *
327 coh901318_desc_get(struct coh901318_chan *cohc)
328 {
329         struct coh901318_desc *desc;
330
331         if (list_empty(&cohc->free)) {
332                 /* alloc new desc because we're out of used ones
333                  * TODO: alloc a pile of descs instead of just one,
334                  * avoid many small allocations.
335                  */
336                 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
337                 if (desc == NULL)
338                         goto out;
339                 INIT_LIST_HEAD(&desc->node);
340                 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
341         } else {
342                 /* Reuse an old desc. */
343                 desc = list_first_entry(&cohc->free,
344                                         struct coh901318_desc,
345                                         node);
346                 list_del(&desc->node);
347                 /* Initialize it a bit so it's not insane */
348                 desc->sg = NULL;
349                 desc->sg_len = 0;
350                 desc->desc.callback = NULL;
351                 desc->desc.callback_param = NULL;
352         }
353
354  out:
355         return desc;
356 }
357
358 static void
359 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
360 {
361         list_add_tail(&cohd->node, &cohc->free);
362 }
363
364 /* call with irq lock held */
365 static void
366 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
367 {
368         list_add_tail(&desc->node, &cohc->active);
369 }
370
371 static struct coh901318_desc *
372 coh901318_first_active_get(struct coh901318_chan *cohc)
373 {
374         struct coh901318_desc *d;
375
376         if (list_empty(&cohc->active))
377                 return NULL;
378
379         d = list_first_entry(&cohc->active,
380                              struct coh901318_desc,
381                              node);
382         return d;
383 }
384
385 static void
386 coh901318_desc_remove(struct coh901318_desc *cohd)
387 {
388         list_del(&cohd->node);
389 }
390
391 static void
392 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
393 {
394         list_add_tail(&desc->node, &cohc->queue);
395 }
396
397 static struct coh901318_desc *
398 coh901318_first_queued(struct coh901318_chan *cohc)
399 {
400         struct coh901318_desc *d;
401
402         if (list_empty(&cohc->queue))
403                 return NULL;
404
405         d = list_first_entry(&cohc->queue,
406                              struct coh901318_desc,
407                              node);
408         return d;
409 }
410
411 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
412 {
413         struct coh901318_lli *lli = in_lli;
414         u32 bytes = 0;
415
416         while (lli) {
417                 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
418                 lli = lli->virt_link_addr;
419         }
420         return bytes;
421 }
422
423 /*
424  * Get the number of bytes left to transfer on this channel,
425  * it is unwise to call this before stopping the channel for
426  * absolute measures, but for a rough guess you can still call
427  * it.
428  */
429 u32 coh901318_get_bytes_left(struct dma_chan *chan)
430 {
431         struct coh901318_chan *cohc = to_coh901318_chan(chan);
432         struct coh901318_desc *cohd;
433         struct list_head *pos;
434         unsigned long flags;
435         u32 left = 0;
436         int i = 0;
437
438         spin_lock_irqsave(&cohc->lock, flags);
439
440         /*
441          * If there are many queued jobs, we iterate and add the
442          * size of them all. We take a special look on the first
443          * job though, since it is probably active.
444          */
445         list_for_each(pos, &cohc->active) {
446                 /*
447                  * The first job in the list will be working on the
448                  * hardware. The job can be stopped but still active,
449                  * so that the transfer counter is somewhere inside
450                  * the buffer.
451                  */
452                 cohd = list_entry(pos, struct coh901318_desc, node);
453
454                 if (i == 0) {
455                         struct coh901318_lli *lli;
456                         dma_addr_t ladd;
457
458                         /* Read current transfer count value */
459                         left = readl(cohc->base->virtbase +
460                                      COH901318_CX_CTRL +
461                                      COH901318_CX_CTRL_SPACING * cohc->id) &
462                                 COH901318_CX_CTRL_TC_VALUE_MASK;
463
464                         /* See if the transfer is linked... */
465                         ladd = readl(cohc->base->virtbase +
466                                      COH901318_CX_LNK_ADDR +
467                                      COH901318_CX_LNK_ADDR_SPACING *
468                                      cohc->id) &
469                                 ~COH901318_CX_LNK_LINK_IMMEDIATE;
470                         /* Single transaction */
471                         if (!ladd)
472                                 continue;
473
474                         /*
475                          * Linked transaction, follow the lli, find the
476                          * currently processing lli, and proceed to the next
477                          */
478                         lli = cohd->lli;
479                         while (lli && lli->link_addr != ladd)
480                                 lli = lli->virt_link_addr;
481
482                         if (lli)
483                                 lli = lli->virt_link_addr;
484
485                         /*
486                          * Follow remaining lli links around to count the total
487                          * number of bytes left
488                          */
489                         left += coh901318_get_bytes_in_lli(lli);
490                 } else {
491                         left += coh901318_get_bytes_in_lli(cohd->lli);
492                 }
493                 i++;
494         }
495
496         /* Also count bytes in the queued jobs */
497         list_for_each(pos, &cohc->queue) {
498                 cohd = list_entry(pos, struct coh901318_desc, node);
499                 left += coh901318_get_bytes_in_lli(cohd->lli);
500         }
501
502         spin_unlock_irqrestore(&cohc->lock, flags);
503
504         return left;
505 }
506 EXPORT_SYMBOL(coh901318_get_bytes_left);
507
508
509 /* Stops a transfer without losing data. Enables power save.
510    Use this function in conjunction with coh901318_continue(..)
511 */
512 void coh901318_stop(struct dma_chan *chan)
513 {
514         u32 val;
515         unsigned long flags;
516         struct coh901318_chan *cohc = to_coh901318_chan(chan);
517         int channel = cohc->id;
518         void __iomem *virtbase = cohc->base->virtbase;
519
520         spin_lock_irqsave(&cohc->lock, flags);
521
522         /* Disable channel in HW */
523         val = readl(virtbase + COH901318_CX_CFG +
524                     COH901318_CX_CFG_SPACING * channel);
525
526         /* Stopping infinit transfer */
527         if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
528             (val & COH901318_CX_CFG_CH_ENABLE))
529                 cohc->stopped = 1;
530
531
532         val &= ~COH901318_CX_CFG_CH_ENABLE;
533         /* Enable twice, HW bug work around */
534         writel(val, virtbase + COH901318_CX_CFG +
535                COH901318_CX_CFG_SPACING * channel);
536         writel(val, virtbase + COH901318_CX_CFG +
537                COH901318_CX_CFG_SPACING * channel);
538
539         /* Spin-wait for it to actually go inactive */
540         while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
541                      channel) & COH901318_CX_STAT_ACTIVE)
542                 cpu_relax();
543
544         /* Check if we stopped an active job */
545         if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
546                    channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
547                 cohc->stopped = 1;
548
549         enable_powersave(cohc);
550
551         spin_unlock_irqrestore(&cohc->lock, flags);
552 }
553 EXPORT_SYMBOL(coh901318_stop);
554
555 /* Continues a transfer that has been stopped via 300_dma_stop(..).
556    Power save is handled.
557 */
558 void coh901318_continue(struct dma_chan *chan)
559 {
560         u32 val;
561         unsigned long flags;
562         struct coh901318_chan *cohc = to_coh901318_chan(chan);
563         int channel = cohc->id;
564
565         spin_lock_irqsave(&cohc->lock, flags);
566
567         disable_powersave(cohc);
568
569         if (cohc->stopped) {
570                 /* Enable channel in HW */
571                 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
572                             COH901318_CX_CFG_SPACING * channel);
573
574                 val |= COH901318_CX_CFG_CH_ENABLE;
575
576                 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
577                        COH901318_CX_CFG_SPACING*channel);
578
579                 cohc->stopped = 0;
580         }
581
582         spin_unlock_irqrestore(&cohc->lock, flags);
583 }
584 EXPORT_SYMBOL(coh901318_continue);
585
586 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
587 {
588         unsigned int ch_nr = (unsigned int) chan_id;
589
590         if (ch_nr == to_coh901318_chan(chan)->id)
591                 return true;
592
593         return false;
594 }
595 EXPORT_SYMBOL(coh901318_filter_id);
596
597 /*
598  * DMA channel allocation
599  */
600 static int coh901318_config(struct coh901318_chan *cohc,
601                             struct coh901318_params *param)
602 {
603         unsigned long flags;
604         const struct coh901318_params *p;
605         int channel = cohc->id;
606         void __iomem *virtbase = cohc->base->virtbase;
607
608         spin_lock_irqsave(&cohc->lock, flags);
609
610         if (param)
611                 p = param;
612         else
613                 p = &cohc->base->platform->chan_conf[channel].param;
614
615         /* Clear any pending BE or TC interrupt */
616         if (channel < 32) {
617                 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
618                 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
619         } else {
620                 writel(1 << (channel - 32), virtbase +
621                        COH901318_BE_INT_CLEAR2);
622                 writel(1 << (channel - 32), virtbase +
623                        COH901318_TC_INT_CLEAR2);
624         }
625
626         coh901318_set_conf(cohc, p->config);
627         coh901318_set_ctrl(cohc, p->ctrl_lli_last);
628
629         spin_unlock_irqrestore(&cohc->lock, flags);
630
631         return 0;
632 }
633
634 /* must lock when calling this function
635  * start queued jobs, if any
636  * TODO: start all queued jobs in one go
637  *
638  * Returns descriptor if queued job is started otherwise NULL.
639  * If the queue is empty NULL is returned.
640  */
641 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
642 {
643         struct coh901318_desc *cohd;
644
645         /*
646          * start queued jobs, if any
647          * TODO: transmit all queued jobs in one go
648          */
649         cohd = coh901318_first_queued(cohc);
650
651         if (cohd != NULL) {
652                 /* Remove from queue */
653                 coh901318_desc_remove(cohd);
654                 /* initiate DMA job */
655                 cohc->busy = 1;
656
657                 coh901318_desc_submit(cohc, cohd);
658
659                 coh901318_prep_linked_list(cohc, cohd->lli);
660
661                 /* start dma job on this channel */
662                 coh901318_start(cohc);
663
664         }
665
666         return cohd;
667 }
668
669 /*
670  * This tasklet is called from the interrupt handler to
671  * handle each descriptor (DMA job) that is sent to a channel.
672  */
673 static void dma_tasklet(unsigned long data)
674 {
675         struct coh901318_chan *cohc = (struct coh901318_chan *) data;
676         struct coh901318_desc *cohd_fin;
677         unsigned long flags;
678         dma_async_tx_callback callback;
679         void *callback_param;
680
681         dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
682                  " nbr_active_done %ld\n", __func__,
683                  cohc->id, cohc->nbr_active_done);
684
685         spin_lock_irqsave(&cohc->lock, flags);
686
687         /* get first active descriptor entry from list */
688         cohd_fin = coh901318_first_active_get(cohc);
689
690         if (cohd_fin == NULL)
691                 goto err;
692
693         /* locate callback to client */
694         callback = cohd_fin->desc.callback;
695         callback_param = cohd_fin->desc.callback_param;
696
697         /* sign this job as completed on the channel */
698         cohc->completed = cohd_fin->desc.cookie;
699
700         /* release the lli allocation and remove the descriptor */
701         coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
702
703         /* return desc to free-list */
704         coh901318_desc_remove(cohd_fin);
705         coh901318_desc_free(cohc, cohd_fin);
706
707         spin_unlock_irqrestore(&cohc->lock, flags);
708
709         /* Call the callback when we're done */
710         if (callback)
711                 callback(callback_param);
712
713         spin_lock_irqsave(&cohc->lock, flags);
714
715         /*
716          * If another interrupt fired while the tasklet was scheduling,
717          * we don't get called twice, so we have this number of active
718          * counter that keep track of the number of IRQs expected to
719          * be handled for this channel. If there happen to be more than
720          * one IRQ to be ack:ed, we simply schedule this tasklet again.
721          */
722         cohc->nbr_active_done--;
723         if (cohc->nbr_active_done) {
724                 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
725                         "came in while we were scheduling this tasklet\n");
726                 if (cohc_chan_conf(cohc)->priority_high)
727                         tasklet_hi_schedule(&cohc->tasklet);
728                 else
729                         tasklet_schedule(&cohc->tasklet);
730         }
731
732         spin_unlock_irqrestore(&cohc->lock, flags);
733
734         return;
735
736  err:
737         spin_unlock_irqrestore(&cohc->lock, flags);
738         dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
739 }
740
741
742 /* called from interrupt context */
743 static void dma_tc_handle(struct coh901318_chan *cohc)
744 {
745         /*
746          * If the channel is not allocated, then we shouldn't have
747          * any TC interrupts on it.
748          */
749         if (!cohc->allocated) {
750                 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
751                         "unallocated channel\n");
752                 return;
753         }
754
755         spin_lock(&cohc->lock);
756
757         /*
758          * When we reach this point, at least one queue item
759          * should have been moved over from cohc->queue to
760          * cohc->active and run to completion, that is why we're
761          * getting a terminal count interrupt is it not?
762          * If you get this BUG() the most probable cause is that
763          * the individual nodes in the lli chain have IRQ enabled,
764          * so check your platform config for lli chain ctrl.
765          */
766         BUG_ON(list_empty(&cohc->active));
767
768         cohc->nbr_active_done++;
769
770         /*
771          * This attempt to take a job from cohc->queue, put it
772          * into cohc->active and start it.
773          */
774         if (coh901318_queue_start(cohc) == NULL)
775                 cohc->busy = 0;
776
777         spin_unlock(&cohc->lock);
778
779         /*
780          * This tasklet will remove items from cohc->active
781          * and thus terminates them.
782          */
783         if (cohc_chan_conf(cohc)->priority_high)
784                 tasklet_hi_schedule(&cohc->tasklet);
785         else
786                 tasklet_schedule(&cohc->tasklet);
787 }
788
789
790 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
791 {
792         u32 status1;
793         u32 status2;
794         int i;
795         int ch;
796         struct coh901318_base *base  = dev_id;
797         struct coh901318_chan *cohc;
798         void __iomem *virtbase = base->virtbase;
799
800         status1 = readl(virtbase + COH901318_INT_STATUS1);
801         status2 = readl(virtbase + COH901318_INT_STATUS2);
802
803         if (unlikely(status1 == 0 && status2 == 0)) {
804                 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
805                 return IRQ_HANDLED;
806         }
807
808         /* TODO: consider handle IRQ in tasklet here to
809          *       minimize interrupt latency */
810
811         /* Check the first 32 DMA channels for IRQ */
812         while (status1) {
813                 /* Find first bit set, return as a number. */
814                 i = ffs(status1) - 1;
815                 ch = i;
816
817                 cohc = &base->chans[ch];
818                 spin_lock(&cohc->lock);
819
820                 /* Mask off this bit */
821                 status1 &= ~(1 << i);
822                 /* Check the individual channel bits */
823                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
824                         dev_crit(COHC_2_DEV(cohc),
825                                  "DMA bus error on channel %d!\n", ch);
826                         BUG_ON(1);
827                         /* Clear BE interrupt */
828                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
829                 } else {
830                         /* Caused by TC, really? */
831                         if (unlikely(!test_bit(i, virtbase +
832                                                COH901318_TC_INT_STATUS1))) {
833                                 dev_warn(COHC_2_DEV(cohc),
834                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
835                                 /* Clear TC interrupt */
836                                 BUG_ON(1);
837                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
838                         } else {
839                                 /* Enable powersave if transfer has finished */
840                                 if (!(readl(virtbase + COH901318_CX_STAT +
841                                             COH901318_CX_STAT_SPACING*ch) &
842                                       COH901318_CX_STAT_ENABLED)) {
843                                         enable_powersave(cohc);
844                                 }
845
846                                 /* Must clear TC interrupt before calling
847                                  * dma_tc_handle
848                                  * in case tc_handle initate a new dma job
849                                  */
850                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
851
852                                 dma_tc_handle(cohc);
853                         }
854                 }
855                 spin_unlock(&cohc->lock);
856         }
857
858         /* Check the remaining 32 DMA channels for IRQ */
859         while (status2) {
860                 /* Find first bit set, return as a number. */
861                 i = ffs(status2) - 1;
862                 ch = i + 32;
863                 cohc = &base->chans[ch];
864                 spin_lock(&cohc->lock);
865
866                 /* Mask off this bit */
867                 status2 &= ~(1 << i);
868                 /* Check the individual channel bits */
869                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
870                         dev_crit(COHC_2_DEV(cohc),
871                                  "DMA bus error on channel %d!\n", ch);
872                         /* Clear BE interrupt */
873                         BUG_ON(1);
874                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
875                 } else {
876                         /* Caused by TC, really? */
877                         if (unlikely(!test_bit(i, virtbase +
878                                                COH901318_TC_INT_STATUS2))) {
879                                 dev_warn(COHC_2_DEV(cohc),
880                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
881                                 /* Clear TC interrupt */
882                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
883                                 BUG_ON(1);
884                         } else {
885                                 /* Enable powersave if transfer has finished */
886                                 if (!(readl(virtbase + COH901318_CX_STAT +
887                                             COH901318_CX_STAT_SPACING*ch) &
888                                       COH901318_CX_STAT_ENABLED)) {
889                                         enable_powersave(cohc);
890                                 }
891                                 /* Must clear TC interrupt before calling
892                                  * dma_tc_handle
893                                  * in case tc_handle initate a new dma job
894                                  */
895                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
896
897                                 dma_tc_handle(cohc);
898                         }
899                 }
900                 spin_unlock(&cohc->lock);
901         }
902
903         return IRQ_HANDLED;
904 }
905
906 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
907 {
908         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
909         unsigned long flags;
910
911         dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
912                  __func__, cohc->id);
913
914         if (chan->client_count > 1)
915                 return -EBUSY;
916
917         spin_lock_irqsave(&cohc->lock, flags);
918
919         coh901318_config(cohc, NULL);
920
921         cohc->allocated = 1;
922         cohc->completed = chan->cookie = 1;
923
924         spin_unlock_irqrestore(&cohc->lock, flags);
925
926         return 1;
927 }
928
929 static void
930 coh901318_free_chan_resources(struct dma_chan *chan)
931 {
932         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
933         int channel = cohc->id;
934         unsigned long flags;
935
936         spin_lock_irqsave(&cohc->lock, flags);
937
938         /* Disable HW */
939         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
940                COH901318_CX_CFG_SPACING*channel);
941         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
942                COH901318_CX_CTRL_SPACING*channel);
943
944         cohc->allocated = 0;
945
946         spin_unlock_irqrestore(&cohc->lock, flags);
947
948         chan->device->device_terminate_all(chan);
949 }
950
951
952 static dma_cookie_t
953 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
954 {
955         struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
956                                                    desc);
957         struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
958         unsigned long flags;
959
960         spin_lock_irqsave(&cohc->lock, flags);
961
962         tx->cookie = coh901318_assign_cookie(cohc, cohd);
963
964         coh901318_desc_queue(cohc, cohd);
965
966         spin_unlock_irqrestore(&cohc->lock, flags);
967
968         return tx->cookie;
969 }
970
971 static struct dma_async_tx_descriptor *
972 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
973                       size_t size, unsigned long flags)
974 {
975         struct coh901318_lli *lli;
976         struct coh901318_desc *cohd;
977         unsigned long flg;
978         struct coh901318_chan *cohc = to_coh901318_chan(chan);
979         int lli_len;
980         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
981         int ret;
982
983         spin_lock_irqsave(&cohc->lock, flg);
984
985         dev_vdbg(COHC_2_DEV(cohc),
986                  "[%s] channel %d src 0x%x dest 0x%x size %d\n",
987                  __func__, cohc->id, src, dest, size);
988
989         if (flags & DMA_PREP_INTERRUPT)
990                 /* Trigger interrupt after last lli */
991                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
992
993         lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
994         if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
995                 lli_len++;
996
997         lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
998
999         if (lli == NULL)
1000                 goto err;
1001
1002         ret = coh901318_lli_fill_memcpy(
1003                 &cohc->base->pool, lli, src, size, dest,
1004                 cohc_chan_param(cohc)->ctrl_lli_chained,
1005                 ctrl_last);
1006         if (ret)
1007                 goto err;
1008
1009         COH_DBG(coh901318_list_print(cohc, lli));
1010
1011         /* Pick a descriptor to handle this transfer */
1012         cohd = coh901318_desc_get(cohc);
1013         cohd->lli = lli;
1014         cohd->flags = flags;
1015         cohd->desc.tx_submit = coh901318_tx_submit;
1016
1017         spin_unlock_irqrestore(&cohc->lock, flg);
1018
1019         return &cohd->desc;
1020  err:
1021         spin_unlock_irqrestore(&cohc->lock, flg);
1022         return NULL;
1023 }
1024
1025 static struct dma_async_tx_descriptor *
1026 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1027                         unsigned int sg_len, enum dma_data_direction direction,
1028                         unsigned long flags)
1029 {
1030         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1031         struct coh901318_lli *lli;
1032         struct coh901318_desc *cohd;
1033         const struct coh901318_params *params;
1034         struct scatterlist *sg;
1035         int len = 0;
1036         int size;
1037         int i;
1038         u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1039         u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1040         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1041         u32 config;
1042         unsigned long flg;
1043         int ret;
1044
1045         if (!sgl)
1046                 goto out;
1047         if (sgl->length == 0)
1048                 goto out;
1049
1050         spin_lock_irqsave(&cohc->lock, flg);
1051
1052         dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1053                  __func__, sg_len, direction);
1054
1055         if (flags & DMA_PREP_INTERRUPT)
1056                 /* Trigger interrupt after last lli */
1057                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1058
1059         params = cohc_chan_param(cohc);
1060         config = params->config;
1061
1062         if (direction == DMA_TO_DEVICE) {
1063                 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1064                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1065
1066                 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1067                 ctrl_chained |= tx_flags;
1068                 ctrl_last |= tx_flags;
1069                 ctrl |= tx_flags;
1070         } else if (direction == DMA_FROM_DEVICE) {
1071                 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1072                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1073
1074                 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1075                 ctrl_chained |= rx_flags;
1076                 ctrl_last |= rx_flags;
1077                 ctrl |= rx_flags;
1078         } else
1079                 goto err_direction;
1080
1081         coh901318_set_conf(cohc, config);
1082
1083         /* The dma only supports transmitting packages up to
1084          * MAX_DMA_PACKET_SIZE. Calculate to total number of
1085          * dma elemts required to send the entire sg list
1086          */
1087         for_each_sg(sgl, sg, sg_len, i) {
1088                 unsigned int factor;
1089                 size = sg_dma_len(sg);
1090
1091                 if (size <= MAX_DMA_PACKET_SIZE) {
1092                         len++;
1093                         continue;
1094                 }
1095
1096                 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1097                 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1098                         factor++;
1099
1100                 len += factor;
1101         }
1102
1103         pr_debug("Allocate %d lli:s for this transfer\n", len);
1104         lli = coh901318_lli_alloc(&cohc->base->pool, len);
1105
1106         if (lli == NULL)
1107                 goto err_dma_alloc;
1108
1109         /* initiate allocated lli list */
1110         ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1111                                     cohc_dev_addr(cohc),
1112                                     ctrl_chained,
1113                                     ctrl,
1114                                     ctrl_last,
1115                                     direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1116         if (ret)
1117                 goto err_lli_fill;
1118
1119         COH_DBG(coh901318_list_print(cohc, lli));
1120
1121         /* Pick a descriptor to handle this transfer */
1122         cohd = coh901318_desc_get(cohc);
1123         cohd->dir = direction;
1124         cohd->flags = flags;
1125         cohd->desc.tx_submit = coh901318_tx_submit;
1126         cohd->lli = lli;
1127
1128         spin_unlock_irqrestore(&cohc->lock, flg);
1129
1130         return &cohd->desc;
1131  err_lli_fill:
1132  err_dma_alloc:
1133  err_direction:
1134         spin_unlock_irqrestore(&cohc->lock, flg);
1135  out:
1136         return NULL;
1137 }
1138
1139 static enum dma_status
1140 coh901318_is_tx_complete(struct dma_chan *chan,
1141                          dma_cookie_t cookie, dma_cookie_t *done,
1142                          dma_cookie_t *used)
1143 {
1144         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1145         dma_cookie_t last_used;
1146         dma_cookie_t last_complete;
1147         int ret;
1148
1149         last_complete = cohc->completed;
1150         last_used = chan->cookie;
1151
1152         ret = dma_async_is_complete(cookie, last_complete, last_used);
1153
1154         if (done)
1155                 *done = last_complete;
1156         if (used)
1157                 *used = last_used;
1158
1159         return ret;
1160 }
1161
1162 static void
1163 coh901318_issue_pending(struct dma_chan *chan)
1164 {
1165         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1166         unsigned long flags;
1167
1168         spin_lock_irqsave(&cohc->lock, flags);
1169
1170         /*
1171          * Busy means that pending jobs are already being processed,
1172          * and then there is no point in starting the queue: the
1173          * terminal count interrupt on the channel will take the next
1174          * job on the queue and execute it anyway.
1175          */
1176         if (!cohc->busy)
1177                 coh901318_queue_start(cohc);
1178
1179         spin_unlock_irqrestore(&cohc->lock, flags);
1180 }
1181
1182 static void
1183 coh901318_terminate_all(struct dma_chan *chan)
1184 {
1185         unsigned long flags;
1186         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1187         struct coh901318_desc *cohd;
1188         void __iomem *virtbase = cohc->base->virtbase;
1189
1190         coh901318_stop(chan);
1191
1192         spin_lock_irqsave(&cohc->lock, flags);
1193
1194         /* Clear any pending BE or TC interrupt */
1195         if (cohc->id < 32) {
1196                 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1197                 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1198         } else {
1199                 writel(1 << (cohc->id - 32), virtbase +
1200                        COH901318_BE_INT_CLEAR2);
1201                 writel(1 << (cohc->id - 32), virtbase +
1202                        COH901318_TC_INT_CLEAR2);
1203         }
1204
1205         enable_powersave(cohc);
1206
1207         while ((cohd = coh901318_first_active_get(cohc))) {
1208                 /* release the lli allocation*/
1209                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1210
1211                 /* return desc to free-list */
1212                 coh901318_desc_remove(cohd);
1213                 coh901318_desc_free(cohc, cohd);
1214         }
1215
1216         while ((cohd = coh901318_first_queued(cohc))) {
1217                 /* release the lli allocation*/
1218                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1219
1220                 /* return desc to free-list */
1221                 coh901318_desc_remove(cohd);
1222                 coh901318_desc_free(cohc, cohd);
1223         }
1224
1225
1226         cohc->nbr_active_done = 0;
1227         cohc->busy = 0;
1228
1229         spin_unlock_irqrestore(&cohc->lock, flags);
1230 }
1231 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1232                          struct coh901318_base *base)
1233 {
1234         int chans_i;
1235         int i = 0;
1236         struct coh901318_chan *cohc;
1237
1238         INIT_LIST_HEAD(&dma->channels);
1239
1240         for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1241                 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1242                         cohc = &base->chans[i];
1243
1244                         cohc->base = base;
1245                         cohc->chan.device = dma;
1246                         cohc->id = i;
1247
1248                         /* TODO: do we really need this lock if only one
1249                          * client is connected to each channel?
1250                          */
1251
1252                         spin_lock_init(&cohc->lock);
1253
1254                         cohc->nbr_active_done = 0;
1255                         cohc->busy = 0;
1256                         INIT_LIST_HEAD(&cohc->free);
1257                         INIT_LIST_HEAD(&cohc->active);
1258                         INIT_LIST_HEAD(&cohc->queue);
1259
1260                         tasklet_init(&cohc->tasklet, dma_tasklet,
1261                                      (unsigned long) cohc);
1262
1263                         list_add_tail(&cohc->chan.device_node,
1264                                       &dma->channels);
1265                 }
1266         }
1267 }
1268
1269 static int __init coh901318_probe(struct platform_device *pdev)
1270 {
1271         int err = 0;
1272         struct coh901318_platform *pdata;
1273         struct coh901318_base *base;
1274         int irq;
1275         struct resource *io;
1276
1277         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1278         if (!io)
1279                 goto err_get_resource;
1280
1281         /* Map DMA controller registers to virtual memory */
1282         if (request_mem_region(io->start,
1283                                resource_size(io),
1284                                pdev->dev.driver->name) == NULL) {
1285                 err = -EBUSY;
1286                 goto err_request_mem;
1287         }
1288
1289         pdata = pdev->dev.platform_data;
1290         if (!pdata)
1291                 goto err_no_platformdata;
1292
1293         base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1294                        pdata->max_channels *
1295                        sizeof(struct coh901318_chan),
1296                        GFP_KERNEL);
1297         if (!base)
1298                 goto err_alloc_coh_dma_channels;
1299
1300         base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1301
1302         base->virtbase = ioremap(io->start, resource_size(io));
1303         if (!base->virtbase) {
1304                 err = -ENOMEM;
1305                 goto err_no_ioremap;
1306         }
1307
1308         base->dev = &pdev->dev;
1309         base->platform = pdata;
1310         spin_lock_init(&base->pm.lock);
1311         base->pm.started_channels = 0;
1312
1313         COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1314
1315         platform_set_drvdata(pdev, base);
1316
1317         irq = platform_get_irq(pdev, 0);
1318         if (irq < 0)
1319                 goto err_no_irq;
1320
1321         err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1322                           "coh901318", base);
1323         if (err) {
1324                 dev_crit(&pdev->dev,
1325                          "Cannot allocate IRQ for DMA controller!\n");
1326                 goto err_request_irq;
1327         }
1328
1329         err = coh901318_pool_create(&base->pool, &pdev->dev,
1330                                     sizeof(struct coh901318_lli),
1331                                     32);
1332         if (err)
1333                 goto err_pool_create;
1334
1335         /* init channels for device transfers */
1336         coh901318_base_init(&base->dma_slave,  base->platform->chans_slave,
1337                             base);
1338
1339         dma_cap_zero(base->dma_slave.cap_mask);
1340         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1341
1342         base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1343         base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1344         base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1345         base->dma_slave.device_is_tx_complete = coh901318_is_tx_complete;
1346         base->dma_slave.device_issue_pending = coh901318_issue_pending;
1347         base->dma_slave.device_terminate_all = coh901318_terminate_all;
1348         base->dma_slave.dev = &pdev->dev;
1349
1350         err = dma_async_device_register(&base->dma_slave);
1351
1352         if (err)
1353                 goto err_register_slave;
1354
1355         /* init channels for memcpy */
1356         coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1357                             base);
1358
1359         dma_cap_zero(base->dma_memcpy.cap_mask);
1360         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1361
1362         base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1363         base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1364         base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1365         base->dma_memcpy.device_is_tx_complete = coh901318_is_tx_complete;
1366         base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1367         base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
1368         base->dma_memcpy.dev = &pdev->dev;
1369         /*
1370          * This controller can only access address at even 32bit boundaries,
1371          * i.e. 2^2
1372          */
1373         base->dma_memcpy.copy_align = 2;
1374         err = dma_async_device_register(&base->dma_memcpy);
1375
1376         if (err)
1377                 goto err_register_memcpy;
1378
1379         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1380                 (u32) base->virtbase);
1381
1382         return err;
1383
1384  err_register_memcpy:
1385         dma_async_device_unregister(&base->dma_slave);
1386  err_register_slave:
1387         coh901318_pool_destroy(&base->pool);
1388  err_pool_create:
1389         free_irq(platform_get_irq(pdev, 0), base);
1390  err_request_irq:
1391  err_no_irq:
1392         iounmap(base->virtbase);
1393  err_no_ioremap:
1394         kfree(base);
1395  err_alloc_coh_dma_channels:
1396  err_no_platformdata:
1397         release_mem_region(pdev->resource->start,
1398                            resource_size(pdev->resource));
1399  err_request_mem:
1400  err_get_resource:
1401         return err;
1402 }
1403
1404 static int __exit coh901318_remove(struct platform_device *pdev)
1405 {
1406         struct coh901318_base *base = platform_get_drvdata(pdev);
1407
1408         dma_async_device_unregister(&base->dma_memcpy);
1409         dma_async_device_unregister(&base->dma_slave);
1410         coh901318_pool_destroy(&base->pool);
1411         free_irq(platform_get_irq(pdev, 0), base);
1412         iounmap(base->virtbase);
1413         kfree(base);
1414         release_mem_region(pdev->resource->start,
1415                            resource_size(pdev->resource));
1416         return 0;
1417 }
1418
1419
1420 static struct platform_driver coh901318_driver = {
1421         .remove = __exit_p(coh901318_remove),
1422         .driver = {
1423                 .name   = "coh901318",
1424         },
1425 };
1426
1427 int __init coh901318_init(void)
1428 {
1429         return platform_driver_probe(&coh901318_driver, coh901318_probe);
1430 }
1431 subsys_initcall(coh901318_init);
1432
1433 void __exit coh901318_exit(void)
1434 {
1435         platform_driver_unregister(&coh901318_driver);
1436 }
1437 module_exit(coh901318_exit);
1438
1439 MODULE_LICENSE("GPL");
1440 MODULE_AUTHOR("Per Friden");