dmaengine: provide helper for setting txstate
[linux-2.6.git] / drivers / dma / coh901318.c
1 /*
2  * driver/dma/coh901318.c
3  *
4  * Copyright (C) 2007-2009 ST-Ericsson
5  * License terms: GNU General Public License (GPL) version 2
6  * DMA driver for COH 901 318
7  * Author: Per Friden <per.friden@stericsson.com>
8  */
9
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/kernel.h> /* printk() */
13 #include <linux/fs.h> /* everything... */
14 #include <linux/slab.h> /* kmalloc() */
15 #include <linux/dmaengine.h>
16 #include <linux/platform_device.h>
17 #include <linux/device.h>
18 #include <linux/irqreturn.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/uaccess.h>
22 #include <linux/debugfs.h>
23 #include <mach/coh901318.h>
24
25 #include "coh901318_lli.h"
26
27 #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
28
29 #ifdef VERBOSE_DEBUG
30 #define COH_DBG(x) ({ if (1) x; 0; })
31 #else
32 #define COH_DBG(x) ({ if (0) x; 0; })
33 #endif
34
35 struct coh901318_desc {
36         struct dma_async_tx_descriptor desc;
37         struct list_head node;
38         struct scatterlist *sg;
39         unsigned int sg_len;
40         struct coh901318_lli *lli;
41         enum dma_data_direction dir;
42         unsigned long flags;
43 };
44
45 struct coh901318_base {
46         struct device *dev;
47         void __iomem *virtbase;
48         struct coh901318_pool pool;
49         struct powersave pm;
50         struct dma_device dma_slave;
51         struct dma_device dma_memcpy;
52         struct coh901318_chan *chans;
53         struct coh901318_platform *platform;
54 };
55
56 struct coh901318_chan {
57         spinlock_t lock;
58         int allocated;
59         int completed;
60         int id;
61         int stopped;
62
63         struct work_struct free_work;
64         struct dma_chan chan;
65
66         struct tasklet_struct tasklet;
67
68         struct list_head active;
69         struct list_head queue;
70         struct list_head free;
71
72         unsigned long nbr_active_done;
73         unsigned long busy;
74
75         struct coh901318_base *base;
76 };
77
78 static void coh901318_list_print(struct coh901318_chan *cohc,
79                                  struct coh901318_lli *lli)
80 {
81         struct coh901318_lli *l = lli;
82         int i = 0;
83
84         while (l) {
85                 dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src 0x%x"
86                          ", dst 0x%x, link 0x%x virt_link_addr 0x%p\n",
87                          i, l, l->control, l->src_addr, l->dst_addr,
88                          l->link_addr, l->virt_link_addr);
89                 i++;
90                 l = l->virt_link_addr;
91         }
92 }
93
94 #ifdef CONFIG_DEBUG_FS
95
96 #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
97
98 static struct coh901318_base *debugfs_dma_base;
99 static struct dentry *dma_dentry;
100
101 static int coh901318_debugfs_open(struct inode *inode, struct file *file)
102 {
103
104         file->private_data = inode->i_private;
105         return 0;
106 }
107
108 static int coh901318_debugfs_read(struct file *file, char __user *buf,
109                                   size_t count, loff_t *f_pos)
110 {
111         u64 started_channels = debugfs_dma_base->pm.started_channels;
112         int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
113         int i;
114         int ret = 0;
115         char *dev_buf;
116         char *tmp;
117         int dev_size;
118
119         dev_buf = kmalloc(4*1024, GFP_KERNEL);
120         if (dev_buf == NULL)
121                 goto err_kmalloc;
122         tmp = dev_buf;
123
124         tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
125
126         for (i = 0; i < debugfs_dma_base->platform->max_channels; i++)
127                 if (started_channels & (1 << i))
128                         tmp += sprintf(tmp, "channel %d\n", i);
129
130         tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
131         dev_size = tmp  - dev_buf;
132
133         /* No more to read if offset != 0 */
134         if (*f_pos > dev_size)
135                 goto out;
136
137         if (count > dev_size - *f_pos)
138                 count = dev_size - *f_pos;
139
140         if (copy_to_user(buf, dev_buf + *f_pos, count))
141                 ret = -EINVAL;
142         ret = count;
143         *f_pos += count;
144
145  out:
146         kfree(dev_buf);
147         return ret;
148
149  err_kmalloc:
150         return 0;
151 }
152
153 static const struct file_operations coh901318_debugfs_status_operations = {
154         .owner          = THIS_MODULE,
155         .open           = coh901318_debugfs_open,
156         .read           = coh901318_debugfs_read,
157 };
158
159
160 static int __init init_coh901318_debugfs(void)
161 {
162
163         dma_dentry = debugfs_create_dir("dma", NULL);
164
165         (void) debugfs_create_file("status",
166                                    S_IFREG | S_IRUGO,
167                                    dma_dentry, NULL,
168                                    &coh901318_debugfs_status_operations);
169         return 0;
170 }
171
172 static void __exit exit_coh901318_debugfs(void)
173 {
174         debugfs_remove_recursive(dma_dentry);
175 }
176
177 module_init(init_coh901318_debugfs);
178 module_exit(exit_coh901318_debugfs);
179 #else
180
181 #define COH901318_DEBUGFS_ASSIGN(x, y)
182
183 #endif /* CONFIG_DEBUG_FS */
184
185 static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
186 {
187         return container_of(chan, struct coh901318_chan, chan);
188 }
189
190 static inline dma_addr_t
191 cohc_dev_addr(struct coh901318_chan *cohc)
192 {
193         return cohc->base->platform->chan_conf[cohc->id].dev_addr;
194 }
195
196 static inline const struct coh901318_params *
197 cohc_chan_param(struct coh901318_chan *cohc)
198 {
199         return &cohc->base->platform->chan_conf[cohc->id].param;
200 }
201
202 static inline const struct coh_dma_channel *
203 cohc_chan_conf(struct coh901318_chan *cohc)
204 {
205         return &cohc->base->platform->chan_conf[cohc->id];
206 }
207
208 static void enable_powersave(struct coh901318_chan *cohc)
209 {
210         unsigned long flags;
211         struct powersave *pm = &cohc->base->pm;
212
213         spin_lock_irqsave(&pm->lock, flags);
214
215         pm->started_channels &= ~(1ULL << cohc->id);
216
217         if (!pm->started_channels) {
218                 /* DMA no longer intends to access memory */
219                 cohc->base->platform->access_memory_state(cohc->base->dev,
220                                                           false);
221         }
222
223         spin_unlock_irqrestore(&pm->lock, flags);
224 }
225 static void disable_powersave(struct coh901318_chan *cohc)
226 {
227         unsigned long flags;
228         struct powersave *pm = &cohc->base->pm;
229
230         spin_lock_irqsave(&pm->lock, flags);
231
232         if (!pm->started_channels) {
233                 /* DMA intends to access memory */
234                 cohc->base->platform->access_memory_state(cohc->base->dev,
235                                                           true);
236         }
237
238         pm->started_channels |= (1ULL << cohc->id);
239
240         spin_unlock_irqrestore(&pm->lock, flags);
241 }
242
243 static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
244 {
245         int channel = cohc->id;
246         void __iomem *virtbase = cohc->base->virtbase;
247
248         writel(control,
249                virtbase + COH901318_CX_CTRL +
250                COH901318_CX_CTRL_SPACING * channel);
251         return 0;
252 }
253
254 static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
255 {
256         int channel = cohc->id;
257         void __iomem *virtbase = cohc->base->virtbase;
258
259         writel(conf,
260                virtbase + COH901318_CX_CFG +
261                COH901318_CX_CFG_SPACING*channel);
262         return 0;
263 }
264
265
266 static int coh901318_start(struct coh901318_chan *cohc)
267 {
268         u32 val;
269         int channel = cohc->id;
270         void __iomem *virtbase = cohc->base->virtbase;
271
272         disable_powersave(cohc);
273
274         val = readl(virtbase + COH901318_CX_CFG +
275                     COH901318_CX_CFG_SPACING * channel);
276
277         /* Enable channel */
278         val |= COH901318_CX_CFG_CH_ENABLE;
279         writel(val, virtbase + COH901318_CX_CFG +
280                COH901318_CX_CFG_SPACING * channel);
281
282         return 0;
283 }
284
285 static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
286                                       struct coh901318_lli *lli)
287 {
288         int channel = cohc->id;
289         void __iomem *virtbase = cohc->base->virtbase;
290
291         BUG_ON(readl(virtbase + COH901318_CX_STAT +
292                      COH901318_CX_STAT_SPACING*channel) &
293                COH901318_CX_STAT_ACTIVE);
294
295         writel(lli->src_addr,
296                virtbase + COH901318_CX_SRC_ADDR +
297                COH901318_CX_SRC_ADDR_SPACING * channel);
298
299         writel(lli->dst_addr, virtbase +
300                COH901318_CX_DST_ADDR +
301                COH901318_CX_DST_ADDR_SPACING * channel);
302
303         writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
304                COH901318_CX_LNK_ADDR_SPACING * channel);
305
306         writel(lli->control, virtbase + COH901318_CX_CTRL +
307                COH901318_CX_CTRL_SPACING * channel);
308
309         return 0;
310 }
311 static dma_cookie_t
312 coh901318_assign_cookie(struct coh901318_chan *cohc,
313                         struct coh901318_desc *cohd)
314 {
315         dma_cookie_t cookie = cohc->chan.cookie;
316
317         if (++cookie < 0)
318                 cookie = 1;
319
320         cohc->chan.cookie = cookie;
321         cohd->desc.cookie = cookie;
322
323         return cookie;
324 }
325
326 static struct coh901318_desc *
327 coh901318_desc_get(struct coh901318_chan *cohc)
328 {
329         struct coh901318_desc *desc;
330
331         if (list_empty(&cohc->free)) {
332                 /* alloc new desc because we're out of used ones
333                  * TODO: alloc a pile of descs instead of just one,
334                  * avoid many small allocations.
335                  */
336                 desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
337                 if (desc == NULL)
338                         goto out;
339                 INIT_LIST_HEAD(&desc->node);
340                 dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
341         } else {
342                 /* Reuse an old desc. */
343                 desc = list_first_entry(&cohc->free,
344                                         struct coh901318_desc,
345                                         node);
346                 list_del(&desc->node);
347                 /* Initialize it a bit so it's not insane */
348                 desc->sg = NULL;
349                 desc->sg_len = 0;
350                 desc->desc.callback = NULL;
351                 desc->desc.callback_param = NULL;
352         }
353
354  out:
355         return desc;
356 }
357
358 static void
359 coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
360 {
361         list_add_tail(&cohd->node, &cohc->free);
362 }
363
364 /* call with irq lock held */
365 static void
366 coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
367 {
368         list_add_tail(&desc->node, &cohc->active);
369 }
370
371 static struct coh901318_desc *
372 coh901318_first_active_get(struct coh901318_chan *cohc)
373 {
374         struct coh901318_desc *d;
375
376         if (list_empty(&cohc->active))
377                 return NULL;
378
379         d = list_first_entry(&cohc->active,
380                              struct coh901318_desc,
381                              node);
382         return d;
383 }
384
385 static void
386 coh901318_desc_remove(struct coh901318_desc *cohd)
387 {
388         list_del(&cohd->node);
389 }
390
391 static void
392 coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
393 {
394         list_add_tail(&desc->node, &cohc->queue);
395 }
396
397 static struct coh901318_desc *
398 coh901318_first_queued(struct coh901318_chan *cohc)
399 {
400         struct coh901318_desc *d;
401
402         if (list_empty(&cohc->queue))
403                 return NULL;
404
405         d = list_first_entry(&cohc->queue,
406                              struct coh901318_desc,
407                              node);
408         return d;
409 }
410
411 static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
412 {
413         struct coh901318_lli *lli = in_lli;
414         u32 bytes = 0;
415
416         while (lli) {
417                 bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
418                 lli = lli->virt_link_addr;
419         }
420         return bytes;
421 }
422
423 /*
424  * Get the number of bytes left to transfer on this channel,
425  * it is unwise to call this before stopping the channel for
426  * absolute measures, but for a rough guess you can still call
427  * it.
428  */
429 static u32 coh901318_get_bytes_left(struct dma_chan *chan)
430 {
431         struct coh901318_chan *cohc = to_coh901318_chan(chan);
432         struct coh901318_desc *cohd;
433         struct list_head *pos;
434         unsigned long flags;
435         u32 left = 0;
436         int i = 0;
437
438         spin_lock_irqsave(&cohc->lock, flags);
439
440         /*
441          * If there are many queued jobs, we iterate and add the
442          * size of them all. We take a special look on the first
443          * job though, since it is probably active.
444          */
445         list_for_each(pos, &cohc->active) {
446                 /*
447                  * The first job in the list will be working on the
448                  * hardware. The job can be stopped but still active,
449                  * so that the transfer counter is somewhere inside
450                  * the buffer.
451                  */
452                 cohd = list_entry(pos, struct coh901318_desc, node);
453
454                 if (i == 0) {
455                         struct coh901318_lli *lli;
456                         dma_addr_t ladd;
457
458                         /* Read current transfer count value */
459                         left = readl(cohc->base->virtbase +
460                                      COH901318_CX_CTRL +
461                                      COH901318_CX_CTRL_SPACING * cohc->id) &
462                                 COH901318_CX_CTRL_TC_VALUE_MASK;
463
464                         /* See if the transfer is linked... */
465                         ladd = readl(cohc->base->virtbase +
466                                      COH901318_CX_LNK_ADDR +
467                                      COH901318_CX_LNK_ADDR_SPACING *
468                                      cohc->id) &
469                                 ~COH901318_CX_LNK_LINK_IMMEDIATE;
470                         /* Single transaction */
471                         if (!ladd)
472                                 continue;
473
474                         /*
475                          * Linked transaction, follow the lli, find the
476                          * currently processing lli, and proceed to the next
477                          */
478                         lli = cohd->lli;
479                         while (lli && lli->link_addr != ladd)
480                                 lli = lli->virt_link_addr;
481
482                         if (lli)
483                                 lli = lli->virt_link_addr;
484
485                         /*
486                          * Follow remaining lli links around to count the total
487                          * number of bytes left
488                          */
489                         left += coh901318_get_bytes_in_lli(lli);
490                 } else {
491                         left += coh901318_get_bytes_in_lli(cohd->lli);
492                 }
493                 i++;
494         }
495
496         /* Also count bytes in the queued jobs */
497         list_for_each(pos, &cohc->queue) {
498                 cohd = list_entry(pos, struct coh901318_desc, node);
499                 left += coh901318_get_bytes_in_lli(cohd->lli);
500         }
501
502         spin_unlock_irqrestore(&cohc->lock, flags);
503
504         return left;
505 }
506
507 /*
508  * Pauses a transfer without losing data. Enables power save.
509  * Use this function in conjunction with coh901318_resume.
510  */
511 static void coh901318_pause(struct dma_chan *chan)
512 {
513         u32 val;
514         unsigned long flags;
515         struct coh901318_chan *cohc = to_coh901318_chan(chan);
516         int channel = cohc->id;
517         void __iomem *virtbase = cohc->base->virtbase;
518
519         spin_lock_irqsave(&cohc->lock, flags);
520
521         /* Disable channel in HW */
522         val = readl(virtbase + COH901318_CX_CFG +
523                     COH901318_CX_CFG_SPACING * channel);
524
525         /* Stopping infinit transfer */
526         if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
527             (val & COH901318_CX_CFG_CH_ENABLE))
528                 cohc->stopped = 1;
529
530
531         val &= ~COH901318_CX_CFG_CH_ENABLE;
532         /* Enable twice, HW bug work around */
533         writel(val, virtbase + COH901318_CX_CFG +
534                COH901318_CX_CFG_SPACING * channel);
535         writel(val, virtbase + COH901318_CX_CFG +
536                COH901318_CX_CFG_SPACING * channel);
537
538         /* Spin-wait for it to actually go inactive */
539         while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
540                      channel) & COH901318_CX_STAT_ACTIVE)
541                 cpu_relax();
542
543         /* Check if we stopped an active job */
544         if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
545                    channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
546                 cohc->stopped = 1;
547
548         enable_powersave(cohc);
549
550         spin_unlock_irqrestore(&cohc->lock, flags);
551 }
552
553 /* Resumes a transfer that has been stopped via 300_dma_stop(..).
554    Power save is handled.
555 */
556 static void coh901318_resume(struct dma_chan *chan)
557 {
558         u32 val;
559         unsigned long flags;
560         struct coh901318_chan *cohc = to_coh901318_chan(chan);
561         int channel = cohc->id;
562
563         spin_lock_irqsave(&cohc->lock, flags);
564
565         disable_powersave(cohc);
566
567         if (cohc->stopped) {
568                 /* Enable channel in HW */
569                 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
570                             COH901318_CX_CFG_SPACING * channel);
571
572                 val |= COH901318_CX_CFG_CH_ENABLE;
573
574                 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
575                        COH901318_CX_CFG_SPACING*channel);
576
577                 cohc->stopped = 0;
578         }
579
580         spin_unlock_irqrestore(&cohc->lock, flags);
581 }
582
583 bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
584 {
585         unsigned int ch_nr = (unsigned int) chan_id;
586
587         if (ch_nr == to_coh901318_chan(chan)->id)
588                 return true;
589
590         return false;
591 }
592 EXPORT_SYMBOL(coh901318_filter_id);
593
594 /*
595  * DMA channel allocation
596  */
597 static int coh901318_config(struct coh901318_chan *cohc,
598                             struct coh901318_params *param)
599 {
600         unsigned long flags;
601         const struct coh901318_params *p;
602         int channel = cohc->id;
603         void __iomem *virtbase = cohc->base->virtbase;
604
605         spin_lock_irqsave(&cohc->lock, flags);
606
607         if (param)
608                 p = param;
609         else
610                 p = &cohc->base->platform->chan_conf[channel].param;
611
612         /* Clear any pending BE or TC interrupt */
613         if (channel < 32) {
614                 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
615                 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
616         } else {
617                 writel(1 << (channel - 32), virtbase +
618                        COH901318_BE_INT_CLEAR2);
619                 writel(1 << (channel - 32), virtbase +
620                        COH901318_TC_INT_CLEAR2);
621         }
622
623         coh901318_set_conf(cohc, p->config);
624         coh901318_set_ctrl(cohc, p->ctrl_lli_last);
625
626         spin_unlock_irqrestore(&cohc->lock, flags);
627
628         return 0;
629 }
630
631 /* must lock when calling this function
632  * start queued jobs, if any
633  * TODO: start all queued jobs in one go
634  *
635  * Returns descriptor if queued job is started otherwise NULL.
636  * If the queue is empty NULL is returned.
637  */
638 static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
639 {
640         struct coh901318_desc *cohd;
641
642         /*
643          * start queued jobs, if any
644          * TODO: transmit all queued jobs in one go
645          */
646         cohd = coh901318_first_queued(cohc);
647
648         if (cohd != NULL) {
649                 /* Remove from queue */
650                 coh901318_desc_remove(cohd);
651                 /* initiate DMA job */
652                 cohc->busy = 1;
653
654                 coh901318_desc_submit(cohc, cohd);
655
656                 coh901318_prep_linked_list(cohc, cohd->lli);
657
658                 /* start dma job on this channel */
659                 coh901318_start(cohc);
660
661         }
662
663         return cohd;
664 }
665
666 /*
667  * This tasklet is called from the interrupt handler to
668  * handle each descriptor (DMA job) that is sent to a channel.
669  */
670 static void dma_tasklet(unsigned long data)
671 {
672         struct coh901318_chan *cohc = (struct coh901318_chan *) data;
673         struct coh901318_desc *cohd_fin;
674         unsigned long flags;
675         dma_async_tx_callback callback;
676         void *callback_param;
677
678         dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
679                  " nbr_active_done %ld\n", __func__,
680                  cohc->id, cohc->nbr_active_done);
681
682         spin_lock_irqsave(&cohc->lock, flags);
683
684         /* get first active descriptor entry from list */
685         cohd_fin = coh901318_first_active_get(cohc);
686
687         if (cohd_fin == NULL)
688                 goto err;
689
690         /* locate callback to client */
691         callback = cohd_fin->desc.callback;
692         callback_param = cohd_fin->desc.callback_param;
693
694         /* sign this job as completed on the channel */
695         cohc->completed = cohd_fin->desc.cookie;
696
697         /* release the lli allocation and remove the descriptor */
698         coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
699
700         /* return desc to free-list */
701         coh901318_desc_remove(cohd_fin);
702         coh901318_desc_free(cohc, cohd_fin);
703
704         spin_unlock_irqrestore(&cohc->lock, flags);
705
706         /* Call the callback when we're done */
707         if (callback)
708                 callback(callback_param);
709
710         spin_lock_irqsave(&cohc->lock, flags);
711
712         /*
713          * If another interrupt fired while the tasklet was scheduling,
714          * we don't get called twice, so we have this number of active
715          * counter that keep track of the number of IRQs expected to
716          * be handled for this channel. If there happen to be more than
717          * one IRQ to be ack:ed, we simply schedule this tasklet again.
718          */
719         cohc->nbr_active_done--;
720         if (cohc->nbr_active_done) {
721                 dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
722                         "came in while we were scheduling this tasklet\n");
723                 if (cohc_chan_conf(cohc)->priority_high)
724                         tasklet_hi_schedule(&cohc->tasklet);
725                 else
726                         tasklet_schedule(&cohc->tasklet);
727         }
728
729         spin_unlock_irqrestore(&cohc->lock, flags);
730
731         return;
732
733  err:
734         spin_unlock_irqrestore(&cohc->lock, flags);
735         dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
736 }
737
738
739 /* called from interrupt context */
740 static void dma_tc_handle(struct coh901318_chan *cohc)
741 {
742         /*
743          * If the channel is not allocated, then we shouldn't have
744          * any TC interrupts on it.
745          */
746         if (!cohc->allocated) {
747                 dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
748                         "unallocated channel\n");
749                 return;
750         }
751
752         spin_lock(&cohc->lock);
753
754         /*
755          * When we reach this point, at least one queue item
756          * should have been moved over from cohc->queue to
757          * cohc->active and run to completion, that is why we're
758          * getting a terminal count interrupt is it not?
759          * If you get this BUG() the most probable cause is that
760          * the individual nodes in the lli chain have IRQ enabled,
761          * so check your platform config for lli chain ctrl.
762          */
763         BUG_ON(list_empty(&cohc->active));
764
765         cohc->nbr_active_done++;
766
767         /*
768          * This attempt to take a job from cohc->queue, put it
769          * into cohc->active and start it.
770          */
771         if (coh901318_queue_start(cohc) == NULL)
772                 cohc->busy = 0;
773
774         spin_unlock(&cohc->lock);
775
776         /*
777          * This tasklet will remove items from cohc->active
778          * and thus terminates them.
779          */
780         if (cohc_chan_conf(cohc)->priority_high)
781                 tasklet_hi_schedule(&cohc->tasklet);
782         else
783                 tasklet_schedule(&cohc->tasklet);
784 }
785
786
787 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
788 {
789         u32 status1;
790         u32 status2;
791         int i;
792         int ch;
793         struct coh901318_base *base  = dev_id;
794         struct coh901318_chan *cohc;
795         void __iomem *virtbase = base->virtbase;
796
797         status1 = readl(virtbase + COH901318_INT_STATUS1);
798         status2 = readl(virtbase + COH901318_INT_STATUS2);
799
800         if (unlikely(status1 == 0 && status2 == 0)) {
801                 dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
802                 return IRQ_HANDLED;
803         }
804
805         /* TODO: consider handle IRQ in tasklet here to
806          *       minimize interrupt latency */
807
808         /* Check the first 32 DMA channels for IRQ */
809         while (status1) {
810                 /* Find first bit set, return as a number. */
811                 i = ffs(status1) - 1;
812                 ch = i;
813
814                 cohc = &base->chans[ch];
815                 spin_lock(&cohc->lock);
816
817                 /* Mask off this bit */
818                 status1 &= ~(1 << i);
819                 /* Check the individual channel bits */
820                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
821                         dev_crit(COHC_2_DEV(cohc),
822                                  "DMA bus error on channel %d!\n", ch);
823                         BUG_ON(1);
824                         /* Clear BE interrupt */
825                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
826                 } else {
827                         /* Caused by TC, really? */
828                         if (unlikely(!test_bit(i, virtbase +
829                                                COH901318_TC_INT_STATUS1))) {
830                                 dev_warn(COHC_2_DEV(cohc),
831                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
832                                 /* Clear TC interrupt */
833                                 BUG_ON(1);
834                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
835                         } else {
836                                 /* Enable powersave if transfer has finished */
837                                 if (!(readl(virtbase + COH901318_CX_STAT +
838                                             COH901318_CX_STAT_SPACING*ch) &
839                                       COH901318_CX_STAT_ENABLED)) {
840                                         enable_powersave(cohc);
841                                 }
842
843                                 /* Must clear TC interrupt before calling
844                                  * dma_tc_handle
845                                  * in case tc_handle initate a new dma job
846                                  */
847                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
848
849                                 dma_tc_handle(cohc);
850                         }
851                 }
852                 spin_unlock(&cohc->lock);
853         }
854
855         /* Check the remaining 32 DMA channels for IRQ */
856         while (status2) {
857                 /* Find first bit set, return as a number. */
858                 i = ffs(status2) - 1;
859                 ch = i + 32;
860                 cohc = &base->chans[ch];
861                 spin_lock(&cohc->lock);
862
863                 /* Mask off this bit */
864                 status2 &= ~(1 << i);
865                 /* Check the individual channel bits */
866                 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
867                         dev_crit(COHC_2_DEV(cohc),
868                                  "DMA bus error on channel %d!\n", ch);
869                         /* Clear BE interrupt */
870                         BUG_ON(1);
871                         __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
872                 } else {
873                         /* Caused by TC, really? */
874                         if (unlikely(!test_bit(i, virtbase +
875                                                COH901318_TC_INT_STATUS2))) {
876                                 dev_warn(COHC_2_DEV(cohc),
877                                          "ignoring interrupt not caused by terminal count on channel %d\n", ch);
878                                 /* Clear TC interrupt */
879                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
880                                 BUG_ON(1);
881                         } else {
882                                 /* Enable powersave if transfer has finished */
883                                 if (!(readl(virtbase + COH901318_CX_STAT +
884                                             COH901318_CX_STAT_SPACING*ch) &
885                                       COH901318_CX_STAT_ENABLED)) {
886                                         enable_powersave(cohc);
887                                 }
888                                 /* Must clear TC interrupt before calling
889                                  * dma_tc_handle
890                                  * in case tc_handle initate a new dma job
891                                  */
892                                 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
893
894                                 dma_tc_handle(cohc);
895                         }
896                 }
897                 spin_unlock(&cohc->lock);
898         }
899
900         return IRQ_HANDLED;
901 }
902
903 static int coh901318_alloc_chan_resources(struct dma_chan *chan)
904 {
905         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
906         unsigned long flags;
907
908         dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
909                  __func__, cohc->id);
910
911         if (chan->client_count > 1)
912                 return -EBUSY;
913
914         spin_lock_irqsave(&cohc->lock, flags);
915
916         coh901318_config(cohc, NULL);
917
918         cohc->allocated = 1;
919         cohc->completed = chan->cookie = 1;
920
921         spin_unlock_irqrestore(&cohc->lock, flags);
922
923         return 1;
924 }
925
926 static void
927 coh901318_free_chan_resources(struct dma_chan *chan)
928 {
929         struct coh901318_chan   *cohc = to_coh901318_chan(chan);
930         int channel = cohc->id;
931         unsigned long flags;
932
933         spin_lock_irqsave(&cohc->lock, flags);
934
935         /* Disable HW */
936         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
937                COH901318_CX_CFG_SPACING*channel);
938         writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
939                COH901318_CX_CTRL_SPACING*channel);
940
941         cohc->allocated = 0;
942
943         spin_unlock_irqrestore(&cohc->lock, flags);
944
945         chan->device->device_control(chan, DMA_TERMINATE_ALL);
946 }
947
948
949 static dma_cookie_t
950 coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
951 {
952         struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
953                                                    desc);
954         struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
955         unsigned long flags;
956
957         spin_lock_irqsave(&cohc->lock, flags);
958
959         tx->cookie = coh901318_assign_cookie(cohc, cohd);
960
961         coh901318_desc_queue(cohc, cohd);
962
963         spin_unlock_irqrestore(&cohc->lock, flags);
964
965         return tx->cookie;
966 }
967
968 static struct dma_async_tx_descriptor *
969 coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
970                       size_t size, unsigned long flags)
971 {
972         struct coh901318_lli *lli;
973         struct coh901318_desc *cohd;
974         unsigned long flg;
975         struct coh901318_chan *cohc = to_coh901318_chan(chan);
976         int lli_len;
977         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
978         int ret;
979
980         spin_lock_irqsave(&cohc->lock, flg);
981
982         dev_vdbg(COHC_2_DEV(cohc),
983                  "[%s] channel %d src 0x%x dest 0x%x size %d\n",
984                  __func__, cohc->id, src, dest, size);
985
986         if (flags & DMA_PREP_INTERRUPT)
987                 /* Trigger interrupt after last lli */
988                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
989
990         lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
991         if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
992                 lli_len++;
993
994         lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
995
996         if (lli == NULL)
997                 goto err;
998
999         ret = coh901318_lli_fill_memcpy(
1000                 &cohc->base->pool, lli, src, size, dest,
1001                 cohc_chan_param(cohc)->ctrl_lli_chained,
1002                 ctrl_last);
1003         if (ret)
1004                 goto err;
1005
1006         COH_DBG(coh901318_list_print(cohc, lli));
1007
1008         /* Pick a descriptor to handle this transfer */
1009         cohd = coh901318_desc_get(cohc);
1010         cohd->lli = lli;
1011         cohd->flags = flags;
1012         cohd->desc.tx_submit = coh901318_tx_submit;
1013
1014         spin_unlock_irqrestore(&cohc->lock, flg);
1015
1016         return &cohd->desc;
1017  err:
1018         spin_unlock_irqrestore(&cohc->lock, flg);
1019         return NULL;
1020 }
1021
1022 static struct dma_async_tx_descriptor *
1023 coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
1024                         unsigned int sg_len, enum dma_data_direction direction,
1025                         unsigned long flags)
1026 {
1027         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1028         struct coh901318_lli *lli;
1029         struct coh901318_desc *cohd;
1030         const struct coh901318_params *params;
1031         struct scatterlist *sg;
1032         int len = 0;
1033         int size;
1034         int i;
1035         u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
1036         u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
1037         u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
1038         u32 config;
1039         unsigned long flg;
1040         int ret;
1041
1042         if (!sgl)
1043                 goto out;
1044         if (sgl->length == 0)
1045                 goto out;
1046
1047         spin_lock_irqsave(&cohc->lock, flg);
1048
1049         dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
1050                  __func__, sg_len, direction);
1051
1052         if (flags & DMA_PREP_INTERRUPT)
1053                 /* Trigger interrupt after last lli */
1054                 ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
1055
1056         params = cohc_chan_param(cohc);
1057         config = params->config;
1058
1059         if (direction == DMA_TO_DEVICE) {
1060                 u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
1061                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
1062
1063                 config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
1064                 ctrl_chained |= tx_flags;
1065                 ctrl_last |= tx_flags;
1066                 ctrl |= tx_flags;
1067         } else if (direction == DMA_FROM_DEVICE) {
1068                 u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
1069                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
1070
1071                 config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
1072                 ctrl_chained |= rx_flags;
1073                 ctrl_last |= rx_flags;
1074                 ctrl |= rx_flags;
1075         } else
1076                 goto err_direction;
1077
1078         coh901318_set_conf(cohc, config);
1079
1080         /* The dma only supports transmitting packages up to
1081          * MAX_DMA_PACKET_SIZE. Calculate to total number of
1082          * dma elemts required to send the entire sg list
1083          */
1084         for_each_sg(sgl, sg, sg_len, i) {
1085                 unsigned int factor;
1086                 size = sg_dma_len(sg);
1087
1088                 if (size <= MAX_DMA_PACKET_SIZE) {
1089                         len++;
1090                         continue;
1091                 }
1092
1093                 factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
1094                 if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
1095                         factor++;
1096
1097                 len += factor;
1098         }
1099
1100         pr_debug("Allocate %d lli:s for this transfer\n", len);
1101         lli = coh901318_lli_alloc(&cohc->base->pool, len);
1102
1103         if (lli == NULL)
1104                 goto err_dma_alloc;
1105
1106         /* initiate allocated lli list */
1107         ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
1108                                     cohc_dev_addr(cohc),
1109                                     ctrl_chained,
1110                                     ctrl,
1111                                     ctrl_last,
1112                                     direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
1113         if (ret)
1114                 goto err_lli_fill;
1115
1116         COH_DBG(coh901318_list_print(cohc, lli));
1117
1118         /* Pick a descriptor to handle this transfer */
1119         cohd = coh901318_desc_get(cohc);
1120         cohd->dir = direction;
1121         cohd->flags = flags;
1122         cohd->desc.tx_submit = coh901318_tx_submit;
1123         cohd->lli = lli;
1124
1125         spin_unlock_irqrestore(&cohc->lock, flg);
1126
1127         return &cohd->desc;
1128  err_lli_fill:
1129  err_dma_alloc:
1130  err_direction:
1131         spin_unlock_irqrestore(&cohc->lock, flg);
1132  out:
1133         return NULL;
1134 }
1135
1136 static enum dma_status
1137 coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
1138                  struct dma_tx_state *txstate)
1139 {
1140         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1141         dma_cookie_t last_used;
1142         dma_cookie_t last_complete;
1143         int ret;
1144
1145         last_complete = cohc->completed;
1146         last_used = chan->cookie;
1147
1148         ret = dma_async_is_complete(cookie, last_complete, last_used);
1149
1150         dma_set_tx_state(txstate, last_complete, last_used,
1151                          coh901318_get_bytes_left(chan));
1152         if (ret == DMA_IN_PROGRESS && cohc->stopped)
1153                 ret = DMA_PAUSED;
1154
1155         return ret;
1156 }
1157
1158 static void
1159 coh901318_issue_pending(struct dma_chan *chan)
1160 {
1161         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1162         unsigned long flags;
1163
1164         spin_lock_irqsave(&cohc->lock, flags);
1165
1166         /*
1167          * Busy means that pending jobs are already being processed,
1168          * and then there is no point in starting the queue: the
1169          * terminal count interrupt on the channel will take the next
1170          * job on the queue and execute it anyway.
1171          */
1172         if (!cohc->busy)
1173                 coh901318_queue_start(cohc);
1174
1175         spin_unlock_irqrestore(&cohc->lock, flags);
1176 }
1177
1178 static int
1179 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd)
1180 {
1181         unsigned long flags;
1182         struct coh901318_chan *cohc = to_coh901318_chan(chan);
1183         struct coh901318_desc *cohd;
1184         void __iomem *virtbase = cohc->base->virtbase;
1185
1186         if (cmd == DMA_PAUSE) {
1187                 coh901318_pause(chan);
1188                 return 0;
1189         }
1190
1191         if (cmd == DMA_RESUME) {
1192                 coh901318_resume(chan);
1193                 return 0;
1194         }
1195
1196         if (cmd != DMA_TERMINATE_ALL)
1197                 return -ENXIO;
1198
1199         /* The remainder of this function terminates the transfer */
1200         coh901318_pause(chan);
1201         spin_lock_irqsave(&cohc->lock, flags);
1202
1203         /* Clear any pending BE or TC interrupt */
1204         if (cohc->id < 32) {
1205                 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
1206                 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
1207         } else {
1208                 writel(1 << (cohc->id - 32), virtbase +
1209                        COH901318_BE_INT_CLEAR2);
1210                 writel(1 << (cohc->id - 32), virtbase +
1211                        COH901318_TC_INT_CLEAR2);
1212         }
1213
1214         enable_powersave(cohc);
1215
1216         while ((cohd = coh901318_first_active_get(cohc))) {
1217                 /* release the lli allocation*/
1218                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1219
1220                 /* return desc to free-list */
1221                 coh901318_desc_remove(cohd);
1222                 coh901318_desc_free(cohc, cohd);
1223         }
1224
1225         while ((cohd = coh901318_first_queued(cohc))) {
1226                 /* release the lli allocation*/
1227                 coh901318_lli_free(&cohc->base->pool, &cohd->lli);
1228
1229                 /* return desc to free-list */
1230                 coh901318_desc_remove(cohd);
1231                 coh901318_desc_free(cohc, cohd);
1232         }
1233
1234
1235         cohc->nbr_active_done = 0;
1236         cohc->busy = 0;
1237
1238         spin_unlock_irqrestore(&cohc->lock, flags);
1239
1240         return 0;
1241 }
1242 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
1243                          struct coh901318_base *base)
1244 {
1245         int chans_i;
1246         int i = 0;
1247         struct coh901318_chan *cohc;
1248
1249         INIT_LIST_HEAD(&dma->channels);
1250
1251         for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
1252                 for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
1253                         cohc = &base->chans[i];
1254
1255                         cohc->base = base;
1256                         cohc->chan.device = dma;
1257                         cohc->id = i;
1258
1259                         /* TODO: do we really need this lock if only one
1260                          * client is connected to each channel?
1261                          */
1262
1263                         spin_lock_init(&cohc->lock);
1264
1265                         cohc->nbr_active_done = 0;
1266                         cohc->busy = 0;
1267                         INIT_LIST_HEAD(&cohc->free);
1268                         INIT_LIST_HEAD(&cohc->active);
1269                         INIT_LIST_HEAD(&cohc->queue);
1270
1271                         tasklet_init(&cohc->tasklet, dma_tasklet,
1272                                      (unsigned long) cohc);
1273
1274                         list_add_tail(&cohc->chan.device_node,
1275                                       &dma->channels);
1276                 }
1277         }
1278 }
1279
1280 static int __init coh901318_probe(struct platform_device *pdev)
1281 {
1282         int err = 0;
1283         struct coh901318_platform *pdata;
1284         struct coh901318_base *base;
1285         int irq;
1286         struct resource *io;
1287
1288         io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1289         if (!io)
1290                 goto err_get_resource;
1291
1292         /* Map DMA controller registers to virtual memory */
1293         if (request_mem_region(io->start,
1294                                resource_size(io),
1295                                pdev->dev.driver->name) == NULL) {
1296                 err = -EBUSY;
1297                 goto err_request_mem;
1298         }
1299
1300         pdata = pdev->dev.platform_data;
1301         if (!pdata)
1302                 goto err_no_platformdata;
1303
1304         base = kmalloc(ALIGN(sizeof(struct coh901318_base), 4) +
1305                        pdata->max_channels *
1306                        sizeof(struct coh901318_chan),
1307                        GFP_KERNEL);
1308         if (!base)
1309                 goto err_alloc_coh_dma_channels;
1310
1311         base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
1312
1313         base->virtbase = ioremap(io->start, resource_size(io));
1314         if (!base->virtbase) {
1315                 err = -ENOMEM;
1316                 goto err_no_ioremap;
1317         }
1318
1319         base->dev = &pdev->dev;
1320         base->platform = pdata;
1321         spin_lock_init(&base->pm.lock);
1322         base->pm.started_channels = 0;
1323
1324         COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
1325
1326         platform_set_drvdata(pdev, base);
1327
1328         irq = platform_get_irq(pdev, 0);
1329         if (irq < 0)
1330                 goto err_no_irq;
1331
1332         err = request_irq(irq, dma_irq_handler, IRQF_DISABLED,
1333                           "coh901318", base);
1334         if (err) {
1335                 dev_crit(&pdev->dev,
1336                          "Cannot allocate IRQ for DMA controller!\n");
1337                 goto err_request_irq;
1338         }
1339
1340         err = coh901318_pool_create(&base->pool, &pdev->dev,
1341                                     sizeof(struct coh901318_lli),
1342                                     32);
1343         if (err)
1344                 goto err_pool_create;
1345
1346         /* init channels for device transfers */
1347         coh901318_base_init(&base->dma_slave,  base->platform->chans_slave,
1348                             base);
1349
1350         dma_cap_zero(base->dma_slave.cap_mask);
1351         dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
1352
1353         base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1354         base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
1355         base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
1356         base->dma_slave.device_tx_status = coh901318_tx_status;
1357         base->dma_slave.device_issue_pending = coh901318_issue_pending;
1358         base->dma_slave.device_control = coh901318_control;
1359         base->dma_slave.dev = &pdev->dev;
1360
1361         err = dma_async_device_register(&base->dma_slave);
1362
1363         if (err)
1364                 goto err_register_slave;
1365
1366         /* init channels for memcpy */
1367         coh901318_base_init(&base->dma_memcpy, base->platform->chans_memcpy,
1368                             base);
1369
1370         dma_cap_zero(base->dma_memcpy.cap_mask);
1371         dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
1372
1373         base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
1374         base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
1375         base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
1376         base->dma_memcpy.device_tx_status = coh901318_tx_status;
1377         base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
1378         base->dma_memcpy.device_control = coh901318_control;
1379         base->dma_memcpy.dev = &pdev->dev;
1380         /*
1381          * This controller can only access address at even 32bit boundaries,
1382          * i.e. 2^2
1383          */
1384         base->dma_memcpy.copy_align = 2;
1385         err = dma_async_device_register(&base->dma_memcpy);
1386
1387         if (err)
1388                 goto err_register_memcpy;
1389
1390         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
1391                 (u32) base->virtbase);
1392
1393         return err;
1394
1395  err_register_memcpy:
1396         dma_async_device_unregister(&base->dma_slave);
1397  err_register_slave:
1398         coh901318_pool_destroy(&base->pool);
1399  err_pool_create:
1400         free_irq(platform_get_irq(pdev, 0), base);
1401  err_request_irq:
1402  err_no_irq:
1403         iounmap(base->virtbase);
1404  err_no_ioremap:
1405         kfree(base);
1406  err_alloc_coh_dma_channels:
1407  err_no_platformdata:
1408         release_mem_region(pdev->resource->start,
1409                            resource_size(pdev->resource));
1410  err_request_mem:
1411  err_get_resource:
1412         return err;
1413 }
1414
1415 static int __exit coh901318_remove(struct platform_device *pdev)
1416 {
1417         struct coh901318_base *base = platform_get_drvdata(pdev);
1418
1419         dma_async_device_unregister(&base->dma_memcpy);
1420         dma_async_device_unregister(&base->dma_slave);
1421         coh901318_pool_destroy(&base->pool);
1422         free_irq(platform_get_irq(pdev, 0), base);
1423         iounmap(base->virtbase);
1424         kfree(base);
1425         release_mem_region(pdev->resource->start,
1426                            resource_size(pdev->resource));
1427         return 0;
1428 }
1429
1430
1431 static struct platform_driver coh901318_driver = {
1432         .remove = __exit_p(coh901318_remove),
1433         .driver = {
1434                 .name   = "coh901318",
1435         },
1436 };
1437
1438 int __init coh901318_init(void)
1439 {
1440         return platform_driver_probe(&coh901318_driver, coh901318_probe);
1441 }
1442 subsys_initcall(coh901318_init);
1443
1444 void __exit coh901318_exit(void)
1445 {
1446         platform_driver_unregister(&coh901318_driver);
1447 }
1448 module_exit(coh901318_exit);
1449
1450 MODULE_LICENSE("GPL");
1451 MODULE_AUTHOR("Per Friden");