ARM: PL08x: prevent dma_set_runtime_config() reconfiguring memcpy channels
[linux-2.6.git] / drivers / dma / amba-pl08x.c
1 /*
2  * Copyright (c) 2006 ARM Ltd.
3  * Copyright (c) 2010 ST-Ericsson SA
4  *
5  * Author: Peter Pearse <peter.pearse@arm.com>
6  * Author: Linus Walleij <linus.walleij@stericsson.com>
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License as published by the Free
10  * Software Foundation; either version 2 of the License, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program; if not, write to the Free Software Foundation, Inc., 59
20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
21  *
22  * The full GNU General Public License is in this distribution in the
23  * file called COPYING.
24  *
25  * Documentation: ARM DDI 0196G == PL080
26  * Documentation: ARM DDI 0218E == PL081
27  *
28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
29  * any channel.
30  *
31  * The PL080 has 8 channels available for simultaneous use, and the PL081
32  * has only two channels. So on these DMA controllers the number of channels
33  * and the number of incoming DMA signals are two totally different things.
34  * It is usually not possible to theoretically handle all physical signals,
35  * so a multiplexing scheme with possible denial of use is necessary.
36  *
37  * The PL080 has a dual bus master, PL081 has a single master.
38  *
39  * Memory to peripheral transfer may be visualized as
40  *      Get data from memory to DMAC
41  *      Until no data left
42  *              On burst request from peripheral
43  *                      Destination burst from DMAC to peripheral
44  *                      Clear burst request
45  *      Raise terminal count interrupt
46  *
47  * For peripherals with a FIFO:
48  * Source      burst size == half the depth of the peripheral FIFO
49  * Destination burst size == the depth of the peripheral FIFO
50  *
51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
52  * signals, the DMA controller will simply facilitate its AHB master.)
53  *
54  * ASSUMES default (little) endianness for DMA transfers
55  *
56  * The PL08x has two flow control settings:
57  *  - DMAC flow control: the transfer size defines the number of transfers
58  *    which occur for the current LLI entry, and the DMAC raises TC at the
59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
60  *    to both the BREQ and SREQ signals (contrary to documented),
61  *    transferring data if either is active.  The LBREQ and LSREQ signals
62  *    are ignored.
63  *
64  *  - Peripheral flow control: the transfer size is ignored (and should be
65  *    zero).  The data is transferred from the current LLI entry, until
66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
67  *    will then move to the next LLI entry.
68  *
69  * Only the former works sanely with scatter lists, so we only implement
70  * the DMAC flow control method.  However, peripherals which use the LBREQ
71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72  * these hardware restrictions prevents them from using scatter DMA.
73  *
74  * Global TODO:
75  * - Break out common code from arch/arm/mach-s3c64xx and share
76  */
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/dmapool.h>
83 #include <linux/dmaengine.h>
84 #include <linux/amba/bus.h>
85 #include <linux/amba/pl08x.h>
86 #include <linux/debugfs.h>
87 #include <linux/seq_file.h>
88
89 #include <asm/hardware/pl080.h>
90
91 #define DRIVER_NAME     "pl08xdmac"
92
93 /**
94  * struct vendor_data - vendor-specific config parameters
95  * for PL08x derivatives
96  * @channels: the number of channels available in this variant
97  * @dualmaster: whether this version supports dual AHB masters
98  * or not.
99  */
100 struct vendor_data {
101         u8 channels;
102         bool dualmaster;
103 };
104
105 /*
106  * PL08X private data structures
107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
108  * start & end do not - their bus bit info is in cctl.  Also note that these
109  * are fixed 32-bit quantities.
110  */
111 struct pl08x_lli {
112         u32 src;
113         u32 dst;
114         u32 lli;
115         u32 cctl;
116 };
117
118 /**
119  * struct pl08x_driver_data - the local state holder for the PL08x
120  * @slave: slave engine for this instance
121  * @memcpy: memcpy engine for this instance
122  * @base: virtual memory base (remapped) for the PL08x
123  * @adev: the corresponding AMBA (PrimeCell) bus entry
124  * @vd: vendor data for this PL08x variant
125  * @pd: platform data passed in from the platform/machine
126  * @phy_chans: array of data for the physical channels
127  * @pool: a pool for the LLI descriptors
128  * @pool_ctr: counter of LLIs in the pool
129  * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
130  * @mem_buses: set to indicate memory transfers on AHB2.
131  * @lock: a spinlock for this struct
132  */
133 struct pl08x_driver_data {
134         struct dma_device slave;
135         struct dma_device memcpy;
136         void __iomem *base;
137         struct amba_device *adev;
138         const struct vendor_data *vd;
139         struct pl08x_platform_data *pd;
140         struct pl08x_phy_chan *phy_chans;
141         struct dma_pool *pool;
142         int pool_ctr;
143         u8 lli_buses;
144         u8 mem_buses;
145         spinlock_t lock;
146 };
147
148 /*
149  * PL08X specific defines
150  */
151
152 /*
153  * Memory boundaries: the manual for PL08x says that the controller
154  * cannot read past a 1KiB boundary, so these defines are used to
155  * create transfer LLIs that do not cross such boundaries.
156  */
157 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
158 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
159
160 /* Minimum period between work queue runs */
161 #define PL08X_WQ_PERIODMIN      20
162
163 /* Size (bytes) of each LLI buffer allocated for one transfer */
164 # define PL08X_LLI_TSFR_SIZE    0x2000
165
166 /* Maximum times we call dma_pool_alloc on this pool without freeing */
167 #define PL08X_MAX_ALLOCS        0x40
168 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
169 #define PL08X_ALIGN             8
170
171 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
172 {
173         return container_of(chan, struct pl08x_dma_chan, chan);
174 }
175
176 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
177 {
178         return container_of(tx, struct pl08x_txd, tx);
179 }
180
181 /*
182  * Physical channel handling
183  */
184
185 /* Whether a certain channel is busy or not */
186 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
187 {
188         unsigned int val;
189
190         val = readl(ch->base + PL080_CH_CONFIG);
191         return val & PL080_CONFIG_ACTIVE;
192 }
193
194 /*
195  * Set the initial DMA register values i.e. those for the first LLI
196  * The next LLI pointer and the configuration interrupt bit have
197  * been set when the LLIs were constructed.  Poke them into the hardware
198  * and start the transfer.
199  */
200 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
201         struct pl08x_txd *txd)
202 {
203         struct pl08x_driver_data *pl08x = plchan->host;
204         struct pl08x_phy_chan *phychan = plchan->phychan;
205         struct pl08x_lli *lli = &txd->llis_va[0];
206         u32 val;
207
208         plchan->at = txd;
209
210         /* Wait for channel inactive */
211         while (pl08x_phy_channel_busy(phychan))
212                 cpu_relax();
213
214         dev_vdbg(&pl08x->adev->dev,
215                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
216                 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
217                 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
218                 txd->ccfg);
219
220         writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
221         writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
222         writel(lli->lli, phychan->base + PL080_CH_LLI);
223         writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
224         writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
225
226         /* Enable the DMA channel */
227         /* Do not access config register until channel shows as disabled */
228         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
229                 cpu_relax();
230
231         /* Do not access config register until channel shows as inactive */
232         val = readl(phychan->base + PL080_CH_CONFIG);
233         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
234                 val = readl(phychan->base + PL080_CH_CONFIG);
235
236         writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
237 }
238
239 /*
240  * Overall DMAC remains enabled always.
241  *
242  * Disabling individual channels could lose data.
243  *
244  * Disable the peripheral DMA after disabling the DMAC
245  * in order to allow the DMAC FIFO to drain, and
246  * hence allow the channel to show inactive
247  *
248  */
249 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
250 {
251         u32 val;
252
253         /* Set the HALT bit and wait for the FIFO to drain */
254         val = readl(ch->base + PL080_CH_CONFIG);
255         val |= PL080_CONFIG_HALT;
256         writel(val, ch->base + PL080_CH_CONFIG);
257
258         /* Wait for channel inactive */
259         while (pl08x_phy_channel_busy(ch))
260                 cpu_relax();
261 }
262
263 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
264 {
265         u32 val;
266
267         /* Clear the HALT bit */
268         val = readl(ch->base + PL080_CH_CONFIG);
269         val &= ~PL080_CONFIG_HALT;
270         writel(val, ch->base + PL080_CH_CONFIG);
271 }
272
273
274 /* Stops the channel */
275 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
276 {
277         u32 val;
278
279         pl08x_pause_phy_chan(ch);
280
281         /* Disable channel */
282         val = readl(ch->base + PL080_CH_CONFIG);
283         val &= ~PL080_CONFIG_ENABLE;
284         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
285         val &= ~PL080_CONFIG_TC_IRQ_MASK;
286         writel(val, ch->base + PL080_CH_CONFIG);
287 }
288
289 static inline u32 get_bytes_in_cctl(u32 cctl)
290 {
291         /* The source width defines the number of bytes */
292         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
293
294         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
295         case PL080_WIDTH_8BIT:
296                 break;
297         case PL080_WIDTH_16BIT:
298                 bytes *= 2;
299                 break;
300         case PL080_WIDTH_32BIT:
301                 bytes *= 4;
302                 break;
303         }
304         return bytes;
305 }
306
307 /* The channel should be paused when calling this */
308 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
309 {
310         struct pl08x_phy_chan *ch;
311         struct pl08x_txd *txd;
312         unsigned long flags;
313         size_t bytes = 0;
314
315         spin_lock_irqsave(&plchan->lock, flags);
316         ch = plchan->phychan;
317         txd = plchan->at;
318
319         /*
320          * Follow the LLIs to get the number of remaining
321          * bytes in the currently active transaction.
322          */
323         if (ch && txd) {
324                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
325
326                 /* First get the remaining bytes in the active transfer */
327                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
328
329                 if (clli) {
330                         struct pl08x_lli *llis_va = txd->llis_va;
331                         dma_addr_t llis_bus = txd->llis_bus;
332                         int index;
333
334                         BUG_ON(clli < llis_bus || clli >= llis_bus +
335                                 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
336
337                         /*
338                          * Locate the next LLI - as this is an array,
339                          * it's simple maths to find.
340                          */
341                         index = (clli - llis_bus) / sizeof(struct pl08x_lli);
342
343                         for (; index < MAX_NUM_TSFR_LLIS; index++) {
344                                 bytes += get_bytes_in_cctl(llis_va[index].cctl);
345
346                                 /*
347                                  * A LLI pointer of 0 terminates the LLI list
348                                  */
349                                 if (!llis_va[index].lli)
350                                         break;
351                         }
352                 }
353         }
354
355         /* Sum up all queued transactions */
356         if (!list_empty(&plchan->pend_list)) {
357                 struct pl08x_txd *txdi;
358                 list_for_each_entry(txdi, &plchan->pend_list, node) {
359                         bytes += txdi->len;
360                 }
361         }
362
363         spin_unlock_irqrestore(&plchan->lock, flags);
364
365         return bytes;
366 }
367
368 /*
369  * Allocate a physical channel for a virtual channel
370  */
371 static struct pl08x_phy_chan *
372 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
373                       struct pl08x_dma_chan *virt_chan)
374 {
375         struct pl08x_phy_chan *ch = NULL;
376         unsigned long flags;
377         int i;
378
379         /*
380          * Try to locate a physical channel to be used for
381          * this transfer. If all are taken return NULL and
382          * the requester will have to cope by using some fallback
383          * PIO mode or retrying later.
384          */
385         for (i = 0; i < pl08x->vd->channels; i++) {
386                 ch = &pl08x->phy_chans[i];
387
388                 spin_lock_irqsave(&ch->lock, flags);
389
390                 if (!ch->serving) {
391                         ch->serving = virt_chan;
392                         ch->signal = -1;
393                         spin_unlock_irqrestore(&ch->lock, flags);
394                         break;
395                 }
396
397                 spin_unlock_irqrestore(&ch->lock, flags);
398         }
399
400         if (i == pl08x->vd->channels) {
401                 /* No physical channel available, cope with it */
402                 return NULL;
403         }
404
405         return ch;
406 }
407
408 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
409                                          struct pl08x_phy_chan *ch)
410 {
411         unsigned long flags;
412
413         /* Stop the channel and clear its interrupts */
414         pl08x_stop_phy_chan(ch);
415         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
416         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
417
418         /* Mark it as free */
419         spin_lock_irqsave(&ch->lock, flags);
420         ch->serving = NULL;
421         spin_unlock_irqrestore(&ch->lock, flags);
422 }
423
424 /*
425  * LLI handling
426  */
427
428 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
429 {
430         switch (coded) {
431         case PL080_WIDTH_8BIT:
432                 return 1;
433         case PL080_WIDTH_16BIT:
434                 return 2;
435         case PL080_WIDTH_32BIT:
436                 return 4;
437         default:
438                 break;
439         }
440         BUG();
441         return 0;
442 }
443
444 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
445                                   size_t tsize)
446 {
447         u32 retbits = cctl;
448
449         /* Remove all src, dst and transfer size bits */
450         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
451         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
452         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
453
454         /* Then set the bits according to the parameters */
455         switch (srcwidth) {
456         case 1:
457                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
458                 break;
459         case 2:
460                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
461                 break;
462         case 4:
463                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
464                 break;
465         default:
466                 BUG();
467                 break;
468         }
469
470         switch (dstwidth) {
471         case 1:
472                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
473                 break;
474         case 2:
475                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
476                 break;
477         case 4:
478                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
479                 break;
480         default:
481                 BUG();
482                 break;
483         }
484
485         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
486         return retbits;
487 }
488
489 struct pl08x_lli_build_data {
490         struct pl08x_txd *txd;
491         struct pl08x_driver_data *pl08x;
492         struct pl08x_bus_data srcbus;
493         struct pl08x_bus_data dstbus;
494         size_t remainder;
495 };
496
497 /*
498  * Autoselect a master bus to use for the transfer
499  * this prefers the destination bus if both available
500  * if fixed address on one bus the other will be chosen
501  */
502 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
503         struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
504 {
505         if (!(cctl & PL080_CONTROL_DST_INCR)) {
506                 *mbus = &bd->srcbus;
507                 *sbus = &bd->dstbus;
508         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
509                 *mbus = &bd->dstbus;
510                 *sbus = &bd->srcbus;
511         } else {
512                 if (bd->dstbus.buswidth == 4) {
513                         *mbus = &bd->dstbus;
514                         *sbus = &bd->srcbus;
515                 } else if (bd->srcbus.buswidth == 4) {
516                         *mbus = &bd->srcbus;
517                         *sbus = &bd->dstbus;
518                 } else if (bd->dstbus.buswidth == 2) {
519                         *mbus = &bd->dstbus;
520                         *sbus = &bd->srcbus;
521                 } else if (bd->srcbus.buswidth == 2) {
522                         *mbus = &bd->srcbus;
523                         *sbus = &bd->dstbus;
524                 } else {
525                         /* bd->srcbus.buswidth == 1 */
526                         *mbus = &bd->dstbus;
527                         *sbus = &bd->srcbus;
528                 }
529         }
530 }
531
532 /*
533  * Fills in one LLI for a certain transfer descriptor
534  * and advance the counter
535  */
536 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
537         int num_llis, int len, u32 cctl)
538 {
539         struct pl08x_lli *llis_va = bd->txd->llis_va;
540         dma_addr_t llis_bus = bd->txd->llis_bus;
541
542         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
543
544         llis_va[num_llis].cctl = cctl;
545         llis_va[num_llis].src = bd->srcbus.addr;
546         llis_va[num_llis].dst = bd->dstbus.addr;
547         llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
548         if (bd->pl08x->lli_buses & PL08X_AHB2)
549                 llis_va[num_llis].lli |= PL080_LLI_LM_AHB2;
550
551         if (cctl & PL080_CONTROL_SRC_INCR)
552                 bd->srcbus.addr += len;
553         if (cctl & PL080_CONTROL_DST_INCR)
554                 bd->dstbus.addr += len;
555
556         BUG_ON(bd->remainder < len);
557
558         bd->remainder -= len;
559 }
560
561 /*
562  * Return number of bytes to fill to boundary, or len.
563  * This calculation works for any value of addr.
564  */
565 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
566 {
567         size_t boundary_len = PL08X_BOUNDARY_SIZE -
568                         (addr & (PL08X_BOUNDARY_SIZE - 1));
569
570         return min(boundary_len, len);
571 }
572
573 /*
574  * This fills in the table of LLIs for the transfer descriptor
575  * Note that we assume we never have to change the burst sizes
576  * Return 0 for error
577  */
578 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
579                               struct pl08x_txd *txd)
580 {
581         struct pl08x_bus_data *mbus, *sbus;
582         struct pl08x_lli_build_data bd;
583         int num_llis = 0;
584         u32 cctl;
585         size_t max_bytes_per_lli;
586         size_t total_bytes = 0;
587         struct pl08x_lli *llis_va;
588
589         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
590                                       &txd->llis_bus);
591         if (!txd->llis_va) {
592                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
593                 return 0;
594         }
595
596         pl08x->pool_ctr++;
597
598         /* Get the default CCTL */
599         cctl = txd->cctl;
600
601         bd.txd = txd;
602         bd.pl08x = pl08x;
603         bd.srcbus.addr = txd->src_addr;
604         bd.dstbus.addr = txd->dst_addr;
605
606         /* Find maximum width of the source bus */
607         bd.srcbus.maxwidth =
608                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
609                                        PL080_CONTROL_SWIDTH_SHIFT);
610
611         /* Find maximum width of the destination bus */
612         bd.dstbus.maxwidth =
613                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
614                                        PL080_CONTROL_DWIDTH_SHIFT);
615
616         /* Set up the bus widths to the maximum */
617         bd.srcbus.buswidth = bd.srcbus.maxwidth;
618         bd.dstbus.buswidth = bd.dstbus.maxwidth;
619         dev_vdbg(&pl08x->adev->dev,
620                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
621                  __func__, bd.srcbus.buswidth, bd.dstbus.buswidth);
622
623
624         /*
625          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
626          */
627         max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
628                 PL080_CONTROL_TRANSFER_SIZE_MASK;
629         dev_vdbg(&pl08x->adev->dev,
630                  "%s max bytes per lli = %zu\n",
631                  __func__, max_bytes_per_lli);
632
633         /* We need to count this down to zero */
634         bd.remainder = txd->len;
635         dev_vdbg(&pl08x->adev->dev,
636                  "%s remainder = %zu\n",
637                  __func__, bd.remainder);
638
639         /*
640          * Choose bus to align to
641          * - prefers destination bus if both available
642          * - if fixed address on one bus chooses other
643          * - modifies cctl to choose an appropriate master
644          */
645         pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
646
647         if (txd->len < mbus->buswidth) {
648                 /*
649                  * Less than a bus width available
650                  * - send as single bytes
651                  */
652                 while (bd.remainder) {
653                         dev_vdbg(&pl08x->adev->dev,
654                                  "%s single byte LLIs for a transfer of "
655                                  "less than a bus width (remain 0x%08x)\n",
656                                  __func__, bd.remainder);
657                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
658                         pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
659                         total_bytes++;
660                 }
661         } else {
662                 /*
663                  *  Make one byte LLIs until master bus is aligned
664                  *  - slave will then be aligned also
665                  */
666                 while ((mbus->addr) % (mbus->buswidth)) {
667                         dev_vdbg(&pl08x->adev->dev,
668                                 "%s adjustment lli for less than bus width "
669                                  "(remain 0x%08x)\n",
670                                  __func__, bd.remainder);
671                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
672                         pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
673                         total_bytes++;
674                 }
675
676                 /*
677                  *  Master now aligned
678                  * - if slave is not then we must set its width down
679                  */
680                 if (sbus->addr % sbus->buswidth) {
681                         dev_dbg(&pl08x->adev->dev,
682                                 "%s set down bus width to one byte\n",
683                                  __func__);
684
685                         sbus->buswidth = 1;
686                 }
687
688                 /*
689                  * Make largest possible LLIs until less than one bus
690                  * width left
691                  */
692                 while (bd.remainder > (mbus->buswidth - 1)) {
693                         size_t lli_len, target_len, tsize, odd_bytes;
694
695                         /*
696                          * If enough left try to send max possible,
697                          * otherwise try to send the remainder
698                          */
699                         target_len = min(bd.remainder, max_bytes_per_lli);
700
701                         /*
702                          * Set bus lengths for incrementing buses to the
703                          * number of bytes which fill to next memory boundary,
704                          * limiting on the target length calculated above.
705                          */
706                         if (cctl & PL080_CONTROL_SRC_INCR)
707                                 bd.srcbus.fill_bytes =
708                                         pl08x_pre_boundary(bd.srcbus.addr,
709                                                 target_len);
710                         else
711                                 bd.srcbus.fill_bytes = target_len;
712
713                         if (cctl & PL080_CONTROL_DST_INCR)
714                                 bd.dstbus.fill_bytes =
715                                         pl08x_pre_boundary(bd.dstbus.addr,
716                                                 target_len);
717                         else
718                                 bd.dstbus.fill_bytes = target_len;
719
720                         /* Find the nearest */
721                         lli_len = min(bd.srcbus.fill_bytes,
722                                       bd.dstbus.fill_bytes);
723
724                         BUG_ON(lli_len > bd.remainder);
725
726                         if (lli_len <= 0) {
727                                 dev_err(&pl08x->adev->dev,
728                                         "%s lli_len is %zu, <= 0\n",
729                                                 __func__, lli_len);
730                                 return 0;
731                         }
732
733                         if (lli_len == target_len) {
734                                 /*
735                                  * Can send what we wanted
736                                  */
737                                 /*
738                                  *  Maintain alignment
739                                  */
740                                 lli_len = (lli_len/mbus->buswidth) *
741                                                         mbus->buswidth;
742                                 odd_bytes = 0;
743                         } else {
744                                 /*
745                                  * So now we know how many bytes to transfer
746                                  * to get to the nearest boundary
747                                  * The next LLI will past the boundary
748                                  * - however we may be working to a boundary
749                                  *   on the slave bus
750                                  *   We need to ensure the master stays aligned
751                                  */
752                                 odd_bytes = lli_len % mbus->buswidth;
753                                 /*
754                                  * - and that we are working in multiples
755                                  *   of the bus widths
756                                  */
757                                 lli_len -= odd_bytes;
758
759                         }
760
761                         if (lli_len) {
762                                 /*
763                                  * Check against minimum bus alignment:
764                                  * Calculate actual transfer size in relation
765                                  * to bus width an get a maximum remainder of
766                                  * the smallest bus width - 1
767                                  */
768                                 /* FIXME: use round_down()? */
769                                 tsize = lli_len / min(mbus->buswidth,
770                                                       sbus->buswidth);
771                                 lli_len = tsize * min(mbus->buswidth,
772                                                       sbus->buswidth);
773
774                                 if (target_len != lli_len) {
775                                         dev_vdbg(&pl08x->adev->dev,
776                                         "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
777                                         __func__, target_len, lli_len, txd->len);
778                                 }
779
780                                 cctl = pl08x_cctl_bits(cctl,
781                                                        bd.srcbus.buswidth,
782                                                        bd.dstbus.buswidth,
783                                                        tsize);
784
785                                 dev_vdbg(&pl08x->adev->dev,
786                                         "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
787                                         __func__, lli_len, bd.remainder);
788                                 pl08x_fill_lli_for_desc(&bd, num_llis++,
789                                         lli_len, cctl);
790                                 total_bytes += lli_len;
791                         }
792
793
794                         if (odd_bytes) {
795                                 /*
796                                  * Creep past the boundary,
797                                  * maintaining master alignment
798                                  */
799                                 int j;
800                                 for (j = 0; (j < mbus->buswidth)
801                                                 && (bd.remainder); j++) {
802                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
803                                         dev_vdbg(&pl08x->adev->dev,
804                                                 "%s align with boundary, single byte (remain 0x%08zx)\n",
805                                                 __func__, bd.remainder);
806                                         pl08x_fill_lli_for_desc(&bd,
807                                                 num_llis++, 1, cctl);
808                                         total_bytes++;
809                                 }
810                         }
811                 }
812
813                 /*
814                  * Send any odd bytes
815                  */
816                 while (bd.remainder) {
817                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
818                         dev_vdbg(&pl08x->adev->dev,
819                                 "%s align with boundary, single odd byte (remain %zu)\n",
820                                 __func__, bd.remainder);
821                         pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
822                         total_bytes++;
823                 }
824         }
825         if (total_bytes != txd->len) {
826                 dev_err(&pl08x->adev->dev,
827                         "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
828                         __func__, total_bytes, txd->len);
829                 return 0;
830         }
831
832         if (num_llis >= MAX_NUM_TSFR_LLIS) {
833                 dev_err(&pl08x->adev->dev,
834                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
835                         __func__, (u32) MAX_NUM_TSFR_LLIS);
836                 return 0;
837         }
838
839         llis_va = txd->llis_va;
840         /*
841          * The final LLI terminates the LLI.
842          */
843         llis_va[num_llis - 1].lli = 0;
844         /*
845          * The final LLI element shall also fire an interrupt
846          */
847         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
848
849 #ifdef VERBOSE_DEBUG
850         {
851                 int i;
852
853                 for (i = 0; i < num_llis; i++) {
854                         dev_vdbg(&pl08x->adev->dev,
855                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
856                                  i,
857                                  &llis_va[i],
858                                  llis_va[i].src,
859                                  llis_va[i].dst,
860                                  llis_va[i].cctl,
861                                  llis_va[i].lli
862                                 );
863                 }
864         }
865 #endif
866
867         return num_llis;
868 }
869
870 /* You should call this with the struct pl08x lock held */
871 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
872                            struct pl08x_txd *txd)
873 {
874         /* Free the LLI */
875         dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
876
877         pl08x->pool_ctr--;
878
879         kfree(txd);
880 }
881
882 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
883                                 struct pl08x_dma_chan *plchan)
884 {
885         struct pl08x_txd *txdi = NULL;
886         struct pl08x_txd *next;
887
888         if (!list_empty(&plchan->pend_list)) {
889                 list_for_each_entry_safe(txdi,
890                                          next, &plchan->pend_list, node) {
891                         list_del(&txdi->node);
892                         pl08x_free_txd(pl08x, txdi);
893                 }
894
895         }
896 }
897
898 /*
899  * The DMA ENGINE API
900  */
901 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
902 {
903         return 0;
904 }
905
906 static void pl08x_free_chan_resources(struct dma_chan *chan)
907 {
908 }
909
910 /*
911  * This should be called with the channel plchan->lock held
912  */
913 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
914                             struct pl08x_txd *txd)
915 {
916         struct pl08x_driver_data *pl08x = plchan->host;
917         struct pl08x_phy_chan *ch;
918         int ret;
919
920         /* Check if we already have a channel */
921         if (plchan->phychan)
922                 return 0;
923
924         ch = pl08x_get_phy_channel(pl08x, plchan);
925         if (!ch) {
926                 /* No physical channel available, cope with it */
927                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
928                 return -EBUSY;
929         }
930
931         /*
932          * OK we have a physical channel: for memcpy() this is all we
933          * need, but for slaves the physical signals may be muxed!
934          * Can the platform allow us to use this channel?
935          */
936         if (plchan->slave &&
937             ch->signal < 0 &&
938             pl08x->pd->get_signal) {
939                 ret = pl08x->pd->get_signal(plchan);
940                 if (ret < 0) {
941                         dev_dbg(&pl08x->adev->dev,
942                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
943                                 ch->id, plchan->name);
944                         /* Release physical channel & return */
945                         pl08x_put_phy_channel(pl08x, ch);
946                         return -EBUSY;
947                 }
948                 ch->signal = ret;
949
950                 /* Assign the flow control signal to this channel */
951                 if (txd->direction == DMA_TO_DEVICE)
952                         txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
953                 else if (txd->direction == DMA_FROM_DEVICE)
954                         txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
955         }
956
957         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
958                  ch->id,
959                  ch->signal,
960                  plchan->name);
961
962         plchan->phychan_hold++;
963         plchan->phychan = ch;
964
965         return 0;
966 }
967
968 static void release_phy_channel(struct pl08x_dma_chan *plchan)
969 {
970         struct pl08x_driver_data *pl08x = plchan->host;
971
972         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
973                 pl08x->pd->put_signal(plchan);
974                 plchan->phychan->signal = -1;
975         }
976         pl08x_put_phy_channel(pl08x, plchan->phychan);
977         plchan->phychan = NULL;
978 }
979
980 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
981 {
982         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
983         struct pl08x_txd *txd = to_pl08x_txd(tx);
984         unsigned long flags;
985
986         spin_lock_irqsave(&plchan->lock, flags);
987
988         plchan->chan.cookie += 1;
989         if (plchan->chan.cookie < 0)
990                 plchan->chan.cookie = 1;
991         tx->cookie = plchan->chan.cookie;
992
993         /* Put this onto the pending list */
994         list_add_tail(&txd->node, &plchan->pend_list);
995
996         /*
997          * If there was no physical channel available for this memcpy,
998          * stack the request up and indicate that the channel is waiting
999          * for a free physical channel.
1000          */
1001         if (!plchan->slave && !plchan->phychan) {
1002                 /* Do this memcpy whenever there is a channel ready */
1003                 plchan->state = PL08X_CHAN_WAITING;
1004                 plchan->waiting = txd;
1005         } else {
1006                 plchan->phychan_hold--;
1007         }
1008
1009         spin_unlock_irqrestore(&plchan->lock, flags);
1010
1011         return tx->cookie;
1012 }
1013
1014 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1015                 struct dma_chan *chan, unsigned long flags)
1016 {
1017         struct dma_async_tx_descriptor *retval = NULL;
1018
1019         return retval;
1020 }
1021
1022 /*
1023  * Code accessing dma_async_is_complete() in a tight loop
1024  * may give problems - could schedule where indicated.
1025  * If slaves are relying on interrupts to signal completion this
1026  * function must not be called with interrupts disabled
1027  */
1028 static enum dma_status
1029 pl08x_dma_tx_status(struct dma_chan *chan,
1030                     dma_cookie_t cookie,
1031                     struct dma_tx_state *txstate)
1032 {
1033         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1034         dma_cookie_t last_used;
1035         dma_cookie_t last_complete;
1036         enum dma_status ret;
1037         u32 bytesleft = 0;
1038
1039         last_used = plchan->chan.cookie;
1040         last_complete = plchan->lc;
1041
1042         ret = dma_async_is_complete(cookie, last_complete, last_used);
1043         if (ret == DMA_SUCCESS) {
1044                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1045                 return ret;
1046         }
1047
1048         /*
1049          * schedule(); could be inserted here
1050          */
1051
1052         /*
1053          * This cookie not complete yet
1054          */
1055         last_used = plchan->chan.cookie;
1056         last_complete = plchan->lc;
1057
1058         /* Get number of bytes left in the active transactions and queue */
1059         bytesleft = pl08x_getbytes_chan(plchan);
1060
1061         dma_set_tx_state(txstate, last_complete, last_used,
1062                          bytesleft);
1063
1064         if (plchan->state == PL08X_CHAN_PAUSED)
1065                 return DMA_PAUSED;
1066
1067         /* Whether waiting or running, we're in progress */
1068         return DMA_IN_PROGRESS;
1069 }
1070
1071 /* PrimeCell DMA extension */
1072 struct burst_table {
1073         int burstwords;
1074         u32 reg;
1075 };
1076
1077 static const struct burst_table burst_sizes[] = {
1078         {
1079                 .burstwords = 256,
1080                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1081                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1082         },
1083         {
1084                 .burstwords = 128,
1085                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1086                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1087         },
1088         {
1089                 .burstwords = 64,
1090                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1091                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1092         },
1093         {
1094                 .burstwords = 32,
1095                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1096                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1097         },
1098         {
1099                 .burstwords = 16,
1100                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1101                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1102         },
1103         {
1104                 .burstwords = 8,
1105                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1106                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1107         },
1108         {
1109                 .burstwords = 4,
1110                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1111                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1112         },
1113         {
1114                 .burstwords = 1,
1115                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1116                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1117         },
1118 };
1119
1120 static int dma_set_runtime_config(struct dma_chan *chan,
1121                                   struct dma_slave_config *config)
1122 {
1123         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1124         struct pl08x_driver_data *pl08x = plchan->host;
1125         struct pl08x_channel_data *cd = plchan->cd;
1126         enum dma_slave_buswidth addr_width;
1127         dma_addr_t addr;
1128         u32 maxburst;
1129         u32 cctl = 0;
1130         int i;
1131
1132         if (!plchan->slave)
1133                 return -EINVAL;
1134
1135         /* Transfer direction */
1136         plchan->runtime_direction = config->direction;
1137         if (config->direction == DMA_TO_DEVICE) {
1138                 addr = config->dst_addr;
1139                 addr_width = config->dst_addr_width;
1140                 maxburst = config->dst_maxburst;
1141         } else if (config->direction == DMA_FROM_DEVICE) {
1142                 addr = config->src_addr;
1143                 addr_width = config->src_addr_width;
1144                 maxburst = config->src_maxburst;
1145         } else {
1146                 dev_err(&pl08x->adev->dev,
1147                         "bad runtime_config: alien transfer direction\n");
1148                 return -EINVAL;
1149         }
1150
1151         switch (addr_width) {
1152         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1153                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1154                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1155                 break;
1156         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1157                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1158                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1159                 break;
1160         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1161                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1162                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1163                 break;
1164         default:
1165                 dev_err(&pl08x->adev->dev,
1166                         "bad runtime_config: alien address width\n");
1167                 return -EINVAL;
1168         }
1169
1170         /*
1171          * Now decide on a maxburst:
1172          * If this channel will only request single transfers, set this
1173          * down to ONE element.  Also select one element if no maxburst
1174          * is specified.
1175          */
1176         if (plchan->cd->single || maxburst == 0) {
1177                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1178                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1179         } else {
1180                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1181                         if (burst_sizes[i].burstwords <= maxburst)
1182                                 break;
1183                 cctl |= burst_sizes[i].reg;
1184         }
1185
1186         plchan->runtime_addr = addr;
1187
1188         /* Modify the default channel data to fit PrimeCell request */
1189         cd->cctl = cctl;
1190
1191         dev_dbg(&pl08x->adev->dev,
1192                 "configured channel %s (%s) for %s, data width %d, "
1193                 "maxburst %d words, LE, CCTL=0x%08x\n",
1194                 dma_chan_name(chan), plchan->name,
1195                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1196                 addr_width,
1197                 maxburst,
1198                 cctl);
1199
1200         return 0;
1201 }
1202
1203 /*
1204  * Slave transactions callback to the slave device to allow
1205  * synchronization of slave DMA signals with the DMAC enable
1206  */
1207 static void pl08x_issue_pending(struct dma_chan *chan)
1208 {
1209         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1210         unsigned long flags;
1211
1212         spin_lock_irqsave(&plchan->lock, flags);
1213         /* Something is already active, or we're waiting for a channel... */
1214         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1215                 spin_unlock_irqrestore(&plchan->lock, flags);
1216                 return;
1217         }
1218
1219         /* Take the first element in the queue and execute it */
1220         if (!list_empty(&plchan->pend_list)) {
1221                 struct pl08x_txd *next;
1222
1223                 next = list_first_entry(&plchan->pend_list,
1224                                         struct pl08x_txd,
1225                                         node);
1226                 list_del(&next->node);
1227                 plchan->state = PL08X_CHAN_RUNNING;
1228
1229                 pl08x_start_txd(plchan, next);
1230         }
1231
1232         spin_unlock_irqrestore(&plchan->lock, flags);
1233 }
1234
1235 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1236                                         struct pl08x_txd *txd)
1237 {
1238         struct pl08x_driver_data *pl08x = plchan->host;
1239         unsigned long flags;
1240         int num_llis, ret;
1241
1242         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1243         if (!num_llis) {
1244                 kfree(txd);
1245                 return -EINVAL;
1246         }
1247
1248         spin_lock_irqsave(&plchan->lock, flags);
1249
1250         /*
1251          * See if we already have a physical channel allocated,
1252          * else this is the time to try to get one.
1253          */
1254         ret = prep_phy_channel(plchan, txd);
1255         if (ret) {
1256                 /*
1257                  * No physical channel was available.
1258                  *
1259                  * memcpy transfers can be sorted out at submission time.
1260                  *
1261                  * Slave transfers may have been denied due to platform
1262                  * channel muxing restrictions.  Since there is no guarantee
1263                  * that this will ever be resolved, and the signal must be
1264                  * acquired AFTER acquiring the physical channel, we will let
1265                  * them be NACK:ed with -EBUSY here. The drivers can retry
1266                  * the prep() call if they are eager on doing this using DMA.
1267                  */
1268                 if (plchan->slave) {
1269                         pl08x_free_txd_list(pl08x, plchan);
1270                         pl08x_free_txd(pl08x, txd);
1271                         spin_unlock_irqrestore(&plchan->lock, flags);
1272                         return -EBUSY;
1273                 }
1274         } else
1275                 /*
1276                  * Else we're all set, paused and ready to roll,
1277                  * status will switch to PL08X_CHAN_RUNNING when
1278                  * we call issue_pending(). If there is something
1279                  * running on the channel already we don't change
1280                  * its state.
1281                  */
1282                 if (plchan->state == PL08X_CHAN_IDLE)
1283                         plchan->state = PL08X_CHAN_PAUSED;
1284
1285         spin_unlock_irqrestore(&plchan->lock, flags);
1286
1287         return 0;
1288 }
1289
1290 /*
1291  * Given the source and destination available bus masks, select which
1292  * will be routed to each port.  We try to have source and destination
1293  * on separate ports, but always respect the allowable settings.
1294  */
1295 static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst)
1296 {
1297         u32 cctl = 0;
1298
1299         if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1300                 cctl |= PL080_CONTROL_DST_AHB2;
1301         if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1302                 cctl |= PL080_CONTROL_SRC_AHB2;
1303
1304         return cctl;
1305 }
1306
1307 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1308         unsigned long flags)
1309 {
1310         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1311
1312         if (txd) {
1313                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1314                 txd->tx.flags = flags;
1315                 txd->tx.tx_submit = pl08x_tx_submit;
1316                 INIT_LIST_HEAD(&txd->node);
1317
1318                 /* Always enable error and terminal interrupts */
1319                 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1320                             PL080_CONFIG_TC_IRQ_MASK;
1321         }
1322         return txd;
1323 }
1324
1325 /*
1326  * Initialize a descriptor to be used by memcpy submit
1327  */
1328 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1329                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1330                 size_t len, unsigned long flags)
1331 {
1332         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1333         struct pl08x_driver_data *pl08x = plchan->host;
1334         struct pl08x_txd *txd;
1335         int ret;
1336
1337         txd = pl08x_get_txd(plchan, flags);
1338         if (!txd) {
1339                 dev_err(&pl08x->adev->dev,
1340                         "%s no memory for descriptor\n", __func__);
1341                 return NULL;
1342         }
1343
1344         txd->direction = DMA_NONE;
1345         txd->src_addr = src;
1346         txd->dst_addr = dest;
1347         txd->len = len;
1348
1349         /* Set platform data for m2m */
1350         txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1351         txd->cctl = pl08x->pd->memcpy_channel.cctl &
1352                         ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1353
1354         /* Both to be incremented or the code will break */
1355         txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1356
1357         if (pl08x->vd->dualmaster)
1358                 txd->cctl |= pl08x_select_bus(pl08x,
1359                                         pl08x->mem_buses, pl08x->mem_buses);
1360
1361         ret = pl08x_prep_channel_resources(plchan, txd);
1362         if (ret)
1363                 return NULL;
1364
1365         return &txd->tx;
1366 }
1367
1368 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1369                 struct dma_chan *chan, struct scatterlist *sgl,
1370                 unsigned int sg_len, enum dma_data_direction direction,
1371                 unsigned long flags)
1372 {
1373         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1374         struct pl08x_driver_data *pl08x = plchan->host;
1375         struct pl08x_txd *txd;
1376         u8 src_buses, dst_buses;
1377         int ret;
1378
1379         /*
1380          * Current implementation ASSUMES only one sg
1381          */
1382         if (sg_len != 1) {
1383                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1384                         __func__);
1385                 BUG();
1386         }
1387
1388         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1389                 __func__, sgl->length, plchan->name);
1390
1391         txd = pl08x_get_txd(plchan, flags);
1392         if (!txd) {
1393                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1394                 return NULL;
1395         }
1396
1397         if (direction != plchan->runtime_direction)
1398                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1399                         "the direction configured for the PrimeCell\n",
1400                         __func__);
1401
1402         /*
1403          * Set up addresses, the PrimeCell configured address
1404          * will take precedence since this may configure the
1405          * channel target address dynamically at runtime.
1406          */
1407         txd->direction = direction;
1408         txd->len = sgl->length;
1409
1410         txd->cctl = plchan->cd->cctl &
1411                         ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1412                           PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1413                           PL080_CONTROL_PROT_MASK);
1414
1415         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1416         txd->cctl |= PL080_CONTROL_PROT_SYS;
1417
1418         if (direction == DMA_TO_DEVICE) {
1419                 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1420                 txd->cctl |= PL080_CONTROL_SRC_INCR;
1421                 txd->src_addr = sgl->dma_address;
1422                 if (plchan->runtime_addr)
1423                         txd->dst_addr = plchan->runtime_addr;
1424                 else
1425                         txd->dst_addr = plchan->cd->addr;
1426                 src_buses = pl08x->mem_buses;
1427                 dst_buses = plchan->cd->periph_buses;
1428         } else if (direction == DMA_FROM_DEVICE) {
1429                 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1430                 txd->cctl |= PL080_CONTROL_DST_INCR;
1431                 if (plchan->runtime_addr)
1432                         txd->src_addr = plchan->runtime_addr;
1433                 else
1434                         txd->src_addr = plchan->cd->addr;
1435                 txd->dst_addr = sgl->dma_address;
1436                 src_buses = plchan->cd->periph_buses;
1437                 dst_buses = pl08x->mem_buses;
1438         } else {
1439                 dev_err(&pl08x->adev->dev,
1440                         "%s direction unsupported\n", __func__);
1441                 return NULL;
1442         }
1443
1444         txd->cctl |= pl08x_select_bus(pl08x, src_buses, dst_buses);
1445
1446         ret = pl08x_prep_channel_resources(plchan, txd);
1447         if (ret)
1448                 return NULL;
1449
1450         return &txd->tx;
1451 }
1452
1453 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1454                          unsigned long arg)
1455 {
1456         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1457         struct pl08x_driver_data *pl08x = plchan->host;
1458         unsigned long flags;
1459         int ret = 0;
1460
1461         /* Controls applicable to inactive channels */
1462         if (cmd == DMA_SLAVE_CONFIG) {
1463                 return dma_set_runtime_config(chan,
1464                                               (struct dma_slave_config *)arg);
1465         }
1466
1467         /*
1468          * Anything succeeds on channels with no physical allocation and
1469          * no queued transfers.
1470          */
1471         spin_lock_irqsave(&plchan->lock, flags);
1472         if (!plchan->phychan && !plchan->at) {
1473                 spin_unlock_irqrestore(&plchan->lock, flags);
1474                 return 0;
1475         }
1476
1477         switch (cmd) {
1478         case DMA_TERMINATE_ALL:
1479                 plchan->state = PL08X_CHAN_IDLE;
1480
1481                 if (plchan->phychan) {
1482                         pl08x_stop_phy_chan(plchan->phychan);
1483
1484                         /*
1485                          * Mark physical channel as free and free any slave
1486                          * signal
1487                          */
1488                         release_phy_channel(plchan);
1489                 }
1490                 /* Dequeue jobs and free LLIs */
1491                 if (plchan->at) {
1492                         pl08x_free_txd(pl08x, plchan->at);
1493                         plchan->at = NULL;
1494                 }
1495                 /* Dequeue jobs not yet fired as well */
1496                 pl08x_free_txd_list(pl08x, plchan);
1497                 break;
1498         case DMA_PAUSE:
1499                 pl08x_pause_phy_chan(plchan->phychan);
1500                 plchan->state = PL08X_CHAN_PAUSED;
1501                 break;
1502         case DMA_RESUME:
1503                 pl08x_resume_phy_chan(plchan->phychan);
1504                 plchan->state = PL08X_CHAN_RUNNING;
1505                 break;
1506         default:
1507                 /* Unknown command */
1508                 ret = -ENXIO;
1509                 break;
1510         }
1511
1512         spin_unlock_irqrestore(&plchan->lock, flags);
1513
1514         return ret;
1515 }
1516
1517 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1518 {
1519         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1520         char *name = chan_id;
1521
1522         /* Check that the channel is not taken! */
1523         if (!strcmp(plchan->name, name))
1524                 return true;
1525
1526         return false;
1527 }
1528
1529 /*
1530  * Just check that the device is there and active
1531  * TODO: turn this bit on/off depending on the number of
1532  * physical channels actually used, if it is zero... well
1533  * shut it off. That will save some power. Cut the clock
1534  * at the same time.
1535  */
1536 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1537 {
1538         u32 val;
1539
1540         val = readl(pl08x->base + PL080_CONFIG);
1541         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1542         /* We implicitly clear bit 1 and that means little-endian mode */
1543         val |= PL080_CONFIG_ENABLE;
1544         writel(val, pl08x->base + PL080_CONFIG);
1545 }
1546
1547 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1548 {
1549         struct device *dev = txd->tx.chan->device->dev;
1550
1551         if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1552                 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1553                         dma_unmap_single(dev, txd->src_addr, txd->len,
1554                                 DMA_TO_DEVICE);
1555                 else
1556                         dma_unmap_page(dev, txd->src_addr, txd->len,
1557                                 DMA_TO_DEVICE);
1558         }
1559         if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1560                 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1561                         dma_unmap_single(dev, txd->dst_addr, txd->len,
1562                                 DMA_FROM_DEVICE);
1563                 else
1564                         dma_unmap_page(dev, txd->dst_addr, txd->len,
1565                                 DMA_FROM_DEVICE);
1566         }
1567 }
1568
1569 static void pl08x_tasklet(unsigned long data)
1570 {
1571         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1572         struct pl08x_driver_data *pl08x = plchan->host;
1573         struct pl08x_txd *txd;
1574         unsigned long flags;
1575
1576         spin_lock_irqsave(&plchan->lock, flags);
1577
1578         txd = plchan->at;
1579         plchan->at = NULL;
1580
1581         if (txd) {
1582                 /*
1583                  * Update last completed
1584                  */
1585                 plchan->lc = txd->tx.cookie;
1586         }
1587
1588         /*
1589          * If a new descriptor is queued, set it up
1590          * plchan->at is NULL here
1591          */
1592         if (!list_empty(&plchan->pend_list)) {
1593                 struct pl08x_txd *next;
1594
1595                 next = list_first_entry(&plchan->pend_list,
1596                                         struct pl08x_txd,
1597                                         node);
1598                 list_del(&next->node);
1599
1600                 pl08x_start_txd(plchan, next);
1601         } else if (plchan->phychan_hold) {
1602                 /*
1603                  * This channel is still in use - we have a new txd being
1604                  * prepared and will soon be queued.  Don't give up the
1605                  * physical channel.
1606                  */
1607         } else {
1608                 struct pl08x_dma_chan *waiting = NULL;
1609
1610                 /*
1611                  * No more jobs, so free up the physical channel
1612                  * Free any allocated signal on slave transfers too
1613                  */
1614                 release_phy_channel(plchan);
1615                 plchan->state = PL08X_CHAN_IDLE;
1616
1617                 /*
1618                  * And NOW before anyone else can grab that free:d
1619                  * up physical channel, see if there is some memcpy
1620                  * pending that seriously needs to start because of
1621                  * being stacked up while we were choking the
1622                  * physical channels with data.
1623                  */
1624                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1625                                     chan.device_node) {
1626                   if (waiting->state == PL08X_CHAN_WAITING &&
1627                             waiting->waiting != NULL) {
1628                                 int ret;
1629
1630                                 /* This should REALLY not fail now */
1631                                 ret = prep_phy_channel(waiting,
1632                                                        waiting->waiting);
1633                                 BUG_ON(ret);
1634                                 waiting->phychan_hold--;
1635                                 waiting->state = PL08X_CHAN_RUNNING;
1636                                 waiting->waiting = NULL;
1637                                 pl08x_issue_pending(&waiting->chan);
1638                                 break;
1639                         }
1640                 }
1641         }
1642
1643         spin_unlock_irqrestore(&plchan->lock, flags);
1644
1645         if (txd) {
1646                 dma_async_tx_callback callback = txd->tx.callback;
1647                 void *callback_param = txd->tx.callback_param;
1648
1649                 /* Don't try to unmap buffers on slave channels */
1650                 if (!plchan->slave)
1651                         pl08x_unmap_buffers(txd);
1652
1653                 /* Free the descriptor */
1654                 spin_lock_irqsave(&plchan->lock, flags);
1655                 pl08x_free_txd(pl08x, txd);
1656                 spin_unlock_irqrestore(&plchan->lock, flags);
1657
1658                 /* Callback to signal completion */
1659                 if (callback)
1660                         callback(callback_param);
1661         }
1662 }
1663
1664 static irqreturn_t pl08x_irq(int irq, void *dev)
1665 {
1666         struct pl08x_driver_data *pl08x = dev;
1667         u32 mask = 0;
1668         u32 val;
1669         int i;
1670
1671         val = readl(pl08x->base + PL080_ERR_STATUS);
1672         if (val) {
1673                 /*
1674                  * An error interrupt (on one or more channels)
1675                  */
1676                 dev_err(&pl08x->adev->dev,
1677                         "%s error interrupt, register value 0x%08x\n",
1678                                 __func__, val);
1679                 /*
1680                  * Simply clear ALL PL08X error interrupts,
1681                  * regardless of channel and cause
1682                  * FIXME: should be 0x00000003 on PL081 really.
1683                  */
1684                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1685         }
1686         val = readl(pl08x->base + PL080_INT_STATUS);
1687         for (i = 0; i < pl08x->vd->channels; i++) {
1688                 if ((1 << i) & val) {
1689                         /* Locate physical channel */
1690                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1691                         struct pl08x_dma_chan *plchan = phychan->serving;
1692
1693                         /* Schedule tasklet on this channel */
1694                         tasklet_schedule(&plchan->tasklet);
1695
1696                         mask |= (1 << i);
1697                 }
1698         }
1699         /*
1700          * Clear only the terminal interrupts on channels we processed
1701          */
1702         writel(mask, pl08x->base + PL080_TC_CLEAR);
1703
1704         return mask ? IRQ_HANDLED : IRQ_NONE;
1705 }
1706
1707 /*
1708  * Initialise the DMAC memcpy/slave channels.
1709  * Make a local wrapper to hold required data
1710  */
1711 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1712                                            struct dma_device *dmadev,
1713                                            unsigned int channels,
1714                                            bool slave)
1715 {
1716         struct pl08x_dma_chan *chan;
1717         int i;
1718
1719         INIT_LIST_HEAD(&dmadev->channels);
1720         /*
1721          * Register as many many memcpy as we have physical channels,
1722          * we won't always be able to use all but the code will have
1723          * to cope with that situation.
1724          */
1725         for (i = 0; i < channels; i++) {
1726                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1727                 if (!chan) {
1728                         dev_err(&pl08x->adev->dev,
1729                                 "%s no memory for channel\n", __func__);
1730                         return -ENOMEM;
1731                 }
1732
1733                 chan->host = pl08x;
1734                 chan->state = PL08X_CHAN_IDLE;
1735
1736                 if (slave) {
1737                         chan->slave = true;
1738                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1739                         chan->cd = &pl08x->pd->slave_channels[i];
1740                 } else {
1741                         chan->cd = &pl08x->pd->memcpy_channel;
1742                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1743                         if (!chan->name) {
1744                                 kfree(chan);
1745                                 return -ENOMEM;
1746                         }
1747                 }
1748                 if (chan->cd->circular_buffer) {
1749                         dev_err(&pl08x->adev->dev,
1750                                 "channel %s: circular buffers not supported\n",
1751                                 chan->name);
1752                         kfree(chan);
1753                         continue;
1754                 }
1755                 dev_info(&pl08x->adev->dev,
1756                          "initialize virtual channel \"%s\"\n",
1757                          chan->name);
1758
1759                 chan->chan.device = dmadev;
1760                 chan->chan.cookie = 0;
1761                 chan->lc = 0;
1762
1763                 spin_lock_init(&chan->lock);
1764                 INIT_LIST_HEAD(&chan->pend_list);
1765                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1766                              (unsigned long) chan);
1767
1768                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1769         }
1770         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1771                  i, slave ? "slave" : "memcpy");
1772         return i;
1773 }
1774
1775 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1776 {
1777         struct pl08x_dma_chan *chan = NULL;
1778         struct pl08x_dma_chan *next;
1779
1780         list_for_each_entry_safe(chan,
1781                                  next, &dmadev->channels, chan.device_node) {
1782                 list_del(&chan->chan.device_node);
1783                 kfree(chan);
1784         }
1785 }
1786
1787 #ifdef CONFIG_DEBUG_FS
1788 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1789 {
1790         switch (state) {
1791         case PL08X_CHAN_IDLE:
1792                 return "idle";
1793         case PL08X_CHAN_RUNNING:
1794                 return "running";
1795         case PL08X_CHAN_PAUSED:
1796                 return "paused";
1797         case PL08X_CHAN_WAITING:
1798                 return "waiting";
1799         default:
1800                 break;
1801         }
1802         return "UNKNOWN STATE";
1803 }
1804
1805 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1806 {
1807         struct pl08x_driver_data *pl08x = s->private;
1808         struct pl08x_dma_chan *chan;
1809         struct pl08x_phy_chan *ch;
1810         unsigned long flags;
1811         int i;
1812
1813         seq_printf(s, "PL08x physical channels:\n");
1814         seq_printf(s, "CHANNEL:\tUSER:\n");
1815         seq_printf(s, "--------\t-----\n");
1816         for (i = 0; i < pl08x->vd->channels; i++) {
1817                 struct pl08x_dma_chan *virt_chan;
1818
1819                 ch = &pl08x->phy_chans[i];
1820
1821                 spin_lock_irqsave(&ch->lock, flags);
1822                 virt_chan = ch->serving;
1823
1824                 seq_printf(s, "%d\t\t%s\n",
1825                            ch->id, virt_chan ? virt_chan->name : "(none)");
1826
1827                 spin_unlock_irqrestore(&ch->lock, flags);
1828         }
1829
1830         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1831         seq_printf(s, "CHANNEL:\tSTATE:\n");
1832         seq_printf(s, "--------\t------\n");
1833         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1834                 seq_printf(s, "%s\t\t%s\n", chan->name,
1835                            pl08x_state_str(chan->state));
1836         }
1837
1838         seq_printf(s, "\nPL08x virtual slave channels:\n");
1839         seq_printf(s, "CHANNEL:\tSTATE:\n");
1840         seq_printf(s, "--------\t------\n");
1841         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1842                 seq_printf(s, "%s\t\t%s\n", chan->name,
1843                            pl08x_state_str(chan->state));
1844         }
1845
1846         return 0;
1847 }
1848
1849 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1850 {
1851         return single_open(file, pl08x_debugfs_show, inode->i_private);
1852 }
1853
1854 static const struct file_operations pl08x_debugfs_operations = {
1855         .open           = pl08x_debugfs_open,
1856         .read           = seq_read,
1857         .llseek         = seq_lseek,
1858         .release        = single_release,
1859 };
1860
1861 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1862 {
1863         /* Expose a simple debugfs interface to view all clocks */
1864         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1865                                    NULL, pl08x,
1866                                    &pl08x_debugfs_operations);
1867 }
1868
1869 #else
1870 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1871 {
1872 }
1873 #endif
1874
1875 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1876 {
1877         struct pl08x_driver_data *pl08x;
1878         const struct vendor_data *vd = id->data;
1879         int ret = 0;
1880         int i;
1881
1882         ret = amba_request_regions(adev, NULL);
1883         if (ret)
1884                 return ret;
1885
1886         /* Create the driver state holder */
1887         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1888         if (!pl08x) {
1889                 ret = -ENOMEM;
1890                 goto out_no_pl08x;
1891         }
1892
1893         /* Initialize memcpy engine */
1894         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1895         pl08x->memcpy.dev = &adev->dev;
1896         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1897         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1898         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1899         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1900         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1901         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1902         pl08x->memcpy.device_control = pl08x_control;
1903
1904         /* Initialize slave engine */
1905         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1906         pl08x->slave.dev = &adev->dev;
1907         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1908         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1909         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1910         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1911         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1912         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1913         pl08x->slave.device_control = pl08x_control;
1914
1915         /* Get the platform data */
1916         pl08x->pd = dev_get_platdata(&adev->dev);
1917         if (!pl08x->pd) {
1918                 dev_err(&adev->dev, "no platform data supplied\n");
1919                 goto out_no_platdata;
1920         }
1921
1922         /* Assign useful pointers to the driver state */
1923         pl08x->adev = adev;
1924         pl08x->vd = vd;
1925
1926         /* By default, AHB1 only.  If dualmaster, from platform */
1927         pl08x->lli_buses = PL08X_AHB1;
1928         pl08x->mem_buses = PL08X_AHB1;
1929         if (pl08x->vd->dualmaster) {
1930                 pl08x->lli_buses = pl08x->pd->lli_buses;
1931                 pl08x->mem_buses = pl08x->pd->mem_buses;
1932         }
1933
1934         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1935         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1936                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1937         if (!pl08x->pool) {
1938                 ret = -ENOMEM;
1939                 goto out_no_lli_pool;
1940         }
1941
1942         spin_lock_init(&pl08x->lock);
1943
1944         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1945         if (!pl08x->base) {
1946                 ret = -ENOMEM;
1947                 goto out_no_ioremap;
1948         }
1949
1950         /* Turn on the PL08x */
1951         pl08x_ensure_on(pl08x);
1952
1953         /*
1954          * Attach the interrupt handler
1955          */
1956         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1957         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1958
1959         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1960                           DRIVER_NAME, pl08x);
1961         if (ret) {
1962                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1963                         __func__, adev->irq[0]);
1964                 goto out_no_irq;
1965         }
1966
1967         /* Initialize physical channels */
1968         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1969                         GFP_KERNEL);
1970         if (!pl08x->phy_chans) {
1971                 dev_err(&adev->dev, "%s failed to allocate "
1972                         "physical channel holders\n",
1973                         __func__);
1974                 goto out_no_phychans;
1975         }
1976
1977         for (i = 0; i < vd->channels; i++) {
1978                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1979
1980                 ch->id = i;
1981                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1982                 spin_lock_init(&ch->lock);
1983                 ch->serving = NULL;
1984                 ch->signal = -1;
1985                 dev_info(&adev->dev,
1986                          "physical channel %d is %s\n", i,
1987                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1988         }
1989
1990         /* Register as many memcpy channels as there are physical channels */
1991         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1992                                               pl08x->vd->channels, false);
1993         if (ret <= 0) {
1994                 dev_warn(&pl08x->adev->dev,
1995                          "%s failed to enumerate memcpy channels - %d\n",
1996                          __func__, ret);
1997                 goto out_no_memcpy;
1998         }
1999         pl08x->memcpy.chancnt = ret;
2000
2001         /* Register slave channels */
2002         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2003                                               pl08x->pd->num_slave_channels,
2004                                               true);
2005         if (ret <= 0) {
2006                 dev_warn(&pl08x->adev->dev,
2007                         "%s failed to enumerate slave channels - %d\n",
2008                                 __func__, ret);
2009                 goto out_no_slave;
2010         }
2011         pl08x->slave.chancnt = ret;
2012
2013         ret = dma_async_device_register(&pl08x->memcpy);
2014         if (ret) {
2015                 dev_warn(&pl08x->adev->dev,
2016                         "%s failed to register memcpy as an async device - %d\n",
2017                         __func__, ret);
2018                 goto out_no_memcpy_reg;
2019         }
2020
2021         ret = dma_async_device_register(&pl08x->slave);
2022         if (ret) {
2023                 dev_warn(&pl08x->adev->dev,
2024                         "%s failed to register slave as an async device - %d\n",
2025                         __func__, ret);
2026                 goto out_no_slave_reg;
2027         }
2028
2029         amba_set_drvdata(adev, pl08x);
2030         init_pl08x_debugfs(pl08x);
2031         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
2032                  amba_part(adev), amba_rev(adev),
2033                  (unsigned long long)adev->res.start, adev->irq[0]);
2034         return 0;
2035
2036 out_no_slave_reg:
2037         dma_async_device_unregister(&pl08x->memcpy);
2038 out_no_memcpy_reg:
2039         pl08x_free_virtual_channels(&pl08x->slave);
2040 out_no_slave:
2041         pl08x_free_virtual_channels(&pl08x->memcpy);
2042 out_no_memcpy:
2043         kfree(pl08x->phy_chans);
2044 out_no_phychans:
2045         free_irq(adev->irq[0], pl08x);
2046 out_no_irq:
2047         iounmap(pl08x->base);
2048 out_no_ioremap:
2049         dma_pool_destroy(pl08x->pool);
2050 out_no_lli_pool:
2051 out_no_platdata:
2052         kfree(pl08x);
2053 out_no_pl08x:
2054         amba_release_regions(adev);
2055         return ret;
2056 }
2057
2058 /* PL080 has 8 channels and the PL080 have just 2 */
2059 static struct vendor_data vendor_pl080 = {
2060         .channels = 8,
2061         .dualmaster = true,
2062 };
2063
2064 static struct vendor_data vendor_pl081 = {
2065         .channels = 2,
2066         .dualmaster = false,
2067 };
2068
2069 static struct amba_id pl08x_ids[] = {
2070         /* PL080 */
2071         {
2072                 .id     = 0x00041080,
2073                 .mask   = 0x000fffff,
2074                 .data   = &vendor_pl080,
2075         },
2076         /* PL081 */
2077         {
2078                 .id     = 0x00041081,
2079                 .mask   = 0x000fffff,
2080                 .data   = &vendor_pl081,
2081         },
2082         /* Nomadik 8815 PL080 variant */
2083         {
2084                 .id     = 0x00280880,
2085                 .mask   = 0x00ffffff,
2086                 .data   = &vendor_pl080,
2087         },
2088         { 0, 0 },
2089 };
2090
2091 static struct amba_driver pl08x_amba_driver = {
2092         .drv.name       = DRIVER_NAME,
2093         .id_table       = pl08x_ids,
2094         .probe          = pl08x_probe,
2095 };
2096
2097 static int __init pl08x_init(void)
2098 {
2099         int retval;
2100         retval = amba_driver_register(&pl08x_amba_driver);
2101         if (retval)
2102                 printk(KERN_WARNING DRIVER_NAME
2103                        "failed to register as an AMBA device (%d)\n",
2104                        retval);
2105         return retval;
2106 }
2107 subsys_initcall(pl08x_init);