ARM: PL08x: fix deadlock in terminate_all
[linux-2.6.git] / drivers / dma / amba-pl08x.c
1 /*
2  * Copyright (c) 2006 ARM Ltd.
3  * Copyright (c) 2010 ST-Ericsson SA
4  *
5  * Author: Peter Pearse <peter.pearse@arm.com>
6  * Author: Linus Walleij <linus.walleij@stericsson.com>
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License as published by the Free
10  * Software Foundation; either version 2 of the License, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program; if not, write to the Free Software Foundation, Inc., 59
20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
21  *
22  * The full GNU General Public License is in this distribution in the
23  * file called COPYING.
24  *
25  * Documentation: ARM DDI 0196G == PL080
26  * Documentation: ARM DDI 0218E == PL081
27  *
28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
29  * any channel.
30  *
31  * The PL080 has 8 channels available for simultaneous use, and the PL081
32  * has only two channels. So on these DMA controllers the number of channels
33  * and the number of incoming DMA signals are two totally different things.
34  * It is usually not possible to theoretically handle all physical signals,
35  * so a multiplexing scheme with possible denial of use is necessary.
36  *
37  * The PL080 has a dual bus master, PL081 has a single master.
38  *
39  * Memory to peripheral transfer may be visualized as
40  *      Get data from memory to DMAC
41  *      Until no data left
42  *              On burst request from peripheral
43  *                      Destination burst from DMAC to peripheral
44  *                      Clear burst request
45  *      Raise terminal count interrupt
46  *
47  * For peripherals with a FIFO:
48  * Source      burst size == half the depth of the peripheral FIFO
49  * Destination burst size == the depth of the peripheral FIFO
50  *
51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
52  * signals, the DMA controller will simply facilitate its AHB master.)
53  *
54  * ASSUMES default (little) endianness for DMA transfers
55  *
56  * Only DMAC flow control is implemented
57  *
58  * Global TODO:
59  * - Break out common code from arch/arm/mach-s3c64xx and share
60  */
61 #include <linux/device.h>
62 #include <linux/init.h>
63 #include <linux/module.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/slab.h>
67 #include <linux/dmapool.h>
68 #include <linux/amba/bus.h>
69 #include <linux/dmaengine.h>
70 #include <linux/amba/pl08x.h>
71 #include <linux/debugfs.h>
72 #include <linux/seq_file.h>
73
74 #include <asm/hardware/pl080.h>
75 #include <asm/dma.h>
76 #include <asm/mach/dma.h>
77 #include <asm/processor.h>
78 #include <asm/cacheflush.h>
79
80 #define DRIVER_NAME     "pl08xdmac"
81
82 /**
83  * struct vendor_data - vendor-specific config parameters
84  * for PL08x derivatives
85  * @name: the name of this specific variant
86  * @channels: the number of channels available in this variant
87  * @dualmaster: whether this version supports dual AHB masters
88  * or not.
89  */
90 struct vendor_data {
91         char *name;
92         u8 channels;
93         bool dualmaster;
94 };
95
96 /*
97  * PL08X private data structures
98  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
99  * start & end do not - their bus bit info is in cctl.
100  */
101 struct lli {
102         dma_addr_t src;
103         dma_addr_t dst;
104         dma_addr_t next;
105         u32 cctl;
106 };
107
108 /**
109  * struct pl08x_driver_data - the local state holder for the PL08x
110  * @slave: slave engine for this instance
111  * @memcpy: memcpy engine for this instance
112  * @base: virtual memory base (remapped) for the PL08x
113  * @adev: the corresponding AMBA (PrimeCell) bus entry
114  * @vd: vendor data for this PL08x variant
115  * @pd: platform data passed in from the platform/machine
116  * @phy_chans: array of data for the physical channels
117  * @pool: a pool for the LLI descriptors
118  * @pool_ctr: counter of LLIs in the pool
119  * @lock: a spinlock for this struct
120  */
121 struct pl08x_driver_data {
122         struct dma_device slave;
123         struct dma_device memcpy;
124         void __iomem *base;
125         struct amba_device *adev;
126         struct vendor_data *vd;
127         struct pl08x_platform_data *pd;
128         struct pl08x_phy_chan *phy_chans;
129         struct dma_pool *pool;
130         int pool_ctr;
131         spinlock_t lock;
132 };
133
134 /*
135  * PL08X specific defines
136  */
137
138 /*
139  * Memory boundaries: the manual for PL08x says that the controller
140  * cannot read past a 1KiB boundary, so these defines are used to
141  * create transfer LLIs that do not cross such boundaries.
142  */
143 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
144 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
145
146 /* Minimum period between work queue runs */
147 #define PL08X_WQ_PERIODMIN      20
148
149 /* Size (bytes) of each LLI buffer allocated for one transfer */
150 # define PL08X_LLI_TSFR_SIZE    0x2000
151
152 /* Maximum times we call dma_pool_alloc on this pool without freeing */
153 #define PL08X_MAX_ALLOCS        0x40
154 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct lli))
155 #define PL08X_ALIGN             8
156
157 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
158 {
159         return container_of(chan, struct pl08x_dma_chan, chan);
160 }
161
162 /*
163  * Physical channel handling
164  */
165
166 /* Whether a certain channel is busy or not */
167 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
168 {
169         unsigned int val;
170
171         val = readl(ch->base + PL080_CH_CONFIG);
172         return val & PL080_CONFIG_ACTIVE;
173 }
174
175 /*
176  * Set the initial DMA register values i.e. those for the first LLI
177  * The next LLI pointer and the configuration interrupt bit have
178  * been set when the LLIs were constructed
179  */
180 static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
181                             struct pl08x_phy_chan *ch)
182 {
183         /* Wait for channel inactive */
184         while (pl08x_phy_channel_busy(ch))
185                 ;
186
187         dev_vdbg(&pl08x->adev->dev,
188                 "WRITE channel %d: csrc=%08x, cdst=%08x, "
189                  "cctl=%08x, clli=%08x, ccfg=%08x\n",
190                 ch->id,
191                 ch->csrc,
192                 ch->cdst,
193                 ch->cctl,
194                 ch->clli,
195                 ch->ccfg);
196
197         writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
198         writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
199         writel(ch->clli, ch->base + PL080_CH_LLI);
200         writel(ch->cctl, ch->base + PL080_CH_CONTROL);
201         writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
202 }
203
204 static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
205 {
206         struct pl08x_channel_data *cd = plchan->cd;
207         struct pl08x_phy_chan *phychan = plchan->phychan;
208         struct pl08x_txd *txd = plchan->at;
209
210         /* Copy the basic control register calculated at transfer config */
211         phychan->csrc = txd->csrc;
212         phychan->cdst = txd->cdst;
213         phychan->clli = txd->clli;
214         phychan->cctl = txd->cctl;
215
216         /* Assign the signal to the proper control registers */
217         phychan->ccfg = cd->ccfg;
218         phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
219         phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
220         /* If it wasn't set from AMBA, ignore it */
221         if (txd->direction == DMA_TO_DEVICE)
222                 /* Select signal as destination */
223                 phychan->ccfg |=
224                         (phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
225         else if (txd->direction == DMA_FROM_DEVICE)
226                 /* Select signal as source */
227                 phychan->ccfg |=
228                         (phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
229         /* Always enable error interrupts */
230         phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
231         /* Always enable terminal interrupts */
232         phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
233 }
234
235 /*
236  * Enable the DMA channel
237  * Assumes all other configuration bits have been set
238  * as desired before this code is called
239  */
240 static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
241                                   struct pl08x_phy_chan *ch)
242 {
243         u32 val;
244
245         /*
246          * Do not access config register until channel shows as disabled
247          */
248         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
249                 ;
250
251         /*
252          * Do not access config register until channel shows as inactive
253          */
254         val = readl(ch->base + PL080_CH_CONFIG);
255         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
256                 val = readl(ch->base + PL080_CH_CONFIG);
257
258         writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
259 }
260
261 /*
262  * Overall DMAC remains enabled always.
263  *
264  * Disabling individual channels could lose data.
265  *
266  * Disable the peripheral DMA after disabling the DMAC
267  * in order to allow the DMAC FIFO to drain, and
268  * hence allow the channel to show inactive
269  *
270  */
271 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
272 {
273         u32 val;
274
275         /* Set the HALT bit and wait for the FIFO to drain */
276         val = readl(ch->base + PL080_CH_CONFIG);
277         val |= PL080_CONFIG_HALT;
278         writel(val, ch->base + PL080_CH_CONFIG);
279
280         /* Wait for channel inactive */
281         while (pl08x_phy_channel_busy(ch))
282                 ;
283 }
284
285 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
286 {
287         u32 val;
288
289         /* Clear the HALT bit */
290         val = readl(ch->base + PL080_CH_CONFIG);
291         val &= ~PL080_CONFIG_HALT;
292         writel(val, ch->base + PL080_CH_CONFIG);
293 }
294
295
296 /* Stops the channel */
297 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
298 {
299         u32 val;
300
301         pl08x_pause_phy_chan(ch);
302
303         /* Disable channel */
304         val = readl(ch->base + PL080_CH_CONFIG);
305         val &= ~PL080_CONFIG_ENABLE;
306         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
307         val &= ~PL080_CONFIG_TC_IRQ_MASK;
308         writel(val, ch->base + PL080_CH_CONFIG);
309 }
310
311 static inline u32 get_bytes_in_cctl(u32 cctl)
312 {
313         /* The source width defines the number of bytes */
314         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
315
316         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
317         case PL080_WIDTH_8BIT:
318                 break;
319         case PL080_WIDTH_16BIT:
320                 bytes *= 2;
321                 break;
322         case PL080_WIDTH_32BIT:
323                 bytes *= 4;
324                 break;
325         }
326         return bytes;
327 }
328
329 /* The channel should be paused when calling this */
330 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
331 {
332         struct pl08x_phy_chan *ch;
333         struct pl08x_txd *txdi = NULL;
334         struct pl08x_txd *txd;
335         unsigned long flags;
336         u32 bytes = 0;
337
338         spin_lock_irqsave(&plchan->lock, flags);
339
340         ch = plchan->phychan;
341         txd = plchan->at;
342
343         /*
344          * Next follow the LLIs to get the number of pending bytes in the
345          * currently active transaction.
346          */
347         if (ch && txd) {
348                 struct lli *llis_va = txd->llis_va;
349                 struct lli *llis_bus = (struct lli *) txd->llis_bus;
350                 u32 clli = readl(ch->base + PL080_CH_LLI);
351
352                 /* First get the bytes in the current active LLI */
353                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
354
355                 if (clli) {
356                         int i = 0;
357
358                         /* Forward to the LLI pointed to by clli */
359                         while ((clli != (u32) &(llis_bus[i])) &&
360                                (i < MAX_NUM_TSFR_LLIS))
361                                 i++;
362
363                         while (clli) {
364                                 bytes += get_bytes_in_cctl(llis_va[i].cctl);
365                                 /*
366                                  * A LLI pointer of 0 terminates the LLI list
367                                  */
368                                 clli = llis_va[i].next;
369                                 i++;
370                         }
371                 }
372         }
373
374         /* Sum up all queued transactions */
375         if (!list_empty(&plchan->desc_list)) {
376                 list_for_each_entry(txdi, &plchan->desc_list, node) {
377                         bytes += txdi->len;
378                 }
379
380         }
381
382         spin_unlock_irqrestore(&plchan->lock, flags);
383
384         return bytes;
385 }
386
387 /*
388  * Allocate a physical channel for a virtual channel
389  */
390 static struct pl08x_phy_chan *
391 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
392                       struct pl08x_dma_chan *virt_chan)
393 {
394         struct pl08x_phy_chan *ch = NULL;
395         unsigned long flags;
396         int i;
397
398         /*
399          * Try to locate a physical channel to be used for
400          * this transfer. If all are taken return NULL and
401          * the requester will have to cope by using some fallback
402          * PIO mode or retrying later.
403          */
404         for (i = 0; i < pl08x->vd->channels; i++) {
405                 ch = &pl08x->phy_chans[i];
406
407                 spin_lock_irqsave(&ch->lock, flags);
408
409                 if (!ch->serving) {
410                         ch->serving = virt_chan;
411                         ch->signal = -1;
412                         spin_unlock_irqrestore(&ch->lock, flags);
413                         break;
414                 }
415
416                 spin_unlock_irqrestore(&ch->lock, flags);
417         }
418
419         if (i == pl08x->vd->channels) {
420                 /* No physical channel available, cope with it */
421                 return NULL;
422         }
423
424         return ch;
425 }
426
427 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
428                                          struct pl08x_phy_chan *ch)
429 {
430         unsigned long flags;
431
432         /* Stop the channel and clear its interrupts */
433         pl08x_stop_phy_chan(ch);
434         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
435         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
436
437         /* Mark it as free */
438         spin_lock_irqsave(&ch->lock, flags);
439         ch->serving = NULL;
440         spin_unlock_irqrestore(&ch->lock, flags);
441 }
442
443 /*
444  * LLI handling
445  */
446
447 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
448 {
449         switch (coded) {
450         case PL080_WIDTH_8BIT:
451                 return 1;
452         case PL080_WIDTH_16BIT:
453                 return 2;
454         case PL080_WIDTH_32BIT:
455                 return 4;
456         default:
457                 break;
458         }
459         BUG();
460         return 0;
461 }
462
463 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
464                                   u32 tsize)
465 {
466         u32 retbits = cctl;
467
468         /* Remove all src, dst and transfer size bits */
469         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
470         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
471         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
472
473         /* Then set the bits according to the parameters */
474         switch (srcwidth) {
475         case 1:
476                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
477                 break;
478         case 2:
479                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
480                 break;
481         case 4:
482                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
483                 break;
484         default:
485                 BUG();
486                 break;
487         }
488
489         switch (dstwidth) {
490         case 1:
491                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
492                 break;
493         case 2:
494                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
495                 break;
496         case 4:
497                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
498                 break;
499         default:
500                 BUG();
501                 break;
502         }
503
504         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
505         return retbits;
506 }
507
508 /*
509  * Autoselect a master bus to use for the transfer
510  * this prefers the destination bus if both available
511  * if fixed address on one bus the other will be chosen
512  */
513 void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
514         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
515         struct pl08x_bus_data **sbus, u32 cctl)
516 {
517         if (!(cctl & PL080_CONTROL_DST_INCR)) {
518                 *mbus = src_bus;
519                 *sbus = dst_bus;
520         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
521                 *mbus = dst_bus;
522                 *sbus = src_bus;
523         } else {
524                 if (dst_bus->buswidth == 4) {
525                         *mbus = dst_bus;
526                         *sbus = src_bus;
527                 } else if (src_bus->buswidth == 4) {
528                         *mbus = src_bus;
529                         *sbus = dst_bus;
530                 } else if (dst_bus->buswidth == 2) {
531                         *mbus = dst_bus;
532                         *sbus = src_bus;
533                 } else if (src_bus->buswidth == 2) {
534                         *mbus = src_bus;
535                         *sbus = dst_bus;
536                 } else {
537                         /* src_bus->buswidth == 1 */
538                         *mbus = dst_bus;
539                         *sbus = src_bus;
540                 }
541         }
542 }
543
544 /*
545  * Fills in one LLI for a certain transfer descriptor
546  * and advance the counter
547  */
548 int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
549                             struct pl08x_txd *txd, int num_llis, int len,
550                             u32 cctl, u32 *remainder)
551 {
552         struct lli *llis_va = txd->llis_va;
553         struct lli *llis_bus = (struct lli *) txd->llis_bus;
554
555         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
556
557         llis_va[num_llis].cctl          = cctl;
558         llis_va[num_llis].src           = txd->srcbus.addr;
559         llis_va[num_llis].dst           = txd->dstbus.addr;
560
561         /*
562          * On versions with dual masters, you can optionally AND on
563          * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
564          * in new LLIs with that controller, but we always try to
565          * choose AHB1 to point into memory. The idea is to have AHB2
566          * fixed on the peripheral and AHB1 messing around in the
567          * memory. So we don't manipulate this bit currently.
568          */
569
570         llis_va[num_llis].next =
571                 (dma_addr_t)((u32) &(llis_bus[num_llis + 1]));
572
573         if (cctl & PL080_CONTROL_SRC_INCR)
574                 txd->srcbus.addr += len;
575         if (cctl & PL080_CONTROL_DST_INCR)
576                 txd->dstbus.addr += len;
577
578         *remainder -= len;
579
580         return num_llis + 1;
581 }
582
583 /*
584  * Return number of bytes to fill to boundary, or len
585  */
586 static inline u32 pl08x_pre_boundary(u32 addr, u32 len)
587 {
588         u32 boundary;
589
590         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
591                 << PL08X_BOUNDARY_SHIFT;
592
593         if (boundary < addr + len)
594                 return boundary - addr;
595         else
596                 return len;
597 }
598
599 /*
600  * This fills in the table of LLIs for the transfer descriptor
601  * Note that we assume we never have to change the burst sizes
602  * Return 0 for error
603  */
604 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
605                               struct pl08x_txd *txd)
606 {
607         struct pl08x_channel_data *cd = txd->cd;
608         struct pl08x_bus_data *mbus, *sbus;
609         u32 remainder;
610         int num_llis = 0;
611         u32 cctl;
612         int max_bytes_per_lli;
613         int total_bytes = 0;
614         struct lli *llis_va;
615         struct lli *llis_bus;
616
617         if (!txd) {
618                 dev_err(&pl08x->adev->dev, "%s no descriptor\n", __func__);
619                 return 0;
620         }
621
622         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
623                                       &txd->llis_bus);
624         if (!txd->llis_va) {
625                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
626                 return 0;
627         }
628
629         pl08x->pool_ctr++;
630
631         /*
632          * Initialize bus values for this transfer
633          * from the passed optimal values
634          */
635         if (!cd) {
636                 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
637                 return 0;
638         }
639
640         /* Get the default CCTL from the platform data */
641         cctl = cd->cctl;
642
643         /*
644          * On the PL080 we have two bus masters and we
645          * should select one for source and one for
646          * destination. We try to use AHB2 for the
647          * bus which does not increment (typically the
648          * peripheral) else we just choose something.
649          */
650         cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
651         if (pl08x->vd->dualmaster) {
652                 if (cctl & PL080_CONTROL_SRC_INCR)
653                         /* Source increments, use AHB2 for destination */
654                         cctl |= PL080_CONTROL_DST_AHB2;
655                 else if (cctl & PL080_CONTROL_DST_INCR)
656                         /* Destination increments, use AHB2 for source */
657                         cctl |= PL080_CONTROL_SRC_AHB2;
658                 else
659                         /* Just pick something, source AHB1 dest AHB2 */
660                         cctl |= PL080_CONTROL_DST_AHB2;
661         }
662
663         /* Find maximum width of the source bus */
664         txd->srcbus.maxwidth =
665                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
666                                        PL080_CONTROL_SWIDTH_SHIFT);
667
668         /* Find maximum width of the destination bus */
669         txd->dstbus.maxwidth =
670                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
671                                        PL080_CONTROL_DWIDTH_SHIFT);
672
673         /* Set up the bus widths to the maximum */
674         txd->srcbus.buswidth = txd->srcbus.maxwidth;
675         txd->dstbus.buswidth = txd->dstbus.maxwidth;
676         dev_vdbg(&pl08x->adev->dev,
677                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
678                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
679
680
681         /*
682          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
683          */
684         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
685                 PL080_CONTROL_TRANSFER_SIZE_MASK;
686         dev_vdbg(&pl08x->adev->dev,
687                  "%s max bytes per lli = %d\n",
688                  __func__, max_bytes_per_lli);
689
690         /* We need to count this down to zero */
691         remainder = txd->len;
692         dev_vdbg(&pl08x->adev->dev,
693                  "%s remainder = %d\n",
694                  __func__, remainder);
695
696         /*
697          * Choose bus to align to
698          * - prefers destination bus if both available
699          * - if fixed address on one bus chooses other
700          * - modifies cctl to choose an appropriate master
701          */
702         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
703                                 &mbus, &sbus, cctl);
704
705
706         /*
707          * The lowest bit of the LLI register
708          * is also used to indicate which master to
709          * use for reading the LLIs.
710          */
711
712         if (txd->len < mbus->buswidth) {
713                 /*
714                  * Less than a bus width available
715                  * - send as single bytes
716                  */
717                 while (remainder) {
718                         dev_vdbg(&pl08x->adev->dev,
719                                  "%s single byte LLIs for a transfer of "
720                                  "less than a bus width (remain %08x)\n",
721                                  __func__, remainder);
722                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
723                         num_llis =
724                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
725                                         cctl, &remainder);
726                         total_bytes++;
727                 }
728         } else {
729                 /*
730                  *  Make one byte LLIs until master bus is aligned
731                  *  - slave will then be aligned also
732                  */
733                 while ((mbus->addr) % (mbus->buswidth)) {
734                         dev_vdbg(&pl08x->adev->dev,
735                                 "%s adjustment lli for less than bus width "
736                                  "(remain %08x)\n",
737                                  __func__, remainder);
738                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
739                         num_llis = pl08x_fill_lli_for_desc
740                                 (pl08x, txd, num_llis, 1, cctl, &remainder);
741                         total_bytes++;
742                 }
743
744                 /*
745                  *  Master now aligned
746                  * - if slave is not then we must set its width down
747                  */
748                 if (sbus->addr % sbus->buswidth) {
749                         dev_dbg(&pl08x->adev->dev,
750                                 "%s set down bus width to one byte\n",
751                                  __func__);
752
753                         sbus->buswidth = 1;
754                 }
755
756                 /*
757                  * Make largest possible LLIs until less than one bus
758                  * width left
759                  */
760                 while (remainder > (mbus->buswidth - 1)) {
761                         int lli_len, target_len;
762                         int tsize;
763                         int odd_bytes;
764
765                         /*
766                          * If enough left try to send max possible,
767                          * otherwise try to send the remainder
768                          */
769                         target_len = remainder;
770                         if (remainder > max_bytes_per_lli)
771                                 target_len = max_bytes_per_lli;
772
773                         /*
774                          * Set bus lengths for incrementing buses
775                          * to number of bytes which fill to next memory
776                          * boundary
777                          */
778                         if (cctl & PL080_CONTROL_SRC_INCR)
779                                 txd->srcbus.fill_bytes =
780                                         pl08x_pre_boundary(
781                                                 txd->srcbus.addr,
782                                                 remainder);
783                         else
784                                 txd->srcbus.fill_bytes =
785                                         max_bytes_per_lli;
786
787                         if (cctl & PL080_CONTROL_DST_INCR)
788                                 txd->dstbus.fill_bytes =
789                                         pl08x_pre_boundary(
790                                                 txd->dstbus.addr,
791                                                 remainder);
792                         else
793                                 txd->dstbus.fill_bytes =
794                                                 max_bytes_per_lli;
795
796                         /*
797                          *  Find the nearest
798                          */
799                         lli_len = min(txd->srcbus.fill_bytes,
800                                 txd->dstbus.fill_bytes);
801
802                         BUG_ON(lli_len > remainder);
803
804                         if (lli_len <= 0) {
805                                 dev_err(&pl08x->adev->dev,
806                                         "%s lli_len is %d, <= 0\n",
807                                                 __func__, lli_len);
808                                 return 0;
809                         }
810
811                         if (lli_len == target_len) {
812                                 /*
813                                  * Can send what we wanted
814                                  */
815                                 /*
816                                  *  Maintain alignment
817                                  */
818                                 lli_len = (lli_len/mbus->buswidth) *
819                                                         mbus->buswidth;
820                                 odd_bytes = 0;
821                         } else {
822                                 /*
823                                  * So now we know how many bytes to transfer
824                                  * to get to the nearest boundary
825                                  * The next LLI will past the boundary
826                                  * - however we may be working to a boundary
827                                  *   on the slave bus
828                                  *   We need to ensure the master stays aligned
829                                  */
830                                 odd_bytes = lli_len % mbus->buswidth;
831                                 /*
832                                  * - and that we are working in multiples
833                                  *   of the bus widths
834                                  */
835                                 lli_len -= odd_bytes;
836
837                         }
838
839                         if (lli_len) {
840                                 /*
841                                  * Check against minimum bus alignment:
842                                  * Calculate actual transfer size in relation
843                                  * to bus width an get a maximum remainder of
844                                  * the smallest bus width - 1
845                                  */
846                                 /* FIXME: use round_down()? */
847                                 tsize = lli_len / min(mbus->buswidth,
848                                                       sbus->buswidth);
849                                 lli_len = tsize * min(mbus->buswidth,
850                                                       sbus->buswidth);
851
852                                 if (target_len != lli_len) {
853                                         dev_vdbg(&pl08x->adev->dev,
854                                         "%s can't send what we want. Desired %08x, lli of %08x bytes in txd of %08x\n",
855                                         __func__, target_len, lli_len, txd->len);
856                                 }
857
858                                 cctl = pl08x_cctl_bits(cctl,
859                                                        txd->srcbus.buswidth,
860                                                        txd->dstbus.buswidth,
861                                                        tsize);
862
863                                 dev_vdbg(&pl08x->adev->dev,
864                                         "%s fill lli with single lli chunk of size %08x (remainder %08x)\n",
865                                         __func__, lli_len, remainder);
866                                 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
867                                                 num_llis, lli_len, cctl,
868                                                 &remainder);
869                                 total_bytes += lli_len;
870                         }
871
872
873                         if (odd_bytes) {
874                                 /*
875                                  * Creep past the boundary,
876                                  * maintaining master alignment
877                                  */
878                                 int j;
879                                 for (j = 0; (j < mbus->buswidth)
880                                                 && (remainder); j++) {
881                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
882                                         dev_vdbg(&pl08x->adev->dev,
883                                                 "%s align with boundary, single byte (remain %08x)\n",
884                                                 __func__, remainder);
885                                         num_llis =
886                                                 pl08x_fill_lli_for_desc(pl08x,
887                                                         txd, num_llis, 1,
888                                                         cctl, &remainder);
889                                         total_bytes++;
890                                 }
891                         }
892                 }
893
894                 /*
895                  * Send any odd bytes
896                  */
897                 if (remainder < 0) {
898                         dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n",
899                                         __func__, remainder);
900                         return 0;
901                 }
902
903                 while (remainder) {
904                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
905                         dev_vdbg(&pl08x->adev->dev,
906                                 "%s align with boundary, single odd byte (remain %d)\n",
907                                 __func__, remainder);
908                         num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
909                                         1, cctl, &remainder);
910                         total_bytes++;
911                 }
912         }
913         if (total_bytes != txd->len) {
914                 dev_err(&pl08x->adev->dev,
915                         "%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
916                         __func__, total_bytes, txd->len);
917                 return 0;
918         }
919
920         if (num_llis >= MAX_NUM_TSFR_LLIS) {
921                 dev_err(&pl08x->adev->dev,
922                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
923                         __func__, (u32) MAX_NUM_TSFR_LLIS);
924                 return 0;
925         }
926         /*
927          * Decide whether this is a loop or a terminated transfer
928          */
929         llis_va = txd->llis_va;
930         llis_bus = (struct lli *) txd->llis_bus;
931
932         if (cd->circular_buffer) {
933                 /*
934                  * Loop the circular buffer so that the next element
935                  * points back to the beginning of the LLI.
936                  */
937                 llis_va[num_llis - 1].next =
938                         (dma_addr_t)((unsigned int)&(llis_bus[0]));
939         } else {
940                 /*
941                  * On non-circular buffers, the final LLI terminates
942                  * the LLI.
943                  */
944                 llis_va[num_llis - 1].next = 0;
945                 /*
946                  * The final LLI element shall also fire an interrupt
947                  */
948                 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
949         }
950
951         /* Now store the channel register values */
952         txd->csrc = llis_va[0].src;
953         txd->cdst = llis_va[0].dst;
954         if (num_llis > 1)
955                 txd->clli = llis_va[0].next;
956         else
957                 txd->clli = 0;
958
959         txd->cctl = llis_va[0].cctl;
960         /* ccfg will be set at physical channel allocation time */
961
962 #ifdef VERBOSE_DEBUG
963         {
964                 int i;
965
966                 for (i = 0; i < num_llis; i++) {
967                         dev_vdbg(&pl08x->adev->dev,
968                                  "lli %d @%p: csrc=%08x, cdst=%08x, cctl=%08x, clli=%08x\n",
969                                  i,
970                                  &llis_va[i],
971                                  llis_va[i].src,
972                                  llis_va[i].dst,
973                                  llis_va[i].cctl,
974                                  llis_va[i].next
975                                 );
976                 }
977         }
978 #endif
979
980         return num_llis;
981 }
982
983 /* You should call this with the struct pl08x lock held */
984 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
985                            struct pl08x_txd *txd)
986 {
987         if (!txd)
988                 dev_err(&pl08x->adev->dev,
989                         "%s no descriptor to free\n",
990                         __func__);
991
992         /* Free the LLI */
993         dma_pool_free(pl08x->pool, txd->llis_va,
994                       txd->llis_bus);
995
996         pl08x->pool_ctr--;
997
998         kfree(txd);
999 }
1000
1001 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
1002                                 struct pl08x_dma_chan *plchan)
1003 {
1004         struct pl08x_txd *txdi = NULL;
1005         struct pl08x_txd *next;
1006
1007         if (!list_empty(&plchan->desc_list)) {
1008                 list_for_each_entry_safe(txdi,
1009                                          next, &plchan->desc_list, node) {
1010                         list_del(&txdi->node);
1011                         pl08x_free_txd(pl08x, txdi);
1012                 }
1013
1014         }
1015 }
1016
1017 /*
1018  * The DMA ENGINE API
1019  */
1020 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
1021 {
1022         return 0;
1023 }
1024
1025 static void pl08x_free_chan_resources(struct dma_chan *chan)
1026 {
1027 }
1028
1029 /*
1030  * This should be called with the channel plchan->lock held
1031  */
1032 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
1033                             struct pl08x_txd *txd)
1034 {
1035         struct pl08x_driver_data *pl08x = plchan->host;
1036         struct pl08x_phy_chan *ch;
1037         int ret;
1038
1039         /* Check if we already have a channel */
1040         if (plchan->phychan)
1041                 return 0;
1042
1043         ch = pl08x_get_phy_channel(pl08x, plchan);
1044         if (!ch) {
1045                 /* No physical channel available, cope with it */
1046                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
1047                 return -EBUSY;
1048         }
1049
1050         /*
1051          * OK we have a physical channel: for memcpy() this is all we
1052          * need, but for slaves the physical signals may be muxed!
1053          * Can the platform allow us to use this channel?
1054          */
1055         if (plchan->slave &&
1056             ch->signal < 0 &&
1057             pl08x->pd->get_signal) {
1058                 ret = pl08x->pd->get_signal(plchan);
1059                 if (ret < 0) {
1060                         dev_dbg(&pl08x->adev->dev,
1061                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
1062                                 ch->id, plchan->name);
1063                         /* Release physical channel & return */
1064                         pl08x_put_phy_channel(pl08x, ch);
1065                         return -EBUSY;
1066                 }
1067                 ch->signal = ret;
1068         }
1069
1070         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1071                  ch->id,
1072                  ch->signal,
1073                  plchan->name);
1074
1075         plchan->phychan = ch;
1076
1077         return 0;
1078 }
1079
1080 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1081 {
1082         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1083
1084         plchan->chan.cookie += 1;
1085         if (plchan->chan.cookie < 0)
1086                 plchan->chan.cookie = 1;
1087         tx->cookie = plchan->chan.cookie;
1088         /* This unlock follows the lock in the prep() function */
1089         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1090
1091         return tx->cookie;
1092 }
1093
1094 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1095                 struct dma_chan *chan, unsigned long flags)
1096 {
1097         struct dma_async_tx_descriptor *retval = NULL;
1098
1099         return retval;
1100 }
1101
1102 /*
1103  * Code accessing dma_async_is_complete() in a tight loop
1104  * may give problems - could schedule where indicated.
1105  * If slaves are relying on interrupts to signal completion this
1106  * function must not be called with interrupts disabled
1107  */
1108 static enum dma_status
1109 pl08x_dma_tx_status(struct dma_chan *chan,
1110                     dma_cookie_t cookie,
1111                     struct dma_tx_state *txstate)
1112 {
1113         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1114         dma_cookie_t last_used;
1115         dma_cookie_t last_complete;
1116         enum dma_status ret;
1117         u32 bytesleft = 0;
1118
1119         last_used = plchan->chan.cookie;
1120         last_complete = plchan->lc;
1121
1122         ret = dma_async_is_complete(cookie, last_complete, last_used);
1123         if (ret == DMA_SUCCESS) {
1124                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1125                 return ret;
1126         }
1127
1128         /*
1129          * schedule(); could be inserted here
1130          */
1131
1132         /*
1133          * This cookie not complete yet
1134          */
1135         last_used = plchan->chan.cookie;
1136         last_complete = plchan->lc;
1137
1138         /* Get number of bytes left in the active transactions and queue */
1139         bytesleft = pl08x_getbytes_chan(plchan);
1140
1141         dma_set_tx_state(txstate, last_complete, last_used,
1142                          bytesleft);
1143
1144         if (plchan->state == PL08X_CHAN_PAUSED)
1145                 return DMA_PAUSED;
1146
1147         /* Whether waiting or running, we're in progress */
1148         return DMA_IN_PROGRESS;
1149 }
1150
1151 /* PrimeCell DMA extension */
1152 struct burst_table {
1153         int burstwords;
1154         u32 reg;
1155 };
1156
1157 static const struct burst_table burst_sizes[] = {
1158         {
1159                 .burstwords = 256,
1160                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1161                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1162         },
1163         {
1164                 .burstwords = 128,
1165                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1166                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1167         },
1168         {
1169                 .burstwords = 64,
1170                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1171                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1172         },
1173         {
1174                 .burstwords = 32,
1175                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1176                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1177         },
1178         {
1179                 .burstwords = 16,
1180                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1181                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1182         },
1183         {
1184                 .burstwords = 8,
1185                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1186                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1187         },
1188         {
1189                 .burstwords = 4,
1190                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1191                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1192         },
1193         {
1194                 .burstwords = 1,
1195                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1196                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1197         },
1198 };
1199
1200 static void dma_set_runtime_config(struct dma_chan *chan,
1201                                struct dma_slave_config *config)
1202 {
1203         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1204         struct pl08x_driver_data *pl08x = plchan->host;
1205         struct pl08x_channel_data *cd = plchan->cd;
1206         enum dma_slave_buswidth addr_width;
1207         u32 maxburst;
1208         u32 cctl = 0;
1209         /* Mask out all except src and dst channel */
1210         u32 ccfg = cd->ccfg & 0x000003DEU;
1211         int i;
1212
1213         /* Transfer direction */
1214         plchan->runtime_direction = config->direction;
1215         if (config->direction == DMA_TO_DEVICE) {
1216                 plchan->runtime_addr = config->dst_addr;
1217                 cctl |= PL080_CONTROL_SRC_INCR;
1218                 ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1219                 addr_width = config->dst_addr_width;
1220                 maxburst = config->dst_maxburst;
1221         } else if (config->direction == DMA_FROM_DEVICE) {
1222                 plchan->runtime_addr = config->src_addr;
1223                 cctl |= PL080_CONTROL_DST_INCR;
1224                 ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1225                 addr_width = config->src_addr_width;
1226                 maxburst = config->src_maxburst;
1227         } else {
1228                 dev_err(&pl08x->adev->dev,
1229                         "bad runtime_config: alien transfer direction\n");
1230                 return;
1231         }
1232
1233         switch (addr_width) {
1234         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1235                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1236                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1237                 break;
1238         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1239                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1240                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1241                 break;
1242         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1243                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1244                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1245                 break;
1246         default:
1247                 dev_err(&pl08x->adev->dev,
1248                         "bad runtime_config: alien address width\n");
1249                 return;
1250         }
1251
1252         /*
1253          * Now decide on a maxburst:
1254          * If this channel will only request single transfers, set this
1255          * down to ONE element.  Also select one element if no maxburst
1256          * is specified.
1257          */
1258         if (plchan->cd->single || maxburst == 0) {
1259                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1260                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1261         } else {
1262                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1263                         if (burst_sizes[i].burstwords <= maxburst)
1264                                 break;
1265                 cctl |= burst_sizes[i].reg;
1266         }
1267
1268         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1269         cctl &= ~PL080_CONTROL_PROT_MASK;
1270         cctl |= PL080_CONTROL_PROT_SYS;
1271
1272         /* Modify the default channel data to fit PrimeCell request */
1273         cd->cctl = cctl;
1274         cd->ccfg = ccfg;
1275
1276         dev_dbg(&pl08x->adev->dev,
1277                 "configured channel %s (%s) for %s, data width %d, "
1278                 "maxburst %d words, LE, CCTL=%08x, CCFG=%08x\n",
1279                 dma_chan_name(chan), plchan->name,
1280                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1281                 addr_width,
1282                 maxburst,
1283                 cctl, ccfg);
1284 }
1285
1286 /*
1287  * Slave transactions callback to the slave device to allow
1288  * synchronization of slave DMA signals with the DMAC enable
1289  */
1290 static void pl08x_issue_pending(struct dma_chan *chan)
1291 {
1292         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1293         struct pl08x_driver_data *pl08x = plchan->host;
1294         unsigned long flags;
1295
1296         spin_lock_irqsave(&plchan->lock, flags);
1297         /* Something is already active, or we're waiting for a channel... */
1298         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1299                 spin_unlock_irqrestore(&plchan->lock, flags);
1300                 return;
1301         }
1302
1303         /* Take the first element in the queue and execute it */
1304         if (!list_empty(&plchan->desc_list)) {
1305                 struct pl08x_txd *next;
1306
1307                 next = list_first_entry(&plchan->desc_list,
1308                                         struct pl08x_txd,
1309                                         node);
1310                 list_del(&next->node);
1311                 plchan->at = next;
1312                 plchan->state = PL08X_CHAN_RUNNING;
1313
1314                 /* Configure the physical channel for the active txd */
1315                 pl08x_config_phychan_for_txd(plchan);
1316                 pl08x_set_cregs(pl08x, plchan->phychan);
1317                 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1318         }
1319
1320         spin_unlock_irqrestore(&plchan->lock, flags);
1321 }
1322
1323 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1324                                         struct pl08x_txd *txd)
1325 {
1326         int num_llis;
1327         struct pl08x_driver_data *pl08x = plchan->host;
1328         int ret;
1329
1330         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1331         if (!num_llis) {
1332                 kfree(txd);
1333                 return -EINVAL;
1334         }
1335
1336         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1337
1338         /*
1339          * If this device is not using a circular buffer then
1340          * queue this new descriptor for transfer.
1341          * The descriptor for a circular buffer continues
1342          * to be used until the channel is freed.
1343          */
1344         if (txd->cd->circular_buffer)
1345                 dev_err(&pl08x->adev->dev,
1346                         "%s attempting to queue a circular buffer\n",
1347                         __func__);
1348         else
1349                 list_add_tail(&txd->node,
1350                               &plchan->desc_list);
1351
1352         /*
1353          * See if we already have a physical channel allocated,
1354          * else this is the time to try to get one.
1355          */
1356         ret = prep_phy_channel(plchan, txd);
1357         if (ret) {
1358                 /*
1359                  * No physical channel available, we will
1360                  * stack up the memcpy channels until there is a channel
1361                  * available to handle it whereas slave transfers may
1362                  * have been denied due to platform channel muxing restrictions
1363                  * and since there is no guarantee that this will ever be
1364                  * resolved, and since the signal must be acquired AFTER
1365                  * acquiring the physical channel, we will let them be NACK:ed
1366                  * with -EBUSY here. The drivers can alway retry the prep()
1367                  * call if they are eager on doing this using DMA.
1368                  */
1369                 if (plchan->slave) {
1370                         pl08x_free_txd_list(pl08x, plchan);
1371                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1372                         return -EBUSY;
1373                 }
1374                 /* Do this memcpy whenever there is a channel ready */
1375                 plchan->state = PL08X_CHAN_WAITING;
1376                 plchan->waiting = txd;
1377         } else
1378                 /*
1379                  * Else we're all set, paused and ready to roll,
1380                  * status will switch to PL08X_CHAN_RUNNING when
1381                  * we call issue_pending(). If there is something
1382                  * running on the channel already we don't change
1383                  * its state.
1384                  */
1385                 if (plchan->state == PL08X_CHAN_IDLE)
1386                         plchan->state = PL08X_CHAN_PAUSED;
1387
1388         /*
1389          * Notice that we leave plchan->lock locked on purpose:
1390          * it will be unlocked in the subsequent tx_submit()
1391          * call. This is a consequence of the current API.
1392          */
1393
1394         return 0;
1395 }
1396
1397 /*
1398  * Initialize a descriptor to be used by memcpy submit
1399  */
1400 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1401                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1402                 size_t len, unsigned long flags)
1403 {
1404         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1405         struct pl08x_driver_data *pl08x = plchan->host;
1406         struct pl08x_txd *txd;
1407         int ret;
1408
1409         txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1410         if (!txd) {
1411                 dev_err(&pl08x->adev->dev,
1412                         "%s no memory for descriptor\n", __func__);
1413                 return NULL;
1414         }
1415
1416         dma_async_tx_descriptor_init(&txd->tx, chan);
1417         txd->direction = DMA_NONE;
1418         txd->srcbus.addr = src;
1419         txd->dstbus.addr = dest;
1420
1421         /* Set platform data for m2m */
1422         txd->cd = &pl08x->pd->memcpy_channel;
1423         /* Both to be incremented or the code will break */
1424         txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1425         txd->tx.tx_submit = pl08x_tx_submit;
1426         txd->tx.callback = NULL;
1427         txd->tx.callback_param = NULL;
1428         txd->len = len;
1429
1430         INIT_LIST_HEAD(&txd->node);
1431         ret = pl08x_prep_channel_resources(plchan, txd);
1432         if (ret)
1433                 return NULL;
1434         /*
1435          * NB: the channel lock is held at this point so tx_submit()
1436          * must be called in direct succession.
1437          */
1438
1439         return &txd->tx;
1440 }
1441
1442 struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1443                 struct dma_chan *chan, struct scatterlist *sgl,
1444                 unsigned int sg_len, enum dma_data_direction direction,
1445                 unsigned long flags)
1446 {
1447         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1448         struct pl08x_driver_data *pl08x = plchan->host;
1449         struct pl08x_txd *txd;
1450         int ret;
1451
1452         /*
1453          * Current implementation ASSUMES only one sg
1454          */
1455         if (sg_len != 1) {
1456                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1457                         __func__);
1458                 BUG();
1459         }
1460
1461         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1462                 __func__, sgl->length, plchan->name);
1463
1464         txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1465         if (!txd) {
1466                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1467                 return NULL;
1468         }
1469
1470         dma_async_tx_descriptor_init(&txd->tx, chan);
1471
1472         if (direction != plchan->runtime_direction)
1473                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1474                         "the direction configured for the PrimeCell\n",
1475                         __func__);
1476
1477         /*
1478          * Set up addresses, the PrimeCell configured address
1479          * will take precedence since this may configure the
1480          * channel target address dynamically at runtime.
1481          */
1482         txd->direction = direction;
1483         if (direction == DMA_TO_DEVICE) {
1484                 txd->srcbus.addr = sgl->dma_address;
1485                 if (plchan->runtime_addr)
1486                         txd->dstbus.addr = plchan->runtime_addr;
1487                 else
1488                         txd->dstbus.addr = plchan->cd->addr;
1489         } else if (direction == DMA_FROM_DEVICE) {
1490                 if (plchan->runtime_addr)
1491                         txd->srcbus.addr = plchan->runtime_addr;
1492                 else
1493                         txd->srcbus.addr = plchan->cd->addr;
1494                 txd->dstbus.addr = sgl->dma_address;
1495         } else {
1496                 dev_err(&pl08x->adev->dev,
1497                         "%s direction unsupported\n", __func__);
1498                 return NULL;
1499         }
1500         txd->cd = plchan->cd;
1501         txd->tx.tx_submit = pl08x_tx_submit;
1502         txd->tx.callback = NULL;
1503         txd->tx.callback_param = NULL;
1504         txd->len = sgl->length;
1505         INIT_LIST_HEAD(&txd->node);
1506
1507         ret = pl08x_prep_channel_resources(plchan, txd);
1508         if (ret)
1509                 return NULL;
1510         /*
1511          * NB: the channel lock is held at this point so tx_submit()
1512          * must be called in direct succession.
1513          */
1514
1515         return &txd->tx;
1516 }
1517
1518 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1519                          unsigned long arg)
1520 {
1521         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1522         struct pl08x_driver_data *pl08x = plchan->host;
1523         unsigned long flags;
1524         int ret = 0;
1525
1526         /* Controls applicable to inactive channels */
1527         if (cmd == DMA_SLAVE_CONFIG) {
1528                 dma_set_runtime_config(chan,
1529                                        (struct dma_slave_config *)
1530                                        arg);
1531                 return 0;
1532         }
1533
1534         /*
1535          * Anything succeeds on channels with no physical allocation and
1536          * no queued transfers.
1537          */
1538         spin_lock_irqsave(&plchan->lock, flags);
1539         if (!plchan->phychan && !plchan->at) {
1540                 spin_unlock_irqrestore(&plchan->lock, flags);
1541                 return 0;
1542         }
1543
1544         switch (cmd) {
1545         case DMA_TERMINATE_ALL:
1546                 plchan->state = PL08X_CHAN_IDLE;
1547
1548                 if (plchan->phychan) {
1549                         pl08x_stop_phy_chan(plchan->phychan);
1550
1551                         /*
1552                          * Mark physical channel as free and free any slave
1553                          * signal
1554                          */
1555                         if ((plchan->phychan->signal >= 0) &&
1556                             pl08x->pd->put_signal) {
1557                                 pl08x->pd->put_signal(plchan);
1558                                 plchan->phychan->signal = -1;
1559                         }
1560                         pl08x_put_phy_channel(pl08x, plchan->phychan);
1561                         plchan->phychan = NULL;
1562                 }
1563                 /* Dequeue jobs and free LLIs */
1564                 if (plchan->at) {
1565                         pl08x_free_txd(pl08x, plchan->at);
1566                         plchan->at = NULL;
1567                 }
1568                 /* Dequeue jobs not yet fired as well */
1569                 pl08x_free_txd_list(pl08x, plchan);
1570                 break;
1571         case DMA_PAUSE:
1572                 pl08x_pause_phy_chan(plchan->phychan);
1573                 plchan->state = PL08X_CHAN_PAUSED;
1574                 break;
1575         case DMA_RESUME:
1576                 pl08x_resume_phy_chan(plchan->phychan);
1577                 plchan->state = PL08X_CHAN_RUNNING;
1578                 break;
1579         default:
1580                 /* Unknown command */
1581                 ret = -ENXIO;
1582                 break;
1583         }
1584
1585         spin_unlock_irqrestore(&plchan->lock, flags);
1586
1587         return ret;
1588 }
1589
1590 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1591 {
1592         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1593         char *name = chan_id;
1594
1595         /* Check that the channel is not taken! */
1596         if (!strcmp(plchan->name, name))
1597                 return true;
1598
1599         return false;
1600 }
1601
1602 /*
1603  * Just check that the device is there and active
1604  * TODO: turn this bit on/off depending on the number of
1605  * physical channels actually used, if it is zero... well
1606  * shut it off. That will save some power. Cut the clock
1607  * at the same time.
1608  */
1609 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1610 {
1611         u32 val;
1612
1613         val = readl(pl08x->base + PL080_CONFIG);
1614         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1615         /* We implicitly clear bit 1 and that means little-endian mode */
1616         val |= PL080_CONFIG_ENABLE;
1617         writel(val, pl08x->base + PL080_CONFIG);
1618 }
1619
1620 static void pl08x_tasklet(unsigned long data)
1621 {
1622         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1623         struct pl08x_phy_chan *phychan = plchan->phychan;
1624         struct pl08x_driver_data *pl08x = plchan->host;
1625         unsigned long flags;
1626
1627         if (!plchan)
1628                 BUG();
1629
1630         spin_lock_irqsave(&plchan->lock, flags);
1631
1632         if (plchan->at) {
1633                 dma_async_tx_callback callback =
1634                         plchan->at->tx.callback;
1635                 void *callback_param =
1636                         plchan->at->tx.callback_param;
1637
1638                 /*
1639                  * Update last completed
1640                  */
1641                 plchan->lc = plchan->at->tx.cookie;
1642
1643                 /*
1644                  * Callback to signal completion
1645                  */
1646                 if (callback)
1647                         callback(callback_param);
1648
1649                 /*
1650                  * Device callbacks should NOT clear
1651                  * the current transaction on the channel
1652                  * Linus: sometimes they should?
1653                  */
1654                 if (!plchan->at)
1655                         BUG();
1656
1657                 /*
1658                  * Free the descriptor if it's not for a device
1659                  * using a circular buffer
1660                  */
1661                 if (!plchan->at->cd->circular_buffer) {
1662                         pl08x_free_txd(pl08x, plchan->at);
1663                         plchan->at = NULL;
1664                 }
1665                 /*
1666                  * else descriptor for circular
1667                  * buffers only freed when
1668                  * client has disabled dma
1669                  */
1670         }
1671         /*
1672          * If a new descriptor is queued, set it up
1673          * plchan->at is NULL here
1674          */
1675         if (!list_empty(&plchan->desc_list)) {
1676                 struct pl08x_txd *next;
1677
1678                 next = list_first_entry(&plchan->desc_list,
1679                                         struct pl08x_txd,
1680                                         node);
1681                 list_del(&next->node);
1682                 plchan->at = next;
1683                 /* Configure the physical channel for the next txd */
1684                 pl08x_config_phychan_for_txd(plchan);
1685                 pl08x_set_cregs(pl08x, plchan->phychan);
1686                 pl08x_enable_phy_chan(pl08x, plchan->phychan);
1687         } else {
1688                 struct pl08x_dma_chan *waiting = NULL;
1689
1690                 /*
1691                  * No more jobs, so free up the physical channel
1692                  * Free any allocated signal on slave transfers too
1693                  */
1694                 if ((phychan->signal >= 0) && pl08x->pd->put_signal) {
1695                         pl08x->pd->put_signal(plchan);
1696                         phychan->signal = -1;
1697                 }
1698                 pl08x_put_phy_channel(pl08x, phychan);
1699                 plchan->phychan = NULL;
1700                 plchan->state = PL08X_CHAN_IDLE;
1701
1702                 /*
1703                  * And NOW before anyone else can grab that free:d
1704                  * up physical channel, see if there is some memcpy
1705                  * pending that seriously needs to start because of
1706                  * being stacked up while we were choking the
1707                  * physical channels with data.
1708                  */
1709                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1710                                     chan.device_node) {
1711                   if (waiting->state == PL08X_CHAN_WAITING &&
1712                             waiting->waiting != NULL) {
1713                                 int ret;
1714
1715                                 /* This should REALLY not fail now */
1716                                 ret = prep_phy_channel(waiting,
1717                                                        waiting->waiting);
1718                                 BUG_ON(ret);
1719                                 waiting->state = PL08X_CHAN_RUNNING;
1720                                 waiting->waiting = NULL;
1721                                 pl08x_issue_pending(&waiting->chan);
1722                                 break;
1723                         }
1724                 }
1725         }
1726
1727         spin_unlock_irqrestore(&plchan->lock, flags);
1728 }
1729
1730 static irqreturn_t pl08x_irq(int irq, void *dev)
1731 {
1732         struct pl08x_driver_data *pl08x = dev;
1733         u32 mask = 0;
1734         u32 val;
1735         int i;
1736
1737         val = readl(pl08x->base + PL080_ERR_STATUS);
1738         if (val) {
1739                 /*
1740                  * An error interrupt (on one or more channels)
1741                  */
1742                 dev_err(&pl08x->adev->dev,
1743                         "%s error interrupt, register value 0x%08x\n",
1744                                 __func__, val);
1745                 /*
1746                  * Simply clear ALL PL08X error interrupts,
1747                  * regardless of channel and cause
1748                  * FIXME: should be 0x00000003 on PL081 really.
1749                  */
1750                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1751         }
1752         val = readl(pl08x->base + PL080_INT_STATUS);
1753         for (i = 0; i < pl08x->vd->channels; i++) {
1754                 if ((1 << i) & val) {
1755                         /* Locate physical channel */
1756                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1757                         struct pl08x_dma_chan *plchan = phychan->serving;
1758
1759                         /* Schedule tasklet on this channel */
1760                         tasklet_schedule(&plchan->tasklet);
1761
1762                         mask |= (1 << i);
1763                 }
1764         }
1765         /*
1766          * Clear only the terminal interrupts on channels we processed
1767          */
1768         writel(mask, pl08x->base + PL080_TC_CLEAR);
1769
1770         return mask ? IRQ_HANDLED : IRQ_NONE;
1771 }
1772
1773 /*
1774  * Initialise the DMAC memcpy/slave channels.
1775  * Make a local wrapper to hold required data
1776  */
1777 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1778                                            struct dma_device *dmadev,
1779                                            unsigned int channels,
1780                                            bool slave)
1781 {
1782         struct pl08x_dma_chan *chan;
1783         int i;
1784
1785         INIT_LIST_HEAD(&dmadev->channels);
1786         /*
1787          * Register as many many memcpy as we have physical channels,
1788          * we won't always be able to use all but the code will have
1789          * to cope with that situation.
1790          */
1791         for (i = 0; i < channels; i++) {
1792                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1793                 if (!chan) {
1794                         dev_err(&pl08x->adev->dev,
1795                                 "%s no memory for channel\n", __func__);
1796                         return -ENOMEM;
1797                 }
1798
1799                 chan->host = pl08x;
1800                 chan->state = PL08X_CHAN_IDLE;
1801
1802                 if (slave) {
1803                         chan->slave = true;
1804                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1805                         chan->cd = &pl08x->pd->slave_channels[i];
1806                 } else {
1807                         chan->cd = &pl08x->pd->memcpy_channel;
1808                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1809                         if (!chan->name) {
1810                                 kfree(chan);
1811                                 return -ENOMEM;
1812                         }
1813                 }
1814                 dev_info(&pl08x->adev->dev,
1815                          "initialize virtual channel \"%s\"\n",
1816                          chan->name);
1817
1818                 chan->chan.device = dmadev;
1819                 chan->chan.cookie = 0;
1820                 chan->lc = 0;
1821
1822                 spin_lock_init(&chan->lock);
1823                 INIT_LIST_HEAD(&chan->desc_list);
1824                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1825                              (unsigned long) chan);
1826
1827                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1828         }
1829         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1830                  i, slave ? "slave" : "memcpy");
1831         return i;
1832 }
1833
1834 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1835 {
1836         struct pl08x_dma_chan *chan = NULL;
1837         struct pl08x_dma_chan *next;
1838
1839         list_for_each_entry_safe(chan,
1840                                  next, &dmadev->channels, chan.device_node) {
1841                 list_del(&chan->chan.device_node);
1842                 kfree(chan);
1843         }
1844 }
1845
1846 #ifdef CONFIG_DEBUG_FS
1847 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1848 {
1849         switch (state) {
1850         case PL08X_CHAN_IDLE:
1851                 return "idle";
1852         case PL08X_CHAN_RUNNING:
1853                 return "running";
1854         case PL08X_CHAN_PAUSED:
1855                 return "paused";
1856         case PL08X_CHAN_WAITING:
1857                 return "waiting";
1858         default:
1859                 break;
1860         }
1861         return "UNKNOWN STATE";
1862 }
1863
1864 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1865 {
1866         struct pl08x_driver_data *pl08x = s->private;
1867         struct pl08x_dma_chan *chan;
1868         struct pl08x_phy_chan *ch;
1869         unsigned long flags;
1870         int i;
1871
1872         seq_printf(s, "PL08x physical channels:\n");
1873         seq_printf(s, "CHANNEL:\tUSER:\n");
1874         seq_printf(s, "--------\t-----\n");
1875         for (i = 0; i < pl08x->vd->channels; i++) {
1876                 struct pl08x_dma_chan *virt_chan;
1877
1878                 ch = &pl08x->phy_chans[i];
1879
1880                 spin_lock_irqsave(&ch->lock, flags);
1881                 virt_chan = ch->serving;
1882
1883                 seq_printf(s, "%d\t\t%s\n",
1884                            ch->id, virt_chan ? virt_chan->name : "(none)");
1885
1886                 spin_unlock_irqrestore(&ch->lock, flags);
1887         }
1888
1889         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1890         seq_printf(s, "CHANNEL:\tSTATE:\n");
1891         seq_printf(s, "--------\t------\n");
1892         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1893                 seq_printf(s, "%s\t\t\%s\n", chan->name,
1894                            pl08x_state_str(chan->state));
1895         }
1896
1897         seq_printf(s, "\nPL08x virtual slave channels:\n");
1898         seq_printf(s, "CHANNEL:\tSTATE:\n");
1899         seq_printf(s, "--------\t------\n");
1900         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1901                 seq_printf(s, "%s\t\t\%s\n", chan->name,
1902                            pl08x_state_str(chan->state));
1903         }
1904
1905         return 0;
1906 }
1907
1908 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1909 {
1910         return single_open(file, pl08x_debugfs_show, inode->i_private);
1911 }
1912
1913 static const struct file_operations pl08x_debugfs_operations = {
1914         .open           = pl08x_debugfs_open,
1915         .read           = seq_read,
1916         .llseek         = seq_lseek,
1917         .release        = single_release,
1918 };
1919
1920 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1921 {
1922         /* Expose a simple debugfs interface to view all clocks */
1923         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1924                                    NULL, pl08x,
1925                                    &pl08x_debugfs_operations);
1926 }
1927
1928 #else
1929 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1930 {
1931 }
1932 #endif
1933
1934 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1935 {
1936         struct pl08x_driver_data *pl08x;
1937         struct vendor_data *vd = id->data;
1938         int ret = 0;
1939         int i;
1940
1941         ret = amba_request_regions(adev, NULL);
1942         if (ret)
1943                 return ret;
1944
1945         /* Create the driver state holder */
1946         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1947         if (!pl08x) {
1948                 ret = -ENOMEM;
1949                 goto out_no_pl08x;
1950         }
1951
1952         /* Initialize memcpy engine */
1953         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1954         pl08x->memcpy.dev = &adev->dev;
1955         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1956         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1957         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1958         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1959         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1960         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1961         pl08x->memcpy.device_control = pl08x_control;
1962
1963         /* Initialize slave engine */
1964         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1965         pl08x->slave.dev = &adev->dev;
1966         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1967         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1968         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1969         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1970         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1971         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1972         pl08x->slave.device_control = pl08x_control;
1973
1974         /* Get the platform data */
1975         pl08x->pd = dev_get_platdata(&adev->dev);
1976         if (!pl08x->pd) {
1977                 dev_err(&adev->dev, "no platform data supplied\n");
1978                 goto out_no_platdata;
1979         }
1980
1981         /* Assign useful pointers to the driver state */
1982         pl08x->adev = adev;
1983         pl08x->vd = vd;
1984
1985         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1986         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1987                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1988         if (!pl08x->pool) {
1989                 ret = -ENOMEM;
1990                 goto out_no_lli_pool;
1991         }
1992
1993         spin_lock_init(&pl08x->lock);
1994
1995         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1996         if (!pl08x->base) {
1997                 ret = -ENOMEM;
1998                 goto out_no_ioremap;
1999         }
2000
2001         /* Turn on the PL08x */
2002         pl08x_ensure_on(pl08x);
2003
2004         /*
2005          * Attach the interrupt handler
2006          */
2007         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2008         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2009
2010         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
2011                           vd->name, pl08x);
2012         if (ret) {
2013                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
2014                         __func__, adev->irq[0]);
2015                 goto out_no_irq;
2016         }
2017
2018         /* Initialize physical channels */
2019         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
2020                         GFP_KERNEL);
2021         if (!pl08x->phy_chans) {
2022                 dev_err(&adev->dev, "%s failed to allocate "
2023                         "physical channel holders\n",
2024                         __func__);
2025                 goto out_no_phychans;
2026         }
2027
2028         for (i = 0; i < vd->channels; i++) {
2029                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2030
2031                 ch->id = i;
2032                 ch->base = pl08x->base + PL080_Cx_BASE(i);
2033                 spin_lock_init(&ch->lock);
2034                 ch->serving = NULL;
2035                 ch->signal = -1;
2036                 dev_info(&adev->dev,
2037                          "physical channel %d is %s\n", i,
2038                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
2039         }
2040
2041         /* Register as many memcpy channels as there are physical channels */
2042         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2043                                               pl08x->vd->channels, false);
2044         if (ret <= 0) {
2045                 dev_warn(&pl08x->adev->dev,
2046                          "%s failed to enumerate memcpy channels - %d\n",
2047                          __func__, ret);
2048                 goto out_no_memcpy;
2049         }
2050         pl08x->memcpy.chancnt = ret;
2051
2052         /* Register slave channels */
2053         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2054                                               pl08x->pd->num_slave_channels,
2055                                               true);
2056         if (ret <= 0) {
2057                 dev_warn(&pl08x->adev->dev,
2058                         "%s failed to enumerate slave channels - %d\n",
2059                                 __func__, ret);
2060                 goto out_no_slave;
2061         }
2062         pl08x->slave.chancnt = ret;
2063
2064         ret = dma_async_device_register(&pl08x->memcpy);
2065         if (ret) {
2066                 dev_warn(&pl08x->adev->dev,
2067                         "%s failed to register memcpy as an async device - %d\n",
2068                         __func__, ret);
2069                 goto out_no_memcpy_reg;
2070         }
2071
2072         ret = dma_async_device_register(&pl08x->slave);
2073         if (ret) {
2074                 dev_warn(&pl08x->adev->dev,
2075                         "%s failed to register slave as an async device - %d\n",
2076                         __func__, ret);
2077                 goto out_no_slave_reg;
2078         }
2079
2080         amba_set_drvdata(adev, pl08x);
2081         init_pl08x_debugfs(pl08x);
2082         dev_info(&pl08x->adev->dev, "ARM(R) %s DMA block initialized @%08x\n",
2083                 vd->name, adev->res.start);
2084         return 0;
2085
2086 out_no_slave_reg:
2087         dma_async_device_unregister(&pl08x->memcpy);
2088 out_no_memcpy_reg:
2089         pl08x_free_virtual_channels(&pl08x->slave);
2090 out_no_slave:
2091         pl08x_free_virtual_channels(&pl08x->memcpy);
2092 out_no_memcpy:
2093         kfree(pl08x->phy_chans);
2094 out_no_phychans:
2095         free_irq(adev->irq[0], pl08x);
2096 out_no_irq:
2097         iounmap(pl08x->base);
2098 out_no_ioremap:
2099         dma_pool_destroy(pl08x->pool);
2100 out_no_lli_pool:
2101 out_no_platdata:
2102         kfree(pl08x);
2103 out_no_pl08x:
2104         amba_release_regions(adev);
2105         return ret;
2106 }
2107
2108 /* PL080 has 8 channels and the PL080 have just 2 */
2109 static struct vendor_data vendor_pl080 = {
2110         .name = "PL080",
2111         .channels = 8,
2112         .dualmaster = true,
2113 };
2114
2115 static struct vendor_data vendor_pl081 = {
2116         .name = "PL081",
2117         .channels = 2,
2118         .dualmaster = false,
2119 };
2120
2121 static struct amba_id pl08x_ids[] = {
2122         /* PL080 */
2123         {
2124                 .id     = 0x00041080,
2125                 .mask   = 0x000fffff,
2126                 .data   = &vendor_pl080,
2127         },
2128         /* PL081 */
2129         {
2130                 .id     = 0x00041081,
2131                 .mask   = 0x000fffff,
2132                 .data   = &vendor_pl081,
2133         },
2134         /* Nomadik 8815 PL080 variant */
2135         {
2136                 .id     = 0x00280880,
2137                 .mask   = 0x00ffffff,
2138                 .data   = &vendor_pl080,
2139         },
2140         { 0, 0 },
2141 };
2142
2143 static struct amba_driver pl08x_amba_driver = {
2144         .drv.name       = DRIVER_NAME,
2145         .id_table       = pl08x_ids,
2146         .probe          = pl08x_probe,
2147 };
2148
2149 static int __init pl08x_init(void)
2150 {
2151         int retval;
2152         retval = amba_driver_register(&pl08x_amba_driver);
2153         if (retval)
2154                 printk(KERN_WARNING DRIVER_NAME
2155                        "failed to register as an AMBA device (%d)\n",
2156                        retval);
2157         return retval;
2158 }
2159 subsys_initcall(pl08x_init);