ARM: PL08x: make pl08x_fill_lli_for_desc() return void
[linux-2.6.git] / drivers / dma / amba-pl08x.c
1 /*
2  * Copyright (c) 2006 ARM Ltd.
3  * Copyright (c) 2010 ST-Ericsson SA
4  *
5  * Author: Peter Pearse <peter.pearse@arm.com>
6  * Author: Linus Walleij <linus.walleij@stericsson.com>
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License as published by the Free
10  * Software Foundation; either version 2 of the License, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program; if not, write to the Free Software Foundation, Inc., 59
20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
21  *
22  * The full GNU General Public License is in this distribution in the
23  * file called COPYING.
24  *
25  * Documentation: ARM DDI 0196G == PL080
26  * Documentation: ARM DDI 0218E == PL081
27  *
28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
29  * any channel.
30  *
31  * The PL080 has 8 channels available for simultaneous use, and the PL081
32  * has only two channels. So on these DMA controllers the number of channels
33  * and the number of incoming DMA signals are two totally different things.
34  * It is usually not possible to theoretically handle all physical signals,
35  * so a multiplexing scheme with possible denial of use is necessary.
36  *
37  * The PL080 has a dual bus master, PL081 has a single master.
38  *
39  * Memory to peripheral transfer may be visualized as
40  *      Get data from memory to DMAC
41  *      Until no data left
42  *              On burst request from peripheral
43  *                      Destination burst from DMAC to peripheral
44  *                      Clear burst request
45  *      Raise terminal count interrupt
46  *
47  * For peripherals with a FIFO:
48  * Source      burst size == half the depth of the peripheral FIFO
49  * Destination burst size == the depth of the peripheral FIFO
50  *
51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
52  * signals, the DMA controller will simply facilitate its AHB master.)
53  *
54  * ASSUMES default (little) endianness for DMA transfers
55  *
56  * The PL08x has two flow control settings:
57  *  - DMAC flow control: the transfer size defines the number of transfers
58  *    which occur for the current LLI entry, and the DMAC raises TC at the
59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
60  *    to both the BREQ and SREQ signals (contrary to documented),
61  *    transferring data if either is active.  The LBREQ and LSREQ signals
62  *    are ignored.
63  *
64  *  - Peripheral flow control: the transfer size is ignored (and should be
65  *    zero).  The data is transferred from the current LLI entry, until
66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
67  *    will then move to the next LLI entry.
68  *
69  * Only the former works sanely with scatter lists, so we only implement
70  * the DMAC flow control method.  However, peripherals which use the LBREQ
71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72  * these hardware restrictions prevents them from using scatter DMA.
73  *
74  * Global TODO:
75  * - Break out common code from arch/arm/mach-s3c64xx and share
76  */
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/dmapool.h>
83 #include <linux/dmaengine.h>
84 #include <linux/amba/bus.h>
85 #include <linux/amba/pl08x.h>
86 #include <linux/debugfs.h>
87 #include <linux/seq_file.h>
88
89 #include <asm/hardware/pl080.h>
90
91 #define DRIVER_NAME     "pl08xdmac"
92
93 /**
94  * struct vendor_data - vendor-specific config parameters
95  * for PL08x derivatives
96  * @channels: the number of channels available in this variant
97  * @dualmaster: whether this version supports dual AHB masters
98  * or not.
99  */
100 struct vendor_data {
101         u8 channels;
102         bool dualmaster;
103 };
104
105 /*
106  * PL08X private data structures
107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
108  * start & end do not - their bus bit info is in cctl.  Also note that these
109  * are fixed 32-bit quantities.
110  */
111 struct pl08x_lli {
112         u32 src;
113         u32 dst;
114         u32 lli;
115         u32 cctl;
116 };
117
118 /**
119  * struct pl08x_driver_data - the local state holder for the PL08x
120  * @slave: slave engine for this instance
121  * @memcpy: memcpy engine for this instance
122  * @base: virtual memory base (remapped) for the PL08x
123  * @adev: the corresponding AMBA (PrimeCell) bus entry
124  * @vd: vendor data for this PL08x variant
125  * @pd: platform data passed in from the platform/machine
126  * @phy_chans: array of data for the physical channels
127  * @pool: a pool for the LLI descriptors
128  * @pool_ctr: counter of LLIs in the pool
129  * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
130  * @mem_buses: set to indicate memory transfers on AHB2.
131  * @lock: a spinlock for this struct
132  */
133 struct pl08x_driver_data {
134         struct dma_device slave;
135         struct dma_device memcpy;
136         void __iomem *base;
137         struct amba_device *adev;
138         const struct vendor_data *vd;
139         struct pl08x_platform_data *pd;
140         struct pl08x_phy_chan *phy_chans;
141         struct dma_pool *pool;
142         int pool_ctr;
143         u8 lli_buses;
144         u8 mem_buses;
145         spinlock_t lock;
146 };
147
148 /*
149  * PL08X specific defines
150  */
151
152 /*
153  * Memory boundaries: the manual for PL08x says that the controller
154  * cannot read past a 1KiB boundary, so these defines are used to
155  * create transfer LLIs that do not cross such boundaries.
156  */
157 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
158 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
159
160 /* Minimum period between work queue runs */
161 #define PL08X_WQ_PERIODMIN      20
162
163 /* Size (bytes) of each LLI buffer allocated for one transfer */
164 # define PL08X_LLI_TSFR_SIZE    0x2000
165
166 /* Maximum times we call dma_pool_alloc on this pool without freeing */
167 #define PL08X_MAX_ALLOCS        0x40
168 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
169 #define PL08X_ALIGN             8
170
171 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
172 {
173         return container_of(chan, struct pl08x_dma_chan, chan);
174 }
175
176 /*
177  * Physical channel handling
178  */
179
180 /* Whether a certain channel is busy or not */
181 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
182 {
183         unsigned int val;
184
185         val = readl(ch->base + PL080_CH_CONFIG);
186         return val & PL080_CONFIG_ACTIVE;
187 }
188
189 /*
190  * Set the initial DMA register values i.e. those for the first LLI
191  * The next LLI pointer and the configuration interrupt bit have
192  * been set when the LLIs were constructed.  Poke them into the hardware
193  * and start the transfer.
194  */
195 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
196         struct pl08x_txd *txd)
197 {
198         struct pl08x_driver_data *pl08x = plchan->host;
199         struct pl08x_phy_chan *phychan = plchan->phychan;
200         struct pl08x_lli *lli = &txd->llis_va[0];
201         u32 val;
202
203         plchan->at = txd;
204
205         /* Wait for channel inactive */
206         while (pl08x_phy_channel_busy(phychan))
207                 cpu_relax();
208
209         dev_vdbg(&pl08x->adev->dev,
210                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
211                 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
212                 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
213                 txd->ccfg);
214
215         writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
216         writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
217         writel(lli->lli, phychan->base + PL080_CH_LLI);
218         writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
219         writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
220
221         /* Enable the DMA channel */
222         /* Do not access config register until channel shows as disabled */
223         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
224                 cpu_relax();
225
226         /* Do not access config register until channel shows as inactive */
227         val = readl(phychan->base + PL080_CH_CONFIG);
228         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
229                 val = readl(phychan->base + PL080_CH_CONFIG);
230
231         writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
232 }
233
234 /*
235  * Overall DMAC remains enabled always.
236  *
237  * Disabling individual channels could lose data.
238  *
239  * Disable the peripheral DMA after disabling the DMAC
240  * in order to allow the DMAC FIFO to drain, and
241  * hence allow the channel to show inactive
242  *
243  */
244 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
245 {
246         u32 val;
247
248         /* Set the HALT bit and wait for the FIFO to drain */
249         val = readl(ch->base + PL080_CH_CONFIG);
250         val |= PL080_CONFIG_HALT;
251         writel(val, ch->base + PL080_CH_CONFIG);
252
253         /* Wait for channel inactive */
254         while (pl08x_phy_channel_busy(ch))
255                 cpu_relax();
256 }
257
258 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
259 {
260         u32 val;
261
262         /* Clear the HALT bit */
263         val = readl(ch->base + PL080_CH_CONFIG);
264         val &= ~PL080_CONFIG_HALT;
265         writel(val, ch->base + PL080_CH_CONFIG);
266 }
267
268
269 /* Stops the channel */
270 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
271 {
272         u32 val;
273
274         pl08x_pause_phy_chan(ch);
275
276         /* Disable channel */
277         val = readl(ch->base + PL080_CH_CONFIG);
278         val &= ~PL080_CONFIG_ENABLE;
279         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
280         val &= ~PL080_CONFIG_TC_IRQ_MASK;
281         writel(val, ch->base + PL080_CH_CONFIG);
282 }
283
284 static inline u32 get_bytes_in_cctl(u32 cctl)
285 {
286         /* The source width defines the number of bytes */
287         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
288
289         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
290         case PL080_WIDTH_8BIT:
291                 break;
292         case PL080_WIDTH_16BIT:
293                 bytes *= 2;
294                 break;
295         case PL080_WIDTH_32BIT:
296                 bytes *= 4;
297                 break;
298         }
299         return bytes;
300 }
301
302 /* The channel should be paused when calling this */
303 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
304 {
305         struct pl08x_phy_chan *ch;
306         struct pl08x_txd *txd;
307         unsigned long flags;
308         size_t bytes = 0;
309
310         spin_lock_irqsave(&plchan->lock, flags);
311         ch = plchan->phychan;
312         txd = plchan->at;
313
314         /*
315          * Follow the LLIs to get the number of remaining
316          * bytes in the currently active transaction.
317          */
318         if (ch && txd) {
319                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
320
321                 /* First get the remaining bytes in the active transfer */
322                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
323
324                 if (clli) {
325                         struct pl08x_lli *llis_va = txd->llis_va;
326                         dma_addr_t llis_bus = txd->llis_bus;
327                         int index;
328
329                         BUG_ON(clli < llis_bus || clli >= llis_bus +
330                                 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
331
332                         /*
333                          * Locate the next LLI - as this is an array,
334                          * it's simple maths to find.
335                          */
336                         index = (clli - llis_bus) / sizeof(struct pl08x_lli);
337
338                         for (; index < MAX_NUM_TSFR_LLIS; index++) {
339                                 bytes += get_bytes_in_cctl(llis_va[index].cctl);
340
341                                 /*
342                                  * A LLI pointer of 0 terminates the LLI list
343                                  */
344                                 if (!llis_va[index].lli)
345                                         break;
346                         }
347                 }
348         }
349
350         /* Sum up all queued transactions */
351         if (!list_empty(&plchan->desc_list)) {
352                 struct pl08x_txd *txdi;
353                 list_for_each_entry(txdi, &plchan->desc_list, node) {
354                         bytes += txdi->len;
355                 }
356         }
357
358         spin_unlock_irqrestore(&plchan->lock, flags);
359
360         return bytes;
361 }
362
363 /*
364  * Allocate a physical channel for a virtual channel
365  */
366 static struct pl08x_phy_chan *
367 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
368                       struct pl08x_dma_chan *virt_chan)
369 {
370         struct pl08x_phy_chan *ch = NULL;
371         unsigned long flags;
372         int i;
373
374         /*
375          * Try to locate a physical channel to be used for
376          * this transfer. If all are taken return NULL and
377          * the requester will have to cope by using some fallback
378          * PIO mode or retrying later.
379          */
380         for (i = 0; i < pl08x->vd->channels; i++) {
381                 ch = &pl08x->phy_chans[i];
382
383                 spin_lock_irqsave(&ch->lock, flags);
384
385                 if (!ch->serving) {
386                         ch->serving = virt_chan;
387                         ch->signal = -1;
388                         spin_unlock_irqrestore(&ch->lock, flags);
389                         break;
390                 }
391
392                 spin_unlock_irqrestore(&ch->lock, flags);
393         }
394
395         if (i == pl08x->vd->channels) {
396                 /* No physical channel available, cope with it */
397                 return NULL;
398         }
399
400         return ch;
401 }
402
403 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
404                                          struct pl08x_phy_chan *ch)
405 {
406         unsigned long flags;
407
408         /* Stop the channel and clear its interrupts */
409         pl08x_stop_phy_chan(ch);
410         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
411         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
412
413         /* Mark it as free */
414         spin_lock_irqsave(&ch->lock, flags);
415         ch->serving = NULL;
416         spin_unlock_irqrestore(&ch->lock, flags);
417 }
418
419 /*
420  * LLI handling
421  */
422
423 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
424 {
425         switch (coded) {
426         case PL080_WIDTH_8BIT:
427                 return 1;
428         case PL080_WIDTH_16BIT:
429                 return 2;
430         case PL080_WIDTH_32BIT:
431                 return 4;
432         default:
433                 break;
434         }
435         BUG();
436         return 0;
437 }
438
439 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
440                                   size_t tsize)
441 {
442         u32 retbits = cctl;
443
444         /* Remove all src, dst and transfer size bits */
445         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
446         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
447         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
448
449         /* Then set the bits according to the parameters */
450         switch (srcwidth) {
451         case 1:
452                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
453                 break;
454         case 2:
455                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
456                 break;
457         case 4:
458                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
459                 break;
460         default:
461                 BUG();
462                 break;
463         }
464
465         switch (dstwidth) {
466         case 1:
467                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
468                 break;
469         case 2:
470                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
471                 break;
472         case 4:
473                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
474                 break;
475         default:
476                 BUG();
477                 break;
478         }
479
480         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
481         return retbits;
482 }
483
484 /*
485  * Autoselect a master bus to use for the transfer
486  * this prefers the destination bus if both available
487  * if fixed address on one bus the other will be chosen
488  */
489 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
490         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
491         struct pl08x_bus_data **sbus, u32 cctl)
492 {
493         if (!(cctl & PL080_CONTROL_DST_INCR)) {
494                 *mbus = src_bus;
495                 *sbus = dst_bus;
496         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
497                 *mbus = dst_bus;
498                 *sbus = src_bus;
499         } else {
500                 if (dst_bus->buswidth == 4) {
501                         *mbus = dst_bus;
502                         *sbus = src_bus;
503                 } else if (src_bus->buswidth == 4) {
504                         *mbus = src_bus;
505                         *sbus = dst_bus;
506                 } else if (dst_bus->buswidth == 2) {
507                         *mbus = dst_bus;
508                         *sbus = src_bus;
509                 } else if (src_bus->buswidth == 2) {
510                         *mbus = src_bus;
511                         *sbus = dst_bus;
512                 } else {
513                         /* src_bus->buswidth == 1 */
514                         *mbus = dst_bus;
515                         *sbus = src_bus;
516                 }
517         }
518 }
519
520 /*
521  * Fills in one LLI for a certain transfer descriptor
522  * and advance the counter
523  */
524 static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
525         struct pl08x_txd *txd, int num_llis, int len, u32 cctl, u32 *remainder)
526 {
527         struct pl08x_lli *llis_va = txd->llis_va;
528         dma_addr_t llis_bus = txd->llis_bus;
529
530         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
531
532         llis_va[num_llis].cctl = cctl;
533         llis_va[num_llis].src = txd->srcbus.addr;
534         llis_va[num_llis].dst = txd->dstbus.addr;
535         llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
536         if (pl08x->lli_buses & PL08X_AHB2)
537                 llis_va[num_llis].lli |= PL080_LLI_LM_AHB2;
538
539         if (cctl & PL080_CONTROL_SRC_INCR)
540                 txd->srcbus.addr += len;
541         if (cctl & PL080_CONTROL_DST_INCR)
542                 txd->dstbus.addr += len;
543
544         BUG_ON(*remainder < len);
545
546         *remainder -= len;
547 }
548
549 /*
550  * Return number of bytes to fill to boundary, or len
551  */
552 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
553 {
554         u32 boundary;
555
556         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
557                 << PL08X_BOUNDARY_SHIFT;
558
559         if (boundary < addr + len)
560                 return boundary - addr;
561         else
562                 return len;
563 }
564
565 /*
566  * This fills in the table of LLIs for the transfer descriptor
567  * Note that we assume we never have to change the burst sizes
568  * Return 0 for error
569  */
570 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
571                               struct pl08x_txd *txd)
572 {
573         struct pl08x_bus_data *mbus, *sbus;
574         size_t remainder;
575         int num_llis = 0;
576         u32 cctl;
577         size_t max_bytes_per_lli;
578         size_t total_bytes = 0;
579         struct pl08x_lli *llis_va;
580
581         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
582                                       &txd->llis_bus);
583         if (!txd->llis_va) {
584                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
585                 return 0;
586         }
587
588         pl08x->pool_ctr++;
589
590         /* Get the default CCTL */
591         cctl = txd->cctl;
592
593         /* Find maximum width of the source bus */
594         txd->srcbus.maxwidth =
595                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
596                                        PL080_CONTROL_SWIDTH_SHIFT);
597
598         /* Find maximum width of the destination bus */
599         txd->dstbus.maxwidth =
600                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
601                                        PL080_CONTROL_DWIDTH_SHIFT);
602
603         /* Set up the bus widths to the maximum */
604         txd->srcbus.buswidth = txd->srcbus.maxwidth;
605         txd->dstbus.buswidth = txd->dstbus.maxwidth;
606         dev_vdbg(&pl08x->adev->dev,
607                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
608                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
609
610
611         /*
612          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
613          */
614         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
615                 PL080_CONTROL_TRANSFER_SIZE_MASK;
616         dev_vdbg(&pl08x->adev->dev,
617                  "%s max bytes per lli = %zu\n",
618                  __func__, max_bytes_per_lli);
619
620         /* We need to count this down to zero */
621         remainder = txd->len;
622         dev_vdbg(&pl08x->adev->dev,
623                  "%s remainder = %zu\n",
624                  __func__, remainder);
625
626         /*
627          * Choose bus to align to
628          * - prefers destination bus if both available
629          * - if fixed address on one bus chooses other
630          * - modifies cctl to choose an appropriate master
631          */
632         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
633                                 &mbus, &sbus, cctl);
634
635         if (txd->len < mbus->buswidth) {
636                 /*
637                  * Less than a bus width available
638                  * - send as single bytes
639                  */
640                 while (remainder) {
641                         dev_vdbg(&pl08x->adev->dev,
642                                  "%s single byte LLIs for a transfer of "
643                                  "less than a bus width (remain 0x%08x)\n",
644                                  __func__, remainder);
645                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
646                         pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1,
647                                         cctl, &remainder);
648                         total_bytes++;
649                 }
650         } else {
651                 /*
652                  *  Make one byte LLIs until master bus is aligned
653                  *  - slave will then be aligned also
654                  */
655                 while ((mbus->addr) % (mbus->buswidth)) {
656                         dev_vdbg(&pl08x->adev->dev,
657                                 "%s adjustment lli for less than bus width "
658                                  "(remain 0x%08x)\n",
659                                  __func__, remainder);
660                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
661                         pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1,
662                                         cctl, &remainder);
663                         total_bytes++;
664                 }
665
666                 /*
667                  *  Master now aligned
668                  * - if slave is not then we must set its width down
669                  */
670                 if (sbus->addr % sbus->buswidth) {
671                         dev_dbg(&pl08x->adev->dev,
672                                 "%s set down bus width to one byte\n",
673                                  __func__);
674
675                         sbus->buswidth = 1;
676                 }
677
678                 /*
679                  * Make largest possible LLIs until less than one bus
680                  * width left
681                  */
682                 while (remainder > (mbus->buswidth - 1)) {
683                         size_t lli_len, target_len, tsize, odd_bytes;
684
685                         /*
686                          * If enough left try to send max possible,
687                          * otherwise try to send the remainder
688                          */
689                         target_len = remainder;
690                         if (remainder > max_bytes_per_lli)
691                                 target_len = max_bytes_per_lli;
692
693                         /*
694                          * Set bus lengths for incrementing buses
695                          * to number of bytes which fill to next memory
696                          * boundary
697                          */
698                         if (cctl & PL080_CONTROL_SRC_INCR)
699                                 txd->srcbus.fill_bytes =
700                                         pl08x_pre_boundary(
701                                                 txd->srcbus.addr,
702                                                 remainder);
703                         else
704                                 txd->srcbus.fill_bytes =
705                                         max_bytes_per_lli;
706
707                         if (cctl & PL080_CONTROL_DST_INCR)
708                                 txd->dstbus.fill_bytes =
709                                         pl08x_pre_boundary(
710                                                 txd->dstbus.addr,
711                                                 remainder);
712                         else
713                                 txd->dstbus.fill_bytes =
714                                                 max_bytes_per_lli;
715
716                         /*
717                          *  Find the nearest
718                          */
719                         lli_len = min(txd->srcbus.fill_bytes,
720                                 txd->dstbus.fill_bytes);
721
722                         BUG_ON(lli_len > remainder);
723
724                         if (lli_len <= 0) {
725                                 dev_err(&pl08x->adev->dev,
726                                         "%s lli_len is %zu, <= 0\n",
727                                                 __func__, lli_len);
728                                 return 0;
729                         }
730
731                         if (lli_len == target_len) {
732                                 /*
733                                  * Can send what we wanted
734                                  */
735                                 /*
736                                  *  Maintain alignment
737                                  */
738                                 lli_len = (lli_len/mbus->buswidth) *
739                                                         mbus->buswidth;
740                                 odd_bytes = 0;
741                         } else {
742                                 /*
743                                  * So now we know how many bytes to transfer
744                                  * to get to the nearest boundary
745                                  * The next LLI will past the boundary
746                                  * - however we may be working to a boundary
747                                  *   on the slave bus
748                                  *   We need to ensure the master stays aligned
749                                  */
750                                 odd_bytes = lli_len % mbus->buswidth;
751                                 /*
752                                  * - and that we are working in multiples
753                                  *   of the bus widths
754                                  */
755                                 lli_len -= odd_bytes;
756
757                         }
758
759                         if (lli_len) {
760                                 /*
761                                  * Check against minimum bus alignment:
762                                  * Calculate actual transfer size in relation
763                                  * to bus width an get a maximum remainder of
764                                  * the smallest bus width - 1
765                                  */
766                                 /* FIXME: use round_down()? */
767                                 tsize = lli_len / min(mbus->buswidth,
768                                                       sbus->buswidth);
769                                 lli_len = tsize * min(mbus->buswidth,
770                                                       sbus->buswidth);
771
772                                 if (target_len != lli_len) {
773                                         dev_vdbg(&pl08x->adev->dev,
774                                         "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
775                                         __func__, target_len, lli_len, txd->len);
776                                 }
777
778                                 cctl = pl08x_cctl_bits(cctl,
779                                                        txd->srcbus.buswidth,
780                                                        txd->dstbus.buswidth,
781                                                        tsize);
782
783                                 dev_vdbg(&pl08x->adev->dev,
784                                         "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
785                                         __func__, lli_len, remainder);
786                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis++,
787                                                 lli_len, cctl, &remainder);
788                                 total_bytes += lli_len;
789                         }
790
791
792                         if (odd_bytes) {
793                                 /*
794                                  * Creep past the boundary,
795                                  * maintaining master alignment
796                                  */
797                                 int j;
798                                 for (j = 0; (j < mbus->buswidth)
799                                                 && (remainder); j++) {
800                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
801                                         dev_vdbg(&pl08x->adev->dev,
802                                                 "%s align with boundary, single byte (remain 0x%08zx)\n",
803                                                 __func__, remainder);
804                                         pl08x_fill_lli_for_desc(pl08x, txd,
805                                                         num_llis++, 1, cctl,
806                                                         &remainder);
807                                         total_bytes++;
808                                 }
809                         }
810                 }
811
812                 /*
813                  * Send any odd bytes
814                  */
815                 while (remainder) {
816                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
817                         dev_vdbg(&pl08x->adev->dev,
818                                 "%s align with boundary, single odd byte (remain %zu)\n",
819                                 __func__, remainder);
820                         pl08x_fill_lli_for_desc(pl08x, txd, num_llis++, 1,
821                                         cctl, &remainder);
822                         total_bytes++;
823                 }
824         }
825         if (total_bytes != txd->len) {
826                 dev_err(&pl08x->adev->dev,
827                         "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
828                         __func__, total_bytes, txd->len);
829                 return 0;
830         }
831
832         if (num_llis >= MAX_NUM_TSFR_LLIS) {
833                 dev_err(&pl08x->adev->dev,
834                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
835                         __func__, (u32) MAX_NUM_TSFR_LLIS);
836                 return 0;
837         }
838
839         llis_va = txd->llis_va;
840         /*
841          * The final LLI terminates the LLI.
842          */
843         llis_va[num_llis - 1].lli = 0;
844         /*
845          * The final LLI element shall also fire an interrupt
846          */
847         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
848
849 #ifdef VERBOSE_DEBUG
850         {
851                 int i;
852
853                 for (i = 0; i < num_llis; i++) {
854                         dev_vdbg(&pl08x->adev->dev,
855                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
856                                  i,
857                                  &llis_va[i],
858                                  llis_va[i].src,
859                                  llis_va[i].dst,
860                                  llis_va[i].cctl,
861                                  llis_va[i].lli
862                                 );
863                 }
864         }
865 #endif
866
867         return num_llis;
868 }
869
870 /* You should call this with the struct pl08x lock held */
871 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
872                            struct pl08x_txd *txd)
873 {
874         /* Free the LLI */
875         dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
876
877         pl08x->pool_ctr--;
878
879         kfree(txd);
880 }
881
882 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
883                                 struct pl08x_dma_chan *plchan)
884 {
885         struct pl08x_txd *txdi = NULL;
886         struct pl08x_txd *next;
887
888         if (!list_empty(&plchan->desc_list)) {
889                 list_for_each_entry_safe(txdi,
890                                          next, &plchan->desc_list, node) {
891                         list_del(&txdi->node);
892                         pl08x_free_txd(pl08x, txdi);
893                 }
894
895         }
896 }
897
898 /*
899  * The DMA ENGINE API
900  */
901 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
902 {
903         return 0;
904 }
905
906 static void pl08x_free_chan_resources(struct dma_chan *chan)
907 {
908 }
909
910 /*
911  * This should be called with the channel plchan->lock held
912  */
913 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
914                             struct pl08x_txd *txd)
915 {
916         struct pl08x_driver_data *pl08x = plchan->host;
917         struct pl08x_phy_chan *ch;
918         int ret;
919
920         /* Check if we already have a channel */
921         if (plchan->phychan)
922                 return 0;
923
924         ch = pl08x_get_phy_channel(pl08x, plchan);
925         if (!ch) {
926                 /* No physical channel available, cope with it */
927                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
928                 return -EBUSY;
929         }
930
931         /*
932          * OK we have a physical channel: for memcpy() this is all we
933          * need, but for slaves the physical signals may be muxed!
934          * Can the platform allow us to use this channel?
935          */
936         if (plchan->slave &&
937             ch->signal < 0 &&
938             pl08x->pd->get_signal) {
939                 ret = pl08x->pd->get_signal(plchan);
940                 if (ret < 0) {
941                         dev_dbg(&pl08x->adev->dev,
942                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
943                                 ch->id, plchan->name);
944                         /* Release physical channel & return */
945                         pl08x_put_phy_channel(pl08x, ch);
946                         return -EBUSY;
947                 }
948                 ch->signal = ret;
949
950                 /* Assign the flow control signal to this channel */
951                 if (txd->direction == DMA_TO_DEVICE)
952                         txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
953                 else if (txd->direction == DMA_FROM_DEVICE)
954                         txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
955         }
956
957         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
958                  ch->id,
959                  ch->signal,
960                  plchan->name);
961
962         plchan->phychan = ch;
963
964         return 0;
965 }
966
967 static void release_phy_channel(struct pl08x_dma_chan *plchan)
968 {
969         struct pl08x_driver_data *pl08x = plchan->host;
970
971         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
972                 pl08x->pd->put_signal(plchan);
973                 plchan->phychan->signal = -1;
974         }
975         pl08x_put_phy_channel(pl08x, plchan->phychan);
976         plchan->phychan = NULL;
977 }
978
979 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
980 {
981         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
982
983         plchan->chan.cookie += 1;
984         if (plchan->chan.cookie < 0)
985                 plchan->chan.cookie = 1;
986         tx->cookie = plchan->chan.cookie;
987         /* This unlock follows the lock in the prep() function */
988         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
989
990         return tx->cookie;
991 }
992
993 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
994                 struct dma_chan *chan, unsigned long flags)
995 {
996         struct dma_async_tx_descriptor *retval = NULL;
997
998         return retval;
999 }
1000
1001 /*
1002  * Code accessing dma_async_is_complete() in a tight loop
1003  * may give problems - could schedule where indicated.
1004  * If slaves are relying on interrupts to signal completion this
1005  * function must not be called with interrupts disabled
1006  */
1007 static enum dma_status
1008 pl08x_dma_tx_status(struct dma_chan *chan,
1009                     dma_cookie_t cookie,
1010                     struct dma_tx_state *txstate)
1011 {
1012         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1013         dma_cookie_t last_used;
1014         dma_cookie_t last_complete;
1015         enum dma_status ret;
1016         u32 bytesleft = 0;
1017
1018         last_used = plchan->chan.cookie;
1019         last_complete = plchan->lc;
1020
1021         ret = dma_async_is_complete(cookie, last_complete, last_used);
1022         if (ret == DMA_SUCCESS) {
1023                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1024                 return ret;
1025         }
1026
1027         /*
1028          * schedule(); could be inserted here
1029          */
1030
1031         /*
1032          * This cookie not complete yet
1033          */
1034         last_used = plchan->chan.cookie;
1035         last_complete = plchan->lc;
1036
1037         /* Get number of bytes left in the active transactions and queue */
1038         bytesleft = pl08x_getbytes_chan(plchan);
1039
1040         dma_set_tx_state(txstate, last_complete, last_used,
1041                          bytesleft);
1042
1043         if (plchan->state == PL08X_CHAN_PAUSED)
1044                 return DMA_PAUSED;
1045
1046         /* Whether waiting or running, we're in progress */
1047         return DMA_IN_PROGRESS;
1048 }
1049
1050 /* PrimeCell DMA extension */
1051 struct burst_table {
1052         int burstwords;
1053         u32 reg;
1054 };
1055
1056 static const struct burst_table burst_sizes[] = {
1057         {
1058                 .burstwords = 256,
1059                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1060                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1061         },
1062         {
1063                 .burstwords = 128,
1064                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1065                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1066         },
1067         {
1068                 .burstwords = 64,
1069                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1070                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1071         },
1072         {
1073                 .burstwords = 32,
1074                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1075                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1076         },
1077         {
1078                 .burstwords = 16,
1079                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1080                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1081         },
1082         {
1083                 .burstwords = 8,
1084                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1085                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1086         },
1087         {
1088                 .burstwords = 4,
1089                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1090                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1091         },
1092         {
1093                 .burstwords = 1,
1094                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1095                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1096         },
1097 };
1098
1099 static void dma_set_runtime_config(struct dma_chan *chan,
1100                                struct dma_slave_config *config)
1101 {
1102         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1103         struct pl08x_driver_data *pl08x = plchan->host;
1104         struct pl08x_channel_data *cd = plchan->cd;
1105         enum dma_slave_buswidth addr_width;
1106         u32 maxburst;
1107         u32 cctl = 0;
1108         int i;
1109
1110         /* Transfer direction */
1111         plchan->runtime_direction = config->direction;
1112         if (config->direction == DMA_TO_DEVICE) {
1113                 plchan->runtime_addr = config->dst_addr;
1114                 addr_width = config->dst_addr_width;
1115                 maxburst = config->dst_maxburst;
1116         } else if (config->direction == DMA_FROM_DEVICE) {
1117                 plchan->runtime_addr = config->src_addr;
1118                 addr_width = config->src_addr_width;
1119                 maxburst = config->src_maxburst;
1120         } else {
1121                 dev_err(&pl08x->adev->dev,
1122                         "bad runtime_config: alien transfer direction\n");
1123                 return;
1124         }
1125
1126         switch (addr_width) {
1127         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1128                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1129                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1130                 break;
1131         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1132                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1133                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1134                 break;
1135         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1136                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1137                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1138                 break;
1139         default:
1140                 dev_err(&pl08x->adev->dev,
1141                         "bad runtime_config: alien address width\n");
1142                 return;
1143         }
1144
1145         /*
1146          * Now decide on a maxburst:
1147          * If this channel will only request single transfers, set this
1148          * down to ONE element.  Also select one element if no maxburst
1149          * is specified.
1150          */
1151         if (plchan->cd->single || maxburst == 0) {
1152                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1153                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1154         } else {
1155                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1156                         if (burst_sizes[i].burstwords <= maxburst)
1157                                 break;
1158                 cctl |= burst_sizes[i].reg;
1159         }
1160
1161         /* Modify the default channel data to fit PrimeCell request */
1162         cd->cctl = cctl;
1163
1164         dev_dbg(&pl08x->adev->dev,
1165                 "configured channel %s (%s) for %s, data width %d, "
1166                 "maxburst %d words, LE, CCTL=0x%08x\n",
1167                 dma_chan_name(chan), plchan->name,
1168                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1169                 addr_width,
1170                 maxburst,
1171                 cctl);
1172 }
1173
1174 /*
1175  * Slave transactions callback to the slave device to allow
1176  * synchronization of slave DMA signals with the DMAC enable
1177  */
1178 static void pl08x_issue_pending(struct dma_chan *chan)
1179 {
1180         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1181         unsigned long flags;
1182
1183         spin_lock_irqsave(&plchan->lock, flags);
1184         /* Something is already active, or we're waiting for a channel... */
1185         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1186                 spin_unlock_irqrestore(&plchan->lock, flags);
1187                 return;
1188         }
1189
1190         /* Take the first element in the queue and execute it */
1191         if (!list_empty(&plchan->desc_list)) {
1192                 struct pl08x_txd *next;
1193
1194                 next = list_first_entry(&plchan->desc_list,
1195                                         struct pl08x_txd,
1196                                         node);
1197                 list_del(&next->node);
1198                 plchan->state = PL08X_CHAN_RUNNING;
1199
1200                 pl08x_start_txd(plchan, next);
1201         }
1202
1203         spin_unlock_irqrestore(&plchan->lock, flags);
1204 }
1205
1206 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1207                                         struct pl08x_txd *txd)
1208 {
1209         int num_llis;
1210         struct pl08x_driver_data *pl08x = plchan->host;
1211         int ret;
1212
1213         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1214         if (!num_llis) {
1215                 kfree(txd);
1216                 return -EINVAL;
1217         }
1218
1219         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1220
1221         list_add_tail(&txd->node, &plchan->desc_list);
1222
1223         /*
1224          * See if we already have a physical channel allocated,
1225          * else this is the time to try to get one.
1226          */
1227         ret = prep_phy_channel(plchan, txd);
1228         if (ret) {
1229                 /*
1230                  * No physical channel available, we will
1231                  * stack up the memcpy channels until there is a channel
1232                  * available to handle it whereas slave transfers may
1233                  * have been denied due to platform channel muxing restrictions
1234                  * and since there is no guarantee that this will ever be
1235                  * resolved, and since the signal must be acquired AFTER
1236                  * acquiring the physical channel, we will let them be NACK:ed
1237                  * with -EBUSY here. The drivers can alway retry the prep()
1238                  * call if they are eager on doing this using DMA.
1239                  */
1240                 if (plchan->slave) {
1241                         pl08x_free_txd_list(pl08x, plchan);
1242                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1243                         return -EBUSY;
1244                 }
1245                 /* Do this memcpy whenever there is a channel ready */
1246                 plchan->state = PL08X_CHAN_WAITING;
1247                 plchan->waiting = txd;
1248         } else
1249                 /*
1250                  * Else we're all set, paused and ready to roll,
1251                  * status will switch to PL08X_CHAN_RUNNING when
1252                  * we call issue_pending(). If there is something
1253                  * running on the channel already we don't change
1254                  * its state.
1255                  */
1256                 if (plchan->state == PL08X_CHAN_IDLE)
1257                         plchan->state = PL08X_CHAN_PAUSED;
1258
1259         /*
1260          * Notice that we leave plchan->lock locked on purpose:
1261          * it will be unlocked in the subsequent tx_submit()
1262          * call. This is a consequence of the current API.
1263          */
1264
1265         return 0;
1266 }
1267
1268 /*
1269  * Given the source and destination available bus masks, select which
1270  * will be routed to each port.  We try to have source and destination
1271  * on separate ports, but always respect the allowable settings.
1272  */
1273 static u32 pl08x_select_bus(struct pl08x_driver_data *pl08x, u8 src, u8 dst)
1274 {
1275         u32 cctl = 0;
1276
1277         if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1278                 cctl |= PL080_CONTROL_DST_AHB2;
1279         if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1280                 cctl |= PL080_CONTROL_SRC_AHB2;
1281
1282         return cctl;
1283 }
1284
1285 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1286 {
1287         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1288
1289         if (txd) {
1290                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1291                 txd->tx.tx_submit = pl08x_tx_submit;
1292                 INIT_LIST_HEAD(&txd->node);
1293
1294                 /* Always enable error and terminal interrupts */
1295                 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1296                             PL080_CONFIG_TC_IRQ_MASK;
1297         }
1298         return txd;
1299 }
1300
1301 /*
1302  * Initialize a descriptor to be used by memcpy submit
1303  */
1304 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1305                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1306                 size_t len, unsigned long flags)
1307 {
1308         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1309         struct pl08x_driver_data *pl08x = plchan->host;
1310         struct pl08x_txd *txd;
1311         int ret;
1312
1313         txd = pl08x_get_txd(plchan);
1314         if (!txd) {
1315                 dev_err(&pl08x->adev->dev,
1316                         "%s no memory for descriptor\n", __func__);
1317                 return NULL;
1318         }
1319
1320         txd->direction = DMA_NONE;
1321         txd->srcbus.addr = src;
1322         txd->dstbus.addr = dest;
1323         txd->len = len;
1324
1325         /* Set platform data for m2m */
1326         txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1327         txd->cctl = pl08x->pd->memcpy_channel.cctl &
1328                         ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1329
1330         /* Both to be incremented or the code will break */
1331         txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1332
1333         if (pl08x->vd->dualmaster)
1334                 txd->cctl |= pl08x_select_bus(pl08x,
1335                                         pl08x->mem_buses, pl08x->mem_buses);
1336
1337         ret = pl08x_prep_channel_resources(plchan, txd);
1338         if (ret)
1339                 return NULL;
1340         /*
1341          * NB: the channel lock is held at this point so tx_submit()
1342          * must be called in direct succession.
1343          */
1344
1345         return &txd->tx;
1346 }
1347
1348 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1349                 struct dma_chan *chan, struct scatterlist *sgl,
1350                 unsigned int sg_len, enum dma_data_direction direction,
1351                 unsigned long flags)
1352 {
1353         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1354         struct pl08x_driver_data *pl08x = plchan->host;
1355         struct pl08x_txd *txd;
1356         u8 src_buses, dst_buses;
1357         int ret;
1358
1359         /*
1360          * Current implementation ASSUMES only one sg
1361          */
1362         if (sg_len != 1) {
1363                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1364                         __func__);
1365                 BUG();
1366         }
1367
1368         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1369                 __func__, sgl->length, plchan->name);
1370
1371         txd = pl08x_get_txd(plchan);
1372         if (!txd) {
1373                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1374                 return NULL;
1375         }
1376
1377         if (direction != plchan->runtime_direction)
1378                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1379                         "the direction configured for the PrimeCell\n",
1380                         __func__);
1381
1382         /*
1383          * Set up addresses, the PrimeCell configured address
1384          * will take precedence since this may configure the
1385          * channel target address dynamically at runtime.
1386          */
1387         txd->direction = direction;
1388         txd->len = sgl->length;
1389
1390         txd->cctl = plchan->cd->cctl &
1391                         ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1392                           PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1393                           PL080_CONTROL_PROT_MASK);
1394
1395         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1396         txd->cctl |= PL080_CONTROL_PROT_SYS;
1397
1398         if (direction == DMA_TO_DEVICE) {
1399                 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1400                 txd->cctl |= PL080_CONTROL_SRC_INCR;
1401                 txd->srcbus.addr = sgl->dma_address;
1402                 if (plchan->runtime_addr)
1403                         txd->dstbus.addr = plchan->runtime_addr;
1404                 else
1405                         txd->dstbus.addr = plchan->cd->addr;
1406                 src_buses = pl08x->mem_buses;
1407                 dst_buses = plchan->cd->periph_buses;
1408         } else if (direction == DMA_FROM_DEVICE) {
1409                 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1410                 txd->cctl |= PL080_CONTROL_DST_INCR;
1411                 if (plchan->runtime_addr)
1412                         txd->srcbus.addr = plchan->runtime_addr;
1413                 else
1414                         txd->srcbus.addr = plchan->cd->addr;
1415                 txd->dstbus.addr = sgl->dma_address;
1416                 src_buses = plchan->cd->periph_buses;
1417                 dst_buses = pl08x->mem_buses;
1418         } else {
1419                 dev_err(&pl08x->adev->dev,
1420                         "%s direction unsupported\n", __func__);
1421                 return NULL;
1422         }
1423
1424         txd->cctl |= pl08x_select_bus(pl08x, src_buses, dst_buses);
1425
1426         ret = pl08x_prep_channel_resources(plchan, txd);
1427         if (ret)
1428                 return NULL;
1429         /*
1430          * NB: the channel lock is held at this point so tx_submit()
1431          * must be called in direct succession.
1432          */
1433
1434         return &txd->tx;
1435 }
1436
1437 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1438                          unsigned long arg)
1439 {
1440         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1441         struct pl08x_driver_data *pl08x = plchan->host;
1442         unsigned long flags;
1443         int ret = 0;
1444
1445         /* Controls applicable to inactive channels */
1446         if (cmd == DMA_SLAVE_CONFIG) {
1447                 dma_set_runtime_config(chan,
1448                                        (struct dma_slave_config *)
1449                                        arg);
1450                 return 0;
1451         }
1452
1453         /*
1454          * Anything succeeds on channels with no physical allocation and
1455          * no queued transfers.
1456          */
1457         spin_lock_irqsave(&plchan->lock, flags);
1458         if (!plchan->phychan && !plchan->at) {
1459                 spin_unlock_irqrestore(&plchan->lock, flags);
1460                 return 0;
1461         }
1462
1463         switch (cmd) {
1464         case DMA_TERMINATE_ALL:
1465                 plchan->state = PL08X_CHAN_IDLE;
1466
1467                 if (plchan->phychan) {
1468                         pl08x_stop_phy_chan(plchan->phychan);
1469
1470                         /*
1471                          * Mark physical channel as free and free any slave
1472                          * signal
1473                          */
1474                         release_phy_channel(plchan);
1475                 }
1476                 /* Dequeue jobs and free LLIs */
1477                 if (plchan->at) {
1478                         pl08x_free_txd(pl08x, plchan->at);
1479                         plchan->at = NULL;
1480                 }
1481                 /* Dequeue jobs not yet fired as well */
1482                 pl08x_free_txd_list(pl08x, plchan);
1483                 break;
1484         case DMA_PAUSE:
1485                 pl08x_pause_phy_chan(plchan->phychan);
1486                 plchan->state = PL08X_CHAN_PAUSED;
1487                 break;
1488         case DMA_RESUME:
1489                 pl08x_resume_phy_chan(plchan->phychan);
1490                 plchan->state = PL08X_CHAN_RUNNING;
1491                 break;
1492         default:
1493                 /* Unknown command */
1494                 ret = -ENXIO;
1495                 break;
1496         }
1497
1498         spin_unlock_irqrestore(&plchan->lock, flags);
1499
1500         return ret;
1501 }
1502
1503 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1504 {
1505         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1506         char *name = chan_id;
1507
1508         /* Check that the channel is not taken! */
1509         if (!strcmp(plchan->name, name))
1510                 return true;
1511
1512         return false;
1513 }
1514
1515 /*
1516  * Just check that the device is there and active
1517  * TODO: turn this bit on/off depending on the number of
1518  * physical channels actually used, if it is zero... well
1519  * shut it off. That will save some power. Cut the clock
1520  * at the same time.
1521  */
1522 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1523 {
1524         u32 val;
1525
1526         val = readl(pl08x->base + PL080_CONFIG);
1527         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1528         /* We implicitly clear bit 1 and that means little-endian mode */
1529         val |= PL080_CONFIG_ENABLE;
1530         writel(val, pl08x->base + PL080_CONFIG);
1531 }
1532
1533 static void pl08x_tasklet(unsigned long data)
1534 {
1535         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1536         struct pl08x_driver_data *pl08x = plchan->host;
1537         struct pl08x_txd *txd;
1538         dma_async_tx_callback callback = NULL;
1539         void *callback_param = NULL;
1540         unsigned long flags;
1541
1542         spin_lock_irqsave(&plchan->lock, flags);
1543
1544         txd = plchan->at;
1545         plchan->at = NULL;
1546
1547         if (txd) {
1548                 callback = txd->tx.callback;
1549                 callback_param = txd->tx.callback_param;
1550
1551                 /*
1552                  * Update last completed
1553                  */
1554                 plchan->lc = txd->tx.cookie;
1555
1556                 /*
1557                  * Free the descriptor
1558                  */
1559                 pl08x_free_txd(pl08x, txd);
1560         }
1561         /*
1562          * If a new descriptor is queued, set it up
1563          * plchan->at is NULL here
1564          */
1565         if (!list_empty(&plchan->desc_list)) {
1566                 struct pl08x_txd *next;
1567
1568                 next = list_first_entry(&plchan->desc_list,
1569                                         struct pl08x_txd,
1570                                         node);
1571                 list_del(&next->node);
1572
1573                 pl08x_start_txd(plchan, next);
1574         } else {
1575                 struct pl08x_dma_chan *waiting = NULL;
1576
1577                 /*
1578                  * No more jobs, so free up the physical channel
1579                  * Free any allocated signal on slave transfers too
1580                  */
1581                 release_phy_channel(plchan);
1582                 plchan->state = PL08X_CHAN_IDLE;
1583
1584                 /*
1585                  * And NOW before anyone else can grab that free:d
1586                  * up physical channel, see if there is some memcpy
1587                  * pending that seriously needs to start because of
1588                  * being stacked up while we were choking the
1589                  * physical channels with data.
1590                  */
1591                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1592                                     chan.device_node) {
1593                   if (waiting->state == PL08X_CHAN_WAITING &&
1594                             waiting->waiting != NULL) {
1595                                 int ret;
1596
1597                                 /* This should REALLY not fail now */
1598                                 ret = prep_phy_channel(waiting,
1599                                                        waiting->waiting);
1600                                 BUG_ON(ret);
1601                                 waiting->state = PL08X_CHAN_RUNNING;
1602                                 waiting->waiting = NULL;
1603                                 pl08x_issue_pending(&waiting->chan);
1604                                 break;
1605                         }
1606                 }
1607         }
1608
1609         spin_unlock_irqrestore(&plchan->lock, flags);
1610
1611         /* Callback to signal completion */
1612         if (callback)
1613                 callback(callback_param);
1614 }
1615
1616 static irqreturn_t pl08x_irq(int irq, void *dev)
1617 {
1618         struct pl08x_driver_data *pl08x = dev;
1619         u32 mask = 0;
1620         u32 val;
1621         int i;
1622
1623         val = readl(pl08x->base + PL080_ERR_STATUS);
1624         if (val) {
1625                 /*
1626                  * An error interrupt (on one or more channels)
1627                  */
1628                 dev_err(&pl08x->adev->dev,
1629                         "%s error interrupt, register value 0x%08x\n",
1630                                 __func__, val);
1631                 /*
1632                  * Simply clear ALL PL08X error interrupts,
1633                  * regardless of channel and cause
1634                  * FIXME: should be 0x00000003 on PL081 really.
1635                  */
1636                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1637         }
1638         val = readl(pl08x->base + PL080_INT_STATUS);
1639         for (i = 0; i < pl08x->vd->channels; i++) {
1640                 if ((1 << i) & val) {
1641                         /* Locate physical channel */
1642                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1643                         struct pl08x_dma_chan *plchan = phychan->serving;
1644
1645                         /* Schedule tasklet on this channel */
1646                         tasklet_schedule(&plchan->tasklet);
1647
1648                         mask |= (1 << i);
1649                 }
1650         }
1651         /*
1652          * Clear only the terminal interrupts on channels we processed
1653          */
1654         writel(mask, pl08x->base + PL080_TC_CLEAR);
1655
1656         return mask ? IRQ_HANDLED : IRQ_NONE;
1657 }
1658
1659 /*
1660  * Initialise the DMAC memcpy/slave channels.
1661  * Make a local wrapper to hold required data
1662  */
1663 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1664                                            struct dma_device *dmadev,
1665                                            unsigned int channels,
1666                                            bool slave)
1667 {
1668         struct pl08x_dma_chan *chan;
1669         int i;
1670
1671         INIT_LIST_HEAD(&dmadev->channels);
1672         /*
1673          * Register as many many memcpy as we have physical channels,
1674          * we won't always be able to use all but the code will have
1675          * to cope with that situation.
1676          */
1677         for (i = 0; i < channels; i++) {
1678                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1679                 if (!chan) {
1680                         dev_err(&pl08x->adev->dev,
1681                                 "%s no memory for channel\n", __func__);
1682                         return -ENOMEM;
1683                 }
1684
1685                 chan->host = pl08x;
1686                 chan->state = PL08X_CHAN_IDLE;
1687
1688                 if (slave) {
1689                         chan->slave = true;
1690                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1691                         chan->cd = &pl08x->pd->slave_channels[i];
1692                 } else {
1693                         chan->cd = &pl08x->pd->memcpy_channel;
1694                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1695                         if (!chan->name) {
1696                                 kfree(chan);
1697                                 return -ENOMEM;
1698                         }
1699                 }
1700                 if (chan->cd->circular_buffer) {
1701                         dev_err(&pl08x->adev->dev,
1702                                 "channel %s: circular buffers not supported\n",
1703                                 chan->name);
1704                         kfree(chan);
1705                         continue;
1706                 }
1707                 dev_info(&pl08x->adev->dev,
1708                          "initialize virtual channel \"%s\"\n",
1709                          chan->name);
1710
1711                 chan->chan.device = dmadev;
1712                 chan->chan.cookie = 0;
1713                 chan->lc = 0;
1714
1715                 spin_lock_init(&chan->lock);
1716                 INIT_LIST_HEAD(&chan->desc_list);
1717                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1718                              (unsigned long) chan);
1719
1720                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1721         }
1722         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1723                  i, slave ? "slave" : "memcpy");
1724         return i;
1725 }
1726
1727 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1728 {
1729         struct pl08x_dma_chan *chan = NULL;
1730         struct pl08x_dma_chan *next;
1731
1732         list_for_each_entry_safe(chan,
1733                                  next, &dmadev->channels, chan.device_node) {
1734                 list_del(&chan->chan.device_node);
1735                 kfree(chan);
1736         }
1737 }
1738
1739 #ifdef CONFIG_DEBUG_FS
1740 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1741 {
1742         switch (state) {
1743         case PL08X_CHAN_IDLE:
1744                 return "idle";
1745         case PL08X_CHAN_RUNNING:
1746                 return "running";
1747         case PL08X_CHAN_PAUSED:
1748                 return "paused";
1749         case PL08X_CHAN_WAITING:
1750                 return "waiting";
1751         default:
1752                 break;
1753         }
1754         return "UNKNOWN STATE";
1755 }
1756
1757 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1758 {
1759         struct pl08x_driver_data *pl08x = s->private;
1760         struct pl08x_dma_chan *chan;
1761         struct pl08x_phy_chan *ch;
1762         unsigned long flags;
1763         int i;
1764
1765         seq_printf(s, "PL08x physical channels:\n");
1766         seq_printf(s, "CHANNEL:\tUSER:\n");
1767         seq_printf(s, "--------\t-----\n");
1768         for (i = 0; i < pl08x->vd->channels; i++) {
1769                 struct pl08x_dma_chan *virt_chan;
1770
1771                 ch = &pl08x->phy_chans[i];
1772
1773                 spin_lock_irqsave(&ch->lock, flags);
1774                 virt_chan = ch->serving;
1775
1776                 seq_printf(s, "%d\t\t%s\n",
1777                            ch->id, virt_chan ? virt_chan->name : "(none)");
1778
1779                 spin_unlock_irqrestore(&ch->lock, flags);
1780         }
1781
1782         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1783         seq_printf(s, "CHANNEL:\tSTATE:\n");
1784         seq_printf(s, "--------\t------\n");
1785         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1786                 seq_printf(s, "%s\t\t%s\n", chan->name,
1787                            pl08x_state_str(chan->state));
1788         }
1789
1790         seq_printf(s, "\nPL08x virtual slave channels:\n");
1791         seq_printf(s, "CHANNEL:\tSTATE:\n");
1792         seq_printf(s, "--------\t------\n");
1793         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1794                 seq_printf(s, "%s\t\t%s\n", chan->name,
1795                            pl08x_state_str(chan->state));
1796         }
1797
1798         return 0;
1799 }
1800
1801 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1802 {
1803         return single_open(file, pl08x_debugfs_show, inode->i_private);
1804 }
1805
1806 static const struct file_operations pl08x_debugfs_operations = {
1807         .open           = pl08x_debugfs_open,
1808         .read           = seq_read,
1809         .llseek         = seq_lseek,
1810         .release        = single_release,
1811 };
1812
1813 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1814 {
1815         /* Expose a simple debugfs interface to view all clocks */
1816         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1817                                    NULL, pl08x,
1818                                    &pl08x_debugfs_operations);
1819 }
1820
1821 #else
1822 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1823 {
1824 }
1825 #endif
1826
1827 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1828 {
1829         struct pl08x_driver_data *pl08x;
1830         const struct vendor_data *vd = id->data;
1831         int ret = 0;
1832         int i;
1833
1834         ret = amba_request_regions(adev, NULL);
1835         if (ret)
1836                 return ret;
1837
1838         /* Create the driver state holder */
1839         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1840         if (!pl08x) {
1841                 ret = -ENOMEM;
1842                 goto out_no_pl08x;
1843         }
1844
1845         /* Initialize memcpy engine */
1846         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1847         pl08x->memcpy.dev = &adev->dev;
1848         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1849         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1850         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1851         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1852         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1853         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1854         pl08x->memcpy.device_control = pl08x_control;
1855
1856         /* Initialize slave engine */
1857         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1858         pl08x->slave.dev = &adev->dev;
1859         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1860         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1861         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1862         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1863         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1864         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1865         pl08x->slave.device_control = pl08x_control;
1866
1867         /* Get the platform data */
1868         pl08x->pd = dev_get_platdata(&adev->dev);
1869         if (!pl08x->pd) {
1870                 dev_err(&adev->dev, "no platform data supplied\n");
1871                 goto out_no_platdata;
1872         }
1873
1874         /* Assign useful pointers to the driver state */
1875         pl08x->adev = adev;
1876         pl08x->vd = vd;
1877
1878         /* By default, AHB1 only.  If dualmaster, from platform */
1879         pl08x->lli_buses = PL08X_AHB1;
1880         pl08x->mem_buses = PL08X_AHB1;
1881         if (pl08x->vd->dualmaster) {
1882                 pl08x->lli_buses = pl08x->pd->lli_buses;
1883                 pl08x->mem_buses = pl08x->pd->mem_buses;
1884         }
1885
1886         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1887         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1888                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1889         if (!pl08x->pool) {
1890                 ret = -ENOMEM;
1891                 goto out_no_lli_pool;
1892         }
1893
1894         spin_lock_init(&pl08x->lock);
1895
1896         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1897         if (!pl08x->base) {
1898                 ret = -ENOMEM;
1899                 goto out_no_ioremap;
1900         }
1901
1902         /* Turn on the PL08x */
1903         pl08x_ensure_on(pl08x);
1904
1905         /*
1906          * Attach the interrupt handler
1907          */
1908         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1909         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1910
1911         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1912                           DRIVER_NAME, pl08x);
1913         if (ret) {
1914                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1915                         __func__, adev->irq[0]);
1916                 goto out_no_irq;
1917         }
1918
1919         /* Initialize physical channels */
1920         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1921                         GFP_KERNEL);
1922         if (!pl08x->phy_chans) {
1923                 dev_err(&adev->dev, "%s failed to allocate "
1924                         "physical channel holders\n",
1925                         __func__);
1926                 goto out_no_phychans;
1927         }
1928
1929         for (i = 0; i < vd->channels; i++) {
1930                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1931
1932                 ch->id = i;
1933                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1934                 spin_lock_init(&ch->lock);
1935                 ch->serving = NULL;
1936                 ch->signal = -1;
1937                 dev_info(&adev->dev,
1938                          "physical channel %d is %s\n", i,
1939                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1940         }
1941
1942         /* Register as many memcpy channels as there are physical channels */
1943         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1944                                               pl08x->vd->channels, false);
1945         if (ret <= 0) {
1946                 dev_warn(&pl08x->adev->dev,
1947                          "%s failed to enumerate memcpy channels - %d\n",
1948                          __func__, ret);
1949                 goto out_no_memcpy;
1950         }
1951         pl08x->memcpy.chancnt = ret;
1952
1953         /* Register slave channels */
1954         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1955                                               pl08x->pd->num_slave_channels,
1956                                               true);
1957         if (ret <= 0) {
1958                 dev_warn(&pl08x->adev->dev,
1959                         "%s failed to enumerate slave channels - %d\n",
1960                                 __func__, ret);
1961                 goto out_no_slave;
1962         }
1963         pl08x->slave.chancnt = ret;
1964
1965         ret = dma_async_device_register(&pl08x->memcpy);
1966         if (ret) {
1967                 dev_warn(&pl08x->adev->dev,
1968                         "%s failed to register memcpy as an async device - %d\n",
1969                         __func__, ret);
1970                 goto out_no_memcpy_reg;
1971         }
1972
1973         ret = dma_async_device_register(&pl08x->slave);
1974         if (ret) {
1975                 dev_warn(&pl08x->adev->dev,
1976                         "%s failed to register slave as an async device - %d\n",
1977                         __func__, ret);
1978                 goto out_no_slave_reg;
1979         }
1980
1981         amba_set_drvdata(adev, pl08x);
1982         init_pl08x_debugfs(pl08x);
1983         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1984                  amba_part(adev), amba_rev(adev),
1985                  (unsigned long long)adev->res.start, adev->irq[0]);
1986         return 0;
1987
1988 out_no_slave_reg:
1989         dma_async_device_unregister(&pl08x->memcpy);
1990 out_no_memcpy_reg:
1991         pl08x_free_virtual_channels(&pl08x->slave);
1992 out_no_slave:
1993         pl08x_free_virtual_channels(&pl08x->memcpy);
1994 out_no_memcpy:
1995         kfree(pl08x->phy_chans);
1996 out_no_phychans:
1997         free_irq(adev->irq[0], pl08x);
1998 out_no_irq:
1999         iounmap(pl08x->base);
2000 out_no_ioremap:
2001         dma_pool_destroy(pl08x->pool);
2002 out_no_lli_pool:
2003 out_no_platdata:
2004         kfree(pl08x);
2005 out_no_pl08x:
2006         amba_release_regions(adev);
2007         return ret;
2008 }
2009
2010 /* PL080 has 8 channels and the PL080 have just 2 */
2011 static struct vendor_data vendor_pl080 = {
2012         .channels = 8,
2013         .dualmaster = true,
2014 };
2015
2016 static struct vendor_data vendor_pl081 = {
2017         .channels = 2,
2018         .dualmaster = false,
2019 };
2020
2021 static struct amba_id pl08x_ids[] = {
2022         /* PL080 */
2023         {
2024                 .id     = 0x00041080,
2025                 .mask   = 0x000fffff,
2026                 .data   = &vendor_pl080,
2027         },
2028         /* PL081 */
2029         {
2030                 .id     = 0x00041081,
2031                 .mask   = 0x000fffff,
2032                 .data   = &vendor_pl081,
2033         },
2034         /* Nomadik 8815 PL080 variant */
2035         {
2036                 .id     = 0x00280880,
2037                 .mask   = 0x00ffffff,
2038                 .data   = &vendor_pl080,
2039         },
2040         { 0, 0 },
2041 };
2042
2043 static struct amba_driver pl08x_amba_driver = {
2044         .drv.name       = DRIVER_NAME,
2045         .id_table       = pl08x_ids,
2046         .probe          = pl08x_probe,
2047 };
2048
2049 static int __init pl08x_init(void)
2050 {
2051         int retval;
2052         retval = amba_driver_register(&pl08x_amba_driver);
2053         if (retval)
2054                 printk(KERN_WARNING DRIVER_NAME
2055                        "failed to register as an AMBA device (%d)\n",
2056                        retval);
2057         return retval;
2058 }
2059 subsys_initcall(pl08x_init);