2 * Copyright (c) 2006 ARM Ltd.
3 * Copyright (c) 2010 ST-Ericsson SA
5 * Author: Peter Pearse <peter.pearse@arm.com>
6 * Author: Linus Walleij <linus.walleij@stericsson.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the Free
10 * Software Foundation; either version 2 of the License, or (at your option)
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc., 59
20 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 * The full GNU General Public License is in this distribution in the file
25 * Documentation: ARM DDI 0196G == PL080
26 * Documentation: ARM DDI 0218E == PL081
28 * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
31 * The PL080 has 8 channels available for simultaneous use, and the PL081
32 * has only two channels. So on these DMA controllers the number of channels
33 * and the number of incoming DMA signals are two totally different things.
34 * It is usually not possible to theoretically handle all physical signals,
35 * so a multiplexing scheme with possible denial of use is necessary.
37 * The PL080 has a dual bus master, PL081 has a single master.
39 * Memory to peripheral transfer may be visualized as
40 * Get data from memory to DMAC
42 * On burst request from peripheral
43 * Destination burst from DMAC to peripheral
45 * Raise terminal count interrupt
47 * For peripherals with a FIFO:
48 * Source burst size == half the depth of the peripheral FIFO
49 * Destination burst size == the depth of the peripheral FIFO
51 * (Bursts are irrelevant for mem to mem transfers - there are no burst
52 * signals, the DMA controller will simply facilitate its AHB master.)
54 * ASSUMES default (little) endianness for DMA transfers
56 * The PL08x has two flow control settings:
57 * - DMAC flow control: the transfer size defines the number of transfers
58 * which occur for the current LLI entry, and the DMAC raises TC at the
59 * end of every LLI entry. Observed behaviour shows the DMAC listening
60 * to both the BREQ and SREQ signals (contrary to documented),
61 * transferring data if either is active. The LBREQ and LSREQ signals
64 * - Peripheral flow control: the transfer size is ignored (and should be
65 * zero). The data is transferred from the current LLI entry, until
66 * after the final transfer signalled by LBREQ or LSREQ. The DMAC
67 * will then move to the next LLI entry.
69 * Only the former works sanely with scatter lists, so we only implement
70 * the DMAC flow control method. However, peripherals which use the LBREQ
71 * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72 * these hardware restrictions prevents them from using scatter DMA.
75 * - Break out common code from arch/arm/mach-s3c64xx and share
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/delay.h>
83 #include <linux/dma-mapping.h>
84 #include <linux/dmapool.h>
85 #include <linux/dmaengine.h>
86 #include <linux/amba/bus.h>
87 #include <linux/amba/pl08x.h>
88 #include <linux/debugfs.h>
89 #include <linux/seq_file.h>
91 #include <asm/hardware/pl080.h>
93 #include "dmaengine.h"
95 #define DRIVER_NAME "pl08xdmac"
98 * struct vendor_data - vendor-specific config parameters for PL08x derivatives
99 * @channels: the number of channels available in this variant
100 * @dualmaster: whether this version supports dual AHB masters or not.
108 * PL08X private data structures
109 * An LLI struct - see PL08x TRM. Note that next uses bit[0] as a bus bit,
110 * start & end do not - their bus bit info is in cctl. Also note that these
111 * are fixed 32-bit quantities.
121 * struct pl08x_driver_data - the local state holder for the PL08x
122 * @slave: slave engine for this instance
123 * @memcpy: memcpy engine for this instance
124 * @base: virtual memory base (remapped) for the PL08x
125 * @adev: the corresponding AMBA (PrimeCell) bus entry
126 * @vd: vendor data for this PL08x variant
127 * @pd: platform data passed in from the platform/machine
128 * @phy_chans: array of data for the physical channels
129 * @pool: a pool for the LLI descriptors
130 * @pool_ctr: counter of LLIs in the pool
131 * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI fetches
132 * @mem_buses: set to indicate memory transfers on AHB2.
133 * @lock: a spinlock for this struct
135 struct pl08x_driver_data {
136 struct dma_device slave;
137 struct dma_device memcpy;
139 struct amba_device *adev;
140 const struct vendor_data *vd;
141 struct pl08x_platform_data *pd;
142 struct pl08x_phy_chan *phy_chans;
143 struct dma_pool *pool;
151 * PL08X specific defines
155 * Memory boundaries: the manual for PL08x says that the controller
156 * cannot read past a 1KiB boundary, so these defines are used to
157 * create transfer LLIs that do not cross such boundaries.
159 #define PL08X_BOUNDARY_SHIFT (10) /* 1KB 0x400 */
160 #define PL08X_BOUNDARY_SIZE (1 << PL08X_BOUNDARY_SHIFT)
162 /* Size (bytes) of each LLI buffer allocated for one transfer */
163 # define PL08X_LLI_TSFR_SIZE 0x2000
165 /* Maximum times we call dma_pool_alloc on this pool without freeing */
166 #define MAX_NUM_TSFR_LLIS (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
167 #define PL08X_ALIGN 8
169 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
171 return container_of(chan, struct pl08x_dma_chan, chan);
174 static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
176 return container_of(tx, struct pl08x_txd, tx);
180 * Physical channel handling
183 /* Whether a certain channel is busy or not */
184 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
188 val = readl(ch->base + PL080_CH_CONFIG);
189 return val & PL080_CONFIG_ACTIVE;
193 * Set the initial DMA register values i.e. those for the first LLI
194 * The next LLI pointer and the configuration interrupt bit have
195 * been set when the LLIs were constructed. Poke them into the hardware
196 * and start the transfer.
198 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
199 struct pl08x_txd *txd)
201 struct pl08x_driver_data *pl08x = plchan->host;
202 struct pl08x_phy_chan *phychan = plchan->phychan;
203 struct pl08x_lli *lli = &txd->llis_va[0];
208 /* Wait for channel inactive */
209 while (pl08x_phy_channel_busy(phychan))
212 dev_vdbg(&pl08x->adev->dev,
213 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
214 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
215 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
218 writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
219 writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
220 writel(lli->lli, phychan->base + PL080_CH_LLI);
221 writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
222 writel(txd->ccfg, phychan->base + PL080_CH_CONFIG);
224 /* Enable the DMA channel */
225 /* Do not access config register until channel shows as disabled */
226 while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
229 /* Do not access config register until channel shows as inactive */
230 val = readl(phychan->base + PL080_CH_CONFIG);
231 while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
232 val = readl(phychan->base + PL080_CH_CONFIG);
234 writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
238 * Pause the channel by setting the HALT bit.
240 * For M->P transfers, pause the DMAC first and then stop the peripheral -
241 * the FIFO can only drain if the peripheral is still requesting data.
242 * (note: this can still timeout if the DMAC FIFO never drains of data.)
244 * For P->M transfers, disable the peripheral first to stop it filling
245 * the DMAC FIFO, and then pause the DMAC.
247 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
252 /* Set the HALT bit and wait for the FIFO to drain */
253 val = readl(ch->base + PL080_CH_CONFIG);
254 val |= PL080_CONFIG_HALT;
255 writel(val, ch->base + PL080_CH_CONFIG);
257 /* Wait for channel inactive */
258 for (timeout = 1000; timeout; timeout--) {
259 if (!pl08x_phy_channel_busy(ch))
263 if (pl08x_phy_channel_busy(ch))
264 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
267 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
271 /* Clear the HALT bit */
272 val = readl(ch->base + PL080_CH_CONFIG);
273 val &= ~PL080_CONFIG_HALT;
274 writel(val, ch->base + PL080_CH_CONFIG);
279 * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
280 * clears any pending interrupt status. This should not be used for
281 * an on-going transfer, but as a method of shutting down a channel
282 * (eg, when it's no longer used) or terminating a transfer.
284 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
285 struct pl08x_phy_chan *ch)
287 u32 val = readl(ch->base + PL080_CH_CONFIG);
289 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
290 PL080_CONFIG_TC_IRQ_MASK);
292 writel(val, ch->base + PL080_CH_CONFIG);
294 writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
295 writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
298 static inline u32 get_bytes_in_cctl(u32 cctl)
300 /* The source width defines the number of bytes */
301 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
303 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
304 case PL080_WIDTH_8BIT:
306 case PL080_WIDTH_16BIT:
309 case PL080_WIDTH_32BIT:
316 /* The channel should be paused when calling this */
317 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
319 struct pl08x_phy_chan *ch;
320 struct pl08x_txd *txd;
324 spin_lock_irqsave(&plchan->lock, flags);
325 ch = plchan->phychan;
329 * Follow the LLIs to get the number of remaining
330 * bytes in the currently active transaction.
333 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
335 /* First get the remaining bytes in the active transfer */
336 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
339 struct pl08x_lli *llis_va = txd->llis_va;
340 dma_addr_t llis_bus = txd->llis_bus;
343 BUG_ON(clli < llis_bus || clli >= llis_bus +
344 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
347 * Locate the next LLI - as this is an array,
348 * it's simple maths to find.
350 index = (clli - llis_bus) / sizeof(struct pl08x_lli);
352 for (; index < MAX_NUM_TSFR_LLIS; index++) {
353 bytes += get_bytes_in_cctl(llis_va[index].cctl);
356 * A LLI pointer of 0 terminates the LLI list
358 if (!llis_va[index].lli)
364 /* Sum up all queued transactions */
365 if (!list_empty(&plchan->pend_list)) {
366 struct pl08x_txd *txdi;
367 list_for_each_entry(txdi, &plchan->pend_list, node) {
372 spin_unlock_irqrestore(&plchan->lock, flags);
378 * Allocate a physical channel for a virtual channel
380 * Try to locate a physical channel to be used for this transfer. If all
381 * are taken return NULL and the requester will have to cope by using
382 * some fallback PIO mode or retrying later.
384 static struct pl08x_phy_chan *
385 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
386 struct pl08x_dma_chan *virt_chan)
388 struct pl08x_phy_chan *ch = NULL;
392 for (i = 0; i < pl08x->vd->channels; i++) {
393 ch = &pl08x->phy_chans[i];
395 spin_lock_irqsave(&ch->lock, flags);
398 ch->serving = virt_chan;
400 spin_unlock_irqrestore(&ch->lock, flags);
404 spin_unlock_irqrestore(&ch->lock, flags);
407 if (i == pl08x->vd->channels) {
408 /* No physical channel available, cope with it */
415 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
416 struct pl08x_phy_chan *ch)
420 spin_lock_irqsave(&ch->lock, flags);
422 /* Stop the channel and clear its interrupts */
423 pl08x_terminate_phy_chan(pl08x, ch);
425 /* Mark it as free */
427 spin_unlock_irqrestore(&ch->lock, flags);
434 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
437 case PL080_WIDTH_8BIT:
439 case PL080_WIDTH_16BIT:
441 case PL080_WIDTH_32BIT:
450 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
455 /* Remove all src, dst and transfer size bits */
456 retbits &= ~PL080_CONTROL_DWIDTH_MASK;
457 retbits &= ~PL080_CONTROL_SWIDTH_MASK;
458 retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
460 /* Then set the bits according to the parameters */
463 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
466 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
469 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
478 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
481 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
484 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
491 retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
495 struct pl08x_lli_build_data {
496 struct pl08x_txd *txd;
497 struct pl08x_bus_data srcbus;
498 struct pl08x_bus_data dstbus;
504 * Autoselect a master bus to use for the transfer this prefers the
505 * destination bus if both available if fixed address on one bus the
506 * other will be chosen
508 static void pl08x_choose_master_bus(struct pl08x_lli_build_data *bd,
509 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl)
511 if (!(cctl & PL080_CONTROL_DST_INCR)) {
514 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
518 if (bd->dstbus.buswidth == 4) {
521 } else if (bd->srcbus.buswidth == 4) {
524 } else if (bd->dstbus.buswidth == 2) {
527 } else if (bd->srcbus.buswidth == 2) {
531 /* bd->srcbus.buswidth == 1 */
539 * Fills in one LLI for a certain transfer descriptor and advance the counter
541 static void pl08x_fill_lli_for_desc(struct pl08x_lli_build_data *bd,
542 int num_llis, int len, u32 cctl)
544 struct pl08x_lli *llis_va = bd->txd->llis_va;
545 dma_addr_t llis_bus = bd->txd->llis_bus;
547 BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
549 llis_va[num_llis].cctl = cctl;
550 llis_va[num_llis].src = bd->srcbus.addr;
551 llis_va[num_llis].dst = bd->dstbus.addr;
552 llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
553 llis_va[num_llis].lli |= bd->lli_bus;
555 if (cctl & PL080_CONTROL_SRC_INCR)
556 bd->srcbus.addr += len;
557 if (cctl & PL080_CONTROL_DST_INCR)
558 bd->dstbus.addr += len;
560 BUG_ON(bd->remainder < len);
562 bd->remainder -= len;
566 * Return number of bytes to fill to boundary, or len.
567 * This calculation works for any value of addr.
569 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
571 size_t boundary_len = PL08X_BOUNDARY_SIZE -
572 (addr & (PL08X_BOUNDARY_SIZE - 1));
574 return min(boundary_len, len);
578 * This fills in the table of LLIs for the transfer descriptor
579 * Note that we assume we never have to change the burst sizes
582 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
583 struct pl08x_txd *txd)
585 struct pl08x_bus_data *mbus, *sbus;
586 struct pl08x_lli_build_data bd;
589 size_t max_bytes_per_lli;
590 size_t total_bytes = 0;
591 struct pl08x_lli *llis_va;
593 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
596 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
602 /* Get the default CCTL */
606 bd.srcbus.addr = txd->src_addr;
607 bd.dstbus.addr = txd->dst_addr;
608 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
610 /* Find maximum width of the source bus */
612 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
613 PL080_CONTROL_SWIDTH_SHIFT);
615 /* Find maximum width of the destination bus */
617 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
618 PL080_CONTROL_DWIDTH_SHIFT);
620 /* Set up the bus widths to the maximum */
621 bd.srcbus.buswidth = bd.srcbus.maxwidth;
622 bd.dstbus.buswidth = bd.dstbus.maxwidth;
625 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
627 max_bytes_per_lli = min(bd.srcbus.buswidth, bd.dstbus.buswidth) *
628 PL080_CONTROL_TRANSFER_SIZE_MASK;
630 /* We need to count this down to zero */
631 bd.remainder = txd->len;
634 * Choose bus to align to
635 * - prefers destination bus if both available
636 * - if fixed address on one bus chooses other
638 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
640 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu llimax=%zu\n",
641 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
643 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "",
645 bd.remainder, max_bytes_per_lli);
646 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
647 mbus == &bd.srcbus ? "src" : "dst",
648 sbus == &bd.srcbus ? "src" : "dst");
650 if (txd->len < mbus->buswidth) {
651 /* Less than a bus width available - send as single bytes */
652 while (bd.remainder) {
653 dev_vdbg(&pl08x->adev->dev,
654 "%s single byte LLIs for a transfer of "
655 "less than a bus width (remain 0x%08x)\n",
656 __func__, bd.remainder);
657 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
658 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
662 /* Make one byte LLIs until master bus is aligned */
663 while ((mbus->addr) % (mbus->buswidth)) {
664 dev_vdbg(&pl08x->adev->dev,
665 "%s adjustment lli for less than bus width "
667 __func__, bd.remainder);
668 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
669 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
675 * - if slave is not then we must set its width down
677 if (sbus->addr % sbus->buswidth) {
678 dev_dbg(&pl08x->adev->dev,
679 "%s set down bus width to one byte\n",
686 * Make largest possible LLIs until less than one bus
689 while (bd.remainder > (mbus->buswidth - 1)) {
690 size_t lli_len, target_len, tsize, odd_bytes;
693 * If enough left try to send max possible,
694 * otherwise try to send the remainder
696 target_len = min(bd.remainder, max_bytes_per_lli);
699 * Set bus lengths for incrementing buses to the
700 * number of bytes which fill to next memory boundary,
701 * limiting on the target length calculated above.
703 if (cctl & PL080_CONTROL_SRC_INCR)
704 bd.srcbus.fill_bytes =
705 pl08x_pre_boundary(bd.srcbus.addr,
708 bd.srcbus.fill_bytes = target_len;
710 if (cctl & PL080_CONTROL_DST_INCR)
711 bd.dstbus.fill_bytes =
712 pl08x_pre_boundary(bd.dstbus.addr,
715 bd.dstbus.fill_bytes = target_len;
717 /* Find the nearest */
718 lli_len = min(bd.srcbus.fill_bytes,
719 bd.dstbus.fill_bytes);
721 BUG_ON(lli_len > bd.remainder);
724 dev_err(&pl08x->adev->dev,
725 "%s lli_len is %zu, <= 0\n",
730 if (lli_len == target_len) {
732 * Can send what we wanted.
735 lli_len = (lli_len/mbus->buswidth) *
740 * So now we know how many bytes to transfer
741 * to get to the nearest boundary. The next
742 * LLI will past the boundary. However, we
743 * may be working to a boundary on the slave
744 * bus. We need to ensure the master stays
745 * aligned, and that we are working in
746 * multiples of the bus widths.
748 odd_bytes = lli_len % mbus->buswidth;
749 lli_len -= odd_bytes;
755 * Check against minimum bus alignment:
756 * Calculate actual transfer size in relation
757 * to bus width an get a maximum remainder of
758 * the smallest bus width - 1
760 /* FIXME: use round_down()? */
761 tsize = lli_len / min(mbus->buswidth,
763 lli_len = tsize * min(mbus->buswidth,
766 if (target_len != lli_len) {
767 dev_vdbg(&pl08x->adev->dev,
768 "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
769 __func__, target_len, lli_len, txd->len);
772 cctl = pl08x_cctl_bits(cctl,
777 dev_vdbg(&pl08x->adev->dev,
778 "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
779 __func__, lli_len, bd.remainder);
780 pl08x_fill_lli_for_desc(&bd, num_llis++,
782 total_bytes += lli_len;
788 * Creep past the boundary, maintaining
792 for (j = 0; (j < mbus->buswidth)
793 && (bd.remainder); j++) {
794 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
795 dev_vdbg(&pl08x->adev->dev,
796 "%s align with boundary, single byte (remain 0x%08zx)\n",
797 __func__, bd.remainder);
798 pl08x_fill_lli_for_desc(&bd,
799 num_llis++, 1, cctl);
808 while (bd.remainder) {
809 cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
810 dev_vdbg(&pl08x->adev->dev,
811 "%s align with boundary, single odd byte (remain %zu)\n",
812 __func__, bd.remainder);
813 pl08x_fill_lli_for_desc(&bd, num_llis++, 1, cctl);
817 if (total_bytes != txd->len) {
818 dev_err(&pl08x->adev->dev,
819 "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
820 __func__, total_bytes, txd->len);
824 if (num_llis >= MAX_NUM_TSFR_LLIS) {
825 dev_err(&pl08x->adev->dev,
826 "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
827 __func__, (u32) MAX_NUM_TSFR_LLIS);
831 llis_va = txd->llis_va;
832 /* The final LLI terminates the LLI. */
833 llis_va[num_llis - 1].lli = 0;
834 /* The final LLI element shall also fire an interrupt. */
835 llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
841 dev_vdbg(&pl08x->adev->dev,
842 "%-3s %-9s %-10s %-10s %-10s %s\n",
843 "lli", "", "csrc", "cdst", "clli", "cctl");
844 for (i = 0; i < num_llis; i++) {
845 dev_vdbg(&pl08x->adev->dev,
846 "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
847 i, &llis_va[i], llis_va[i].src,
848 llis_va[i].dst, llis_va[i].lli, llis_va[i].cctl
857 /* You should call this with the struct pl08x lock held */
858 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
859 struct pl08x_txd *txd)
862 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
869 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
870 struct pl08x_dma_chan *plchan)
872 struct pl08x_txd *txdi = NULL;
873 struct pl08x_txd *next;
875 if (!list_empty(&plchan->pend_list)) {
876 list_for_each_entry_safe(txdi,
877 next, &plchan->pend_list, node) {
878 list_del(&txdi->node);
879 pl08x_free_txd(pl08x, txdi);
887 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
892 static void pl08x_free_chan_resources(struct dma_chan *chan)
897 * This should be called with the channel plchan->lock held
899 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
900 struct pl08x_txd *txd)
902 struct pl08x_driver_data *pl08x = plchan->host;
903 struct pl08x_phy_chan *ch;
906 /* Check if we already have a channel */
910 ch = pl08x_get_phy_channel(pl08x, plchan);
912 /* No physical channel available, cope with it */
913 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
918 * OK we have a physical channel: for memcpy() this is all we
919 * need, but for slaves the physical signals may be muxed!
920 * Can the platform allow us to use this channel?
924 pl08x->pd->get_signal) {
925 ret = pl08x->pd->get_signal(plchan);
927 dev_dbg(&pl08x->adev->dev,
928 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
929 ch->id, plchan->name);
930 /* Release physical channel & return */
931 pl08x_put_phy_channel(pl08x, ch);
936 /* Assign the flow control signal to this channel */
937 if (txd->direction == DMA_TO_DEVICE)
938 txd->ccfg |= ch->signal << PL080_CONFIG_DST_SEL_SHIFT;
939 else if (txd->direction == DMA_FROM_DEVICE)
940 txd->ccfg |= ch->signal << PL080_CONFIG_SRC_SEL_SHIFT;
943 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
948 plchan->phychan_hold++;
949 plchan->phychan = ch;
954 static void release_phy_channel(struct pl08x_dma_chan *plchan)
956 struct pl08x_driver_data *pl08x = plchan->host;
958 if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
959 pl08x->pd->put_signal(plchan);
960 plchan->phychan->signal = -1;
962 pl08x_put_phy_channel(pl08x, plchan->phychan);
963 plchan->phychan = NULL;
966 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
968 struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
969 struct pl08x_txd *txd = to_pl08x_txd(tx);
973 spin_lock_irqsave(&plchan->lock, flags);
974 cookie = dma_cookie_assign(tx);
976 /* Put this onto the pending list */
977 list_add_tail(&txd->node, &plchan->pend_list);
980 * If there was no physical channel available for this memcpy,
981 * stack the request up and indicate that the channel is waiting
982 * for a free physical channel.
984 if (!plchan->slave && !plchan->phychan) {
985 /* Do this memcpy whenever there is a channel ready */
986 plchan->state = PL08X_CHAN_WAITING;
987 plchan->waiting = txd;
989 plchan->phychan_hold--;
992 spin_unlock_irqrestore(&plchan->lock, flags);
997 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
998 struct dma_chan *chan, unsigned long flags)
1000 struct dma_async_tx_descriptor *retval = NULL;
1006 * Code accessing dma_async_is_complete() in a tight loop may give problems.
1007 * If slaves are relying on interrupts to signal completion this function
1008 * must not be called with interrupts disabled.
1010 static enum dma_status
1011 pl08x_dma_tx_status(struct dma_chan *chan,
1012 dma_cookie_t cookie,
1013 struct dma_tx_state *txstate)
1015 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1016 enum dma_status ret;
1018 ret = dma_cookie_status(chan, cookie, txstate);
1019 if (ret == DMA_SUCCESS)
1023 * This cookie not complete yet
1024 * Get number of bytes left in the active transactions and queue
1026 dma_set_residue(txstate, pl08x_getbytes_chan(plchan));
1028 if (plchan->state == PL08X_CHAN_PAUSED)
1031 /* Whether waiting or running, we're in progress */
1032 return DMA_IN_PROGRESS;
1035 /* PrimeCell DMA extension */
1036 struct burst_table {
1041 static const struct burst_table burst_sizes[] = {
1044 .reg = PL080_BSIZE_256,
1048 .reg = PL080_BSIZE_128,
1052 .reg = PL080_BSIZE_64,
1056 .reg = PL080_BSIZE_32,
1060 .reg = PL080_BSIZE_16,
1064 .reg = PL080_BSIZE_8,
1068 .reg = PL080_BSIZE_4,
1072 .reg = PL080_BSIZE_1,
1077 * Given the source and destination available bus masks, select which
1078 * will be routed to each port. We try to have source and destination
1079 * on separate ports, but always respect the allowable settings.
1081 static u32 pl08x_select_bus(u8 src, u8 dst)
1085 if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
1086 cctl |= PL080_CONTROL_DST_AHB2;
1087 if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
1088 cctl |= PL080_CONTROL_SRC_AHB2;
1093 static u32 pl08x_cctl(u32 cctl)
1095 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
1096 PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
1097 PL080_CONTROL_PROT_MASK);
1099 /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1100 return cctl | PL080_CONTROL_PROT_SYS;
1103 static u32 pl08x_width(enum dma_slave_buswidth width)
1106 case DMA_SLAVE_BUSWIDTH_1_BYTE:
1107 return PL080_WIDTH_8BIT;
1108 case DMA_SLAVE_BUSWIDTH_2_BYTES:
1109 return PL080_WIDTH_16BIT;
1110 case DMA_SLAVE_BUSWIDTH_4_BYTES:
1111 return PL080_WIDTH_32BIT;
1117 static u32 pl08x_burst(u32 maxburst)
1121 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1122 if (burst_sizes[i].burstwords <= maxburst)
1125 return burst_sizes[i].reg;
1128 static int dma_set_runtime_config(struct dma_chan *chan,
1129 struct dma_slave_config *config)
1131 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1132 struct pl08x_driver_data *pl08x = plchan->host;
1133 enum dma_slave_buswidth addr_width;
1134 u32 width, burst, maxburst;
1140 /* Transfer direction */
1141 plchan->runtime_direction = config->direction;
1142 if (config->direction == DMA_TO_DEVICE) {
1143 addr_width = config->dst_addr_width;
1144 maxburst = config->dst_maxburst;
1145 } else if (config->direction == DMA_FROM_DEVICE) {
1146 addr_width = config->src_addr_width;
1147 maxburst = config->src_maxburst;
1149 dev_err(&pl08x->adev->dev,
1150 "bad runtime_config: alien transfer direction\n");
1154 width = pl08x_width(addr_width);
1156 dev_err(&pl08x->adev->dev,
1157 "bad runtime_config: alien address width\n");
1161 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1162 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1165 * If this channel will only request single transfers, set this
1166 * down to ONE element. Also select one element if no maxburst
1169 if (plchan->cd->single)
1172 burst = pl08x_burst(maxburst);
1173 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
1174 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
1176 if (plchan->runtime_direction == DMA_FROM_DEVICE) {
1177 plchan->src_addr = config->src_addr;
1178 plchan->src_cctl = pl08x_cctl(cctl) | PL080_CONTROL_DST_INCR |
1179 pl08x_select_bus(plchan->cd->periph_buses,
1182 plchan->dst_addr = config->dst_addr;
1183 plchan->dst_cctl = pl08x_cctl(cctl) | PL080_CONTROL_SRC_INCR |
1184 pl08x_select_bus(pl08x->mem_buses,
1185 plchan->cd->periph_buses);
1188 dev_dbg(&pl08x->adev->dev,
1189 "configured channel %s (%s) for %s, data width %d, "
1190 "maxburst %d words, LE, CCTL=0x%08x\n",
1191 dma_chan_name(chan), plchan->name,
1192 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1201 * Slave transactions callback to the slave device to allow
1202 * synchronization of slave DMA signals with the DMAC enable
1204 static void pl08x_issue_pending(struct dma_chan *chan)
1206 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1207 unsigned long flags;
1209 spin_lock_irqsave(&plchan->lock, flags);
1210 /* Something is already active, or we're waiting for a channel... */
1211 if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1212 spin_unlock_irqrestore(&plchan->lock, flags);
1216 /* Take the first element in the queue and execute it */
1217 if (!list_empty(&plchan->pend_list)) {
1218 struct pl08x_txd *next;
1220 next = list_first_entry(&plchan->pend_list,
1223 list_del(&next->node);
1224 plchan->state = PL08X_CHAN_RUNNING;
1226 pl08x_start_txd(plchan, next);
1229 spin_unlock_irqrestore(&plchan->lock, flags);
1232 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1233 struct pl08x_txd *txd)
1235 struct pl08x_driver_data *pl08x = plchan->host;
1236 unsigned long flags;
1239 num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1245 spin_lock_irqsave(&plchan->lock, flags);
1248 * See if we already have a physical channel allocated,
1249 * else this is the time to try to get one.
1251 ret = prep_phy_channel(plchan, txd);
1254 * No physical channel was available.
1256 * memcpy transfers can be sorted out at submission time.
1258 * Slave transfers may have been denied due to platform
1259 * channel muxing restrictions. Since there is no guarantee
1260 * that this will ever be resolved, and the signal must be
1261 * acquired AFTER acquiring the physical channel, we will let
1262 * them be NACK:ed with -EBUSY here. The drivers can retry
1263 * the prep() call if they are eager on doing this using DMA.
1265 if (plchan->slave) {
1266 pl08x_free_txd_list(pl08x, plchan);
1267 pl08x_free_txd(pl08x, txd);
1268 spin_unlock_irqrestore(&plchan->lock, flags);
1273 * Else we're all set, paused and ready to roll, status
1274 * will switch to PL08X_CHAN_RUNNING when we call
1275 * issue_pending(). If there is something running on the
1276 * channel already we don't change its state.
1278 if (plchan->state == PL08X_CHAN_IDLE)
1279 plchan->state = PL08X_CHAN_PAUSED;
1281 spin_unlock_irqrestore(&plchan->lock, flags);
1286 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan,
1287 unsigned long flags)
1289 struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1292 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1293 txd->tx.flags = flags;
1294 txd->tx.tx_submit = pl08x_tx_submit;
1295 INIT_LIST_HEAD(&txd->node);
1297 /* Always enable error and terminal interrupts */
1298 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1299 PL080_CONFIG_TC_IRQ_MASK;
1305 * Initialize a descriptor to be used by memcpy submit
1307 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1308 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1309 size_t len, unsigned long flags)
1311 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1312 struct pl08x_driver_data *pl08x = plchan->host;
1313 struct pl08x_txd *txd;
1316 txd = pl08x_get_txd(plchan, flags);
1318 dev_err(&pl08x->adev->dev,
1319 "%s no memory for descriptor\n", __func__);
1323 txd->direction = DMA_NONE;
1324 txd->src_addr = src;
1325 txd->dst_addr = dest;
1328 /* Set platform data for m2m */
1329 txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1330 txd->cctl = pl08x->pd->memcpy_channel.cctl &
1331 ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
1333 /* Both to be incremented or the code will break */
1334 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1336 if (pl08x->vd->dualmaster)
1337 txd->cctl |= pl08x_select_bus(pl08x->mem_buses,
1340 ret = pl08x_prep_channel_resources(plchan, txd);
1347 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1348 struct dma_chan *chan, struct scatterlist *sgl,
1349 unsigned long flags, void *context)
1351 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1352 struct pl08x_driver_data *pl08x = plchan->host;
1353 struct pl08x_txd *txd;
1357 * Current implementation ASSUMES only one sg
1360 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1365 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1366 __func__, sgl->length, plchan->name);
1368 txd = pl08x_get_txd(plchan, flags);
1370 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1374 if (direction != plchan->runtime_direction)
1375 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1376 "the direction configured for the PrimeCell\n",
1380 * Set up addresses, the PrimeCell configured address
1381 * will take precedence since this may configure the
1382 * channel target address dynamically at runtime.
1384 txd->direction = direction;
1385 txd->len = sgl->length;
1387 if (direction == DMA_TO_DEVICE) {
1388 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1389 txd->cctl = plchan->dst_cctl;
1390 txd->src_addr = sgl->dma_address;
1391 txd->dst_addr = plchan->dst_addr;
1392 } else if (direction == DMA_FROM_DEVICE) {
1393 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1394 txd->cctl = plchan->src_cctl;
1395 txd->src_addr = plchan->src_addr;
1396 txd->dst_addr = sgl->dma_address;
1398 dev_err(&pl08x->adev->dev,
1399 "%s direction unsupported\n", __func__);
1403 ret = pl08x_prep_channel_resources(plchan, txd);
1410 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1413 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1414 struct pl08x_driver_data *pl08x = plchan->host;
1415 unsigned long flags;
1418 /* Controls applicable to inactive channels */
1419 if (cmd == DMA_SLAVE_CONFIG) {
1420 return dma_set_runtime_config(chan,
1421 (struct dma_slave_config *)arg);
1425 * Anything succeeds on channels with no physical allocation and
1426 * no queued transfers.
1428 spin_lock_irqsave(&plchan->lock, flags);
1429 if (!plchan->phychan && !plchan->at) {
1430 spin_unlock_irqrestore(&plchan->lock, flags);
1435 case DMA_TERMINATE_ALL:
1436 plchan->state = PL08X_CHAN_IDLE;
1438 if (plchan->phychan) {
1439 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
1442 * Mark physical channel as free and free any slave
1445 release_phy_channel(plchan);
1447 /* Dequeue jobs and free LLIs */
1449 pl08x_free_txd(pl08x, plchan->at);
1452 /* Dequeue jobs not yet fired as well */
1453 pl08x_free_txd_list(pl08x, plchan);
1456 pl08x_pause_phy_chan(plchan->phychan);
1457 plchan->state = PL08X_CHAN_PAUSED;
1460 pl08x_resume_phy_chan(plchan->phychan);
1461 plchan->state = PL08X_CHAN_RUNNING;
1464 /* Unknown command */
1469 spin_unlock_irqrestore(&plchan->lock, flags);
1474 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1476 struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1477 char *name = chan_id;
1479 /* Check that the channel is not taken! */
1480 if (!strcmp(plchan->name, name))
1487 * Just check that the device is there and active
1488 * TODO: turn this bit on/off depending on the number of physical channels
1489 * actually used, if it is zero... well shut it off. That will save some
1490 * power. Cut the clock at the same time.
1492 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1496 val = readl(pl08x->base + PL080_CONFIG);
1497 val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1498 /* We implicitly clear bit 1 and that means little-endian mode */
1499 val |= PL080_CONFIG_ENABLE;
1500 writel(val, pl08x->base + PL080_CONFIG);
1503 static void pl08x_unmap_buffers(struct pl08x_txd *txd)
1505 struct device *dev = txd->tx.chan->device->dev;
1507 if (!(txd->tx.flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
1508 if (txd->tx.flags & DMA_COMPL_SRC_UNMAP_SINGLE)
1509 dma_unmap_single(dev, txd->src_addr, txd->len,
1512 dma_unmap_page(dev, txd->src_addr, txd->len,
1515 if (!(txd->tx.flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
1516 if (txd->tx.flags & DMA_COMPL_DEST_UNMAP_SINGLE)
1517 dma_unmap_single(dev, txd->dst_addr, txd->len,
1520 dma_unmap_page(dev, txd->dst_addr, txd->len,
1525 static void pl08x_tasklet(unsigned long data)
1527 struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1528 struct pl08x_driver_data *pl08x = plchan->host;
1529 struct pl08x_txd *txd;
1530 unsigned long flags;
1532 spin_lock_irqsave(&plchan->lock, flags);
1538 /* Update last completed */
1539 dma_cookie_complete(&txd->tx);
1542 /* If a new descriptor is queued, set it up plchan->at is NULL here */
1543 if (!list_empty(&plchan->pend_list)) {
1544 struct pl08x_txd *next;
1546 next = list_first_entry(&plchan->pend_list,
1549 list_del(&next->node);
1551 pl08x_start_txd(plchan, next);
1552 } else if (plchan->phychan_hold) {
1554 * This channel is still in use - we have a new txd being
1555 * prepared and will soon be queued. Don't give up the
1559 struct pl08x_dma_chan *waiting = NULL;
1562 * No more jobs, so free up the physical channel
1563 * Free any allocated signal on slave transfers too
1565 release_phy_channel(plchan);
1566 plchan->state = PL08X_CHAN_IDLE;
1569 * And NOW before anyone else can grab that free:d up
1570 * physical channel, see if there is some memcpy pending
1571 * that seriously needs to start because of being stacked
1572 * up while we were choking the physical channels with data.
1574 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1576 if (waiting->state == PL08X_CHAN_WAITING &&
1577 waiting->waiting != NULL) {
1580 /* This should REALLY not fail now */
1581 ret = prep_phy_channel(waiting,
1584 waiting->phychan_hold--;
1585 waiting->state = PL08X_CHAN_RUNNING;
1586 waiting->waiting = NULL;
1587 pl08x_issue_pending(&waiting->chan);
1593 spin_unlock_irqrestore(&plchan->lock, flags);
1596 dma_async_tx_callback callback = txd->tx.callback;
1597 void *callback_param = txd->tx.callback_param;
1599 /* Don't try to unmap buffers on slave channels */
1601 pl08x_unmap_buffers(txd);
1603 /* Free the descriptor */
1604 spin_lock_irqsave(&plchan->lock, flags);
1605 pl08x_free_txd(pl08x, txd);
1606 spin_unlock_irqrestore(&plchan->lock, flags);
1608 /* Callback to signal completion */
1610 callback(callback_param);
1614 static irqreturn_t pl08x_irq(int irq, void *dev)
1616 struct pl08x_driver_data *pl08x = dev;
1621 val = readl(pl08x->base + PL080_ERR_STATUS);
1623 /* An error interrupt (on one or more channels) */
1624 dev_err(&pl08x->adev->dev,
1625 "%s error interrupt, register value 0x%08x\n",
1628 * Simply clear ALL PL08X error interrupts,
1629 * regardless of channel and cause
1630 * FIXME: should be 0x00000003 on PL081 really.
1632 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1634 val = readl(pl08x->base + PL080_INT_STATUS);
1635 for (i = 0; i < pl08x->vd->channels; i++) {
1636 if ((1 << i) & val) {
1637 /* Locate physical channel */
1638 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1639 struct pl08x_dma_chan *plchan = phychan->serving;
1641 /* Schedule tasklet on this channel */
1642 tasklet_schedule(&plchan->tasklet);
1647 /* Clear only the terminal interrupts on channels we processed */
1648 writel(mask, pl08x->base + PL080_TC_CLEAR);
1650 return mask ? IRQ_HANDLED : IRQ_NONE;
1653 static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
1655 u32 cctl = pl08x_cctl(chan->cd->cctl);
1658 chan->name = chan->cd->bus_id;
1659 chan->src_addr = chan->cd->addr;
1660 chan->dst_addr = chan->cd->addr;
1661 chan->src_cctl = cctl | PL080_CONTROL_DST_INCR |
1662 pl08x_select_bus(chan->cd->periph_buses, chan->host->mem_buses);
1663 chan->dst_cctl = cctl | PL080_CONTROL_SRC_INCR |
1664 pl08x_select_bus(chan->host->mem_buses, chan->cd->periph_buses);
1668 * Initialise the DMAC memcpy/slave channels.
1669 * Make a local wrapper to hold required data
1671 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1672 struct dma_device *dmadev,
1673 unsigned int channels,
1676 struct pl08x_dma_chan *chan;
1679 INIT_LIST_HEAD(&dmadev->channels);
1682 * Register as many many memcpy as we have physical channels,
1683 * we won't always be able to use all but the code will have
1684 * to cope with that situation.
1686 for (i = 0; i < channels; i++) {
1687 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1689 dev_err(&pl08x->adev->dev,
1690 "%s no memory for channel\n", __func__);
1695 chan->state = PL08X_CHAN_IDLE;
1698 chan->cd = &pl08x->pd->slave_channels[i];
1699 pl08x_dma_slave_init(chan);
1701 chan->cd = &pl08x->pd->memcpy_channel;
1702 chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1708 if (chan->cd->circular_buffer) {
1709 dev_err(&pl08x->adev->dev,
1710 "channel %s: circular buffers not supported\n",
1715 dev_info(&pl08x->adev->dev,
1716 "initialize virtual channel \"%s\"\n",
1719 chan->chan.device = dmadev;
1720 dma_cookie_init(&chan->chan);
1722 spin_lock_init(&chan->lock);
1723 INIT_LIST_HEAD(&chan->pend_list);
1724 tasklet_init(&chan->tasklet, pl08x_tasklet,
1725 (unsigned long) chan);
1727 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1729 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1730 i, slave ? "slave" : "memcpy");
1734 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1736 struct pl08x_dma_chan *chan = NULL;
1737 struct pl08x_dma_chan *next;
1739 list_for_each_entry_safe(chan,
1740 next, &dmadev->channels, chan.device_node) {
1741 list_del(&chan->chan.device_node);
1746 #ifdef CONFIG_DEBUG_FS
1747 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1750 case PL08X_CHAN_IDLE:
1752 case PL08X_CHAN_RUNNING:
1754 case PL08X_CHAN_PAUSED:
1756 case PL08X_CHAN_WAITING:
1761 return "UNKNOWN STATE";
1764 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1766 struct pl08x_driver_data *pl08x = s->private;
1767 struct pl08x_dma_chan *chan;
1768 struct pl08x_phy_chan *ch;
1769 unsigned long flags;
1772 seq_printf(s, "PL08x physical channels:\n");
1773 seq_printf(s, "CHANNEL:\tUSER:\n");
1774 seq_printf(s, "--------\t-----\n");
1775 for (i = 0; i < pl08x->vd->channels; i++) {
1776 struct pl08x_dma_chan *virt_chan;
1778 ch = &pl08x->phy_chans[i];
1780 spin_lock_irqsave(&ch->lock, flags);
1781 virt_chan = ch->serving;
1783 seq_printf(s, "%d\t\t%s\n",
1784 ch->id, virt_chan ? virt_chan->name : "(none)");
1786 spin_unlock_irqrestore(&ch->lock, flags);
1789 seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1790 seq_printf(s, "CHANNEL:\tSTATE:\n");
1791 seq_printf(s, "--------\t------\n");
1792 list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1793 seq_printf(s, "%s\t\t%s\n", chan->name,
1794 pl08x_state_str(chan->state));
1797 seq_printf(s, "\nPL08x virtual slave channels:\n");
1798 seq_printf(s, "CHANNEL:\tSTATE:\n");
1799 seq_printf(s, "--------\t------\n");
1800 list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1801 seq_printf(s, "%s\t\t%s\n", chan->name,
1802 pl08x_state_str(chan->state));
1808 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1810 return single_open(file, pl08x_debugfs_show, inode->i_private);
1813 static const struct file_operations pl08x_debugfs_operations = {
1814 .open = pl08x_debugfs_open,
1816 .llseek = seq_lseek,
1817 .release = single_release,
1820 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1822 /* Expose a simple debugfs interface to view all clocks */
1823 (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1825 &pl08x_debugfs_operations);
1829 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1834 static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
1836 struct pl08x_driver_data *pl08x;
1837 const struct vendor_data *vd = id->data;
1841 ret = amba_request_regions(adev, NULL);
1845 /* Create the driver state holder */
1846 pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1852 /* Initialize memcpy engine */
1853 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1854 pl08x->memcpy.dev = &adev->dev;
1855 pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1856 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1857 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1858 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1859 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1860 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1861 pl08x->memcpy.device_control = pl08x_control;
1863 /* Initialize slave engine */
1864 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1865 pl08x->slave.dev = &adev->dev;
1866 pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1867 pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1868 pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1869 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1870 pl08x->slave.device_issue_pending = pl08x_issue_pending;
1871 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1872 pl08x->slave.device_control = pl08x_control;
1874 /* Get the platform data */
1875 pl08x->pd = dev_get_platdata(&adev->dev);
1877 dev_err(&adev->dev, "no platform data supplied\n");
1878 goto out_no_platdata;
1881 /* Assign useful pointers to the driver state */
1885 /* By default, AHB1 only. If dualmaster, from platform */
1886 pl08x->lli_buses = PL08X_AHB1;
1887 pl08x->mem_buses = PL08X_AHB1;
1888 if (pl08x->vd->dualmaster) {
1889 pl08x->lli_buses = pl08x->pd->lli_buses;
1890 pl08x->mem_buses = pl08x->pd->mem_buses;
1893 /* A DMA memory pool for LLIs, align on 1-byte boundary */
1894 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1895 PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1898 goto out_no_lli_pool;
1901 spin_lock_init(&pl08x->lock);
1903 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1906 goto out_no_ioremap;
1909 /* Turn on the PL08x */
1910 pl08x_ensure_on(pl08x);
1912 /* Attach the interrupt handler */
1913 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1914 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1916 ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1917 DRIVER_NAME, pl08x);
1919 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1920 __func__, adev->irq[0]);
1924 /* Initialize physical channels */
1925 pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1927 if (!pl08x->phy_chans) {
1928 dev_err(&adev->dev, "%s failed to allocate "
1929 "physical channel holders\n",
1931 goto out_no_phychans;
1934 for (i = 0; i < vd->channels; i++) {
1935 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1938 ch->base = pl08x->base + PL080_Cx_BASE(i);
1939 spin_lock_init(&ch->lock);
1942 dev_info(&adev->dev,
1943 "physical channel %d is %s\n", i,
1944 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1947 /* Register as many memcpy channels as there are physical channels */
1948 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1949 pl08x->vd->channels, false);
1951 dev_warn(&pl08x->adev->dev,
1952 "%s failed to enumerate memcpy channels - %d\n",
1956 pl08x->memcpy.chancnt = ret;
1958 /* Register slave channels */
1959 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1960 pl08x->pd->num_slave_channels,
1963 dev_warn(&pl08x->adev->dev,
1964 "%s failed to enumerate slave channels - %d\n",
1968 pl08x->slave.chancnt = ret;
1970 ret = dma_async_device_register(&pl08x->memcpy);
1972 dev_warn(&pl08x->adev->dev,
1973 "%s failed to register memcpy as an async device - %d\n",
1975 goto out_no_memcpy_reg;
1978 ret = dma_async_device_register(&pl08x->slave);
1980 dev_warn(&pl08x->adev->dev,
1981 "%s failed to register slave as an async device - %d\n",
1983 goto out_no_slave_reg;
1986 amba_set_drvdata(adev, pl08x);
1987 init_pl08x_debugfs(pl08x);
1988 dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1989 amba_part(adev), amba_rev(adev),
1990 (unsigned long long)adev->res.start, adev->irq[0]);
1994 dma_async_device_unregister(&pl08x->memcpy);
1996 pl08x_free_virtual_channels(&pl08x->slave);
1998 pl08x_free_virtual_channels(&pl08x->memcpy);
2000 kfree(pl08x->phy_chans);
2002 free_irq(adev->irq[0], pl08x);
2004 iounmap(pl08x->base);
2006 dma_pool_destroy(pl08x->pool);
2011 amba_release_regions(adev);
2015 /* PL080 has 8 channels and the PL080 have just 2 */
2016 static struct vendor_data vendor_pl080 = {
2021 static struct vendor_data vendor_pl081 = {
2023 .dualmaster = false,
2026 static struct amba_id pl08x_ids[] = {
2031 .data = &vendor_pl080,
2037 .data = &vendor_pl081,
2039 /* Nomadik 8815 PL080 variant */
2043 .data = &vendor_pl080,
2048 static struct amba_driver pl08x_amba_driver = {
2049 .drv.name = DRIVER_NAME,
2050 .id_table = pl08x_ids,
2051 .probe = pl08x_probe,
2054 static int __init pl08x_init(void)
2057 retval = amba_driver_register(&pl08x_amba_driver);
2059 printk(KERN_WARNING DRIVER_NAME
2060 "failed to register as an AMBA device (%d)\n",
2064 subsys_initcall(pl08x_init);