75f9e2d4b0322a3cf458ef1e0a75991e2394c549
[linux-2.6.git] / drivers / dma / amba-pl08x.c
1 /*
2  * Copyright (c) 2006 ARM Ltd.
3  * Copyright (c) 2010 ST-Ericsson SA
4  *
5  * Author: Peter Pearse <peter.pearse@arm.com>
6  * Author: Linus Walleij <linus.walleij@stericsson.com>
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms of the GNU General Public License as published by the Free
10  * Software Foundation; either version 2 of the License, or (at your option)
11  * any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along with
19  * this program; if not, write to the Free Software Foundation, Inc., 59
20  * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
21  *
22  * The full GNU General Public License is in this distribution in the
23  * file called COPYING.
24  *
25  * Documentation: ARM DDI 0196G == PL080
26  * Documentation: ARM DDI 0218E == PL081
27  *
28  * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
29  * any channel.
30  *
31  * The PL080 has 8 channels available for simultaneous use, and the PL081
32  * has only two channels. So on these DMA controllers the number of channels
33  * and the number of incoming DMA signals are two totally different things.
34  * It is usually not possible to theoretically handle all physical signals,
35  * so a multiplexing scheme with possible denial of use is necessary.
36  *
37  * The PL080 has a dual bus master, PL081 has a single master.
38  *
39  * Memory to peripheral transfer may be visualized as
40  *      Get data from memory to DMAC
41  *      Until no data left
42  *              On burst request from peripheral
43  *                      Destination burst from DMAC to peripheral
44  *                      Clear burst request
45  *      Raise terminal count interrupt
46  *
47  * For peripherals with a FIFO:
48  * Source      burst size == half the depth of the peripheral FIFO
49  * Destination burst size == the depth of the peripheral FIFO
50  *
51  * (Bursts are irrelevant for mem to mem transfers - there are no burst
52  * signals, the DMA controller will simply facilitate its AHB master.)
53  *
54  * ASSUMES default (little) endianness for DMA transfers
55  *
56  * The PL08x has two flow control settings:
57  *  - DMAC flow control: the transfer size defines the number of transfers
58  *    which occur for the current LLI entry, and the DMAC raises TC at the
59  *    end of every LLI entry.  Observed behaviour shows the DMAC listening
60  *    to both the BREQ and SREQ signals (contrary to documented),
61  *    transferring data if either is active.  The LBREQ and LSREQ signals
62  *    are ignored.
63  *
64  *  - Peripheral flow control: the transfer size is ignored (and should be
65  *    zero).  The data is transferred from the current LLI entry, until
66  *    after the final transfer signalled by LBREQ or LSREQ.  The DMAC
67  *    will then move to the next LLI entry.
68  *
69  * Only the former works sanely with scatter lists, so we only implement
70  * the DMAC flow control method.  However, peripherals which use the LBREQ
71  * and LSREQ signals (eg, MMCI) are unable to use this mode, which through
72  * these hardware restrictions prevents them from using scatter DMA.
73  *
74  * Global TODO:
75  * - Break out common code from arch/arm/mach-s3c64xx and share
76  */
77 #include <linux/device.h>
78 #include <linux/init.h>
79 #include <linux/module.h>
80 #include <linux/interrupt.h>
81 #include <linux/slab.h>
82 #include <linux/dmapool.h>
83 #include <linux/dmaengine.h>
84 #include <linux/amba/bus.h>
85 #include <linux/amba/pl08x.h>
86 #include <linux/debugfs.h>
87 #include <linux/seq_file.h>
88
89 #include <asm/hardware/pl080.h>
90
91 #define DRIVER_NAME     "pl08xdmac"
92
93 /**
94  * struct vendor_data - vendor-specific config parameters
95  * for PL08x derivatives
96  * @channels: the number of channels available in this variant
97  * @dualmaster: whether this version supports dual AHB masters
98  * or not.
99  */
100 struct vendor_data {
101         u8 channels;
102         bool dualmaster;
103 };
104
105 /*
106  * PL08X private data structures
107  * An LLI struct - see PL08x TRM.  Note that next uses bit[0] as a bus bit,
108  * start & end do not - their bus bit info is in cctl.  Also note that these
109  * are fixed 32-bit quantities.
110  */
111 struct pl08x_lli {
112         u32 src;
113         u32 dst;
114         u32 lli;
115         u32 cctl;
116 };
117
118 /**
119  * struct pl08x_driver_data - the local state holder for the PL08x
120  * @slave: slave engine for this instance
121  * @memcpy: memcpy engine for this instance
122  * @base: virtual memory base (remapped) for the PL08x
123  * @adev: the corresponding AMBA (PrimeCell) bus entry
124  * @vd: vendor data for this PL08x variant
125  * @pd: platform data passed in from the platform/machine
126  * @phy_chans: array of data for the physical channels
127  * @pool: a pool for the LLI descriptors
128  * @pool_ctr: counter of LLIs in the pool
129  * @lock: a spinlock for this struct
130  */
131 struct pl08x_driver_data {
132         struct dma_device slave;
133         struct dma_device memcpy;
134         void __iomem *base;
135         struct amba_device *adev;
136         const struct vendor_data *vd;
137         struct pl08x_platform_data *pd;
138         struct pl08x_phy_chan *phy_chans;
139         struct dma_pool *pool;
140         int pool_ctr;
141         spinlock_t lock;
142 };
143
144 /*
145  * PL08X specific defines
146  */
147
148 /*
149  * Memory boundaries: the manual for PL08x says that the controller
150  * cannot read past a 1KiB boundary, so these defines are used to
151  * create transfer LLIs that do not cross such boundaries.
152  */
153 #define PL08X_BOUNDARY_SHIFT            (10)    /* 1KB 0x400 */
154 #define PL08X_BOUNDARY_SIZE             (1 << PL08X_BOUNDARY_SHIFT)
155
156 /* Minimum period between work queue runs */
157 #define PL08X_WQ_PERIODMIN      20
158
159 /* Size (bytes) of each LLI buffer allocated for one transfer */
160 # define PL08X_LLI_TSFR_SIZE    0x2000
161
162 /* Maximum times we call dma_pool_alloc on this pool without freeing */
163 #define PL08X_MAX_ALLOCS        0x40
164 #define MAX_NUM_TSFR_LLIS       (PL08X_LLI_TSFR_SIZE/sizeof(struct pl08x_lli))
165 #define PL08X_ALIGN             8
166
167 static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
168 {
169         return container_of(chan, struct pl08x_dma_chan, chan);
170 }
171
172 /*
173  * Physical channel handling
174  */
175
176 /* Whether a certain channel is busy or not */
177 static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
178 {
179         unsigned int val;
180
181         val = readl(ch->base + PL080_CH_CONFIG);
182         return val & PL080_CONFIG_ACTIVE;
183 }
184
185 /*
186  * Set the initial DMA register values i.e. those for the first LLI
187  * The next LLI pointer and the configuration interrupt bit have
188  * been set when the LLIs were constructed.  Poke them into the hardware
189  * and start the transfer.
190  */
191 static void pl08x_start_txd(struct pl08x_dma_chan *plchan,
192         struct pl08x_txd *txd)
193 {
194         struct pl08x_driver_data *pl08x = plchan->host;
195         struct pl08x_phy_chan *phychan = plchan->phychan;
196         struct pl08x_lli *lli = &txd->llis_va[0];
197         u32 val, ccfg = txd->ccfg;
198
199         plchan->at = txd;
200
201         /* Assign the flow control signal to this channel */
202         if (txd->direction == DMA_TO_DEVICE)
203                 /* Select signal as destination */
204                 ccfg |= phychan->signal << PL080_CONFIG_DST_SEL_SHIFT;
205         else if (txd->direction == DMA_FROM_DEVICE)
206                 /* Select signal as source */
207                 ccfg |= phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
208
209         /* Wait for channel inactive */
210         while (pl08x_phy_channel_busy(phychan))
211                 cpu_relax();
212
213         dev_vdbg(&pl08x->adev->dev,
214                 "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
215                 "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
216                 phychan->id, lli->src, lli->dst, lli->lli, lli->cctl,
217                 ccfg);
218
219         writel(lli->src, phychan->base + PL080_CH_SRC_ADDR);
220         writel(lli->dst, phychan->base + PL080_CH_DST_ADDR);
221         writel(lli->lli, phychan->base + PL080_CH_LLI);
222         writel(lli->cctl, phychan->base + PL080_CH_CONTROL);
223         writel(ccfg, phychan->base + PL080_CH_CONFIG);
224
225         /* Enable the DMA channel */
226         /* Do not access config register until channel shows as disabled */
227         while (readl(pl08x->base + PL080_EN_CHAN) & (1 << phychan->id))
228                 cpu_relax();
229
230         /* Do not access config register until channel shows as inactive */
231         val = readl(phychan->base + PL080_CH_CONFIG);
232         while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
233                 val = readl(phychan->base + PL080_CH_CONFIG);
234
235         writel(val | PL080_CONFIG_ENABLE, phychan->base + PL080_CH_CONFIG);
236 }
237
238 /*
239  * Overall DMAC remains enabled always.
240  *
241  * Disabling individual channels could lose data.
242  *
243  * Disable the peripheral DMA after disabling the DMAC
244  * in order to allow the DMAC FIFO to drain, and
245  * hence allow the channel to show inactive
246  *
247  */
248 static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
249 {
250         u32 val;
251
252         /* Set the HALT bit and wait for the FIFO to drain */
253         val = readl(ch->base + PL080_CH_CONFIG);
254         val |= PL080_CONFIG_HALT;
255         writel(val, ch->base + PL080_CH_CONFIG);
256
257         /* Wait for channel inactive */
258         while (pl08x_phy_channel_busy(ch))
259                 cpu_relax();
260 }
261
262 static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
263 {
264         u32 val;
265
266         /* Clear the HALT bit */
267         val = readl(ch->base + PL080_CH_CONFIG);
268         val &= ~PL080_CONFIG_HALT;
269         writel(val, ch->base + PL080_CH_CONFIG);
270 }
271
272
273 /* Stops the channel */
274 static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
275 {
276         u32 val;
277
278         pl08x_pause_phy_chan(ch);
279
280         /* Disable channel */
281         val = readl(ch->base + PL080_CH_CONFIG);
282         val &= ~PL080_CONFIG_ENABLE;
283         val &= ~PL080_CONFIG_ERR_IRQ_MASK;
284         val &= ~PL080_CONFIG_TC_IRQ_MASK;
285         writel(val, ch->base + PL080_CH_CONFIG);
286 }
287
288 static inline u32 get_bytes_in_cctl(u32 cctl)
289 {
290         /* The source width defines the number of bytes */
291         u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
292
293         switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
294         case PL080_WIDTH_8BIT:
295                 break;
296         case PL080_WIDTH_16BIT:
297                 bytes *= 2;
298                 break;
299         case PL080_WIDTH_32BIT:
300                 bytes *= 4;
301                 break;
302         }
303         return bytes;
304 }
305
306 /* The channel should be paused when calling this */
307 static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
308 {
309         struct pl08x_phy_chan *ch;
310         struct pl08x_txd *txd;
311         unsigned long flags;
312         size_t bytes = 0;
313
314         spin_lock_irqsave(&plchan->lock, flags);
315         ch = plchan->phychan;
316         txd = plchan->at;
317
318         /*
319          * Follow the LLIs to get the number of remaining
320          * bytes in the currently active transaction.
321          */
322         if (ch && txd) {
323                 u32 clli = readl(ch->base + PL080_CH_LLI) & ~PL080_LLI_LM_AHB2;
324
325                 /* First get the remaining bytes in the active transfer */
326                 bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
327
328                 if (clli) {
329                         struct pl08x_lli *llis_va = txd->llis_va;
330                         dma_addr_t llis_bus = txd->llis_bus;
331                         int index;
332
333                         BUG_ON(clli < llis_bus || clli >= llis_bus +
334                                 sizeof(struct pl08x_lli) * MAX_NUM_TSFR_LLIS);
335
336                         /*
337                          * Locate the next LLI - as this is an array,
338                          * it's simple maths to find.
339                          */
340                         index = (clli - llis_bus) / sizeof(struct pl08x_lli);
341
342                         for (; index < MAX_NUM_TSFR_LLIS; index++) {
343                                 bytes += get_bytes_in_cctl(llis_va[index].cctl);
344
345                                 /*
346                                  * A LLI pointer of 0 terminates the LLI list
347                                  */
348                                 if (!llis_va[index].lli)
349                                         break;
350                         }
351                 }
352         }
353
354         /* Sum up all queued transactions */
355         if (!list_empty(&plchan->desc_list)) {
356                 struct pl08x_txd *txdi;
357                 list_for_each_entry(txdi, &plchan->desc_list, node) {
358                         bytes += txdi->len;
359                 }
360         }
361
362         spin_unlock_irqrestore(&plchan->lock, flags);
363
364         return bytes;
365 }
366
367 /*
368  * Allocate a physical channel for a virtual channel
369  */
370 static struct pl08x_phy_chan *
371 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
372                       struct pl08x_dma_chan *virt_chan)
373 {
374         struct pl08x_phy_chan *ch = NULL;
375         unsigned long flags;
376         int i;
377
378         /*
379          * Try to locate a physical channel to be used for
380          * this transfer. If all are taken return NULL and
381          * the requester will have to cope by using some fallback
382          * PIO mode or retrying later.
383          */
384         for (i = 0; i < pl08x->vd->channels; i++) {
385                 ch = &pl08x->phy_chans[i];
386
387                 spin_lock_irqsave(&ch->lock, flags);
388
389                 if (!ch->serving) {
390                         ch->serving = virt_chan;
391                         ch->signal = -1;
392                         spin_unlock_irqrestore(&ch->lock, flags);
393                         break;
394                 }
395
396                 spin_unlock_irqrestore(&ch->lock, flags);
397         }
398
399         if (i == pl08x->vd->channels) {
400                 /* No physical channel available, cope with it */
401                 return NULL;
402         }
403
404         return ch;
405 }
406
407 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
408                                          struct pl08x_phy_chan *ch)
409 {
410         unsigned long flags;
411
412         /* Stop the channel and clear its interrupts */
413         pl08x_stop_phy_chan(ch);
414         writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
415         writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
416
417         /* Mark it as free */
418         spin_lock_irqsave(&ch->lock, flags);
419         ch->serving = NULL;
420         spin_unlock_irqrestore(&ch->lock, flags);
421 }
422
423 /*
424  * LLI handling
425  */
426
427 static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
428 {
429         switch (coded) {
430         case PL080_WIDTH_8BIT:
431                 return 1;
432         case PL080_WIDTH_16BIT:
433                 return 2;
434         case PL080_WIDTH_32BIT:
435                 return 4;
436         default:
437                 break;
438         }
439         BUG();
440         return 0;
441 }
442
443 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
444                                   size_t tsize)
445 {
446         u32 retbits = cctl;
447
448         /* Remove all src, dst and transfer size bits */
449         retbits &= ~PL080_CONTROL_DWIDTH_MASK;
450         retbits &= ~PL080_CONTROL_SWIDTH_MASK;
451         retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
452
453         /* Then set the bits according to the parameters */
454         switch (srcwidth) {
455         case 1:
456                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
457                 break;
458         case 2:
459                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
460                 break;
461         case 4:
462                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
463                 break;
464         default:
465                 BUG();
466                 break;
467         }
468
469         switch (dstwidth) {
470         case 1:
471                 retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
472                 break;
473         case 2:
474                 retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
475                 break;
476         case 4:
477                 retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
478                 break;
479         default:
480                 BUG();
481                 break;
482         }
483
484         retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
485         return retbits;
486 }
487
488 /*
489  * Autoselect a master bus to use for the transfer
490  * this prefers the destination bus if both available
491  * if fixed address on one bus the other will be chosen
492  */
493 static void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
494         struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
495         struct pl08x_bus_data **sbus, u32 cctl)
496 {
497         if (!(cctl & PL080_CONTROL_DST_INCR)) {
498                 *mbus = src_bus;
499                 *sbus = dst_bus;
500         } else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
501                 *mbus = dst_bus;
502                 *sbus = src_bus;
503         } else {
504                 if (dst_bus->buswidth == 4) {
505                         *mbus = dst_bus;
506                         *sbus = src_bus;
507                 } else if (src_bus->buswidth == 4) {
508                         *mbus = src_bus;
509                         *sbus = dst_bus;
510                 } else if (dst_bus->buswidth == 2) {
511                         *mbus = dst_bus;
512                         *sbus = src_bus;
513                 } else if (src_bus->buswidth == 2) {
514                         *mbus = src_bus;
515                         *sbus = dst_bus;
516                 } else {
517                         /* src_bus->buswidth == 1 */
518                         *mbus = dst_bus;
519                         *sbus = src_bus;
520                 }
521         }
522 }
523
524 /*
525  * Fills in one LLI for a certain transfer descriptor
526  * and advance the counter
527  */
528 static int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
529                             struct pl08x_txd *txd, int num_llis, int len,
530                             u32 cctl, u32 *remainder)
531 {
532         struct pl08x_lli *llis_va = txd->llis_va;
533         dma_addr_t llis_bus = txd->llis_bus;
534
535         BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
536
537         llis_va[num_llis].cctl          = cctl;
538         llis_va[num_llis].src           = txd->srcbus.addr;
539         llis_va[num_llis].dst           = txd->dstbus.addr;
540
541         /*
542          * On versions with dual masters, you can optionally AND on
543          * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
544          * in new LLIs with that controller, but we always try to
545          * choose AHB1 to point into memory. The idea is to have AHB2
546          * fixed on the peripheral and AHB1 messing around in the
547          * memory. So we don't manipulate this bit currently.
548          */
549
550         llis_va[num_llis].lli = llis_bus + (num_llis + 1) * sizeof(struct pl08x_lli);
551
552         if (cctl & PL080_CONTROL_SRC_INCR)
553                 txd->srcbus.addr += len;
554         if (cctl & PL080_CONTROL_DST_INCR)
555                 txd->dstbus.addr += len;
556
557         BUG_ON(*remainder < len);
558
559         *remainder -= len;
560
561         return num_llis + 1;
562 }
563
564 /*
565  * Return number of bytes to fill to boundary, or len
566  */
567 static inline size_t pl08x_pre_boundary(u32 addr, size_t len)
568 {
569         u32 boundary;
570
571         boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
572                 << PL08X_BOUNDARY_SHIFT;
573
574         if (boundary < addr + len)
575                 return boundary - addr;
576         else
577                 return len;
578 }
579
580 /*
581  * This fills in the table of LLIs for the transfer descriptor
582  * Note that we assume we never have to change the burst sizes
583  * Return 0 for error
584  */
585 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
586                               struct pl08x_txd *txd)
587 {
588         struct pl08x_channel_data *cd = txd->cd;
589         struct pl08x_bus_data *mbus, *sbus;
590         size_t remainder;
591         int num_llis = 0;
592         u32 cctl;
593         size_t max_bytes_per_lli;
594         size_t total_bytes = 0;
595         struct pl08x_lli *llis_va;
596
597         txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT,
598                                       &txd->llis_bus);
599         if (!txd->llis_va) {
600                 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
601                 return 0;
602         }
603
604         pl08x->pool_ctr++;
605
606         /*
607          * Initialize bus values for this transfer
608          * from the passed optimal values
609          */
610         if (!cd) {
611                 dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
612                 return 0;
613         }
614
615         /* Get the default CCTL from the platform data */
616         cctl = cd->cctl;
617
618         /*
619          * On the PL080 we have two bus masters and we
620          * should select one for source and one for
621          * destination. We try to use AHB2 for the
622          * bus which does not increment (typically the
623          * peripheral) else we just choose something.
624          */
625         cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
626         if (pl08x->vd->dualmaster) {
627                 if (cctl & PL080_CONTROL_SRC_INCR)
628                         /* Source increments, use AHB2 for destination */
629                         cctl |= PL080_CONTROL_DST_AHB2;
630                 else if (cctl & PL080_CONTROL_DST_INCR)
631                         /* Destination increments, use AHB2 for source */
632                         cctl |= PL080_CONTROL_SRC_AHB2;
633                 else
634                         /* Just pick something, source AHB1 dest AHB2 */
635                         cctl |= PL080_CONTROL_DST_AHB2;
636         }
637
638         /* Find maximum width of the source bus */
639         txd->srcbus.maxwidth =
640                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
641                                        PL080_CONTROL_SWIDTH_SHIFT);
642
643         /* Find maximum width of the destination bus */
644         txd->dstbus.maxwidth =
645                 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
646                                        PL080_CONTROL_DWIDTH_SHIFT);
647
648         /* Set up the bus widths to the maximum */
649         txd->srcbus.buswidth = txd->srcbus.maxwidth;
650         txd->dstbus.buswidth = txd->dstbus.maxwidth;
651         dev_vdbg(&pl08x->adev->dev,
652                  "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
653                  __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
654
655
656         /*
657          * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
658          */
659         max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
660                 PL080_CONTROL_TRANSFER_SIZE_MASK;
661         dev_vdbg(&pl08x->adev->dev,
662                  "%s max bytes per lli = %zu\n",
663                  __func__, max_bytes_per_lli);
664
665         /* We need to count this down to zero */
666         remainder = txd->len;
667         dev_vdbg(&pl08x->adev->dev,
668                  "%s remainder = %zu\n",
669                  __func__, remainder);
670
671         /*
672          * Choose bus to align to
673          * - prefers destination bus if both available
674          * - if fixed address on one bus chooses other
675          * - modifies cctl to choose an appropriate master
676          */
677         pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
678                                 &mbus, &sbus, cctl);
679
680
681         /*
682          * The lowest bit of the LLI register
683          * is also used to indicate which master to
684          * use for reading the LLIs.
685          */
686
687         if (txd->len < mbus->buswidth) {
688                 /*
689                  * Less than a bus width available
690                  * - send as single bytes
691                  */
692                 while (remainder) {
693                         dev_vdbg(&pl08x->adev->dev,
694                                  "%s single byte LLIs for a transfer of "
695                                  "less than a bus width (remain 0x%08x)\n",
696                                  __func__, remainder);
697                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
698                         num_llis =
699                                 pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
700                                         cctl, &remainder);
701                         total_bytes++;
702                 }
703         } else {
704                 /*
705                  *  Make one byte LLIs until master bus is aligned
706                  *  - slave will then be aligned also
707                  */
708                 while ((mbus->addr) % (mbus->buswidth)) {
709                         dev_vdbg(&pl08x->adev->dev,
710                                 "%s adjustment lli for less than bus width "
711                                  "(remain 0x%08x)\n",
712                                  __func__, remainder);
713                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
714                         num_llis = pl08x_fill_lli_for_desc
715                                 (pl08x, txd, num_llis, 1, cctl, &remainder);
716                         total_bytes++;
717                 }
718
719                 /*
720                  *  Master now aligned
721                  * - if slave is not then we must set its width down
722                  */
723                 if (sbus->addr % sbus->buswidth) {
724                         dev_dbg(&pl08x->adev->dev,
725                                 "%s set down bus width to one byte\n",
726                                  __func__);
727
728                         sbus->buswidth = 1;
729                 }
730
731                 /*
732                  * Make largest possible LLIs until less than one bus
733                  * width left
734                  */
735                 while (remainder > (mbus->buswidth - 1)) {
736                         size_t lli_len, target_len, tsize, odd_bytes;
737
738                         /*
739                          * If enough left try to send max possible,
740                          * otherwise try to send the remainder
741                          */
742                         target_len = remainder;
743                         if (remainder > max_bytes_per_lli)
744                                 target_len = max_bytes_per_lli;
745
746                         /*
747                          * Set bus lengths for incrementing buses
748                          * to number of bytes which fill to next memory
749                          * boundary
750                          */
751                         if (cctl & PL080_CONTROL_SRC_INCR)
752                                 txd->srcbus.fill_bytes =
753                                         pl08x_pre_boundary(
754                                                 txd->srcbus.addr,
755                                                 remainder);
756                         else
757                                 txd->srcbus.fill_bytes =
758                                         max_bytes_per_lli;
759
760                         if (cctl & PL080_CONTROL_DST_INCR)
761                                 txd->dstbus.fill_bytes =
762                                         pl08x_pre_boundary(
763                                                 txd->dstbus.addr,
764                                                 remainder);
765                         else
766                                 txd->dstbus.fill_bytes =
767                                                 max_bytes_per_lli;
768
769                         /*
770                          *  Find the nearest
771                          */
772                         lli_len = min(txd->srcbus.fill_bytes,
773                                 txd->dstbus.fill_bytes);
774
775                         BUG_ON(lli_len > remainder);
776
777                         if (lli_len <= 0) {
778                                 dev_err(&pl08x->adev->dev,
779                                         "%s lli_len is %zu, <= 0\n",
780                                                 __func__, lli_len);
781                                 return 0;
782                         }
783
784                         if (lli_len == target_len) {
785                                 /*
786                                  * Can send what we wanted
787                                  */
788                                 /*
789                                  *  Maintain alignment
790                                  */
791                                 lli_len = (lli_len/mbus->buswidth) *
792                                                         mbus->buswidth;
793                                 odd_bytes = 0;
794                         } else {
795                                 /*
796                                  * So now we know how many bytes to transfer
797                                  * to get to the nearest boundary
798                                  * The next LLI will past the boundary
799                                  * - however we may be working to a boundary
800                                  *   on the slave bus
801                                  *   We need to ensure the master stays aligned
802                                  */
803                                 odd_bytes = lli_len % mbus->buswidth;
804                                 /*
805                                  * - and that we are working in multiples
806                                  *   of the bus widths
807                                  */
808                                 lli_len -= odd_bytes;
809
810                         }
811
812                         if (lli_len) {
813                                 /*
814                                  * Check against minimum bus alignment:
815                                  * Calculate actual transfer size in relation
816                                  * to bus width an get a maximum remainder of
817                                  * the smallest bus width - 1
818                                  */
819                                 /* FIXME: use round_down()? */
820                                 tsize = lli_len / min(mbus->buswidth,
821                                                       sbus->buswidth);
822                                 lli_len = tsize * min(mbus->buswidth,
823                                                       sbus->buswidth);
824
825                                 if (target_len != lli_len) {
826                                         dev_vdbg(&pl08x->adev->dev,
827                                         "%s can't send what we want. Desired 0x%08zx, lli of 0x%08zx bytes in txd of 0x%08zx\n",
828                                         __func__, target_len, lli_len, txd->len);
829                                 }
830
831                                 cctl = pl08x_cctl_bits(cctl,
832                                                        txd->srcbus.buswidth,
833                                                        txd->dstbus.buswidth,
834                                                        tsize);
835
836                                 dev_vdbg(&pl08x->adev->dev,
837                                         "%s fill lli with single lli chunk of size 0x%08zx (remainder 0x%08zx)\n",
838                                         __func__, lli_len, remainder);
839                                 num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
840                                                 num_llis, lli_len, cctl,
841                                                 &remainder);
842                                 total_bytes += lli_len;
843                         }
844
845
846                         if (odd_bytes) {
847                                 /*
848                                  * Creep past the boundary,
849                                  * maintaining master alignment
850                                  */
851                                 int j;
852                                 for (j = 0; (j < mbus->buswidth)
853                                                 && (remainder); j++) {
854                                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
855                                         dev_vdbg(&pl08x->adev->dev,
856                                                 "%s align with boundary, single byte (remain 0x%08zx)\n",
857                                                 __func__, remainder);
858                                         num_llis =
859                                                 pl08x_fill_lli_for_desc(pl08x,
860                                                         txd, num_llis, 1,
861                                                         cctl, &remainder);
862                                         total_bytes++;
863                                 }
864                         }
865                 }
866
867                 /*
868                  * Send any odd bytes
869                  */
870                 while (remainder) {
871                         cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
872                         dev_vdbg(&pl08x->adev->dev,
873                                 "%s align with boundary, single odd byte (remain %zu)\n",
874                                 __func__, remainder);
875                         num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
876                                         1, cctl, &remainder);
877                         total_bytes++;
878                 }
879         }
880         if (total_bytes != txd->len) {
881                 dev_err(&pl08x->adev->dev,
882                         "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
883                         __func__, total_bytes, txd->len);
884                 return 0;
885         }
886
887         if (num_llis >= MAX_NUM_TSFR_LLIS) {
888                 dev_err(&pl08x->adev->dev,
889                         "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
890                         __func__, (u32) MAX_NUM_TSFR_LLIS);
891                 return 0;
892         }
893
894         llis_va = txd->llis_va;
895         /*
896          * The final LLI terminates the LLI.
897          */
898         llis_va[num_llis - 1].lli = 0;
899         /*
900          * The final LLI element shall also fire an interrupt
901          */
902         llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
903
904 #ifdef VERBOSE_DEBUG
905         {
906                 int i;
907
908                 for (i = 0; i < num_llis; i++) {
909                         dev_vdbg(&pl08x->adev->dev,
910                                  "lli %d @%p: csrc=0x%08x, cdst=0x%08x, cctl=0x%08x, clli=0x%08x\n",
911                                  i,
912                                  &llis_va[i],
913                                  llis_va[i].src,
914                                  llis_va[i].dst,
915                                  llis_va[i].cctl,
916                                  llis_va[i].lli
917                                 );
918                 }
919         }
920 #endif
921
922         return num_llis;
923 }
924
925 /* You should call this with the struct pl08x lock held */
926 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
927                            struct pl08x_txd *txd)
928 {
929         /* Free the LLI */
930         dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
931
932         pl08x->pool_ctr--;
933
934         kfree(txd);
935 }
936
937 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
938                                 struct pl08x_dma_chan *plchan)
939 {
940         struct pl08x_txd *txdi = NULL;
941         struct pl08x_txd *next;
942
943         if (!list_empty(&plchan->desc_list)) {
944                 list_for_each_entry_safe(txdi,
945                                          next, &plchan->desc_list, node) {
946                         list_del(&txdi->node);
947                         pl08x_free_txd(pl08x, txdi);
948                 }
949
950         }
951 }
952
953 /*
954  * The DMA ENGINE API
955  */
956 static int pl08x_alloc_chan_resources(struct dma_chan *chan)
957 {
958         return 0;
959 }
960
961 static void pl08x_free_chan_resources(struct dma_chan *chan)
962 {
963 }
964
965 /*
966  * This should be called with the channel plchan->lock held
967  */
968 static int prep_phy_channel(struct pl08x_dma_chan *plchan,
969                             struct pl08x_txd *txd)
970 {
971         struct pl08x_driver_data *pl08x = plchan->host;
972         struct pl08x_phy_chan *ch;
973         int ret;
974
975         /* Check if we already have a channel */
976         if (plchan->phychan)
977                 return 0;
978
979         ch = pl08x_get_phy_channel(pl08x, plchan);
980         if (!ch) {
981                 /* No physical channel available, cope with it */
982                 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
983                 return -EBUSY;
984         }
985
986         /*
987          * OK we have a physical channel: for memcpy() this is all we
988          * need, but for slaves the physical signals may be muxed!
989          * Can the platform allow us to use this channel?
990          */
991         if (plchan->slave &&
992             ch->signal < 0 &&
993             pl08x->pd->get_signal) {
994                 ret = pl08x->pd->get_signal(plchan);
995                 if (ret < 0) {
996                         dev_dbg(&pl08x->adev->dev,
997                                 "unable to use physical channel %d for transfer on %s due to platform restrictions\n",
998                                 ch->id, plchan->name);
999                         /* Release physical channel & return */
1000                         pl08x_put_phy_channel(pl08x, ch);
1001                         return -EBUSY;
1002                 }
1003                 ch->signal = ret;
1004         }
1005
1006         dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
1007                  ch->id,
1008                  ch->signal,
1009                  plchan->name);
1010
1011         plchan->phychan = ch;
1012
1013         return 0;
1014 }
1015
1016 static void release_phy_channel(struct pl08x_dma_chan *plchan)
1017 {
1018         struct pl08x_driver_data *pl08x = plchan->host;
1019
1020         if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal) {
1021                 pl08x->pd->put_signal(plchan);
1022                 plchan->phychan->signal = -1;
1023         }
1024         pl08x_put_phy_channel(pl08x, plchan->phychan);
1025         plchan->phychan = NULL;
1026 }
1027
1028 static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
1029 {
1030         struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
1031
1032         plchan->chan.cookie += 1;
1033         if (plchan->chan.cookie < 0)
1034                 plchan->chan.cookie = 1;
1035         tx->cookie = plchan->chan.cookie;
1036         /* This unlock follows the lock in the prep() function */
1037         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1038
1039         return tx->cookie;
1040 }
1041
1042 static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
1043                 struct dma_chan *chan, unsigned long flags)
1044 {
1045         struct dma_async_tx_descriptor *retval = NULL;
1046
1047         return retval;
1048 }
1049
1050 /*
1051  * Code accessing dma_async_is_complete() in a tight loop
1052  * may give problems - could schedule where indicated.
1053  * If slaves are relying on interrupts to signal completion this
1054  * function must not be called with interrupts disabled
1055  */
1056 static enum dma_status
1057 pl08x_dma_tx_status(struct dma_chan *chan,
1058                     dma_cookie_t cookie,
1059                     struct dma_tx_state *txstate)
1060 {
1061         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1062         dma_cookie_t last_used;
1063         dma_cookie_t last_complete;
1064         enum dma_status ret;
1065         u32 bytesleft = 0;
1066
1067         last_used = plchan->chan.cookie;
1068         last_complete = plchan->lc;
1069
1070         ret = dma_async_is_complete(cookie, last_complete, last_used);
1071         if (ret == DMA_SUCCESS) {
1072                 dma_set_tx_state(txstate, last_complete, last_used, 0);
1073                 return ret;
1074         }
1075
1076         /*
1077          * schedule(); could be inserted here
1078          */
1079
1080         /*
1081          * This cookie not complete yet
1082          */
1083         last_used = plchan->chan.cookie;
1084         last_complete = plchan->lc;
1085
1086         /* Get number of bytes left in the active transactions and queue */
1087         bytesleft = pl08x_getbytes_chan(plchan);
1088
1089         dma_set_tx_state(txstate, last_complete, last_used,
1090                          bytesleft);
1091
1092         if (plchan->state == PL08X_CHAN_PAUSED)
1093                 return DMA_PAUSED;
1094
1095         /* Whether waiting or running, we're in progress */
1096         return DMA_IN_PROGRESS;
1097 }
1098
1099 /* PrimeCell DMA extension */
1100 struct burst_table {
1101         int burstwords;
1102         u32 reg;
1103 };
1104
1105 static const struct burst_table burst_sizes[] = {
1106         {
1107                 .burstwords = 256,
1108                 .reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
1109                         (PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
1110         },
1111         {
1112                 .burstwords = 128,
1113                 .reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
1114                         (PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
1115         },
1116         {
1117                 .burstwords = 64,
1118                 .reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
1119                         (PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
1120         },
1121         {
1122                 .burstwords = 32,
1123                 .reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
1124                         (PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
1125         },
1126         {
1127                 .burstwords = 16,
1128                 .reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
1129                         (PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
1130         },
1131         {
1132                 .burstwords = 8,
1133                 .reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
1134                         (PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
1135         },
1136         {
1137                 .burstwords = 4,
1138                 .reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
1139                         (PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
1140         },
1141         {
1142                 .burstwords = 1,
1143                 .reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1144                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
1145         },
1146 };
1147
1148 static void dma_set_runtime_config(struct dma_chan *chan,
1149                                struct dma_slave_config *config)
1150 {
1151         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1152         struct pl08x_driver_data *pl08x = plchan->host;
1153         struct pl08x_channel_data *cd = plchan->cd;
1154         enum dma_slave_buswidth addr_width;
1155         u32 maxburst;
1156         u32 cctl = 0;
1157         int i;
1158
1159         /* Transfer direction */
1160         plchan->runtime_direction = config->direction;
1161         if (config->direction == DMA_TO_DEVICE) {
1162                 plchan->runtime_addr = config->dst_addr;
1163                 cctl |= PL080_CONTROL_SRC_INCR;
1164                 addr_width = config->dst_addr_width;
1165                 maxburst = config->dst_maxburst;
1166         } else if (config->direction == DMA_FROM_DEVICE) {
1167                 plchan->runtime_addr = config->src_addr;
1168                 cctl |= PL080_CONTROL_DST_INCR;
1169                 addr_width = config->src_addr_width;
1170                 maxburst = config->src_maxburst;
1171         } else {
1172                 dev_err(&pl08x->adev->dev,
1173                         "bad runtime_config: alien transfer direction\n");
1174                 return;
1175         }
1176
1177         switch (addr_width) {
1178         case DMA_SLAVE_BUSWIDTH_1_BYTE:
1179                 cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1180                         (PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
1181                 break;
1182         case DMA_SLAVE_BUSWIDTH_2_BYTES:
1183                 cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1184                         (PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
1185                 break;
1186         case DMA_SLAVE_BUSWIDTH_4_BYTES:
1187                 cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
1188                         (PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
1189                 break;
1190         default:
1191                 dev_err(&pl08x->adev->dev,
1192                         "bad runtime_config: alien address width\n");
1193                 return;
1194         }
1195
1196         /*
1197          * Now decide on a maxburst:
1198          * If this channel will only request single transfers, set this
1199          * down to ONE element.  Also select one element if no maxburst
1200          * is specified.
1201          */
1202         if (plchan->cd->single || maxburst == 0) {
1203                 cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
1204                         (PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
1205         } else {
1206                 for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
1207                         if (burst_sizes[i].burstwords <= maxburst)
1208                                 break;
1209                 cctl |= burst_sizes[i].reg;
1210         }
1211
1212         /* Access the cell in privileged mode, non-bufferable, non-cacheable */
1213         cctl &= ~PL080_CONTROL_PROT_MASK;
1214         cctl |= PL080_CONTROL_PROT_SYS;
1215
1216         /* Modify the default channel data to fit PrimeCell request */
1217         cd->cctl = cctl;
1218
1219         dev_dbg(&pl08x->adev->dev,
1220                 "configured channel %s (%s) for %s, data width %d, "
1221                 "maxburst %d words, LE, CCTL=0x%08x\n",
1222                 dma_chan_name(chan), plchan->name,
1223                 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
1224                 addr_width,
1225                 maxburst,
1226                 cctl);
1227 }
1228
1229 /*
1230  * Slave transactions callback to the slave device to allow
1231  * synchronization of slave DMA signals with the DMAC enable
1232  */
1233 static void pl08x_issue_pending(struct dma_chan *chan)
1234 {
1235         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1236         unsigned long flags;
1237
1238         spin_lock_irqsave(&plchan->lock, flags);
1239         /* Something is already active, or we're waiting for a channel... */
1240         if (plchan->at || plchan->state == PL08X_CHAN_WAITING) {
1241                 spin_unlock_irqrestore(&plchan->lock, flags);
1242                 return;
1243         }
1244
1245         /* Take the first element in the queue and execute it */
1246         if (!list_empty(&plchan->desc_list)) {
1247                 struct pl08x_txd *next;
1248
1249                 next = list_first_entry(&plchan->desc_list,
1250                                         struct pl08x_txd,
1251                                         node);
1252                 list_del(&next->node);
1253                 plchan->state = PL08X_CHAN_RUNNING;
1254
1255                 pl08x_start_txd(plchan, next);
1256         }
1257
1258         spin_unlock_irqrestore(&plchan->lock, flags);
1259 }
1260
1261 static int pl08x_prep_channel_resources(struct pl08x_dma_chan *plchan,
1262                                         struct pl08x_txd *txd)
1263 {
1264         int num_llis;
1265         struct pl08x_driver_data *pl08x = plchan->host;
1266         int ret;
1267
1268         num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
1269         if (!num_llis) {
1270                 kfree(txd);
1271                 return -EINVAL;
1272         }
1273
1274         spin_lock_irqsave(&plchan->lock, plchan->lockflags);
1275
1276         list_add_tail(&txd->node, &plchan->desc_list);
1277
1278         /*
1279          * See if we already have a physical channel allocated,
1280          * else this is the time to try to get one.
1281          */
1282         ret = prep_phy_channel(plchan, txd);
1283         if (ret) {
1284                 /*
1285                  * No physical channel available, we will
1286                  * stack up the memcpy channels until there is a channel
1287                  * available to handle it whereas slave transfers may
1288                  * have been denied due to platform channel muxing restrictions
1289                  * and since there is no guarantee that this will ever be
1290                  * resolved, and since the signal must be acquired AFTER
1291                  * acquiring the physical channel, we will let them be NACK:ed
1292                  * with -EBUSY here. The drivers can alway retry the prep()
1293                  * call if they are eager on doing this using DMA.
1294                  */
1295                 if (plchan->slave) {
1296                         pl08x_free_txd_list(pl08x, plchan);
1297                         spin_unlock_irqrestore(&plchan->lock, plchan->lockflags);
1298                         return -EBUSY;
1299                 }
1300                 /* Do this memcpy whenever there is a channel ready */
1301                 plchan->state = PL08X_CHAN_WAITING;
1302                 plchan->waiting = txd;
1303         } else
1304                 /*
1305                  * Else we're all set, paused and ready to roll,
1306                  * status will switch to PL08X_CHAN_RUNNING when
1307                  * we call issue_pending(). If there is something
1308                  * running on the channel already we don't change
1309                  * its state.
1310                  */
1311                 if (plchan->state == PL08X_CHAN_IDLE)
1312                         plchan->state = PL08X_CHAN_PAUSED;
1313
1314         /*
1315          * Notice that we leave plchan->lock locked on purpose:
1316          * it will be unlocked in the subsequent tx_submit()
1317          * call. This is a consequence of the current API.
1318          */
1319
1320         return 0;
1321 }
1322
1323 static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
1324 {
1325         struct pl08x_txd *txd = kzalloc(sizeof(struct pl08x_txd), GFP_NOWAIT);
1326
1327         if (txd) {
1328                 dma_async_tx_descriptor_init(&txd->tx, &plchan->chan);
1329                 txd->tx.tx_submit = pl08x_tx_submit;
1330                 INIT_LIST_HEAD(&txd->node);
1331
1332                 /* Always enable error and terminal interrupts */
1333                 txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
1334                             PL080_CONFIG_TC_IRQ_MASK;
1335         }
1336         return txd;
1337 }
1338
1339 /*
1340  * Initialize a descriptor to be used by memcpy submit
1341  */
1342 static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
1343                 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1344                 size_t len, unsigned long flags)
1345 {
1346         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1347         struct pl08x_driver_data *pl08x = plchan->host;
1348         struct pl08x_txd *txd;
1349         int ret;
1350
1351         txd = pl08x_get_txd(plchan);
1352         if (!txd) {
1353                 dev_err(&pl08x->adev->dev,
1354                         "%s no memory for descriptor\n", __func__);
1355                 return NULL;
1356         }
1357
1358         txd->direction = DMA_NONE;
1359         txd->srcbus.addr = src;
1360         txd->dstbus.addr = dest;
1361
1362         /* Set platform data for m2m */
1363         txd->cd = &pl08x->pd->memcpy_channel;
1364         txd->ccfg |= PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1365
1366         /* Both to be incremented or the code will break */
1367         txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
1368         txd->len = len;
1369
1370         ret = pl08x_prep_channel_resources(plchan, txd);
1371         if (ret)
1372                 return NULL;
1373         /*
1374          * NB: the channel lock is held at this point so tx_submit()
1375          * must be called in direct succession.
1376          */
1377
1378         return &txd->tx;
1379 }
1380
1381 static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
1382                 struct dma_chan *chan, struct scatterlist *sgl,
1383                 unsigned int sg_len, enum dma_data_direction direction,
1384                 unsigned long flags)
1385 {
1386         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1387         struct pl08x_driver_data *pl08x = plchan->host;
1388         struct pl08x_txd *txd;
1389         int ret;
1390
1391         /*
1392          * Current implementation ASSUMES only one sg
1393          */
1394         if (sg_len != 1) {
1395                 dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
1396                         __func__);
1397                 BUG();
1398         }
1399
1400         dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
1401                 __func__, sgl->length, plchan->name);
1402
1403         txd = pl08x_get_txd(plchan);
1404         if (!txd) {
1405                 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1406                 return NULL;
1407         }
1408
1409         if (direction != plchan->runtime_direction)
1410                 dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
1411                         "the direction configured for the PrimeCell\n",
1412                         __func__);
1413
1414         /*
1415          * Set up addresses, the PrimeCell configured address
1416          * will take precedence since this may configure the
1417          * channel target address dynamically at runtime.
1418          */
1419         txd->direction = direction;
1420         if (direction == DMA_TO_DEVICE) {
1421                 txd->ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1422                 txd->srcbus.addr = sgl->dma_address;
1423                 if (plchan->runtime_addr)
1424                         txd->dstbus.addr = plchan->runtime_addr;
1425                 else
1426                         txd->dstbus.addr = plchan->cd->addr;
1427         } else if (direction == DMA_FROM_DEVICE) {
1428                 txd->ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
1429                 if (plchan->runtime_addr)
1430                         txd->srcbus.addr = plchan->runtime_addr;
1431                 else
1432                         txd->srcbus.addr = plchan->cd->addr;
1433                 txd->dstbus.addr = sgl->dma_address;
1434         } else {
1435                 dev_err(&pl08x->adev->dev,
1436                         "%s direction unsupported\n", __func__);
1437                 return NULL;
1438         }
1439         txd->cd = plchan->cd;
1440         txd->len = sgl->length;
1441
1442         ret = pl08x_prep_channel_resources(plchan, txd);
1443         if (ret)
1444                 return NULL;
1445         /*
1446          * NB: the channel lock is held at this point so tx_submit()
1447          * must be called in direct succession.
1448          */
1449
1450         return &txd->tx;
1451 }
1452
1453 static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
1454                          unsigned long arg)
1455 {
1456         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1457         struct pl08x_driver_data *pl08x = plchan->host;
1458         unsigned long flags;
1459         int ret = 0;
1460
1461         /* Controls applicable to inactive channels */
1462         if (cmd == DMA_SLAVE_CONFIG) {
1463                 dma_set_runtime_config(chan,
1464                                        (struct dma_slave_config *)
1465                                        arg);
1466                 return 0;
1467         }
1468
1469         /*
1470          * Anything succeeds on channels with no physical allocation and
1471          * no queued transfers.
1472          */
1473         spin_lock_irqsave(&plchan->lock, flags);
1474         if (!plchan->phychan && !plchan->at) {
1475                 spin_unlock_irqrestore(&plchan->lock, flags);
1476                 return 0;
1477         }
1478
1479         switch (cmd) {
1480         case DMA_TERMINATE_ALL:
1481                 plchan->state = PL08X_CHAN_IDLE;
1482
1483                 if (plchan->phychan) {
1484                         pl08x_stop_phy_chan(plchan->phychan);
1485
1486                         /*
1487                          * Mark physical channel as free and free any slave
1488                          * signal
1489                          */
1490                         release_phy_channel(plchan);
1491                 }
1492                 /* Dequeue jobs and free LLIs */
1493                 if (plchan->at) {
1494                         pl08x_free_txd(pl08x, plchan->at);
1495                         plchan->at = NULL;
1496                 }
1497                 /* Dequeue jobs not yet fired as well */
1498                 pl08x_free_txd_list(pl08x, plchan);
1499                 break;
1500         case DMA_PAUSE:
1501                 pl08x_pause_phy_chan(plchan->phychan);
1502                 plchan->state = PL08X_CHAN_PAUSED;
1503                 break;
1504         case DMA_RESUME:
1505                 pl08x_resume_phy_chan(plchan->phychan);
1506                 plchan->state = PL08X_CHAN_RUNNING;
1507                 break;
1508         default:
1509                 /* Unknown command */
1510                 ret = -ENXIO;
1511                 break;
1512         }
1513
1514         spin_unlock_irqrestore(&plchan->lock, flags);
1515
1516         return ret;
1517 }
1518
1519 bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
1520 {
1521         struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
1522         char *name = chan_id;
1523
1524         /* Check that the channel is not taken! */
1525         if (!strcmp(plchan->name, name))
1526                 return true;
1527
1528         return false;
1529 }
1530
1531 /*
1532  * Just check that the device is there and active
1533  * TODO: turn this bit on/off depending on the number of
1534  * physical channels actually used, if it is zero... well
1535  * shut it off. That will save some power. Cut the clock
1536  * at the same time.
1537  */
1538 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
1539 {
1540         u32 val;
1541
1542         val = readl(pl08x->base + PL080_CONFIG);
1543         val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
1544         /* We implicitly clear bit 1 and that means little-endian mode */
1545         val |= PL080_CONFIG_ENABLE;
1546         writel(val, pl08x->base + PL080_CONFIG);
1547 }
1548
1549 static void pl08x_tasklet(unsigned long data)
1550 {
1551         struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
1552         struct pl08x_driver_data *pl08x = plchan->host;
1553         unsigned long flags;
1554
1555         spin_lock_irqsave(&plchan->lock, flags);
1556
1557         if (plchan->at) {
1558                 dma_async_tx_callback callback =
1559                         plchan->at->tx.callback;
1560                 void *callback_param =
1561                         plchan->at->tx.callback_param;
1562
1563                 /*
1564                  * Update last completed
1565                  */
1566                 plchan->lc = plchan->at->tx.cookie;
1567
1568                 /*
1569                  * Callback to signal completion
1570                  */
1571                 if (callback)
1572                         callback(callback_param);
1573
1574                 /*
1575                  * Free the descriptor
1576                  */
1577                 pl08x_free_txd(pl08x, plchan->at);
1578                 plchan->at = NULL;
1579         }
1580         /*
1581          * If a new descriptor is queued, set it up
1582          * plchan->at is NULL here
1583          */
1584         if (!list_empty(&plchan->desc_list)) {
1585                 struct pl08x_txd *next;
1586
1587                 next = list_first_entry(&plchan->desc_list,
1588                                         struct pl08x_txd,
1589                                         node);
1590                 list_del(&next->node);
1591
1592                 pl08x_start_txd(plchan, next);
1593         } else {
1594                 struct pl08x_dma_chan *waiting = NULL;
1595
1596                 /*
1597                  * No more jobs, so free up the physical channel
1598                  * Free any allocated signal on slave transfers too
1599                  */
1600                 release_phy_channel(plchan);
1601                 plchan->state = PL08X_CHAN_IDLE;
1602
1603                 /*
1604                  * And NOW before anyone else can grab that free:d
1605                  * up physical channel, see if there is some memcpy
1606                  * pending that seriously needs to start because of
1607                  * being stacked up while we were choking the
1608                  * physical channels with data.
1609                  */
1610                 list_for_each_entry(waiting, &pl08x->memcpy.channels,
1611                                     chan.device_node) {
1612                   if (waiting->state == PL08X_CHAN_WAITING &&
1613                             waiting->waiting != NULL) {
1614                                 int ret;
1615
1616                                 /* This should REALLY not fail now */
1617                                 ret = prep_phy_channel(waiting,
1618                                                        waiting->waiting);
1619                                 BUG_ON(ret);
1620                                 waiting->state = PL08X_CHAN_RUNNING;
1621                                 waiting->waiting = NULL;
1622                                 pl08x_issue_pending(&waiting->chan);
1623                                 break;
1624                         }
1625                 }
1626         }
1627
1628         spin_unlock_irqrestore(&plchan->lock, flags);
1629 }
1630
1631 static irqreturn_t pl08x_irq(int irq, void *dev)
1632 {
1633         struct pl08x_driver_data *pl08x = dev;
1634         u32 mask = 0;
1635         u32 val;
1636         int i;
1637
1638         val = readl(pl08x->base + PL080_ERR_STATUS);
1639         if (val) {
1640                 /*
1641                  * An error interrupt (on one or more channels)
1642                  */
1643                 dev_err(&pl08x->adev->dev,
1644                         "%s error interrupt, register value 0x%08x\n",
1645                                 __func__, val);
1646                 /*
1647                  * Simply clear ALL PL08X error interrupts,
1648                  * regardless of channel and cause
1649                  * FIXME: should be 0x00000003 on PL081 really.
1650                  */
1651                 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1652         }
1653         val = readl(pl08x->base + PL080_INT_STATUS);
1654         for (i = 0; i < pl08x->vd->channels; i++) {
1655                 if ((1 << i) & val) {
1656                         /* Locate physical channel */
1657                         struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
1658                         struct pl08x_dma_chan *plchan = phychan->serving;
1659
1660                         /* Schedule tasklet on this channel */
1661                         tasklet_schedule(&plchan->tasklet);
1662
1663                         mask |= (1 << i);
1664                 }
1665         }
1666         /*
1667          * Clear only the terminal interrupts on channels we processed
1668          */
1669         writel(mask, pl08x->base + PL080_TC_CLEAR);
1670
1671         return mask ? IRQ_HANDLED : IRQ_NONE;
1672 }
1673
1674 /*
1675  * Initialise the DMAC memcpy/slave channels.
1676  * Make a local wrapper to hold required data
1677  */
1678 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
1679                                            struct dma_device *dmadev,
1680                                            unsigned int channels,
1681                                            bool slave)
1682 {
1683         struct pl08x_dma_chan *chan;
1684         int i;
1685
1686         INIT_LIST_HEAD(&dmadev->channels);
1687         /*
1688          * Register as many many memcpy as we have physical channels,
1689          * we won't always be able to use all but the code will have
1690          * to cope with that situation.
1691          */
1692         for (i = 0; i < channels; i++) {
1693                 chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
1694                 if (!chan) {
1695                         dev_err(&pl08x->adev->dev,
1696                                 "%s no memory for channel\n", __func__);
1697                         return -ENOMEM;
1698                 }
1699
1700                 chan->host = pl08x;
1701                 chan->state = PL08X_CHAN_IDLE;
1702
1703                 if (slave) {
1704                         chan->slave = true;
1705                         chan->name = pl08x->pd->slave_channels[i].bus_id;
1706                         chan->cd = &pl08x->pd->slave_channels[i];
1707                 } else {
1708                         chan->cd = &pl08x->pd->memcpy_channel;
1709                         chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
1710                         if (!chan->name) {
1711                                 kfree(chan);
1712                                 return -ENOMEM;
1713                         }
1714                 }
1715                 if (chan->cd->circular_buffer) {
1716                         dev_err(&pl08x->adev->dev,
1717                                 "channel %s: circular buffers not supported\n",
1718                                 chan->name);
1719                         kfree(chan);
1720                         continue;
1721                 }
1722                 dev_info(&pl08x->adev->dev,
1723                          "initialize virtual channel \"%s\"\n",
1724                          chan->name);
1725
1726                 chan->chan.device = dmadev;
1727                 chan->chan.cookie = 0;
1728                 chan->lc = 0;
1729
1730                 spin_lock_init(&chan->lock);
1731                 INIT_LIST_HEAD(&chan->desc_list);
1732                 tasklet_init(&chan->tasklet, pl08x_tasklet,
1733                              (unsigned long) chan);
1734
1735                 list_add_tail(&chan->chan.device_node, &dmadev->channels);
1736         }
1737         dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
1738                  i, slave ? "slave" : "memcpy");
1739         return i;
1740 }
1741
1742 static void pl08x_free_virtual_channels(struct dma_device *dmadev)
1743 {
1744         struct pl08x_dma_chan *chan = NULL;
1745         struct pl08x_dma_chan *next;
1746
1747         list_for_each_entry_safe(chan,
1748                                  next, &dmadev->channels, chan.device_node) {
1749                 list_del(&chan->chan.device_node);
1750                 kfree(chan);
1751         }
1752 }
1753
1754 #ifdef CONFIG_DEBUG_FS
1755 static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
1756 {
1757         switch (state) {
1758         case PL08X_CHAN_IDLE:
1759                 return "idle";
1760         case PL08X_CHAN_RUNNING:
1761                 return "running";
1762         case PL08X_CHAN_PAUSED:
1763                 return "paused";
1764         case PL08X_CHAN_WAITING:
1765                 return "waiting";
1766         default:
1767                 break;
1768         }
1769         return "UNKNOWN STATE";
1770 }
1771
1772 static int pl08x_debugfs_show(struct seq_file *s, void *data)
1773 {
1774         struct pl08x_driver_data *pl08x = s->private;
1775         struct pl08x_dma_chan *chan;
1776         struct pl08x_phy_chan *ch;
1777         unsigned long flags;
1778         int i;
1779
1780         seq_printf(s, "PL08x physical channels:\n");
1781         seq_printf(s, "CHANNEL:\tUSER:\n");
1782         seq_printf(s, "--------\t-----\n");
1783         for (i = 0; i < pl08x->vd->channels; i++) {
1784                 struct pl08x_dma_chan *virt_chan;
1785
1786                 ch = &pl08x->phy_chans[i];
1787
1788                 spin_lock_irqsave(&ch->lock, flags);
1789                 virt_chan = ch->serving;
1790
1791                 seq_printf(s, "%d\t\t%s\n",
1792                            ch->id, virt_chan ? virt_chan->name : "(none)");
1793
1794                 spin_unlock_irqrestore(&ch->lock, flags);
1795         }
1796
1797         seq_printf(s, "\nPL08x virtual memcpy channels:\n");
1798         seq_printf(s, "CHANNEL:\tSTATE:\n");
1799         seq_printf(s, "--------\t------\n");
1800         list_for_each_entry(chan, &pl08x->memcpy.channels, chan.device_node) {
1801                 seq_printf(s, "%s\t\t%s\n", chan->name,
1802                            pl08x_state_str(chan->state));
1803         }
1804
1805         seq_printf(s, "\nPL08x virtual slave channels:\n");
1806         seq_printf(s, "CHANNEL:\tSTATE:\n");
1807         seq_printf(s, "--------\t------\n");
1808         list_for_each_entry(chan, &pl08x->slave.channels, chan.device_node) {
1809                 seq_printf(s, "%s\t\t%s\n", chan->name,
1810                            pl08x_state_str(chan->state));
1811         }
1812
1813         return 0;
1814 }
1815
1816 static int pl08x_debugfs_open(struct inode *inode, struct file *file)
1817 {
1818         return single_open(file, pl08x_debugfs_show, inode->i_private);
1819 }
1820
1821 static const struct file_operations pl08x_debugfs_operations = {
1822         .open           = pl08x_debugfs_open,
1823         .read           = seq_read,
1824         .llseek         = seq_lseek,
1825         .release        = single_release,
1826 };
1827
1828 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1829 {
1830         /* Expose a simple debugfs interface to view all clocks */
1831         (void) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
1832                                    NULL, pl08x,
1833                                    &pl08x_debugfs_operations);
1834 }
1835
1836 #else
1837 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
1838 {
1839 }
1840 #endif
1841
1842 static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
1843 {
1844         struct pl08x_driver_data *pl08x;
1845         const struct vendor_data *vd = id->data;
1846         int ret = 0;
1847         int i;
1848
1849         ret = amba_request_regions(adev, NULL);
1850         if (ret)
1851                 return ret;
1852
1853         /* Create the driver state holder */
1854         pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
1855         if (!pl08x) {
1856                 ret = -ENOMEM;
1857                 goto out_no_pl08x;
1858         }
1859
1860         /* Initialize memcpy engine */
1861         dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
1862         pl08x->memcpy.dev = &adev->dev;
1863         pl08x->memcpy.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1864         pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
1865         pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
1866         pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1867         pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
1868         pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
1869         pl08x->memcpy.device_control = pl08x_control;
1870
1871         /* Initialize slave engine */
1872         dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
1873         pl08x->slave.dev = &adev->dev;
1874         pl08x->slave.device_alloc_chan_resources = pl08x_alloc_chan_resources;
1875         pl08x->slave.device_free_chan_resources = pl08x_free_chan_resources;
1876         pl08x->slave.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
1877         pl08x->slave.device_tx_status = pl08x_dma_tx_status;
1878         pl08x->slave.device_issue_pending = pl08x_issue_pending;
1879         pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
1880         pl08x->slave.device_control = pl08x_control;
1881
1882         /* Get the platform data */
1883         pl08x->pd = dev_get_platdata(&adev->dev);
1884         if (!pl08x->pd) {
1885                 dev_err(&adev->dev, "no platform data supplied\n");
1886                 goto out_no_platdata;
1887         }
1888
1889         /* Assign useful pointers to the driver state */
1890         pl08x->adev = adev;
1891         pl08x->vd = vd;
1892
1893         /* A DMA memory pool for LLIs, align on 1-byte boundary */
1894         pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
1895                         PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
1896         if (!pl08x->pool) {
1897                 ret = -ENOMEM;
1898                 goto out_no_lli_pool;
1899         }
1900
1901         spin_lock_init(&pl08x->lock);
1902
1903         pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
1904         if (!pl08x->base) {
1905                 ret = -ENOMEM;
1906                 goto out_no_ioremap;
1907         }
1908
1909         /* Turn on the PL08x */
1910         pl08x_ensure_on(pl08x);
1911
1912         /*
1913          * Attach the interrupt handler
1914          */
1915         writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
1916         writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
1917
1918         ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
1919                           DRIVER_NAME, pl08x);
1920         if (ret) {
1921                 dev_err(&adev->dev, "%s failed to request interrupt %d\n",
1922                         __func__, adev->irq[0]);
1923                 goto out_no_irq;
1924         }
1925
1926         /* Initialize physical channels */
1927         pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
1928                         GFP_KERNEL);
1929         if (!pl08x->phy_chans) {
1930                 dev_err(&adev->dev, "%s failed to allocate "
1931                         "physical channel holders\n",
1932                         __func__);
1933                 goto out_no_phychans;
1934         }
1935
1936         for (i = 0; i < vd->channels; i++) {
1937                 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
1938
1939                 ch->id = i;
1940                 ch->base = pl08x->base + PL080_Cx_BASE(i);
1941                 spin_lock_init(&ch->lock);
1942                 ch->serving = NULL;
1943                 ch->signal = -1;
1944                 dev_info(&adev->dev,
1945                          "physical channel %d is %s\n", i,
1946                          pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
1947         }
1948
1949         /* Register as many memcpy channels as there are physical channels */
1950         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
1951                                               pl08x->vd->channels, false);
1952         if (ret <= 0) {
1953                 dev_warn(&pl08x->adev->dev,
1954                          "%s failed to enumerate memcpy channels - %d\n",
1955                          __func__, ret);
1956                 goto out_no_memcpy;
1957         }
1958         pl08x->memcpy.chancnt = ret;
1959
1960         /* Register slave channels */
1961         ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
1962                                               pl08x->pd->num_slave_channels,
1963                                               true);
1964         if (ret <= 0) {
1965                 dev_warn(&pl08x->adev->dev,
1966                         "%s failed to enumerate slave channels - %d\n",
1967                                 __func__, ret);
1968                 goto out_no_slave;
1969         }
1970         pl08x->slave.chancnt = ret;
1971
1972         ret = dma_async_device_register(&pl08x->memcpy);
1973         if (ret) {
1974                 dev_warn(&pl08x->adev->dev,
1975                         "%s failed to register memcpy as an async device - %d\n",
1976                         __func__, ret);
1977                 goto out_no_memcpy_reg;
1978         }
1979
1980         ret = dma_async_device_register(&pl08x->slave);
1981         if (ret) {
1982                 dev_warn(&pl08x->adev->dev,
1983                         "%s failed to register slave as an async device - %d\n",
1984                         __func__, ret);
1985                 goto out_no_slave_reg;
1986         }
1987
1988         amba_set_drvdata(adev, pl08x);
1989         init_pl08x_debugfs(pl08x);
1990         dev_info(&pl08x->adev->dev, "DMA: PL%03x rev%u at 0x%08llx irq %d\n",
1991                  amba_part(adev), amba_rev(adev),
1992                  (unsigned long long)adev->res.start, adev->irq[0]);
1993         return 0;
1994
1995 out_no_slave_reg:
1996         dma_async_device_unregister(&pl08x->memcpy);
1997 out_no_memcpy_reg:
1998         pl08x_free_virtual_channels(&pl08x->slave);
1999 out_no_slave:
2000         pl08x_free_virtual_channels(&pl08x->memcpy);
2001 out_no_memcpy:
2002         kfree(pl08x->phy_chans);
2003 out_no_phychans:
2004         free_irq(adev->irq[0], pl08x);
2005 out_no_irq:
2006         iounmap(pl08x->base);
2007 out_no_ioremap:
2008         dma_pool_destroy(pl08x->pool);
2009 out_no_lli_pool:
2010 out_no_platdata:
2011         kfree(pl08x);
2012 out_no_pl08x:
2013         amba_release_regions(adev);
2014         return ret;
2015 }
2016
2017 /* PL080 has 8 channels and the PL080 have just 2 */
2018 static struct vendor_data vendor_pl080 = {
2019         .channels = 8,
2020         .dualmaster = true,
2021 };
2022
2023 static struct vendor_data vendor_pl081 = {
2024         .channels = 2,
2025         .dualmaster = false,
2026 };
2027
2028 static struct amba_id pl08x_ids[] = {
2029         /* PL080 */
2030         {
2031                 .id     = 0x00041080,
2032                 .mask   = 0x000fffff,
2033                 .data   = &vendor_pl080,
2034         },
2035         /* PL081 */
2036         {
2037                 .id     = 0x00041081,
2038                 .mask   = 0x000fffff,
2039                 .data   = &vendor_pl081,
2040         },
2041         /* Nomadik 8815 PL080 variant */
2042         {
2043                 .id     = 0x00280880,
2044                 .mask   = 0x00ffffff,
2045                 .data   = &vendor_pl080,
2046         },
2047         { 0, 0 },
2048 };
2049
2050 static struct amba_driver pl08x_amba_driver = {
2051         .drv.name       = DRIVER_NAME,
2052         .id_table       = pl08x_ids,
2053         .probe          = pl08x_probe,
2054 };
2055
2056 static int __init pl08x_init(void)
2057 {
2058         int retval;
2059         retval = amba_driver_register(&pl08x_amba_driver);
2060         if (retval)
2061                 printk(KERN_WARNING DRIVER_NAME
2062                        "failed to register as an AMBA device (%d)\n",
2063                        retval);
2064         return retval;
2065 }
2066 subsys_initcall(pl08x_init);