crypto: tegra-aes: get hardware ownership before copying key
[linux-2.6.git] / drivers / crypto / tegra-aes.c
1 /*
2  * drivers/crypto/tegra-aes.c
3  *
4  * aes driver for NVIDIA tegra aes hardware
5  *
6  * Copyright (c) 2010-2011, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/errno.h>
26 #include <linux/kernel.h>
27 #include <linux/clk.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/io.h>
32 #include <linux/mutex.h>
33 #include <linux/interrupt.h>
34 #include <linux/completion.h>
35 #include <linux/workqueue.h>
36
37 #include <mach/arb_sema.h>
38 #include <mach/clk.h>
39 #include "../video/tegra/nvmap/nvmap.h"
40
41 #include <crypto/scatterwalk.h>
42 #include <crypto/aes.h>
43 #include <crypto/internal/rng.h>
44
45 #include "tegra-aes.h"
46
47 #define FLAGS_MODE_MASK         0x00ff
48 #define FLAGS_ENCRYPT           BIT(0)
49 #define FLAGS_CBC               BIT(1)
50 #define FLAGS_GIV               BIT(2)
51 #define FLAGS_RNG               BIT(3)
52 #define FLAGS_OFB               BIT(4)
53 #define FLAGS_INIT              BIT(5)
54 #define FLAGS_BUSY              1
55
56 /*
57  * Defines AES engine Max process bytes size in one go, which takes 1 msec.
58  * AES engine spends about 176 cycles/16-bytes or 11 cycles/byte
59  * The duration CPU can use the BSE to 1 msec, then the number of available
60  * cycles of AVP/BSE is 216K. In this duration, AES can process 216/11 ~= 19KB
61  * Based on this AES_HW_DMA_BUFFER_SIZE_BYTES is configured to 16KB.
62  */
63 #define AES_HW_DMA_BUFFER_SIZE_BYTES    0x4000
64
65 /*
66  * The key table length is 64 bytes
67  * (This includes first upto 32 bytes key + 16 bytes original initial vector
68  * and 16 bytes updated initial vector)
69  */
70 #define AES_HW_KEY_TABLE_LENGTH_BYTES   64
71
72 #define AES_HW_IV_SIZE  16
73 #define AES_HW_KEYSCHEDULE_LEN  256
74 #define ARB_SEMA_TIMEOUT        500
75
76 /*
77  * The memory being used is divides as follows:
78  * 1. Key - 32 bytes
79  * 2. Original IV - 16 bytes
80  * 3. Updated IV - 16 bytes
81  * 4. Key schedule - 256 bytes
82  *
83  * 1+2+3 constitute the hw key table.
84  */
85 #define AES_IVKEY_SIZE (AES_HW_KEY_TABLE_LENGTH_BYTES + AES_HW_KEYSCHEDULE_LEN)
86
87 #define DEFAULT_RNG_BLK_SZ      16
88
89 /* As of now only 5 commands are USED for AES encryption/Decryption */
90 #define AES_HW_MAX_ICQ_LENGTH   4
91
92 #define ICQBITSHIFT_BLKCNT      0
93
94 /* memdma_vd command */
95 #define MEMDMA_DIR_DTOVRAM      0
96 #define MEMDMA_DIR_VTODRAM      1
97 #define MEMDMABITSHIFT_DIR      25
98 #define MEMDMABITSHIFT_NUM_WORDS        12
99
100 /* Define AES Interactive command Queue commands Bit positions */
101 enum {
102         ICQBITSHIFT_KEYTABLEADDR = 0,
103         ICQBITSHIFT_KEYTABLEID = 17,
104         ICQBITSHIFT_VRAMSEL = 23,
105         ICQBITSHIFT_TABLESEL = 24,
106         ICQBITSHIFT_OPCODE = 26,
107 };
108
109 /* Define Ucq opcodes required for AES operation */
110 enum {
111         UCQOPCODE_BLKSTARTENGINE = 0x0E,
112         UCQOPCODE_DMASETUP = 0x10,
113         UCQOPCODE_DMACOMPLETE = 0x11,
114         UCQOPCODE_SETTABLE = 0x15,
115         UCQOPCODE_MEMDMAVD = 0x22,
116 };
117
118 /* Define Aes command values */
119 enum {
120         UCQCMD_VRAM_SEL = 0x1,
121         UCQCMD_CRYPTO_TABLESEL = 0x3,
122         UCQCMD_KEYSCHEDTABLESEL = 0x4,
123         UCQCMD_KEYTABLESEL = 0x8,
124 };
125
126 #define UCQCMD_KEYTABLEADDRMASK 0x1FFFF
127
128 #define AES_NR_KEYSLOTS 8
129 #define SSK_SLOT_NUM    4
130
131 struct tegra_aes_slot {
132         struct list_head node;
133         int slot_num;
134         bool available;
135 };
136
137 struct tegra_aes_reqctx {
138         unsigned long mode;
139 };
140
141 #define TEGRA_AES_QUEUE_LENGTH  500
142
143 struct tegra_aes_engine {
144         struct tegra_aes_dev *dd;
145         struct tegra_aes_ctx *ctx;
146         struct clk *iclk;
147         struct clk *pclk;
148         struct ablkcipher_request *req;
149         struct scatterlist *in_sg;
150         struct completion op_complete;
151         struct scatterlist *out_sg;
152         void __iomem *io_base;
153         void __iomem *ivkey_base;
154         unsigned long phys_base;
155         unsigned long iram_phys;
156         void *iram_virt;
157         dma_addr_t ivkey_phys_base;
158         dma_addr_t dma_buf_in;
159         dma_addr_t dma_buf_out;
160         size_t total;
161         size_t in_offset;
162         size_t out_offset;
163         u32 engine_offset;
164         u32 *buf_in;
165         u32 *buf_out;
166         int res_id;
167         unsigned long busy;
168         u8 irq;
169         bool new_key;
170         u32 status;
171 };
172
173 struct tegra_aes_dev {
174         struct device *dev;
175         struct tegra_aes_slot *slots;
176         struct tegra_aes_engine bsev;
177         struct tegra_aes_engine bsea;
178         struct nvmap_client *client;
179         struct nvmap_handle_ref *h_ref;
180         struct crypto_queue queue;
181         spinlock_t lock;
182         u64 ctr;
183         unsigned long flags;
184         u8 dt[DEFAULT_RNG_BLK_SZ];
185 };
186
187 static struct tegra_aes_dev *aes_dev;
188
189 struct tegra_aes_ctx {
190         struct tegra_aes_dev *dd;
191         struct tegra_aes_engine *eng;
192         struct tegra_aes_slot *slot;
193         int key[AES_MAX_KEY_SIZE];
194         int keylen;
195         bool use_ssk;
196         u8 dt[DEFAULT_RNG_BLK_SZ];
197 };
198
199 static struct tegra_aes_ctx rng_ctx;
200
201 /* keep registered devices data here */
202 static LIST_HEAD(slot_list);
203 static DEFINE_SPINLOCK(list_lock);
204
205 /* Engine specific work queues */
206 static void bsev_workqueue_handler(struct work_struct *work);
207 static void bsea_workqueue_handler(struct work_struct *work);
208
209 static DECLARE_WORK(bsev_work, bsev_workqueue_handler);
210 static DECLARE_WORK(bsea_work, bsea_workqueue_handler);
211
212 static struct workqueue_struct *bsev_wq;
213 static struct workqueue_struct *bsea_wq;
214
215 extern unsigned long long tegra_chip_uid(void);
216
217 static inline u32 aes_readl(struct tegra_aes_engine *engine, u32 offset)
218 {
219         return readl(engine->io_base + offset);
220 }
221
222 static inline void aes_writel(struct tegra_aes_engine *engine,
223         u32 val, u32 offset)
224 {
225         writel(val, engine->io_base + offset);
226 }
227
228 static int alloc_iram(struct tegra_aes_dev *dd)
229 {
230         size_t size;
231         int err;
232
233         dd->h_ref = NULL;
234
235         /* [key+iv+u-iv=64B] * 8 = 512Bytes */
236         size = AES_MAX_KEY_SIZE;
237         dd->client = nvmap_create_client(nvmap_dev, "aes_bsea");
238         if (IS_ERR(dd->client)) {
239                 dev_err(dd->dev, "nvmap_create_client failed\n");
240                 goto out;
241         }
242
243         dd->h_ref = nvmap_create_handle(dd->client, size);
244         if (IS_ERR(dd->h_ref)) {
245                 dev_err(dd->dev, "nvmap_create_handle failed\n");
246                 goto out;
247         }
248
249         /* Allocate memory in the iram */
250         err = nvmap_alloc_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref),
251                 NVMAP_HEAP_CARVEOUT_IRAM, size, 0);
252         if (err) {
253                 dev_err(dd->dev, "nvmap_alloc_handle_id failed\n");
254                 nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
255                 goto out;
256         }
257         dd->bsea.iram_phys = nvmap_handle_address(dd->client,
258                                         nvmap_ref_to_id(dd->h_ref));
259
260         dd->bsea.iram_virt = nvmap_mmap(dd->h_ref);     /* get virtual address */
261         if (!dd->bsea.iram_virt) {
262                 dev_err(dd->dev, "%s: no mem, BSEA IRAM alloc failure\n",
263                         __func__);
264                 goto out;
265         }
266
267         memset(dd->bsea.iram_virt, 0, size);
268         return 0;
269
270 out:
271         if (dd->bsea.iram_virt)
272                 nvmap_munmap(dd->h_ref, dd->bsea.iram_virt);
273
274         if (dd->client) {
275                 nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
276                 nvmap_client_put(dd->client);
277         }
278
279         return -ENOMEM;
280 }
281
282 static void free_iram(struct tegra_aes_dev *dd)
283 {
284         if (dd->bsea.iram_virt)
285                 nvmap_munmap(dd->h_ref, dd->bsea.iram_virt);
286
287         if (dd->client) {
288                 nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
289                 nvmap_client_put(dd->client);
290         }
291 }
292
293 static int aes_hw_init(struct tegra_aes_engine *engine)
294 {
295         struct tegra_aes_dev *dd = aes_dev;
296         int ret = 0;
297
298         if (engine->pclk) {
299                 ret = clk_enable(engine->pclk);
300                 if (ret < 0) {
301                         dev_err(dd->dev, "%s: pclock enable fail(%d)\n",
302                         __func__, ret);
303                         return ret;
304                 }
305         }
306
307         if (engine->iclk) {
308                 ret = clk_enable(engine->iclk);
309                 if (ret < 0) {
310                         dev_err(dd->dev, "%s: iclock enable fail(%d)\n",
311                         __func__, ret);
312                         if (engine->pclk)
313                                 clk_disable(engine->pclk);
314                         return ret;
315                 }
316         }
317
318         return ret;
319 }
320
321 static void aes_hw_deinit(struct tegra_aes_engine *engine)
322 {
323         if (engine->pclk)
324                 clk_disable(engine->pclk);
325
326         if (engine->iclk)
327                 clk_disable(engine->iclk);
328 }
329
330 #define MIN_RETRIES     3
331 static int aes_start_crypt(struct tegra_aes_engine *eng, u32 in_addr,
332         u32 out_addr, int nblocks, int mode, bool upd_iv)
333 {
334         u32 cmdq[AES_HW_MAX_ICQ_LENGTH];
335         int qlen = 0, i, eng_busy, icq_empty, ret;
336         u32 value;
337         int retries = MIN_RETRIES;
338
339 start:
340         do {
341                 value = aes_readl(eng, INTR_STATUS);
342                 eng_busy = value & BIT(0);
343                 icq_empty = value & BIT(3);
344         } while (eng_busy || (!icq_empty));
345
346         aes_writel(eng, 0xFFFFFFFF, INTR_STATUS);
347
348         /* error, dma xfer complete */
349         aes_writel(eng, 0x33, INT_ENB);
350         enable_irq(eng->irq);
351
352         cmdq[qlen++] = UCQOPCODE_DMASETUP << ICQBITSHIFT_OPCODE;
353         cmdq[qlen++] = in_addr;
354         cmdq[qlen++] = UCQOPCODE_BLKSTARTENGINE << ICQBITSHIFT_OPCODE |
355                 (nblocks-1) << ICQBITSHIFT_BLKCNT;
356         cmdq[qlen++] = UCQOPCODE_DMACOMPLETE << ICQBITSHIFT_OPCODE;
357
358         value = aes_readl(eng, CMDQUE_CONTROL);
359         /* access SDRAM through AHB */
360         value &= (~CMDQ_CTRL_SRC_STM_SEL_FIELD & ~CMDQ_CTRL_DST_STM_SEL_FIELD);
361         value |= (CMDQ_CTRL_SRC_STM_SEL_FIELD | CMDQ_CTRL_DST_STM_SEL_FIELD |
362                 CMDQ_CTRL_ICMDQEN_FIELD | CMDQ_CTRL_ERROR_FLUSH_ENB);
363         aes_writel(eng, value, CMDQUE_CONTROL);
364
365         value = 0;
366         if (mode & FLAGS_CBC) {
367                 value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
368                         ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
369                         ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
370                         (((mode & FLAGS_ENCRYPT) ? 2 : 3)
371                                 << SECURE_XOR_POS_SHIFT) |
372                         (0 << SECURE_INPUT_SEL_SHIFT) |
373                         (((mode & FLAGS_ENCRYPT) ? 2 : 3)
374                                 << SECURE_VCTRAM_SEL_SHIFT) |
375                         ((mode & FLAGS_ENCRYPT) ? 1 : 0)
376                                 << SECURE_CORE_SEL_SHIFT |
377                         (0 << SECURE_RNG_ENB_SHIFT) |
378                         (0 << SECURE_HASH_ENB_SHIFT));
379         } else if (mode & FLAGS_OFB) {
380                 value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
381                         ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
382                         ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
383                         ((u32)0 << SECURE_IV_SELECT_SHIFT) |
384                         (SECURE_XOR_POS_FIELD) |
385                         (2 << SECURE_INPUT_SEL_SHIFT) |
386                         (0 << SECURE_VCTRAM_SEL_SHIFT) |
387                         (SECURE_CORE_SEL_FIELD) |
388                         (0 << SECURE_RNG_ENB_SHIFT) |
389                         (0 << SECURE_HASH_ENB_SHIFT));
390         } else if (mode & FLAGS_RNG){
391                 value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
392                         ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
393                         ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
394                         (0 << SECURE_XOR_POS_SHIFT) |
395                         (0 << SECURE_INPUT_SEL_SHIFT) |
396                         ((mode & FLAGS_ENCRYPT) ? 1 : 0)
397                                 << SECURE_CORE_SEL_SHIFT |
398                         (1 << SECURE_RNG_ENB_SHIFT) |
399                         (0 << SECURE_HASH_ENB_SHIFT));
400         } else {
401                 value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
402                         ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
403                         ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
404                         (0 << SECURE_XOR_POS_SHIFT) |
405                         (0 << SECURE_INPUT_SEL_SHIFT) |
406                         (((mode & FLAGS_ENCRYPT) ? 1 : 0)
407                                 << SECURE_CORE_SEL_SHIFT) |
408                         (0 << SECURE_RNG_ENB_SHIFT) |
409                                 (0 << SECURE_HASH_ENB_SHIFT));
410         }
411         aes_writel(eng, value, SECURE_INPUT_SELECT);
412
413         aes_writel(eng, out_addr, SECURE_DEST_ADDR);
414         INIT_COMPLETION(eng->op_complete);
415
416         for (i = 0; i < qlen - 1; i++) {
417                 do {
418                         value = aes_readl(eng, INTR_STATUS);
419                         eng_busy = value & BIT(0);
420                         icq_empty = value & BIT(3);
421                 } while (eng_busy || (!icq_empty));
422                 aes_writel(eng, cmdq[i], ICMDQUE_WR);
423         }
424
425         ret = wait_for_completion_timeout(&eng->op_complete,
426                 msecs_to_jiffies(150));
427         if (ret == 0) {
428                 dev_err(aes_dev->dev, "engine%d timed out (0x%x)\n",
429                         eng->res_id, aes_readl(eng, INTR_STATUS));
430                 disable_irq(eng->irq);
431                 return -ETIMEDOUT;
432         }
433
434         disable_irq(eng->irq);
435         aes_writel(eng, cmdq[qlen - 1], ICMDQUE_WR);
436
437         if ((eng->status != 0) && (retries-- > 0)) {
438                 qlen = 0;
439                 goto start;
440         }
441
442         return 0;
443 }
444
445 static void aes_release_key_slot(struct tegra_aes_ctx *ctx)
446 {
447         spin_lock(&list_lock);
448         ctx->slot->available = true;
449         ctx->slot = NULL;
450         spin_unlock(&list_lock);
451 }
452
453 static struct tegra_aes_slot *aes_find_key_slot(struct tegra_aes_dev *dd)
454 {
455         struct tegra_aes_slot *slot = NULL;
456         bool found = 0;
457
458         spin_lock(&list_lock);
459         list_for_each_entry(slot, &slot_list, node) {
460                 dev_dbg(dd->dev, "empty:%d, num:%d\n", slot->available,
461                         slot->slot_num);
462                 if (slot->available) {
463                         slot->available = false;
464                         found = 1;
465                         break;
466                 }
467         }
468
469         spin_unlock(&list_lock);
470         return found ? slot : NULL;
471 }
472
473 static int aes_set_key(struct tegra_aes_engine *eng, int slot_num)
474 {
475         struct tegra_aes_dev *dd = aes_dev;
476         u32 value, cmdq[2];
477         int i, eng_busy, icq_empty, dma_busy;
478
479         if (!eng) {
480                 dev_err(dd->dev, "%s: context invalid\n", __func__);
481                 return -EINVAL;
482         }
483
484         /* enable key schedule generation in hardware */
485         value = aes_readl(eng, SECURE_CONFIG_EXT);
486         value &= ~SECURE_KEY_SCH_DIS_FIELD;
487         aes_writel(eng, value, SECURE_CONFIG_EXT);
488
489         /* select the key slot */
490         value = aes_readl(eng, SECURE_CONFIG);
491         value &= ~SECURE_KEY_INDEX_FIELD;
492         value |= (slot_num << SECURE_KEY_INDEX_SHIFT);
493         aes_writel(eng, value, SECURE_CONFIG);
494
495         if (slot_num == SSK_SLOT_NUM)
496                 goto out;
497
498         if (eng->res_id == TEGRA_ARB_BSEV) {
499                 memset(dd->bsev.ivkey_base, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
500                 memcpy(dd->bsev.ivkey_base, eng->ctx->key, eng->ctx->keylen);
501
502                 /* copy the key table from sdram to vram */
503                 cmdq[0] = 0;
504                 cmdq[0] = UCQOPCODE_MEMDMAVD << ICQBITSHIFT_OPCODE |
505                                 (MEMDMA_DIR_DTOVRAM << MEMDMABITSHIFT_DIR) |
506                         (AES_HW_KEY_TABLE_LENGTH_BYTES/sizeof(u32))
507                         << MEMDMABITSHIFT_NUM_WORDS;
508                 cmdq[1] = (u32)eng->ivkey_phys_base;
509                 for (i = 0; i < ARRAY_SIZE(cmdq); i++)
510                         aes_writel(eng, cmdq[i], ICMDQUE_WR);
511                 do {
512                         value = aes_readl(eng, INTR_STATUS);
513                         eng_busy = value & BIT(0);
514                         icq_empty = value & BIT(3);
515                         dma_busy = value & BIT(23);
516                 } while (eng_busy & (!icq_empty) & dma_busy);
517
518                 /* settable command to get key into internal registers */
519                 value = 0;
520                 value = UCQOPCODE_SETTABLE << ICQBITSHIFT_OPCODE |
521                         UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL |
522                         UCQCMD_VRAM_SEL << ICQBITSHIFT_VRAMSEL |
523                         (UCQCMD_KEYTABLESEL | slot_num)
524                         << ICQBITSHIFT_KEYTABLEID;
525                 aes_writel(eng, value, ICMDQUE_WR);
526                 do {
527                         value = aes_readl(eng, INTR_STATUS);
528                         eng_busy = value & BIT(0);
529                         icq_empty = value & BIT(3);
530                 } while (eng_busy & (!icq_empty));
531         } else {
532                 memset(dd->bsea.iram_virt, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
533                 memcpy(dd->bsea.iram_virt, eng->ctx->key, eng->ctx->keylen);
534
535                 /* set iram access cfg bit 0 if address >128K */
536                 if (dd->bsea.iram_phys > 0x00020000)
537                         aes_writel(eng, BIT(0), IRAM_ACCESS_CFG);
538                 else
539                         aes_writel(eng, 0, IRAM_ACCESS_CFG);
540
541                 /* settable command to get key into internal registers */
542                 value = 0;
543                 value = UCQOPCODE_SETTABLE << ICQBITSHIFT_OPCODE |
544                         UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL |
545                         (UCQCMD_KEYTABLESEL | slot_num)
546                         << ICQBITSHIFT_KEYTABLEID |
547                         dd->bsea.iram_phys >> 2;
548                         aes_writel(eng, value, ICMDQUE_WR);
549                 do {
550                         value = aes_readl(eng, INTR_STATUS);
551                         eng_busy = value & BIT(0);
552                         icq_empty = value & BIT(3);
553                 } while (eng_busy & (!icq_empty));
554         }
555
556 out:
557         return 0;
558 }
559
560 static int tegra_aes_handle_req(struct tegra_aes_engine *eng)
561 {
562         struct tegra_aes_dev *dd = aes_dev;
563         struct tegra_aes_ctx *ctx;
564         struct crypto_async_request *async_req, *backlog;
565         struct tegra_aes_reqctx *rctx;
566         struct ablkcipher_request *req;
567         unsigned long irq_flags;
568         int dma_max = AES_HW_DMA_BUFFER_SIZE_BYTES;
569         int nblocks, total, ret = 0, count = 0;
570         dma_addr_t addr_in, addr_out;
571         struct scatterlist *in_sg, *out_sg;
572
573         spin_lock_irqsave(&dd->lock, irq_flags);
574         backlog = crypto_get_backlog(&dd->queue);
575         async_req = crypto_dequeue_request(&dd->queue);
576         if (!async_req)
577                 clear_bit(FLAGS_BUSY, &eng->busy);
578         spin_unlock_irqrestore(&dd->lock, irq_flags);
579
580         if (!async_req)
581                 return -ENODATA;
582
583         if (backlog)
584                 backlog->complete(backlog, -EINPROGRESS);
585
586         req = ablkcipher_request_cast(async_req);
587         dev_dbg(dd->dev, "%s: get new req (engine #%d)\n", __func__,
588                 eng->res_id);
589
590         if (!req->src || !req->dst)
591                 return -EINVAL;
592
593         /* take the hardware semaphore */
594         if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
595                 dev_err(dd->dev, "aes hardware (%d) not available\n",
596                 eng->res_id);
597                 return -EBUSY;
598         }
599
600         /* assign new request to device */
601         eng->req = req;
602         eng->total = req->nbytes;
603         eng->in_offset = 0;
604         eng->in_sg = req->src;
605         eng->out_offset = 0;
606         eng->out_sg = req->dst;
607
608         in_sg = eng->in_sg;
609         out_sg = eng->out_sg;
610         total = eng->total;
611
612         rctx = ablkcipher_request_ctx(req);
613         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
614         rctx->mode &= FLAGS_MODE_MASK;
615         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
616         eng->ctx = ctx;
617
618         if (eng->new_key) {
619                 if (ctx->use_ssk)
620                         aes_set_key(eng, SSK_SLOT_NUM);
621                 else
622                         aes_set_key(eng, ctx->slot->slot_num);
623
624                 eng->new_key = false;
625         }
626
627         if (((dd->flags & FLAGS_CBC) || (dd->flags & FLAGS_OFB)) && req->info) {
628                 /* set iv to the aes hw slot
629                  * Hw generates updated iv only after iv is set in slot.
630                  * So key and iv is passed asynchronously.
631                 */
632                 memcpy(eng->buf_in, (u8 *)req->info, AES_BLOCK_SIZE);
633
634                 ret = aes_start_crypt(eng, (u32)eng->dma_buf_in,
635                         (u32)eng->dma_buf_out, 1, FLAGS_CBC, false);
636                 if (ret < 0) {
637                         dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
638                         goto out;
639                 }
640         }
641
642         while (total) {
643                 dev_dbg(dd->dev, "remain: %d\n", total);
644                 ret = dma_map_sg(dd->dev, in_sg, 1, DMA_TO_DEVICE);
645                 if (!ret) {
646                         dev_err(dd->dev, "dma_map_sg() error\n");
647                         goto out;
648                 }
649
650                 ret = dma_map_sg(dd->dev, out_sg, 1, DMA_FROM_DEVICE);
651                 if (!ret) {
652                         dev_err(dd->dev, "dma_map_sg() error\n");
653                         dma_unmap_sg(dd->dev, eng->in_sg,
654                                 1, DMA_TO_DEVICE);
655                         goto out;
656                 }
657
658                 addr_in = sg_dma_address(in_sg);
659                 addr_out = sg_dma_address(out_sg);
660                 count = min((int)sg_dma_len(in_sg), (int)dma_max);
661                 WARN_ON(sg_dma_len(in_sg) != sg_dma_len(out_sg));
662                 nblocks = DIV_ROUND_UP(count, AES_BLOCK_SIZE);
663
664                 ret = aes_start_crypt(eng, addr_in, addr_out, nblocks,
665                         dd->flags, true);
666
667                 dma_unmap_sg(dd->dev, out_sg, 1, DMA_FROM_DEVICE);
668                 dma_unmap_sg(dd->dev, in_sg, 1, DMA_TO_DEVICE);
669                 if (ret < 0) {
670                         dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
671                         goto out;
672                 }
673
674                 dev_dbg(dd->dev, "out: copied %d\n", count);
675                 total -= count;
676                 in_sg = sg_next(in_sg);
677                 out_sg = sg_next(out_sg);
678                 WARN_ON(((total != 0) && (!in_sg || !out_sg)));
679         }
680
681 out:
682         /* release the hardware semaphore */
683         tegra_arb_mutex_unlock(eng->res_id);
684         eng->total = total;
685
686         if (eng->req->base.complete)
687                 eng->req->base.complete(&eng->req->base, ret);
688
689         dev_dbg(dd->dev, "%s: exit\n", __func__);
690         return ret;
691 }
692
693 static int tegra_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
694         unsigned int keylen)
695 {
696         struct tegra_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
697         struct tegra_aes_dev *dd = aes_dev;
698         struct tegra_aes_slot *key_slot;
699
700         if (!ctx || !dd) {
701                 pr_err("ctx=0x%x, dd=0x%x\n",
702                         (unsigned int)ctx, (unsigned int)dd);
703                 return -EINVAL;
704         }
705
706         if ((keylen != AES_KEYSIZE_128) && (keylen != AES_KEYSIZE_192) &&
707                 (keylen != AES_KEYSIZE_256)) {
708                 dev_err(dd->dev, "unsupported key size\n");
709                 return -EINVAL;
710         }
711
712         /* take the hardware semaphore */
713         if (tegra_arb_mutex_lock_timeout(dd->bsev.res_id, ARB_SEMA_TIMEOUT) < 0) {
714                 dev_err(dd->dev, "aes hardware (%d) not available\n", dd->bsev.res_id);
715                 return -EBUSY;
716         }
717
718         if (tegra_arb_mutex_lock_timeout(dd->bsea.res_id, ARB_SEMA_TIMEOUT) < 0) {
719                 dev_err(dd->dev, "aes hardware (%d) not available\n", dd->bsea.res_id);
720                 tegra_arb_mutex_unlock(dd->bsev.res_id);
721                 return -EBUSY;
722         }
723
724         dev_dbg(dd->dev, "keylen: %d\n", keylen);
725
726         ctx->dd = dd;
727
728         if (key) {
729                 if (!ctx->slot) {
730                         key_slot = aes_find_key_slot(dd);
731                         if (!key_slot) {
732                                 dev_err(dd->dev, "no empty slot\n");
733                                 goto out;
734                         }
735                         ctx->slot = key_slot;
736                 }
737
738                 /* copy the key to the proper slot */
739                 memset(ctx->key, 0, AES_MAX_KEY_SIZE);
740                 memcpy(ctx->key, key, keylen);
741                 ctx->keylen = keylen;
742                 ctx->use_ssk = false;
743         } else {
744                 ctx->use_ssk = true;
745                 ctx->keylen = AES_KEYSIZE_128;
746         }
747
748         dd->bsev.new_key = true;
749         dd->bsea.new_key = true;
750
751 out:
752         tegra_arb_mutex_unlock(dd->bsev.res_id);
753         tegra_arb_mutex_unlock(dd->bsea.res_id);
754         dev_dbg(dd->dev, "done\n");
755         return 0;
756 }
757
758 static void bsev_workqueue_handler(struct work_struct *work)
759 {
760         struct tegra_aes_dev *dd = aes_dev;
761         struct tegra_aes_engine *engine = &dd->bsev;
762         int ret;
763
764         aes_hw_init(engine);
765
766         /* empty the crypto queue and then return */
767         do {
768                 ret = tegra_aes_handle_req(engine);
769         } while (!ret);
770
771         aes_hw_deinit(engine);
772 }
773
774 static void bsea_workqueue_handler(struct work_struct *work)
775 {
776         struct tegra_aes_dev *dd = aes_dev;
777         struct tegra_aes_engine *engine = &dd->bsea;
778         int ret;
779
780         aes_hw_init(engine);
781
782         /* empty the crypto queue and then return */
783         do {
784                 ret = tegra_aes_handle_req(engine);
785         } while (!ret);
786
787         aes_hw_deinit(engine);
788 }
789
790 #define INT_ERROR_MASK  0xFFF000
791 static irqreturn_t aes_bsev_irq(int irq, void *dev_id)
792 {
793         struct tegra_aes_dev *dd = (struct tegra_aes_dev *)dev_id;
794         u32 value = aes_readl(&dd->bsev, INTR_STATUS);
795
796         dev_dbg(dd->dev, "bsev irq_stat: 0x%x", value);
797         dd->bsev.status = 0;
798         if (value & INT_ERROR_MASK) {
799                 aes_writel(&dd->bsev, INT_ERROR_MASK, INTR_STATUS);
800                 dd->bsev.status = value & INT_ERROR_MASK;
801         }
802
803         value = aes_readl(&dd->bsev, INTR_STATUS);
804         if (!(value & ENGINE_BUSY_FIELD))
805                 complete(&dd->bsev.op_complete);
806
807         return IRQ_HANDLED;
808 }
809
810 static irqreturn_t aes_bsea_irq(int irq, void *dev_id)
811 {
812         struct tegra_aes_dev *dd = (struct tegra_aes_dev *)dev_id;
813         u32 value = aes_readl(&dd->bsea, INTR_STATUS);
814
815         dev_dbg(dd->dev, "bsea irq_stat: 0x%x", value);
816         dd->bsea.status = 0;
817         if (value & INT_ERROR_MASK) {
818                 aes_writel(&dd->bsea, INT_ERROR_MASK, INTR_STATUS);
819                 dd->bsea.status = value & INT_ERROR_MASK;
820         }
821
822         value = aes_readl(&dd->bsea, INTR_STATUS);
823         if (!(value & ENGINE_BUSY_FIELD))
824                 complete(&dd->bsea.op_complete);
825
826         return IRQ_HANDLED;
827 }
828
829 static int tegra_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
830 {
831         struct tegra_aes_reqctx *rctx = ablkcipher_request_ctx(req);
832         struct tegra_aes_dev *dd = aes_dev;
833         unsigned long flags;
834         int err = 0;
835         int bsev_busy;
836         int bsea_busy;
837
838         dev_dbg(dd->dev, "nbytes: %d, enc: %d, cbc: %d, ofb: %d\n", req->nbytes,
839                 !!(mode & FLAGS_ENCRYPT),
840                 !!(mode & FLAGS_CBC),
841                 !!(mode & FLAGS_OFB));
842
843         rctx->mode = mode;
844
845         spin_lock_irqsave(&dd->lock, flags);
846         err = ablkcipher_enqueue_request(&dd->queue, req);
847         bsev_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsev.busy);
848         bsea_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsea.busy);
849         spin_unlock_irqrestore(&dd->lock, flags);
850
851         if (!bsev_busy)
852                 queue_work(bsev_wq, &bsev_work);
853         if (!bsea_busy)
854                 queue_work(bsea_wq, &bsea_work);
855
856         return err;
857 }
858
859 static int tegra_aes_ecb_encrypt(struct ablkcipher_request *req)
860 {
861         return tegra_aes_crypt(req, FLAGS_ENCRYPT);
862 }
863
864 static int tegra_aes_ecb_decrypt(struct ablkcipher_request *req)
865 {
866         return tegra_aes_crypt(req, 0);
867 }
868
869 static int tegra_aes_cbc_encrypt(struct ablkcipher_request *req)
870 {
871         return tegra_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
872 }
873
874 static int tegra_aes_cbc_decrypt(struct ablkcipher_request *req)
875 {
876         return tegra_aes_crypt(req, FLAGS_CBC);
877 }
878 static int tegra_aes_ofb_encrypt(struct ablkcipher_request *req)
879 {
880         return tegra_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_OFB);
881 }
882
883 static int tegra_aes_ofb_decrypt(struct ablkcipher_request *req)
884 {
885         return tegra_aes_crypt(req, FLAGS_OFB);
886 }
887
888 static int tegra_aes_get_random(struct crypto_rng *tfm, u8 *rdata,
889         unsigned int dlen)
890 {
891         struct tegra_aes_dev *dd = aes_dev;
892         struct tegra_aes_engine *eng = rng_ctx.eng;
893         unsigned long flags;
894         int ret, i;
895         u8 *dest = rdata, *dt = rng_ctx.dt;
896
897         /* take the hardware semaphore */
898         if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
899                 dev_err(dd->dev, "aes hardware (%d) not available\n",
900                 eng->res_id);
901                 return -EBUSY;
902         }
903
904         ret = aes_hw_init(eng);
905         if (ret < 0) {
906                 dev_err(dd->dev, "%s: hw init fail(%d)\n", __func__, ret);
907                 dlen = ret;
908                 goto fail;
909         }
910
911         memset(eng->buf_in, 0, AES_BLOCK_SIZE);
912         memcpy(eng->buf_in, dt, DEFAULT_RNG_BLK_SZ);
913
914         ret = aes_start_crypt(eng, (u32)eng->dma_buf_in, (u32)eng->dma_buf_out,
915                 1, FLAGS_ENCRYPT | FLAGS_RNG, true);
916         if (ret < 0) {
917                 dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
918                 dlen = ret;
919                 goto out;
920         }
921         memcpy(dest, eng->buf_out, dlen);
922
923         /* update the DT */
924         for (i = DEFAULT_RNG_BLK_SZ - 1; i >= 0; i--) {
925                 dt[i] += 1;
926                 if (dt[i] != 0)
927                         break;
928         }
929
930 out:
931         aes_hw_deinit(eng);
932
933         spin_lock_irqsave(&dd->lock, flags);
934         clear_bit(FLAGS_BUSY, &eng->busy);
935         spin_unlock_irqrestore(&dd->lock, flags);
936
937 fail:
938         /* release the hardware semaphore */
939         tegra_arb_mutex_unlock(eng->res_id);
940         dev_dbg(dd->dev, "%s: done\n", __func__);
941         return dlen;
942 }
943
944 static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
945         unsigned int slen)
946 {
947         struct tegra_aes_dev *dd = aes_dev;
948         struct tegra_aes_ctx *ctx = &rng_ctx;
949         struct tegra_aes_engine *eng = NULL;
950         struct tegra_aes_slot *key_slot;
951         int bsea_busy = false;
952         unsigned long flags;
953         struct timespec ts;
954         u64 nsec, tmp[2];
955         int ret = 0;
956         u8 *dt;
957
958         if (!dd)
959                 return -EINVAL;
960
961         if (slen < (DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128)) {
962                 return -ENOMEM;
963         }
964
965         spin_lock_irqsave(&dd->lock, flags);
966         bsea_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsea.busy);
967         spin_unlock_irqrestore(&dd->lock, flags);
968
969         if (!bsea_busy)
970                 eng = &dd->bsea;
971         else
972                 return -EBUSY;
973
974         ctx->eng = eng;
975         dd->flags = FLAGS_ENCRYPT | FLAGS_RNG;
976
977         if (!ctx->slot) {
978                 key_slot = aes_find_key_slot(dd);
979                 if (!key_slot) {
980                         dev_err(dd->dev, "no empty slot\n");
981                         return -ENOMEM;
982                 }
983                 ctx->slot = key_slot;
984         }
985
986         /* take the hardware semaphore */
987         if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
988                 dev_err(dd->dev, "aes hardware (%d) not available\n",
989                 eng->res_id);
990                 return -EBUSY;
991         }
992
993         ret = aes_hw_init(eng);
994         if (ret < 0) {
995                 dev_err(dd->dev, "%s: hw init fail(%d)\n", __func__, ret);
996                 goto fail;
997         }
998
999         memcpy(ctx->key, seed + DEFAULT_RNG_BLK_SZ, AES_KEYSIZE_128);
1000
1001         eng->ctx = ctx;
1002         eng->ctx->keylen = AES_KEYSIZE_128;
1003         aes_set_key(eng, ctx->slot->slot_num);
1004
1005         /* set seed to the aes hw slot */
1006         memset(eng->buf_in, 0, AES_BLOCK_SIZE);
1007         memcpy(eng->buf_in, seed, DEFAULT_RNG_BLK_SZ);
1008         ret = aes_start_crypt(eng, (u32)eng->dma_buf_in,
1009           (u32)eng->dma_buf_out, 1, FLAGS_CBC, false);
1010         if (ret < 0) {
1011                 dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
1012                 goto out;
1013         }
1014
1015         if (slen >= (2 * DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128)) {
1016                 dt = seed + DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128;
1017         } else {
1018                 getnstimeofday(&ts);
1019                 nsec = timespec_to_ns(&ts);
1020                 do_div(nsec, 1000);
1021                 nsec ^= dd->ctr << 56;
1022                 dd->ctr++;
1023                 tmp[0] = nsec;
1024                 tmp[1] = tegra_chip_uid();
1025                 dt = (u8 *)tmp;
1026         }
1027         memcpy(ctx->dt, dt, DEFAULT_RNG_BLK_SZ);
1028
1029 out:
1030         aes_hw_deinit(eng);
1031
1032 fail:
1033         /* release the hardware semaphore */
1034         tegra_arb_mutex_unlock(eng->res_id);
1035
1036         dev_dbg(dd->dev, "%s: done\n", __func__);
1037         return ret;
1038 }
1039
1040 static int tegra_aes_cra_init(struct crypto_tfm *tfm)
1041 {
1042         tfm->crt_ablkcipher.reqsize = sizeof(struct tegra_aes_reqctx);
1043         return 0;
1044 }
1045
1046 void tegra_aes_cra_exit(struct crypto_tfm *tfm)
1047 {
1048         struct tegra_aes_ctx *ctx = crypto_ablkcipher_ctx((struct crypto_ablkcipher *)tfm);
1049
1050         if (ctx && ctx->slot)
1051                 aes_release_key_slot(ctx);
1052 }
1053
1054 static struct crypto_alg algs[] = {
1055         {
1056                 .cra_name = "disabled_ecb(aes)",
1057                 .cra_driver_name = "ecb-aes-tegra",
1058                 .cra_priority = 100,
1059                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1060                 .cra_blocksize = AES_BLOCK_SIZE,
1061                 .cra_ctxsize = sizeof(struct tegra_aes_ctx),
1062                 .cra_alignmask = 3,
1063                 .cra_type = &crypto_ablkcipher_type,
1064                 .cra_module = THIS_MODULE,
1065                 .cra_init = tegra_aes_cra_init,
1066                 .cra_exit = tegra_aes_cra_exit,
1067                 .cra_u.ablkcipher = {
1068                         .min_keysize = AES_MIN_KEY_SIZE,
1069                         .max_keysize = AES_MAX_KEY_SIZE,
1070                         .setkey = tegra_aes_setkey,
1071                         .encrypt = tegra_aes_ecb_encrypt,
1072                         .decrypt = tegra_aes_ecb_decrypt,
1073                 },
1074         }, {
1075                 .cra_name = "disabled_cbc(aes)",
1076                 .cra_driver_name = "cbc-aes-tegra",
1077                 .cra_priority = 100,
1078                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1079                 .cra_blocksize = AES_BLOCK_SIZE,
1080                 .cra_ctxsize  = sizeof(struct tegra_aes_ctx),
1081                 .cra_alignmask = 3,
1082                 .cra_type = &crypto_ablkcipher_type,
1083                 .cra_module = THIS_MODULE,
1084                 .cra_init = tegra_aes_cra_init,
1085                 .cra_exit = tegra_aes_cra_exit,
1086                 .cra_u.ablkcipher = {
1087                         .min_keysize = AES_MIN_KEY_SIZE,
1088                         .max_keysize = AES_MAX_KEY_SIZE,
1089                         .ivsize = AES_MIN_KEY_SIZE,
1090                         .setkey = tegra_aes_setkey,
1091                         .encrypt = tegra_aes_cbc_encrypt,
1092                         .decrypt = tegra_aes_cbc_decrypt,
1093                 }
1094         }, {
1095                 .cra_name = "disabled_ofb(aes)",
1096                 .cra_driver_name = "ofb-aes-tegra",
1097                 .cra_priority = 100,
1098                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1099                 .cra_blocksize = AES_BLOCK_SIZE,
1100                 .cra_ctxsize  = sizeof(struct tegra_aes_ctx),
1101                 .cra_alignmask = 3,
1102                 .cra_type = &crypto_ablkcipher_type,
1103                 .cra_module = THIS_MODULE,
1104                 .cra_init = tegra_aes_cra_init,
1105                 .cra_exit = tegra_aes_cra_exit,
1106                 .cra_u.ablkcipher = {
1107                         .min_keysize = AES_MIN_KEY_SIZE,
1108                         .max_keysize = AES_MAX_KEY_SIZE,
1109                         .ivsize = AES_MIN_KEY_SIZE,
1110                         .setkey = tegra_aes_setkey,
1111                         .encrypt = tegra_aes_ofb_encrypt,
1112                         .decrypt = tegra_aes_ofb_decrypt,
1113                 }
1114         }, {
1115                 .cra_name = "disabled_ansi_cprng",
1116                 .cra_driver_name = "rng-aes-tegra",
1117                 .cra_priority = 100,
1118                 .cra_flags = CRYPTO_ALG_TYPE_RNG,
1119                 .cra_ctxsize = sizeof(struct tegra_aes_ctx),
1120                 .cra_type = &crypto_rng_type,
1121                 .cra_module = THIS_MODULE,
1122                 .cra_init = tegra_aes_cra_init,
1123                 .cra_exit = tegra_aes_cra_exit,
1124                 .cra_u.rng = {
1125                         .rng_make_random = tegra_aes_get_random,
1126                         .rng_reset = tegra_aes_rng_reset,
1127                         .seedsize = AES_KEYSIZE_128 + (2 * DEFAULT_RNG_BLK_SZ),
1128                 }
1129         }
1130 };
1131
1132 static int tegra_aes_probe(struct platform_device *pdev)
1133 {
1134         struct device *dev = &pdev->dev;
1135         struct tegra_aes_dev *dd;
1136         struct resource *res[2];
1137         int err = -ENOMEM, i = 0, j;
1138
1139         if (aes_dev)
1140                 return -EEXIST;
1141
1142         dd = kzalloc(sizeof(struct tegra_aes_dev), GFP_KERNEL);
1143         if (dd == NULL) {
1144                 dev_err(dev, "unable to alloc data struct.\n");
1145                 return -ENOMEM;;
1146         }
1147         dd->dev = dev;
1148         platform_set_drvdata(pdev, dd);
1149
1150         dd->slots = kzalloc(sizeof(struct tegra_aes_slot) * AES_NR_KEYSLOTS,
1151                 GFP_KERNEL);
1152         if (dd->slots == NULL) {
1153                 dev_err(dev, "unable to alloc slot struct.\n");
1154                 goto out;
1155         }
1156
1157         spin_lock_init(&dd->lock);
1158         crypto_init_queue(&dd->queue, TEGRA_AES_QUEUE_LENGTH);
1159
1160         /* Get the module base address */
1161         res[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1162         res[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1163         if (!res[0] || !res[1]) {
1164                 dev_err(dev, "invalid resource type: base\n");
1165                 err = -ENODEV;
1166                 goto out;
1167         }
1168         dd->bsev.phys_base = res[0]->start;
1169         dd->bsev.io_base = ioremap(dd->bsev.phys_base, resource_size(res[0]));
1170         dd->bsea.phys_base = res[1]->start;
1171         dd->bsea.io_base = ioremap(dd->bsea.phys_base, resource_size(res[1]));
1172
1173         if (!dd->bsev.io_base || !dd->bsea.io_base) {
1174                 dev_err(dev, "can't ioremap phys_base\n");
1175                 err = -ENOMEM;
1176                 goto out;
1177         }
1178
1179         err = alloc_iram(dd);
1180         if (err < 0) {
1181                 dev_err(dev, "Failed to allocate IRAM for BSEA\n");
1182                 goto out;
1183         }
1184
1185         dd->bsev.res_id = TEGRA_ARB_BSEV;
1186         dd->bsea.res_id = TEGRA_ARB_BSEA;
1187
1188         dd->bsev.pclk = clk_get(dev, "bsev");
1189         if (IS_ERR(dd->bsev.pclk)) {
1190                 dev_err(dev, "v: pclock intialization failed.\n");
1191                 err = -ENODEV;
1192                 goto out;
1193         }
1194
1195         dd->bsev.iclk = clk_get(dev, "vde");
1196         if (IS_ERR(dd->bsev.iclk)) {
1197                 dev_err(dev, "v: iclock intialization failed.\n");
1198                 err = -ENODEV;
1199                 goto out;
1200         }
1201
1202         dd->bsea.pclk = clk_get(dev, "bsea");
1203         if (IS_ERR(dd->bsea.pclk)) {
1204                 dev_err(dev, "a: pclock intialization failed.\n");
1205                 err = -ENODEV;
1206                 goto out;
1207         }
1208
1209         dd->bsea.iclk = clk_get(dev, "sclk");
1210         if (IS_ERR(dd->bsea.iclk)) {
1211                 dev_err(dev, "a: iclock intialization failed.\n");
1212                 err = -ENODEV;
1213                 goto out;
1214         }
1215
1216         err = clk_set_rate(dd->bsev.iclk, ULONG_MAX);
1217         if (err) {
1218                 dev_err(dd->dev, "bsev iclk set_rate fail(%d)\n", err);
1219                 goto out;
1220         }
1221
1222         err = clk_set_rate(dd->bsea.iclk, ULONG_MAX);
1223         if (err) {
1224                 dev_err(dd->dev, "bsea iclk set_rate fail(%d)\n", err);
1225                 goto out;
1226         }
1227
1228         /*
1229          * the foll contiguous memory is allocated as follows -
1230          * - hardware key table
1231          * - key schedule
1232          */
1233         dd->bsea.ivkey_base = NULL;
1234         dd->bsev.ivkey_base = dma_alloc_coherent(dev, AES_MAX_KEY_SIZE,
1235                 &dd->bsev.ivkey_phys_base, GFP_KERNEL);
1236         if (!dd->bsev.ivkey_base) {
1237                 dev_err(dev, "can not allocate iv/key buffer for BSEV\n");
1238                 err = -ENOMEM;
1239                 goto out;
1240         }
1241         memset(dd->bsev.ivkey_base, 0, AES_MAX_KEY_SIZE);
1242
1243         dd->bsev.buf_in = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1244                 &dd->bsev.dma_buf_in, GFP_KERNEL);
1245         dd->bsea.buf_in = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1246                 &dd->bsea.dma_buf_in, GFP_KERNEL);
1247         if (!dd->bsev.buf_in || !dd->bsea.buf_in) {
1248                 dev_err(dev, "can not allocate dma-in buffer\n");
1249                 err = -ENOMEM;
1250                 goto out;
1251         }
1252
1253         dd->bsev.buf_out = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1254                 &dd->bsev.dma_buf_out, GFP_KERNEL);
1255         dd->bsea.buf_out = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1256                 &dd->bsea.dma_buf_out, GFP_KERNEL);
1257         if (!dd->bsev.buf_out || !dd->bsea.buf_out) {
1258                 dev_err(dev, "can not allocate dma-out buffer\n");
1259                 err = -ENOMEM;
1260                 goto out;
1261         }
1262
1263         init_completion(&dd->bsev.op_complete);
1264         init_completion(&dd->bsea.op_complete);
1265
1266         bsev_wq = alloc_workqueue("bsev_wq", WQ_HIGHPRI | WQ_UNBOUND, 1);
1267         bsea_wq = alloc_workqueue("bsea_wq", WQ_HIGHPRI | WQ_UNBOUND, 1);
1268         if (!bsev_wq || !bsea_wq) {
1269                 dev_err(dev, "alloc_workqueue failed\n");
1270                 goto out;
1271         }
1272
1273         /* get the irq */
1274         dd->bsev.irq = INT_VDE_BSE_V;
1275         err = request_irq(dd->bsev.irq, aes_bsev_irq, IRQF_TRIGGER_HIGH,
1276                 "tegra-aes", dd);
1277         if (err) {
1278                 dev_err(dev, "request_irq failed fir BSEV Engine\n");
1279                 goto out;
1280         }
1281         disable_irq(dd->bsev.irq);
1282
1283         dd->bsea.irq = INT_VDE_BSE_A;
1284         err = request_irq(dd->bsea.irq, aes_bsea_irq, IRQF_TRIGGER_HIGH,
1285                 "tegra-aes", dd);
1286         if (err) {
1287                 dev_err(dev, "request_irq failed for BSEA Engine\n");
1288                 goto out;
1289         }
1290         disable_irq(dd->bsea.irq);
1291
1292         spin_lock_init(&list_lock);
1293         spin_lock(&list_lock);
1294         for (i = 0; i < AES_NR_KEYSLOTS; i++) {
1295                 if (i == SSK_SLOT_NUM)
1296                         continue;
1297                 dd->slots[i].available = true;
1298                 dd->slots[i].slot_num = i;
1299                 INIT_LIST_HEAD(&dd->slots[i].node);
1300                 list_add_tail(&dd->slots[i].node, &slot_list);
1301         }
1302         spin_unlock(&list_lock);
1303
1304         aes_dev = dd;
1305
1306         for (i = 0; i < ARRAY_SIZE(algs); i++) {
1307                 INIT_LIST_HEAD(&algs[i].cra_list);
1308                 err = crypto_register_alg(&algs[i]);
1309                 if (err)
1310                         goto out;
1311         }
1312
1313         dev_info(dev, "registered");
1314         return 0;
1315
1316 out:
1317         for (j = 0; j < i; j++)
1318                 crypto_unregister_alg(&algs[j]);
1319
1320         free_iram(dd);
1321
1322         if (dd->bsev.ivkey_base) {
1323                 dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base,
1324                         dd->bsev.ivkey_phys_base);
1325         }
1326
1327         if (dd->bsev.buf_in && dd->bsea.buf_in) {
1328                 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1329                         dd->bsev.buf_in, dd->bsev.dma_buf_in);
1330                 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1331                         dd->bsea.buf_in, dd->bsea.dma_buf_in);
1332         }
1333
1334         if (dd->bsev.buf_out && dd->bsea.buf_out) {
1335                 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1336                         dd->bsev.buf_out, dd->bsev.dma_buf_out);
1337                 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1338                         dd->bsea.buf_out, dd->bsea.dma_buf_out);
1339         }
1340
1341         if (dd->bsev.io_base && dd->bsea.io_base) {
1342                 iounmap(dd->bsev.io_base);
1343                 iounmap(dd->bsea.io_base);
1344         }
1345
1346         if (dd->bsev.pclk)
1347                 clk_put(dd->bsev.pclk);
1348
1349         if (dd->bsev.iclk)
1350                 clk_put(dd->bsev.iclk);
1351
1352         if (dd->bsea.pclk)
1353                 clk_put(dd->bsea.pclk);
1354
1355         if (bsev_wq)
1356                 destroy_workqueue(bsev_wq);
1357
1358         if (bsea_wq)
1359                 destroy_workqueue(bsea_wq);
1360
1361         if (dd->bsev.irq)
1362                 free_irq(dd->bsev.irq, dd);
1363
1364         if (dd->bsea.irq)
1365                 free_irq(dd->bsea.irq, dd);
1366
1367         spin_lock(&list_lock);
1368         list_del(&slot_list);
1369         spin_unlock(&list_lock);
1370
1371         kfree(dd->slots);
1372         kfree(dd);
1373         aes_dev = NULL;
1374
1375         dev_err(dev, "%s: initialization failed.\n", __func__);
1376         return err;
1377 }
1378
1379 static int __devexit tegra_aes_remove(struct platform_device *pdev)
1380 {
1381         struct device *dev = &pdev->dev;
1382         struct tegra_aes_dev *dd = platform_get_drvdata(pdev);
1383         int i;
1384
1385         if (!dd)
1386                 return -ENODEV;
1387
1388         cancel_work_sync(&bsev_work);
1389         cancel_work_sync(&bsea_work);
1390         destroy_workqueue(bsev_wq);
1391         destroy_workqueue(bsea_wq);
1392         free_irq(dd->bsev.irq, dd);
1393         free_irq(dd->bsea.irq, dd);
1394         spin_lock(&list_lock);
1395         list_del(&slot_list);
1396         spin_unlock(&list_lock);
1397
1398         for (i = 0; i < ARRAY_SIZE(algs); i++)
1399                 crypto_unregister_alg(&algs[i]);
1400
1401         free_iram(dd);
1402         dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base,
1403                 dd->bsev.ivkey_phys_base);
1404         dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsev.buf_in,
1405                 dd->bsev.dma_buf_in);
1406         dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsea.buf_in,
1407                 dd->bsea.dma_buf_in);
1408         dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsev.buf_out,
1409                 dd->bsev.dma_buf_out);
1410         dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsea.buf_out,
1411                 dd->bsea.dma_buf_out);
1412
1413         iounmap(dd->bsev.io_base);
1414         iounmap(dd->bsea.io_base);
1415         clk_put(dd->bsev.iclk);
1416         clk_put(dd->bsev.pclk);
1417         clk_put(dd->bsea.pclk);
1418         kfree(dd->slots);
1419         kfree(dd);
1420         aes_dev = NULL;
1421
1422         return 0;
1423 }
1424
1425 static struct platform_driver tegra_aes_driver = {
1426         .probe  = tegra_aes_probe,
1427         .remove = __devexit_p(tegra_aes_remove),
1428         .driver = {
1429                 .name   = "tegra-aes",
1430                 .owner  = THIS_MODULE,
1431         },
1432 };
1433
1434 static int __init tegra_aes_mod_init(void)
1435 {
1436         INIT_LIST_HEAD(&slot_list);
1437         return  platform_driver_register(&tegra_aes_driver);
1438 }
1439
1440 static void __exit tegra_aes_mod_exit(void)
1441 {
1442         platform_driver_unregister(&tegra_aes_driver);
1443 }
1444
1445 module_init(tegra_aes_mod_init);
1446 module_exit(tegra_aes_mod_exit);
1447
1448 MODULE_DESCRIPTION("Tegra AES hw acceleration support.");
1449 MODULE_AUTHOR("NVIDIA Corporation");
1450 MODULE_LICENSE("GPLv2");