22a96ed343eb24db8d82c002615b81defe7282c1
[linux-2.6.git] / drivers / crypto / tegra-aes.c
1 /*
2  * drivers/crypto/tegra-aes.c
3  *
4  * aes driver for NVIDIA tegra aes hardware
5  *
6  * Copyright (c) 2010-2011, NVIDIA Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful, but WITHOUT
14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16  * more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, write to the Free Software Foundation, Inc.,
20  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/errno.h>
26 #include <linux/kernel.h>
27 #include <linux/clk.h>
28 #include <linux/platform_device.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/io.h>
32 #include <linux/mutex.h>
33 #include <linux/interrupt.h>
34 #include <linux/completion.h>
35 #include <linux/workqueue.h>
36 #include <linux/delay.h>
37
38 #include <mach/arb_sema.h>
39 #include <mach/clk.h>
40 #include "../video/tegra/nvmap/nvmap.h"
41
42 #include <crypto/scatterwalk.h>
43 #include <crypto/aes.h>
44 #include <crypto/internal/rng.h>
45
46 #include "tegra-aes.h"
47
48 #define FLAGS_MODE_MASK         0x00ff
49 #define FLAGS_ENCRYPT           BIT(0)
50 #define FLAGS_CBC               BIT(1)
51 #define FLAGS_GIV               BIT(2)
52 #define FLAGS_RNG               BIT(3)
53 #define FLAGS_OFB               BIT(4)
54 #define FLAGS_INIT              BIT(5)
55 #define FLAGS_BUSY              1
56
57 /*
58  * Defines AES engine Max process bytes size in one go, which takes 1 msec.
59  * AES engine spends about 176 cycles/16-bytes or 11 cycles/byte
60  * The duration CPU can use the BSE to 1 msec, then the number of available
61  * cycles of AVP/BSE is 216K. In this duration, AES can process 216/11 ~= 19KB
62  * Based on this AES_HW_DMA_BUFFER_SIZE_BYTES is configured to 16KB.
63  */
64 #define AES_HW_DMA_BUFFER_SIZE_BYTES    0x4000
65
66 /*
67  * The key table length is 64 bytes
68  * (This includes first upto 32 bytes key + 16 bytes original initial vector
69  * and 16 bytes updated initial vector)
70  */
71 #define AES_HW_KEY_TABLE_LENGTH_BYTES   64
72
73 #define AES_HW_IV_SIZE  16
74 #define AES_HW_KEYSCHEDULE_LEN  256
75 #define ARB_SEMA_TIMEOUT        500
76
77 /*
78  * The memory being used is divides as follows:
79  * 1. Key - 32 bytes
80  * 2. Original IV - 16 bytes
81  * 3. Updated IV - 16 bytes
82  * 4. Key schedule - 256 bytes
83  *
84  * 1+2+3 constitute the hw key table.
85  */
86 #define AES_IVKEY_SIZE (AES_HW_KEY_TABLE_LENGTH_BYTES + AES_HW_KEYSCHEDULE_LEN)
87
88 #define DEFAULT_RNG_BLK_SZ      16
89
90 /* As of now only 5 commands are USED for AES encryption/Decryption */
91 #define AES_HW_MAX_ICQ_LENGTH   4
92
93 #define ICQBITSHIFT_BLKCNT      0
94
95 /* memdma_vd command */
96 #define MEMDMA_DIR_DTOVRAM      0
97 #define MEMDMA_DIR_VTODRAM      1
98 #define MEMDMABITSHIFT_DIR      25
99 #define MEMDMABITSHIFT_NUM_WORDS        12
100
101 /* Define AES Interactive command Queue commands Bit positions */
102 enum {
103         ICQBITSHIFT_KEYTABLEADDR = 0,
104         ICQBITSHIFT_KEYTABLEID = 17,
105         ICQBITSHIFT_VRAMSEL = 23,
106         ICQBITSHIFT_TABLESEL = 24,
107         ICQBITSHIFT_OPCODE = 26,
108 };
109
110 /* Define Ucq opcodes required for AES operation */
111 enum {
112         UCQOPCODE_BLKSTARTENGINE = 0x0E,
113         UCQOPCODE_DMASETUP = 0x10,
114         UCQOPCODE_DMACOMPLETE = 0x11,
115         UCQOPCODE_SETTABLE = 0x15,
116         UCQOPCODE_MEMDMAVD = 0x22,
117 };
118
119 /* Define Aes command values */
120 enum {
121         UCQCMD_VRAM_SEL = 0x1,
122         UCQCMD_CRYPTO_TABLESEL = 0x3,
123         UCQCMD_KEYSCHEDTABLESEL = 0x4,
124         UCQCMD_KEYTABLESEL = 0x8,
125 };
126
127 #define UCQCMD_KEYTABLEADDRMASK 0x1FFFF
128
129 #define AES_NR_KEYSLOTS 8
130 #define SSK_SLOT_NUM    4
131
132 struct tegra_aes_slot {
133         struct list_head node;
134         int slot_num;
135         bool available;
136 };
137
138 struct tegra_aes_reqctx {
139         unsigned long mode;
140 };
141
142 #define TEGRA_AES_QUEUE_LENGTH  500
143
144 struct tegra_aes_engine {
145         struct tegra_aes_dev *dd;
146         struct tegra_aes_ctx *ctx;
147         struct clk *iclk;
148         struct clk *pclk;
149         struct ablkcipher_request *req;
150         struct scatterlist *in_sg;
151         struct completion op_complete;
152         struct scatterlist *out_sg;
153         void __iomem *io_base;
154         void __iomem *ivkey_base;
155         unsigned long phys_base;
156         unsigned long iram_phys;
157         void *iram_virt;
158         dma_addr_t ivkey_phys_base;
159         dma_addr_t dma_buf_in;
160         dma_addr_t dma_buf_out;
161         size_t total;
162         size_t in_offset;
163         size_t out_offset;
164         u32 engine_offset;
165         u32 *buf_in;
166         u32 *buf_out;
167         int res_id;
168         unsigned long busy;
169         u8 irq;
170         u32 status;
171 };
172
173 struct tegra_aes_dev {
174         struct device *dev;
175         struct tegra_aes_slot *slots;
176         struct tegra_aes_engine bsev;
177         struct tegra_aes_engine bsea;
178         struct nvmap_client *client;
179         struct nvmap_handle_ref *h_ref;
180         struct crypto_queue queue;
181         spinlock_t lock;
182         u64 ctr;
183         unsigned long flags;
184         u8 dt[DEFAULT_RNG_BLK_SZ];
185 };
186
187 static struct tegra_aes_dev *aes_dev;
188
189 struct tegra_aes_ctx {
190         struct tegra_aes_dev *dd;
191         struct tegra_aes_engine *eng;
192         struct tegra_aes_slot *slot;
193         int key[AES_MAX_KEY_SIZE];
194         int keylen;
195         bool use_ssk;
196         u8 dt[DEFAULT_RNG_BLK_SZ];
197 };
198
199 static struct tegra_aes_ctx rng_ctx;
200
201 /* keep registered devices data here */
202 static LIST_HEAD(slot_list);
203 static DEFINE_SPINLOCK(list_lock);
204
205 /* Engine specific work queues */
206 static void bsev_workqueue_handler(struct work_struct *work);
207 static void bsea_workqueue_handler(struct work_struct *work);
208
209 static DECLARE_WORK(bsev_work, bsev_workqueue_handler);
210 static DECLARE_WORK(bsea_work, bsea_workqueue_handler);
211
212 static struct workqueue_struct *bsev_wq;
213 static struct workqueue_struct *bsea_wq;
214
215 extern unsigned long long tegra_chip_uid(void);
216
217 static inline u32 aes_readl(struct tegra_aes_engine *engine, u32 offset)
218 {
219         return readl(engine->io_base + offset);
220 }
221
222 static inline void aes_writel(struct tegra_aes_engine *engine,
223         u32 val, u32 offset)
224 {
225         writel(val, engine->io_base + offset);
226 }
227
228 static int alloc_iram(struct tegra_aes_dev *dd)
229 {
230         size_t size;
231         int err;
232
233         dd->h_ref = NULL;
234
235         /* [key+iv+u-iv=64B] * 8 = 512Bytes */
236         size = AES_MAX_KEY_SIZE;
237         dd->client = nvmap_create_client(nvmap_dev, "aes_bsea");
238         if (IS_ERR(dd->client)) {
239                 dev_err(dd->dev, "nvmap_create_client failed\n");
240                 goto out;
241         }
242
243         dd->h_ref = nvmap_create_handle(dd->client, size);
244         if (IS_ERR(dd->h_ref)) {
245                 dev_err(dd->dev, "nvmap_create_handle failed\n");
246                 goto out;
247         }
248
249         /* Allocate memory in the iram */
250         err = nvmap_alloc_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref),
251                 NVMAP_HEAP_CARVEOUT_IRAM, size, 0);
252         if (err) {
253                 dev_err(dd->dev, "nvmap_alloc_handle_id failed\n");
254                 nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
255                 goto out;
256         }
257         dd->bsea.iram_phys = nvmap_handle_address(dd->client,
258                                         nvmap_ref_to_id(dd->h_ref));
259
260         dd->bsea.iram_virt = nvmap_mmap(dd->h_ref);     /* get virtual address */
261         if (!dd->bsea.iram_virt) {
262                 dev_err(dd->dev, "%s: no mem, BSEA IRAM alloc failure\n",
263                         __func__);
264                 goto out;
265         }
266
267         memset(dd->bsea.iram_virt, 0, size);
268         return 0;
269
270 out:
271         if (dd->bsea.iram_virt)
272                 nvmap_munmap(dd->h_ref, dd->bsea.iram_virt);
273
274         if (dd->client) {
275                 nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
276                 nvmap_client_put(dd->client);
277         }
278
279         return -ENOMEM;
280 }
281
282 static void free_iram(struct tegra_aes_dev *dd)
283 {
284         if (dd->bsea.iram_virt)
285                 nvmap_munmap(dd->h_ref, dd->bsea.iram_virt);
286
287         if (dd->client) {
288                 nvmap_free_handle_id(dd->client, nvmap_ref_to_id(dd->h_ref));
289                 nvmap_client_put(dd->client);
290         }
291 }
292
293 static int aes_hw_init(struct tegra_aes_engine *engine)
294 {
295         struct tegra_aes_dev *dd = aes_dev;
296         int ret = 0;
297
298         if (engine->pclk) {
299                 ret = clk_enable(engine->pclk);
300                 if (ret < 0) {
301                         dev_err(dd->dev, "%s: pclock enable fail(%d)\n",
302                         __func__, ret);
303                         return ret;
304                 }
305         }
306
307         if (engine->iclk) {
308                 ret = clk_enable(engine->iclk);
309                 if (ret < 0) {
310                         dev_err(dd->dev, "%s: iclock enable fail(%d)\n",
311                         __func__, ret);
312                         if (engine->pclk)
313                                 clk_disable(engine->pclk);
314                         return ret;
315                 }
316         }
317
318         return ret;
319 }
320
321 static void aes_hw_deinit(struct tegra_aes_engine *engine)
322 {
323         if (engine->pclk)
324                 clk_disable(engine->pclk);
325
326         if (engine->iclk)
327                 clk_disable(engine->iclk);
328 }
329
330 #define MIN_RETRIES     3
331 static int aes_start_crypt(struct tegra_aes_engine *eng, u32 in_addr,
332         u32 out_addr, int nblocks, int mode, bool upd_iv)
333 {
334         u32 cmdq[AES_HW_MAX_ICQ_LENGTH];
335         int qlen = 0, i, eng_busy, icq_empty, ret;
336         u32 value;
337         int retries = MIN_RETRIES;
338
339 start:
340         do {
341                 value = aes_readl(eng, INTR_STATUS);
342                 eng_busy = value & BIT(0);
343                 icq_empty = value & BIT(3);
344         } while (eng_busy || (!icq_empty));
345
346         aes_writel(eng, 0xFFFFFFFF, INTR_STATUS);
347
348         /* error, dma xfer complete */
349         aes_writel(eng, 0x33, INT_ENB);
350         enable_irq(eng->irq);
351
352         cmdq[qlen++] = UCQOPCODE_DMASETUP << ICQBITSHIFT_OPCODE;
353         cmdq[qlen++] = in_addr;
354         cmdq[qlen++] = UCQOPCODE_BLKSTARTENGINE << ICQBITSHIFT_OPCODE |
355                 (nblocks-1) << ICQBITSHIFT_BLKCNT;
356         cmdq[qlen++] = UCQOPCODE_DMACOMPLETE << ICQBITSHIFT_OPCODE;
357
358         value = aes_readl(eng, CMDQUE_CONTROL);
359         /* access SDRAM through AHB */
360         value &= (~CMDQ_CTRL_SRC_STM_SEL_FIELD & ~CMDQ_CTRL_DST_STM_SEL_FIELD);
361         value |= (CMDQ_CTRL_SRC_STM_SEL_FIELD | CMDQ_CTRL_DST_STM_SEL_FIELD |
362                 CMDQ_CTRL_ICMDQEN_FIELD | CMDQ_CTRL_ERROR_FLUSH_ENB);
363         aes_writel(eng, value, CMDQUE_CONTROL);
364
365         value = 0;
366         if (mode & FLAGS_CBC) {
367                 value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
368                         ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
369                         ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
370                         (((mode & FLAGS_ENCRYPT) ? 2 : 3)
371                                 << SECURE_XOR_POS_SHIFT) |
372                         (0 << SECURE_INPUT_SEL_SHIFT) |
373                         (((mode & FLAGS_ENCRYPT) ? 2 : 3)
374                                 << SECURE_VCTRAM_SEL_SHIFT) |
375                         ((mode & FLAGS_ENCRYPT) ? 1 : 0)
376                                 << SECURE_CORE_SEL_SHIFT |
377                         (0 << SECURE_RNG_ENB_SHIFT) |
378                         (0 << SECURE_HASH_ENB_SHIFT));
379         } else if (mode & FLAGS_OFB) {
380                 value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
381                         ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
382                         ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
383                         ((u32)0 << SECURE_IV_SELECT_SHIFT) |
384                         (SECURE_XOR_POS_FIELD) |
385                         (2 << SECURE_INPUT_SEL_SHIFT) |
386                         (0 << SECURE_VCTRAM_SEL_SHIFT) |
387                         (SECURE_CORE_SEL_FIELD) |
388                         (0 << SECURE_RNG_ENB_SHIFT) |
389                         (0 << SECURE_HASH_ENB_SHIFT));
390         } else if (mode & FLAGS_RNG){
391                 value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
392                         ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
393                         ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
394                         (0 << SECURE_XOR_POS_SHIFT) |
395                         (0 << SECURE_INPUT_SEL_SHIFT) |
396                         ((mode & FLAGS_ENCRYPT) ? 1 : 0)
397                                 << SECURE_CORE_SEL_SHIFT |
398                         (1 << SECURE_RNG_ENB_SHIFT) |
399                         (0 << SECURE_HASH_ENB_SHIFT));
400         } else {
401                 value = ((0x1 << SECURE_INPUT_ALG_SEL_SHIFT) |
402                         ((eng->ctx->keylen * 8) << SECURE_INPUT_KEY_LEN_SHIFT) |
403                         ((u32)upd_iv << SECURE_IV_SELECT_SHIFT) |
404                         (0 << SECURE_XOR_POS_SHIFT) |
405                         (0 << SECURE_INPUT_SEL_SHIFT) |
406                         (((mode & FLAGS_ENCRYPT) ? 1 : 0)
407                                 << SECURE_CORE_SEL_SHIFT) |
408                         (0 << SECURE_RNG_ENB_SHIFT) |
409                                 (0 << SECURE_HASH_ENB_SHIFT));
410         }
411         aes_writel(eng, value, SECURE_INPUT_SELECT);
412
413         aes_writel(eng, out_addr, SECURE_DEST_ADDR);
414         INIT_COMPLETION(eng->op_complete);
415
416         for (i = 0; i < qlen - 1; i++) {
417                 do {
418                         value = aes_readl(eng, INTR_STATUS);
419                         eng_busy = value & BIT(0);
420                         icq_empty = value & BIT(3);
421                 } while (eng_busy || (!icq_empty));
422                 aes_writel(eng, cmdq[i], ICMDQUE_WR);
423         }
424
425         ret = wait_for_completion_timeout(&eng->op_complete,
426                 msecs_to_jiffies(150));
427         if (ret == 0) {
428                 dev_err(aes_dev->dev, "engine%d timed out (0x%x)\n",
429                         eng->res_id, aes_readl(eng, INTR_STATUS));
430                 disable_irq(eng->irq);
431                 return -ETIMEDOUT;
432         }
433
434         disable_irq(eng->irq);
435         aes_writel(eng, cmdq[qlen - 1], ICMDQUE_WR);
436
437         if ((eng->status != 0) && (retries-- > 0)) {
438                 qlen = 0;
439                 goto start;
440         }
441
442         return 0;
443 }
444
445 static void aes_release_key_slot(struct tegra_aes_ctx *ctx)
446 {
447         spin_lock(&list_lock);
448         ctx->slot->available = true;
449         ctx->slot = NULL;
450         spin_unlock(&list_lock);
451 }
452
453 static struct tegra_aes_slot *aes_find_key_slot(struct tegra_aes_dev *dd)
454 {
455         struct tegra_aes_slot *slot = NULL;
456         bool found = 0;
457
458         spin_lock(&list_lock);
459         list_for_each_entry(slot, &slot_list, node) {
460                 dev_dbg(dd->dev, "empty:%d, num:%d\n", slot->available,
461                         slot->slot_num);
462                 if (slot->available) {
463                         slot->available = false;
464                         found = 1;
465                         break;
466                 }
467         }
468
469         spin_unlock(&list_lock);
470         return found ? slot : NULL;
471 }
472
473 static int aes_set_key(struct tegra_aes_engine *eng, int slot_num)
474 {
475         struct tegra_aes_dev *dd = aes_dev;
476         u32 value, cmdq[2];
477         int i, eng_busy, icq_empty, dma_busy;
478
479         if (!eng) {
480                 dev_err(dd->dev, "%s: context invalid\n", __func__);
481                 return -EINVAL;
482         }
483
484         /* enable key schedule generation in hardware */
485         value = aes_readl(eng, SECURE_CONFIG_EXT);
486         value &= ~SECURE_KEY_SCH_DIS_FIELD;
487         aes_writel(eng, value, SECURE_CONFIG_EXT);
488
489         /* select the key slot */
490         value = aes_readl(eng, SECURE_CONFIG);
491         value &= ~SECURE_KEY_INDEX_FIELD;
492         value |= (slot_num << SECURE_KEY_INDEX_SHIFT);
493         aes_writel(eng, value, SECURE_CONFIG);
494
495         if (slot_num == SSK_SLOT_NUM)
496                 goto out;
497
498         if (eng->res_id == TEGRA_ARB_BSEV) {
499                 memset(dd->bsev.ivkey_base, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
500                 memcpy(dd->bsev.ivkey_base, eng->ctx->key, eng->ctx->keylen);
501
502                 /* copy the key table from sdram to vram */
503                 cmdq[0] = 0;
504                 cmdq[0] = UCQOPCODE_MEMDMAVD << ICQBITSHIFT_OPCODE |
505                                 (MEMDMA_DIR_DTOVRAM << MEMDMABITSHIFT_DIR) |
506                         (AES_HW_KEY_TABLE_LENGTH_BYTES/sizeof(u32))
507                         << MEMDMABITSHIFT_NUM_WORDS;
508                 cmdq[1] = (u32)eng->ivkey_phys_base;
509                 for (i = 0; i < ARRAY_SIZE(cmdq); i++)
510                         aes_writel(eng, cmdq[i], ICMDQUE_WR);
511                 do {
512                         value = aes_readl(eng, INTR_STATUS);
513                         eng_busy = value & BIT(0);
514                         icq_empty = value & BIT(3);
515                         dma_busy = value & BIT(23);
516                 } while (eng_busy & (!icq_empty) & dma_busy);
517
518                 /* settable command to get key into internal registers */
519                 value = 0;
520                 value = UCQOPCODE_SETTABLE << ICQBITSHIFT_OPCODE |
521                         UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL |
522                         UCQCMD_VRAM_SEL << ICQBITSHIFT_VRAMSEL |
523                         (UCQCMD_KEYTABLESEL | slot_num)
524                         << ICQBITSHIFT_KEYTABLEID;
525                 aes_writel(eng, value, ICMDQUE_WR);
526                 do {
527                         value = aes_readl(eng, INTR_STATUS);
528                         eng_busy = value & BIT(0);
529                         icq_empty = value & BIT(3);
530                 } while (eng_busy & (!icq_empty));
531         } else {
532                 memset(dd->bsea.iram_virt, 0, AES_HW_KEY_TABLE_LENGTH_BYTES);
533                 memcpy(dd->bsea.iram_virt, eng->ctx->key, eng->ctx->keylen);
534
535                 /* set iram access cfg bit 0 if address >128K */
536                 if (dd->bsea.iram_phys > 0x00020000)
537                         aes_writel(eng, BIT(0), IRAM_ACCESS_CFG);
538                 else
539                         aes_writel(eng, 0, IRAM_ACCESS_CFG);
540
541                 /* settable command to get key into internal registers */
542                 value = 0;
543                 value = UCQOPCODE_SETTABLE << ICQBITSHIFT_OPCODE |
544                         UCQCMD_CRYPTO_TABLESEL << ICQBITSHIFT_TABLESEL |
545                         (UCQCMD_KEYTABLESEL | slot_num)
546                         << ICQBITSHIFT_KEYTABLEID |
547                         dd->bsea.iram_phys >> 2;
548                         aes_writel(eng, value, ICMDQUE_WR);
549                 do {
550                         value = aes_readl(eng, INTR_STATUS);
551                         eng_busy = value & BIT(0);
552                         icq_empty = value & BIT(3);
553                 } while (eng_busy & (!icq_empty));
554         }
555
556 out:
557         return 0;
558 }
559
560 static int tegra_aes_handle_req(struct tegra_aes_engine *eng)
561 {
562         struct tegra_aes_dev *dd = aes_dev;
563         struct tegra_aes_ctx *ctx;
564         struct crypto_async_request *async_req, *backlog;
565         struct tegra_aes_reqctx *rctx;
566         struct ablkcipher_request *req;
567         unsigned long irq_flags;
568         int dma_max = AES_HW_DMA_BUFFER_SIZE_BYTES;
569         int nblocks, total, ret = 0, count = 0;
570         dma_addr_t addr_in, addr_out;
571         struct scatterlist *in_sg, *out_sg;
572
573         spin_lock_irqsave(&dd->lock, irq_flags);
574         backlog = crypto_get_backlog(&dd->queue);
575         async_req = crypto_dequeue_request(&dd->queue);
576         if (!async_req)
577                 clear_bit(FLAGS_BUSY, &eng->busy);
578         spin_unlock_irqrestore(&dd->lock, irq_flags);
579
580         if (!async_req)
581                 return -ENODATA;
582
583         if (backlog)
584                 backlog->complete(backlog, -EINPROGRESS);
585
586         req = ablkcipher_request_cast(async_req);
587         dev_dbg(dd->dev, "%s: get new req (engine #%d)\n", __func__,
588                 eng->res_id);
589
590         if (!req->src || !req->dst)
591                 return -EINVAL;
592
593         /* take the hardware semaphore */
594         if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
595                 dev_err(dd->dev, "aes hardware (%d) not available\n",
596                 eng->res_id);
597                 return -EBUSY;
598         }
599
600         /* assign new request to device */
601         eng->req = req;
602         eng->total = req->nbytes;
603         eng->in_offset = 0;
604         eng->in_sg = req->src;
605         eng->out_offset = 0;
606         eng->out_sg = req->dst;
607
608         in_sg = eng->in_sg;
609         out_sg = eng->out_sg;
610         total = eng->total;
611
612         rctx = ablkcipher_request_ctx(req);
613         ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
614         rctx->mode &= FLAGS_MODE_MASK;
615         dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
616         eng->ctx = ctx;
617
618         if (((dd->flags & FLAGS_CBC) || (dd->flags & FLAGS_OFB)) && req->info) {
619                 /* set iv to the aes hw slot
620                  * Hw generates updated iv only after iv is set in slot.
621                  * So key and iv is passed asynchronously.
622                 */
623                 memcpy(eng->buf_in, (u8 *)req->info, AES_BLOCK_SIZE);
624
625                 ret = aes_start_crypt(eng, (u32)eng->dma_buf_in,
626                         (u32)eng->dma_buf_out, 1, FLAGS_CBC, false);
627                 if (ret < 0) {
628                         dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
629                         goto out;
630                 }
631         }
632
633         while (total) {
634                 dev_dbg(dd->dev, "remain: %d\n", total);
635                 ret = dma_map_sg(dd->dev, in_sg, 1, DMA_TO_DEVICE);
636                 if (!ret) {
637                         dev_err(dd->dev, "dma_map_sg() error\n");
638                         goto out;
639                 }
640
641                 ret = dma_map_sg(dd->dev, out_sg, 1, DMA_FROM_DEVICE);
642                 if (!ret) {
643                         dev_err(dd->dev, "dma_map_sg() error\n");
644                         dma_unmap_sg(dd->dev, eng->in_sg,
645                                 1, DMA_TO_DEVICE);
646                         goto out;
647                 }
648
649                 addr_in = sg_dma_address(in_sg);
650                 addr_out = sg_dma_address(out_sg);
651                 count = min((int)sg_dma_len(in_sg), (int)dma_max);
652                 WARN_ON(sg_dma_len(in_sg) != sg_dma_len(out_sg));
653                 nblocks = DIV_ROUND_UP(count, AES_BLOCK_SIZE);
654
655                 ret = aes_start_crypt(eng, addr_in, addr_out, nblocks,
656                         dd->flags, true);
657
658                 dma_unmap_sg(dd->dev, out_sg, 1, DMA_FROM_DEVICE);
659                 dma_unmap_sg(dd->dev, in_sg, 1, DMA_TO_DEVICE);
660                 if (ret < 0) {
661                         dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
662                         goto out;
663                 }
664
665                 dev_dbg(dd->dev, "out: copied %d\n", count);
666                 total -= count;
667                 in_sg = sg_next(in_sg);
668                 out_sg = sg_next(out_sg);
669                 WARN_ON(((total != 0) && (!in_sg || !out_sg)));
670         }
671
672 out:
673         /* release the hardware semaphore */
674         tegra_arb_mutex_unlock(eng->res_id);
675         eng->total = total;
676
677         if (eng->req->base.complete)
678                 eng->req->base.complete(&eng->req->base, ret);
679
680         dev_dbg(dd->dev, "%s: exit\n", __func__);
681         return ret;
682 }
683
684 static int tegra_aes_key_save(struct tegra_aes_ctx *ctx)
685 {
686         struct tegra_aes_dev *dd = aes_dev;
687         int retry_count, eng_busy, ret, eng_no;
688         struct tegra_aes_engine *eng[2] = {&dd->bsev, &dd->bsea};
689         unsigned long flags;
690
691         /* check for engine free state */
692         for (eng_no = 0; eng_no < ARRAY_SIZE(eng); eng_no++) {
693                 for (retry_count = 0; retry_count <= 10; retry_count++) {
694                         spin_lock_irqsave(&dd->lock, flags);
695                         eng_busy = test_and_set_bit(FLAGS_BUSY,
696                                                         &eng[eng_no]->busy);
697                         spin_unlock_irqrestore(&dd->lock, flags);
698
699                         if (!eng_busy)
700                                 break;
701
702                         if (retry_count == 10) {
703                                 dev_err(dd->dev,
704                                         "%s: eng=%d busy, wait timeout\n",
705                                         __func__, eng[eng_no]->res_id);
706                                 ret = -EBUSY;
707                                 goto out;
708                         }
709                         mdelay(5);
710                 }
711         }
712
713         /* save key in the engine */
714         for (eng_no = 0;  eng_no < ARRAY_SIZE(eng); eng_no++) {
715                 ret = aes_hw_init(eng[eng_no]);
716                 if (ret < 0) {
717                         dev_err(dd->dev, "%s: eng=%d hw init fail(%d)\n",
718                         __func__, eng[eng_no]->res_id, ret);
719                         goto out;
720                 }
721                 eng[eng_no]->ctx = ctx;
722                 if (ctx->use_ssk)
723                         aes_set_key(eng[eng_no], SSK_SLOT_NUM);
724                 else
725                         aes_set_key(eng[eng_no], ctx->slot->slot_num);
726
727                 aes_hw_deinit(eng[eng_no]);
728         }
729 out:
730         spin_lock_irqsave(&dd->lock, flags);
731         while (--eng_no >= 0)
732                 clear_bit(FLAGS_BUSY, &eng[eng_no]->busy);
733         spin_unlock_irqrestore(&dd->lock, flags);
734
735         return ret;
736 }
737
738 static int tegra_aes_setkey(struct crypto_ablkcipher *tfm, const u8 *key,
739         unsigned int keylen)
740 {
741         struct tegra_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
742         struct tegra_aes_dev *dd = aes_dev;
743         struct tegra_aes_slot *key_slot;
744         int ret = 0;
745
746         if (!ctx || !dd) {
747                 pr_err("ctx=0x%x, dd=0x%x\n",
748                         (unsigned int)ctx, (unsigned int)dd);
749                 return -EINVAL;
750         }
751
752         if ((keylen != AES_KEYSIZE_128) && (keylen != AES_KEYSIZE_192) &&
753                 (keylen != AES_KEYSIZE_256)) {
754                 dev_err(dd->dev, "unsupported key size\n");
755                 return -EINVAL;
756         }
757
758         /* take the hardware semaphore */
759         if (tegra_arb_mutex_lock_timeout(dd->bsev.res_id, ARB_SEMA_TIMEOUT) < 0) {
760                 dev_err(dd->dev, "aes hardware (%d) not available\n", dd->bsev.res_id);
761                 return -EBUSY;
762         }
763
764         if (tegra_arb_mutex_lock_timeout(dd->bsea.res_id, ARB_SEMA_TIMEOUT) < 0) {
765                 dev_err(dd->dev, "aes hardware (%d) not available\n", dd->bsea.res_id);
766                 tegra_arb_mutex_unlock(dd->bsev.res_id);
767                 return -EBUSY;
768         }
769
770         dev_dbg(dd->dev, "keylen: %d\n", keylen);
771         ctx->dd = dd;
772
773         if (key) {
774                 if (!ctx->slot) {
775                         key_slot = aes_find_key_slot(dd);
776                         if (!key_slot) {
777                                 dev_err(dd->dev, "no empty slot\n");
778                                 ret = -EBUSY;
779                                 goto out;
780                         }
781                         ctx->slot = key_slot;
782                 }
783
784                 /* copy the key to the proper slot */
785                 memset(ctx->key, 0, AES_MAX_KEY_SIZE);
786                 memcpy(ctx->key, key, keylen);
787                 ctx->keylen = keylen;
788                 ctx->use_ssk = false;
789         } else {
790                 ctx->use_ssk = true;
791                 ctx->keylen = AES_KEYSIZE_128;
792         }
793
794         ret = tegra_aes_key_save(ctx);
795         if (ret != 0)
796                 dev_err(dd->dev, "%s failed\n", __func__);
797 out:
798         tegra_arb_mutex_unlock(dd->bsev.res_id);
799         tegra_arb_mutex_unlock(dd->bsea.res_id);
800         dev_dbg(dd->dev, "done\n");
801         return ret;
802 }
803
804 static void bsev_workqueue_handler(struct work_struct *work)
805 {
806         struct tegra_aes_dev *dd = aes_dev;
807         struct tegra_aes_engine *engine = &dd->bsev;
808         int ret;
809
810         aes_hw_init(engine);
811
812         /* empty the crypto queue and then return */
813         do {
814                 ret = tegra_aes_handle_req(engine);
815         } while (!ret);
816
817         aes_hw_deinit(engine);
818 }
819
820 static void bsea_workqueue_handler(struct work_struct *work)
821 {
822         struct tegra_aes_dev *dd = aes_dev;
823         struct tegra_aes_engine *engine = &dd->bsea;
824         int ret;
825
826         aes_hw_init(engine);
827
828         /* empty the crypto queue and then return */
829         do {
830                 ret = tegra_aes_handle_req(engine);
831         } while (!ret);
832
833         aes_hw_deinit(engine);
834 }
835
836 #define INT_ERROR_MASK  0xFFF000
837 static irqreturn_t aes_bsev_irq(int irq, void *dev_id)
838 {
839         struct tegra_aes_dev *dd = (struct tegra_aes_dev *)dev_id;
840         u32 value = aes_readl(&dd->bsev, INTR_STATUS);
841
842         dev_dbg(dd->dev, "bsev irq_stat: 0x%x", value);
843         dd->bsev.status = 0;
844         if (value & INT_ERROR_MASK) {
845                 aes_writel(&dd->bsev, INT_ERROR_MASK, INTR_STATUS);
846                 dd->bsev.status = value & INT_ERROR_MASK;
847         }
848
849         value = aes_readl(&dd->bsev, INTR_STATUS);
850         if (!(value & ENGINE_BUSY_FIELD))
851                 complete(&dd->bsev.op_complete);
852
853         return IRQ_HANDLED;
854 }
855
856 static irqreturn_t aes_bsea_irq(int irq, void *dev_id)
857 {
858         struct tegra_aes_dev *dd = (struct tegra_aes_dev *)dev_id;
859         u32 value = aes_readl(&dd->bsea, INTR_STATUS);
860
861         dev_dbg(dd->dev, "bsea irq_stat: 0x%x", value);
862         dd->bsea.status = 0;
863         if (value & INT_ERROR_MASK) {
864                 aes_writel(&dd->bsea, INT_ERROR_MASK, INTR_STATUS);
865                 dd->bsea.status = value & INT_ERROR_MASK;
866         }
867
868         value = aes_readl(&dd->bsea, INTR_STATUS);
869         if (!(value & ENGINE_BUSY_FIELD))
870                 complete(&dd->bsea.op_complete);
871
872         return IRQ_HANDLED;
873 }
874
875 static int tegra_aes_crypt(struct ablkcipher_request *req, unsigned long mode)
876 {
877         struct tegra_aes_reqctx *rctx = ablkcipher_request_ctx(req);
878         struct tegra_aes_dev *dd = aes_dev;
879         unsigned long flags;
880         int err = 0;
881         int bsev_busy;
882         int bsea_busy;
883
884         dev_dbg(dd->dev, "nbytes: %d, enc: %d, cbc: %d, ofb: %d\n", req->nbytes,
885                 !!(mode & FLAGS_ENCRYPT),
886                 !!(mode & FLAGS_CBC),
887                 !!(mode & FLAGS_OFB));
888
889         rctx->mode = mode;
890
891         spin_lock_irqsave(&dd->lock, flags);
892         err = ablkcipher_enqueue_request(&dd->queue, req);
893         bsev_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsev.busy);
894         bsea_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsea.busy);
895         spin_unlock_irqrestore(&dd->lock, flags);
896
897         if (!bsev_busy)
898                 queue_work(bsev_wq, &bsev_work);
899         if (!bsea_busy)
900                 queue_work(bsea_wq, &bsea_work);
901
902         return err;
903 }
904
905 static int tegra_aes_ecb_encrypt(struct ablkcipher_request *req)
906 {
907         return tegra_aes_crypt(req, FLAGS_ENCRYPT);
908 }
909
910 static int tegra_aes_ecb_decrypt(struct ablkcipher_request *req)
911 {
912         return tegra_aes_crypt(req, 0);
913 }
914
915 static int tegra_aes_cbc_encrypt(struct ablkcipher_request *req)
916 {
917         return tegra_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
918 }
919
920 static int tegra_aes_cbc_decrypt(struct ablkcipher_request *req)
921 {
922         return tegra_aes_crypt(req, FLAGS_CBC);
923 }
924 static int tegra_aes_ofb_encrypt(struct ablkcipher_request *req)
925 {
926         return tegra_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_OFB);
927 }
928
929 static int tegra_aes_ofb_decrypt(struct ablkcipher_request *req)
930 {
931         return tegra_aes_crypt(req, FLAGS_OFB);
932 }
933
934 static int tegra_aes_get_random(struct crypto_rng *tfm, u8 *rdata,
935         unsigned int dlen)
936 {
937         struct tegra_aes_dev *dd = aes_dev;
938         struct tegra_aes_engine *eng = rng_ctx.eng;
939         unsigned long flags;
940         int ret, i;
941         u8 *dest = rdata, *dt = rng_ctx.dt;
942
943         /* take the hardware semaphore */
944         if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
945                 dev_err(dd->dev, "aes hardware (%d) not available\n",
946                 eng->res_id);
947                 return -EBUSY;
948         }
949
950         ret = aes_hw_init(eng);
951         if (ret < 0) {
952                 dev_err(dd->dev, "%s: hw init fail(%d)\n", __func__, ret);
953                 dlen = ret;
954                 goto fail;
955         }
956
957         memset(eng->buf_in, 0, AES_BLOCK_SIZE);
958         memcpy(eng->buf_in, dt, DEFAULT_RNG_BLK_SZ);
959
960         ret = aes_start_crypt(eng, (u32)eng->dma_buf_in, (u32)eng->dma_buf_out,
961                 1, FLAGS_ENCRYPT | FLAGS_RNG, true);
962         if (ret < 0) {
963                 dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
964                 dlen = ret;
965                 goto out;
966         }
967         memcpy(dest, eng->buf_out, dlen);
968
969         /* update the DT */
970         for (i = DEFAULT_RNG_BLK_SZ - 1; i >= 0; i--) {
971                 dt[i] += 1;
972                 if (dt[i] != 0)
973                         break;
974         }
975
976 out:
977         aes_hw_deinit(eng);
978
979         spin_lock_irqsave(&dd->lock, flags);
980         clear_bit(FLAGS_BUSY, &eng->busy);
981         spin_unlock_irqrestore(&dd->lock, flags);
982
983 fail:
984         /* release the hardware semaphore */
985         tegra_arb_mutex_unlock(eng->res_id);
986         dev_dbg(dd->dev, "%s: done\n", __func__);
987         return dlen;
988 }
989
990 static int tegra_aes_rng_reset(struct crypto_rng *tfm, u8 *seed,
991         unsigned int slen)
992 {
993         struct tegra_aes_dev *dd = aes_dev;
994         struct tegra_aes_ctx *ctx = &rng_ctx;
995         struct tegra_aes_engine *eng = NULL;
996         struct tegra_aes_slot *key_slot;
997         int bsea_busy = false;
998         unsigned long flags;
999         struct timespec ts;
1000         u64 nsec, tmp[2];
1001         int ret = 0;
1002         u8 *dt;
1003
1004         if (!dd)
1005                 return -EINVAL;
1006
1007         if (slen < (DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128)) {
1008                 return -ENOMEM;
1009         }
1010
1011         spin_lock_irqsave(&dd->lock, flags);
1012         bsea_busy = test_and_set_bit(FLAGS_BUSY, &dd->bsea.busy);
1013         spin_unlock_irqrestore(&dd->lock, flags);
1014
1015         if (!bsea_busy)
1016                 eng = &dd->bsea;
1017         else
1018                 return -EBUSY;
1019
1020         ctx->eng = eng;
1021         dd->flags = FLAGS_ENCRYPT | FLAGS_RNG;
1022
1023         if (!ctx->slot) {
1024                 key_slot = aes_find_key_slot(dd);
1025                 if (!key_slot) {
1026                         dev_err(dd->dev, "no empty slot\n");
1027                         return -ENOMEM;
1028                 }
1029                 ctx->slot = key_slot;
1030         }
1031
1032         /* take the hardware semaphore */
1033         if (tegra_arb_mutex_lock_timeout(eng->res_id, ARB_SEMA_TIMEOUT) < 0) {
1034                 dev_err(dd->dev, "aes hardware (%d) not available\n",
1035                 eng->res_id);
1036                 return -EBUSY;
1037         }
1038
1039         ret = aes_hw_init(eng);
1040         if (ret < 0) {
1041                 dev_err(dd->dev, "%s: hw init fail(%d)\n", __func__, ret);
1042                 goto fail;
1043         }
1044
1045         memcpy(ctx->key, seed + DEFAULT_RNG_BLK_SZ, AES_KEYSIZE_128);
1046
1047         eng->ctx = ctx;
1048         eng->ctx->keylen = AES_KEYSIZE_128;
1049         aes_set_key(eng, ctx->slot->slot_num);
1050
1051         /* set seed to the aes hw slot */
1052         memset(eng->buf_in, 0, AES_BLOCK_SIZE);
1053         memcpy(eng->buf_in, seed, DEFAULT_RNG_BLK_SZ);
1054         ret = aes_start_crypt(eng, (u32)eng->dma_buf_in,
1055           (u32)eng->dma_buf_out, 1, FLAGS_CBC, false);
1056         if (ret < 0) {
1057                 dev_err(dd->dev, "aes_start_crypt fail(%d)\n", ret);
1058                 goto out;
1059         }
1060
1061         if (slen >= (2 * DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128)) {
1062                 dt = seed + DEFAULT_RNG_BLK_SZ + AES_KEYSIZE_128;
1063         } else {
1064                 getnstimeofday(&ts);
1065                 nsec = timespec_to_ns(&ts);
1066                 do_div(nsec, 1000);
1067                 nsec ^= dd->ctr << 56;
1068                 dd->ctr++;
1069                 tmp[0] = nsec;
1070                 tmp[1] = tegra_chip_uid();
1071                 dt = (u8 *)tmp;
1072         }
1073         memcpy(ctx->dt, dt, DEFAULT_RNG_BLK_SZ);
1074
1075 out:
1076         aes_hw_deinit(eng);
1077
1078 fail:
1079         /* release the hardware semaphore */
1080         tegra_arb_mutex_unlock(eng->res_id);
1081
1082         dev_dbg(dd->dev, "%s: done\n", __func__);
1083         return ret;
1084 }
1085
1086 static int tegra_aes_cra_init(struct crypto_tfm *tfm)
1087 {
1088         tfm->crt_ablkcipher.reqsize = sizeof(struct tegra_aes_reqctx);
1089         return 0;
1090 }
1091
1092 void tegra_aes_cra_exit(struct crypto_tfm *tfm)
1093 {
1094         struct tegra_aes_ctx *ctx = crypto_ablkcipher_ctx((struct crypto_ablkcipher *)tfm);
1095
1096         if (ctx && ctx->slot)
1097                 aes_release_key_slot(ctx);
1098 }
1099
1100 static struct crypto_alg algs[] = {
1101         {
1102                 .cra_name = "disabled_ecb(aes)",
1103                 .cra_driver_name = "ecb-aes-tegra",
1104                 .cra_priority = 100,
1105                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1106                 .cra_blocksize = AES_BLOCK_SIZE,
1107                 .cra_ctxsize = sizeof(struct tegra_aes_ctx),
1108                 .cra_alignmask = 3,
1109                 .cra_type = &crypto_ablkcipher_type,
1110                 .cra_module = THIS_MODULE,
1111                 .cra_init = tegra_aes_cra_init,
1112                 .cra_exit = tegra_aes_cra_exit,
1113                 .cra_u.ablkcipher = {
1114                         .min_keysize = AES_MIN_KEY_SIZE,
1115                         .max_keysize = AES_MAX_KEY_SIZE,
1116                         .setkey = tegra_aes_setkey,
1117                         .encrypt = tegra_aes_ecb_encrypt,
1118                         .decrypt = tegra_aes_ecb_decrypt,
1119                 },
1120         }, {
1121                 .cra_name = "disabled_cbc(aes)",
1122                 .cra_driver_name = "cbc-aes-tegra",
1123                 .cra_priority = 100,
1124                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1125                 .cra_blocksize = AES_BLOCK_SIZE,
1126                 .cra_ctxsize  = sizeof(struct tegra_aes_ctx),
1127                 .cra_alignmask = 3,
1128                 .cra_type = &crypto_ablkcipher_type,
1129                 .cra_module = THIS_MODULE,
1130                 .cra_init = tegra_aes_cra_init,
1131                 .cra_exit = tegra_aes_cra_exit,
1132                 .cra_u.ablkcipher = {
1133                         .min_keysize = AES_MIN_KEY_SIZE,
1134                         .max_keysize = AES_MAX_KEY_SIZE,
1135                         .ivsize = AES_MIN_KEY_SIZE,
1136                         .setkey = tegra_aes_setkey,
1137                         .encrypt = tegra_aes_cbc_encrypt,
1138                         .decrypt = tegra_aes_cbc_decrypt,
1139                 }
1140         }, {
1141                 .cra_name = "disabled_ofb(aes)",
1142                 .cra_driver_name = "ofb-aes-tegra",
1143                 .cra_priority = 100,
1144                 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
1145                 .cra_blocksize = AES_BLOCK_SIZE,
1146                 .cra_ctxsize  = sizeof(struct tegra_aes_ctx),
1147                 .cra_alignmask = 3,
1148                 .cra_type = &crypto_ablkcipher_type,
1149                 .cra_module = THIS_MODULE,
1150                 .cra_init = tegra_aes_cra_init,
1151                 .cra_exit = tegra_aes_cra_exit,
1152                 .cra_u.ablkcipher = {
1153                         .min_keysize = AES_MIN_KEY_SIZE,
1154                         .max_keysize = AES_MAX_KEY_SIZE,
1155                         .ivsize = AES_MIN_KEY_SIZE,
1156                         .setkey = tegra_aes_setkey,
1157                         .encrypt = tegra_aes_ofb_encrypt,
1158                         .decrypt = tegra_aes_ofb_decrypt,
1159                 }
1160         }, {
1161                 .cra_name = "disabled_ansi_cprng",
1162                 .cra_driver_name = "rng-aes-tegra",
1163                 .cra_priority = 100,
1164                 .cra_flags = CRYPTO_ALG_TYPE_RNG,
1165                 .cra_ctxsize = sizeof(struct tegra_aes_ctx),
1166                 .cra_type = &crypto_rng_type,
1167                 .cra_module = THIS_MODULE,
1168                 .cra_init = tegra_aes_cra_init,
1169                 .cra_exit = tegra_aes_cra_exit,
1170                 .cra_u.rng = {
1171                         .rng_make_random = tegra_aes_get_random,
1172                         .rng_reset = tegra_aes_rng_reset,
1173                         .seedsize = AES_KEYSIZE_128 + (2 * DEFAULT_RNG_BLK_SZ),
1174                 }
1175         }
1176 };
1177
1178 static int tegra_aes_probe(struct platform_device *pdev)
1179 {
1180         struct device *dev = &pdev->dev;
1181         struct tegra_aes_dev *dd;
1182         struct resource *res[2];
1183         int err = -ENOMEM, i = 0, j;
1184
1185         if (aes_dev)
1186                 return -EEXIST;
1187
1188         dd = kzalloc(sizeof(struct tegra_aes_dev), GFP_KERNEL);
1189         if (dd == NULL) {
1190                 dev_err(dev, "unable to alloc data struct.\n");
1191                 return -ENOMEM;;
1192         }
1193         dd->dev = dev;
1194         platform_set_drvdata(pdev, dd);
1195
1196         dd->slots = kzalloc(sizeof(struct tegra_aes_slot) * AES_NR_KEYSLOTS,
1197                 GFP_KERNEL);
1198         if (dd->slots == NULL) {
1199                 dev_err(dev, "unable to alloc slot struct.\n");
1200                 goto out;
1201         }
1202
1203         spin_lock_init(&dd->lock);
1204         crypto_init_queue(&dd->queue, TEGRA_AES_QUEUE_LENGTH);
1205
1206         /* Get the module base address */
1207         res[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1208         res[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1209         if (!res[0] || !res[1]) {
1210                 dev_err(dev, "invalid resource type: base\n");
1211                 err = -ENODEV;
1212                 goto out;
1213         }
1214         dd->bsev.phys_base = res[0]->start;
1215         dd->bsev.io_base = ioremap(dd->bsev.phys_base, resource_size(res[0]));
1216         dd->bsea.phys_base = res[1]->start;
1217         dd->bsea.io_base = ioremap(dd->bsea.phys_base, resource_size(res[1]));
1218
1219         if (!dd->bsev.io_base || !dd->bsea.io_base) {
1220                 dev_err(dev, "can't ioremap phys_base\n");
1221                 err = -ENOMEM;
1222                 goto out;
1223         }
1224
1225         err = alloc_iram(dd);
1226         if (err < 0) {
1227                 dev_err(dev, "Failed to allocate IRAM for BSEA\n");
1228                 goto out;
1229         }
1230
1231         dd->bsev.res_id = TEGRA_ARB_BSEV;
1232         dd->bsea.res_id = TEGRA_ARB_BSEA;
1233
1234         dd->bsev.pclk = clk_get(dev, "bsev");
1235         if (IS_ERR(dd->bsev.pclk)) {
1236                 dev_err(dev, "v: pclock intialization failed.\n");
1237                 err = -ENODEV;
1238                 goto out;
1239         }
1240
1241         dd->bsev.iclk = clk_get(dev, "vde");
1242         if (IS_ERR(dd->bsev.iclk)) {
1243                 dev_err(dev, "v: iclock intialization failed.\n");
1244                 err = -ENODEV;
1245                 goto out;
1246         }
1247
1248         dd->bsea.pclk = clk_get(dev, "bsea");
1249         if (IS_ERR(dd->bsea.pclk)) {
1250                 dev_err(dev, "a: pclock intialization failed.\n");
1251                 err = -ENODEV;
1252                 goto out;
1253         }
1254
1255         dd->bsea.iclk = clk_get(dev, "sclk");
1256         if (IS_ERR(dd->bsea.iclk)) {
1257                 dev_err(dev, "a: iclock intialization failed.\n");
1258                 err = -ENODEV;
1259                 goto out;
1260         }
1261
1262         err = clk_set_rate(dd->bsev.iclk, ULONG_MAX);
1263         if (err) {
1264                 dev_err(dd->dev, "bsev iclk set_rate fail(%d)\n", err);
1265                 goto out;
1266         }
1267
1268         err = clk_set_rate(dd->bsea.iclk, ULONG_MAX);
1269         if (err) {
1270                 dev_err(dd->dev, "bsea iclk set_rate fail(%d)\n", err);
1271                 goto out;
1272         }
1273
1274         /*
1275          * the foll contiguous memory is allocated as follows -
1276          * - hardware key table
1277          * - key schedule
1278          */
1279         dd->bsea.ivkey_base = NULL;
1280         dd->bsev.ivkey_base = dma_alloc_coherent(dev, AES_MAX_KEY_SIZE,
1281                 &dd->bsev.ivkey_phys_base, GFP_KERNEL);
1282         if (!dd->bsev.ivkey_base) {
1283                 dev_err(dev, "can not allocate iv/key buffer for BSEV\n");
1284                 err = -ENOMEM;
1285                 goto out;
1286         }
1287         memset(dd->bsev.ivkey_base, 0, AES_MAX_KEY_SIZE);
1288
1289         dd->bsev.buf_in = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1290                 &dd->bsev.dma_buf_in, GFP_KERNEL);
1291         dd->bsea.buf_in = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1292                 &dd->bsea.dma_buf_in, GFP_KERNEL);
1293         if (!dd->bsev.buf_in || !dd->bsea.buf_in) {
1294                 dev_err(dev, "can not allocate dma-in buffer\n");
1295                 err = -ENOMEM;
1296                 goto out;
1297         }
1298
1299         dd->bsev.buf_out = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1300                 &dd->bsev.dma_buf_out, GFP_KERNEL);
1301         dd->bsea.buf_out = dma_alloc_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1302                 &dd->bsea.dma_buf_out, GFP_KERNEL);
1303         if (!dd->bsev.buf_out || !dd->bsea.buf_out) {
1304                 dev_err(dev, "can not allocate dma-out buffer\n");
1305                 err = -ENOMEM;
1306                 goto out;
1307         }
1308
1309         init_completion(&dd->bsev.op_complete);
1310         init_completion(&dd->bsea.op_complete);
1311
1312         bsev_wq = alloc_workqueue("bsev_wq", WQ_HIGHPRI | WQ_UNBOUND, 1);
1313         bsea_wq = alloc_workqueue("bsea_wq", WQ_HIGHPRI | WQ_UNBOUND, 1);
1314         if (!bsev_wq || !bsea_wq) {
1315                 dev_err(dev, "alloc_workqueue failed\n");
1316                 goto out;
1317         }
1318
1319         /* get the irq */
1320         dd->bsev.irq = INT_VDE_BSE_V;
1321         err = request_irq(dd->bsev.irq, aes_bsev_irq, IRQF_TRIGGER_HIGH,
1322                 "tegra-aes", dd);
1323         if (err) {
1324                 dev_err(dev, "request_irq failed fir BSEV Engine\n");
1325                 goto out;
1326         }
1327         disable_irq(dd->bsev.irq);
1328
1329         dd->bsea.irq = INT_VDE_BSE_A;
1330         err = request_irq(dd->bsea.irq, aes_bsea_irq, IRQF_TRIGGER_HIGH,
1331                 "tegra-aes", dd);
1332         if (err) {
1333                 dev_err(dev, "request_irq failed for BSEA Engine\n");
1334                 goto out;
1335         }
1336         disable_irq(dd->bsea.irq);
1337
1338         spin_lock_init(&list_lock);
1339         spin_lock(&list_lock);
1340         for (i = 0; i < AES_NR_KEYSLOTS; i++) {
1341                 if (i == SSK_SLOT_NUM)
1342                         continue;
1343                 dd->slots[i].available = true;
1344                 dd->slots[i].slot_num = i;
1345                 INIT_LIST_HEAD(&dd->slots[i].node);
1346                 list_add_tail(&dd->slots[i].node, &slot_list);
1347         }
1348         spin_unlock(&list_lock);
1349
1350         aes_dev = dd;
1351
1352         for (i = 0; i < ARRAY_SIZE(algs); i++) {
1353                 INIT_LIST_HEAD(&algs[i].cra_list);
1354                 err = crypto_register_alg(&algs[i]);
1355                 if (err)
1356                         goto out;
1357         }
1358
1359         dev_info(dev, "registered");
1360         return 0;
1361
1362 out:
1363         for (j = 0; j < i; j++)
1364                 crypto_unregister_alg(&algs[j]);
1365
1366         free_iram(dd);
1367
1368         if (dd->bsev.ivkey_base) {
1369                 dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base,
1370                         dd->bsev.ivkey_phys_base);
1371         }
1372
1373         if (dd->bsev.buf_in && dd->bsea.buf_in) {
1374                 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1375                         dd->bsev.buf_in, dd->bsev.dma_buf_in);
1376                 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1377                         dd->bsea.buf_in, dd->bsea.dma_buf_in);
1378         }
1379
1380         if (dd->bsev.buf_out && dd->bsea.buf_out) {
1381                 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1382                         dd->bsev.buf_out, dd->bsev.dma_buf_out);
1383                 dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES,
1384                         dd->bsea.buf_out, dd->bsea.dma_buf_out);
1385         }
1386
1387         if (dd->bsev.io_base && dd->bsea.io_base) {
1388                 iounmap(dd->bsev.io_base);
1389                 iounmap(dd->bsea.io_base);
1390         }
1391
1392         if (dd->bsev.pclk)
1393                 clk_put(dd->bsev.pclk);
1394
1395         if (dd->bsev.iclk)
1396                 clk_put(dd->bsev.iclk);
1397
1398         if (dd->bsea.pclk)
1399                 clk_put(dd->bsea.pclk);
1400
1401         if (bsev_wq)
1402                 destroy_workqueue(bsev_wq);
1403
1404         if (bsea_wq)
1405                 destroy_workqueue(bsea_wq);
1406
1407         if (dd->bsev.irq)
1408                 free_irq(dd->bsev.irq, dd);
1409
1410         if (dd->bsea.irq)
1411                 free_irq(dd->bsea.irq, dd);
1412
1413         spin_lock(&list_lock);
1414         list_del(&slot_list);
1415         spin_unlock(&list_lock);
1416
1417         kfree(dd->slots);
1418         kfree(dd);
1419         aes_dev = NULL;
1420
1421         dev_err(dev, "%s: initialization failed.\n", __func__);
1422         return err;
1423 }
1424
1425 static int __devexit tegra_aes_remove(struct platform_device *pdev)
1426 {
1427         struct device *dev = &pdev->dev;
1428         struct tegra_aes_dev *dd = platform_get_drvdata(pdev);
1429         int i;
1430
1431         if (!dd)
1432                 return -ENODEV;
1433
1434         cancel_work_sync(&bsev_work);
1435         cancel_work_sync(&bsea_work);
1436         destroy_workqueue(bsev_wq);
1437         destroy_workqueue(bsea_wq);
1438         free_irq(dd->bsev.irq, dd);
1439         free_irq(dd->bsea.irq, dd);
1440         spin_lock(&list_lock);
1441         list_del(&slot_list);
1442         spin_unlock(&list_lock);
1443
1444         for (i = 0; i < ARRAY_SIZE(algs); i++)
1445                 crypto_unregister_alg(&algs[i]);
1446
1447         free_iram(dd);
1448         dma_free_coherent(dev, SZ_512, dd->bsev.ivkey_base,
1449                 dd->bsev.ivkey_phys_base);
1450         dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsev.buf_in,
1451                 dd->bsev.dma_buf_in);
1452         dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsea.buf_in,
1453                 dd->bsea.dma_buf_in);
1454         dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsev.buf_out,
1455                 dd->bsev.dma_buf_out);
1456         dma_free_coherent(dev, AES_HW_DMA_BUFFER_SIZE_BYTES, dd->bsea.buf_out,
1457                 dd->bsea.dma_buf_out);
1458
1459         iounmap(dd->bsev.io_base);
1460         iounmap(dd->bsea.io_base);
1461         clk_put(dd->bsev.iclk);
1462         clk_put(dd->bsev.pclk);
1463         clk_put(dd->bsea.pclk);
1464         kfree(dd->slots);
1465         kfree(dd);
1466         aes_dev = NULL;
1467
1468         return 0;
1469 }
1470
1471 static struct platform_driver tegra_aes_driver = {
1472         .probe  = tegra_aes_probe,
1473         .remove = __devexit_p(tegra_aes_remove),
1474         .driver = {
1475                 .name   = "tegra-aes",
1476                 .owner  = THIS_MODULE,
1477         },
1478 };
1479
1480 static int __init tegra_aes_mod_init(void)
1481 {
1482         INIT_LIST_HEAD(&slot_list);
1483         return  platform_driver_register(&tegra_aes_driver);
1484 }
1485
1486 static void __exit tegra_aes_mod_exit(void)
1487 {
1488         platform_driver_unregister(&tegra_aes_driver);
1489 }
1490
1491 module_init(tegra_aes_mod_init);
1492 module_exit(tegra_aes_mod_exit);
1493
1494 MODULE_DESCRIPTION("Tegra AES hw acceleration support.");
1495 MODULE_AUTHOR("NVIDIA Corporation");
1496 MODULE_LICENSE("GPL v2");