random: Reorder struct entropy_store to remove padding on 64bits
[linux-2.6.git] / drivers / crypto / talitos.c
1 /*
2  * talitos - Freescale Integrated Security Engine (SEC) device driver
3  *
4  * Copyright (c) 2008-2010 Freescale Semiconductor, Inc.
5  *
6  * Scatterlist Crypto API glue code copied from files with the following:
7  * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
8  *
9  * Crypto algorithm registration code copied from hifn driver:
10  * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
11  * All rights reserved.
12  *
13  * This program is free software; you can redistribute it and/or modify
14  * it under the terms of the GNU General Public License as published by
15  * the Free Software Foundation; either version 2 of the License, or
16  * (at your option) any later version.
17  *
18  * This program is distributed in the hope that it will be useful,
19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  * GNU General Public License for more details.
22  *
23  * You should have received a copy of the GNU General Public License
24  * along with this program; if not, write to the Free Software
25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
26  */
27
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/device.h>
32 #include <linux/interrupt.h>
33 #include <linux/crypto.h>
34 #include <linux/hw_random.h>
35 #include <linux/of_platform.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/io.h>
38 #include <linux/spinlock.h>
39 #include <linux/rtnetlink.h>
40 #include <linux/slab.h>
41
42 #include <crypto/algapi.h>
43 #include <crypto/aes.h>
44 #include <crypto/des.h>
45 #include <crypto/sha.h>
46 #include <crypto/md5.h>
47 #include <crypto/aead.h>
48 #include <crypto/authenc.h>
49 #include <crypto/skcipher.h>
50 #include <crypto/hash.h>
51 #include <crypto/internal/hash.h>
52 #include <crypto/scatterwalk.h>
53
54 #include "talitos.h"
55
56 #define TALITOS_TIMEOUT 100000
57 #define TALITOS_MAX_DATA_LEN 65535
58
59 #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
60 #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
61 #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
62
63 /* descriptor pointer entry */
64 struct talitos_ptr {
65         __be16 len;     /* length */
66         u8 j_extent;    /* jump to sg link table and/or extent */
67         u8 eptr;        /* extended address */
68         __be32 ptr;     /* address */
69 };
70
71 static const struct talitos_ptr zero_entry = {
72         .len = 0,
73         .j_extent = 0,
74         .eptr = 0,
75         .ptr = 0
76 };
77
78 /* descriptor */
79 struct talitos_desc {
80         __be32 hdr;                     /* header high bits */
81         __be32 hdr_lo;                  /* header low bits */
82         struct talitos_ptr ptr[7];      /* ptr/len pair array */
83 };
84
85 /**
86  * talitos_request - descriptor submission request
87  * @desc: descriptor pointer (kernel virtual)
88  * @dma_desc: descriptor's physical bus address
89  * @callback: whom to call when descriptor processing is done
90  * @context: caller context (optional)
91  */
92 struct talitos_request {
93         struct talitos_desc *desc;
94         dma_addr_t dma_desc;
95         void (*callback) (struct device *dev, struct talitos_desc *desc,
96                           void *context, int error);
97         void *context;
98 };
99
100 /* per-channel fifo management */
101 struct talitos_channel {
102         /* request fifo */
103         struct talitos_request *fifo;
104
105         /* number of requests pending in channel h/w fifo */
106         atomic_t submit_count ____cacheline_aligned;
107
108         /* request submission (head) lock */
109         spinlock_t head_lock ____cacheline_aligned;
110         /* index to next free descriptor request */
111         int head;
112
113         /* request release (tail) lock */
114         spinlock_t tail_lock ____cacheline_aligned;
115         /* index to next in-progress/done descriptor request */
116         int tail;
117 };
118
119 struct talitos_private {
120         struct device *dev;
121         struct of_device *ofdev;
122         void __iomem *reg;
123         int irq;
124
125         /* SEC version geometry (from device tree node) */
126         unsigned int num_channels;
127         unsigned int chfifo_len;
128         unsigned int exec_units;
129         unsigned int desc_types;
130
131         /* SEC Compatibility info */
132         unsigned long features;
133
134         /*
135          * length of the request fifo
136          * fifo_len is chfifo_len rounded up to next power of 2
137          * so we can use bitwise ops to wrap
138          */
139         unsigned int fifo_len;
140
141         struct talitos_channel *chan;
142
143         /* next channel to be assigned next incoming descriptor */
144         atomic_t last_chan ____cacheline_aligned;
145
146         /* request callback tasklet */
147         struct tasklet_struct done_task;
148
149         /* list of registered algorithms */
150         struct list_head alg_list;
151
152         /* hwrng device */
153         struct hwrng rng;
154 };
155
156 /* .features flag */
157 #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
158 #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
159 #define TALITOS_FTR_SHA224_HWINIT 0x00000004
160
161 static void to_talitos_ptr(struct talitos_ptr *talitos_ptr, dma_addr_t dma_addr)
162 {
163         talitos_ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
164         talitos_ptr->eptr = cpu_to_be32(upper_32_bits(dma_addr));
165 }
166
167 /*
168  * map virtual single (contiguous) pointer to h/w descriptor pointer
169  */
170 static void map_single_talitos_ptr(struct device *dev,
171                                    struct talitos_ptr *talitos_ptr,
172                                    unsigned short len, void *data,
173                                    unsigned char extent,
174                                    enum dma_data_direction dir)
175 {
176         dma_addr_t dma_addr = dma_map_single(dev, data, len, dir);
177
178         talitos_ptr->len = cpu_to_be16(len);
179         to_talitos_ptr(talitos_ptr, dma_addr);
180         talitos_ptr->j_extent = extent;
181 }
182
183 /*
184  * unmap bus single (contiguous) h/w descriptor pointer
185  */
186 static void unmap_single_talitos_ptr(struct device *dev,
187                                      struct talitos_ptr *talitos_ptr,
188                                      enum dma_data_direction dir)
189 {
190         dma_unmap_single(dev, be32_to_cpu(talitos_ptr->ptr),
191                          be16_to_cpu(talitos_ptr->len), dir);
192 }
193
194 static int reset_channel(struct device *dev, int ch)
195 {
196         struct talitos_private *priv = dev_get_drvdata(dev);
197         unsigned int timeout = TALITOS_TIMEOUT;
198
199         setbits32(priv->reg + TALITOS_CCCR(ch), TALITOS_CCCR_RESET);
200
201         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) & TALITOS_CCCR_RESET)
202                && --timeout)
203                 cpu_relax();
204
205         if (timeout == 0) {
206                 dev_err(dev, "failed to reset channel %d\n", ch);
207                 return -EIO;
208         }
209
210         /* set 36-bit addressing, done writeback enable and done IRQ enable */
211         setbits32(priv->reg + TALITOS_CCCR_LO(ch), TALITOS_CCCR_LO_EAE |
212                   TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
213
214         /* and ICCR writeback, if available */
215         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
216                 setbits32(priv->reg + TALITOS_CCCR_LO(ch),
217                           TALITOS_CCCR_LO_IWSE);
218
219         return 0;
220 }
221
222 static int reset_device(struct device *dev)
223 {
224         struct talitos_private *priv = dev_get_drvdata(dev);
225         unsigned int timeout = TALITOS_TIMEOUT;
226
227         setbits32(priv->reg + TALITOS_MCR, TALITOS_MCR_SWR);
228
229         while ((in_be32(priv->reg + TALITOS_MCR) & TALITOS_MCR_SWR)
230                && --timeout)
231                 cpu_relax();
232
233         if (timeout == 0) {
234                 dev_err(dev, "failed to reset device\n");
235                 return -EIO;
236         }
237
238         return 0;
239 }
240
241 /*
242  * Reset and initialize the device
243  */
244 static int init_device(struct device *dev)
245 {
246         struct talitos_private *priv = dev_get_drvdata(dev);
247         int ch, err;
248
249         /*
250          * Master reset
251          * errata documentation: warning: certain SEC interrupts
252          * are not fully cleared by writing the MCR:SWR bit,
253          * set bit twice to completely reset
254          */
255         err = reset_device(dev);
256         if (err)
257                 return err;
258
259         err = reset_device(dev);
260         if (err)
261                 return err;
262
263         /* reset channels */
264         for (ch = 0; ch < priv->num_channels; ch++) {
265                 err = reset_channel(dev, ch);
266                 if (err)
267                         return err;
268         }
269
270         /* enable channel done and error interrupts */
271         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
272         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
273
274         /* disable integrity check error interrupts (use writeback instead) */
275         if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
276                 setbits32(priv->reg + TALITOS_MDEUICR_LO,
277                           TALITOS_MDEUICR_LO_ICE);
278
279         return 0;
280 }
281
282 /**
283  * talitos_submit - submits a descriptor to the device for processing
284  * @dev:        the SEC device to be used
285  * @desc:       the descriptor to be processed by the device
286  * @callback:   whom to call when processing is complete
287  * @context:    a handle for use by caller (optional)
288  *
289  * desc must contain valid dma-mapped (bus physical) address pointers.
290  * callback must check err and feedback in descriptor header
291  * for device processing status.
292  */
293 static int talitos_submit(struct device *dev, struct talitos_desc *desc,
294                           void (*callback)(struct device *dev,
295                                            struct talitos_desc *desc,
296                                            void *context, int error),
297                           void *context)
298 {
299         struct talitos_private *priv = dev_get_drvdata(dev);
300         struct talitos_request *request;
301         unsigned long flags, ch;
302         int head;
303
304         /* select done notification */
305         desc->hdr |= DESC_HDR_DONE_NOTIFY;
306
307         /* emulate SEC's round-robin channel fifo polling scheme */
308         ch = atomic_inc_return(&priv->last_chan) & (priv->num_channels - 1);
309
310         spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
311
312         if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
313                 /* h/w fifo is full */
314                 spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
315                 return -EAGAIN;
316         }
317
318         head = priv->chan[ch].head;
319         request = &priv->chan[ch].fifo[head];
320
321         /* map descriptor and save caller data */
322         request->dma_desc = dma_map_single(dev, desc, sizeof(*desc),
323                                            DMA_BIDIRECTIONAL);
324         request->callback = callback;
325         request->context = context;
326
327         /* increment fifo head */
328         priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
329
330         smp_wmb();
331         request->desc = desc;
332
333         /* GO! */
334         wmb();
335         out_be32(priv->reg + TALITOS_FF(ch),
336                  cpu_to_be32(upper_32_bits(request->dma_desc)));
337         out_be32(priv->reg + TALITOS_FF_LO(ch),
338                  cpu_to_be32(lower_32_bits(request->dma_desc)));
339
340         spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
341
342         return -EINPROGRESS;
343 }
344
345 /*
346  * process what was done, notify callback of error if not
347  */
348 static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
349 {
350         struct talitos_private *priv = dev_get_drvdata(dev);
351         struct talitos_request *request, saved_req;
352         unsigned long flags;
353         int tail, status;
354
355         spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
356
357         tail = priv->chan[ch].tail;
358         while (priv->chan[ch].fifo[tail].desc) {
359                 request = &priv->chan[ch].fifo[tail];
360
361                 /* descriptors with their done bits set don't get the error */
362                 rmb();
363                 if ((request->desc->hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
364                         status = 0;
365                 else
366                         if (!error)
367                                 break;
368                         else
369                                 status = error;
370
371                 dma_unmap_single(dev, request->dma_desc,
372                                  sizeof(struct talitos_desc),
373                                  DMA_BIDIRECTIONAL);
374
375                 /* copy entries so we can call callback outside lock */
376                 saved_req.desc = request->desc;
377                 saved_req.callback = request->callback;
378                 saved_req.context = request->context;
379
380                 /* release request entry in fifo */
381                 smp_wmb();
382                 request->desc = NULL;
383
384                 /* increment fifo tail */
385                 priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
386
387                 spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
388
389                 atomic_dec(&priv->chan[ch].submit_count);
390
391                 saved_req.callback(dev, saved_req.desc, saved_req.context,
392                                    status);
393                 /* channel may resume processing in single desc error case */
394                 if (error && !reset_ch && status == error)
395                         return;
396                 spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
397                 tail = priv->chan[ch].tail;
398         }
399
400         spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
401 }
402
403 /*
404  * process completed requests for channels that have done status
405  */
406 static void talitos_done(unsigned long data)
407 {
408         struct device *dev = (struct device *)data;
409         struct talitos_private *priv = dev_get_drvdata(dev);
410         int ch;
411
412         for (ch = 0; ch < priv->num_channels; ch++)
413                 flush_channel(dev, ch, 0, 0);
414
415         /* At this point, all completed channels have been processed.
416          * Unmask done interrupts for channels completed later on.
417          */
418         setbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_INIT);
419         setbits32(priv->reg + TALITOS_IMR_LO, TALITOS_IMR_LO_INIT);
420 }
421
422 /*
423  * locate current (offending) descriptor
424  */
425 static struct talitos_desc *current_desc(struct device *dev, int ch)
426 {
427         struct talitos_private *priv = dev_get_drvdata(dev);
428         int tail = priv->chan[ch].tail;
429         dma_addr_t cur_desc;
430
431         cur_desc = in_be32(priv->reg + TALITOS_CDPR_LO(ch));
432
433         while (priv->chan[ch].fifo[tail].dma_desc != cur_desc) {
434                 tail = (tail + 1) & (priv->fifo_len - 1);
435                 if (tail == priv->chan[ch].tail) {
436                         dev_err(dev, "couldn't locate current descriptor\n");
437                         return NULL;
438                 }
439         }
440
441         return priv->chan[ch].fifo[tail].desc;
442 }
443
444 /*
445  * user diagnostics; report root cause of error based on execution unit status
446  */
447 static void report_eu_error(struct device *dev, int ch,
448                             struct talitos_desc *desc)
449 {
450         struct talitos_private *priv = dev_get_drvdata(dev);
451         int i;
452
453         switch (desc->hdr & DESC_HDR_SEL0_MASK) {
454         case DESC_HDR_SEL0_AFEU:
455                 dev_err(dev, "AFEUISR 0x%08x_%08x\n",
456                         in_be32(priv->reg + TALITOS_AFEUISR),
457                         in_be32(priv->reg + TALITOS_AFEUISR_LO));
458                 break;
459         case DESC_HDR_SEL0_DEU:
460                 dev_err(dev, "DEUISR 0x%08x_%08x\n",
461                         in_be32(priv->reg + TALITOS_DEUISR),
462                         in_be32(priv->reg + TALITOS_DEUISR_LO));
463                 break;
464         case DESC_HDR_SEL0_MDEUA:
465         case DESC_HDR_SEL0_MDEUB:
466                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
467                         in_be32(priv->reg + TALITOS_MDEUISR),
468                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
469                 break;
470         case DESC_HDR_SEL0_RNG:
471                 dev_err(dev, "RNGUISR 0x%08x_%08x\n",
472                         in_be32(priv->reg + TALITOS_RNGUISR),
473                         in_be32(priv->reg + TALITOS_RNGUISR_LO));
474                 break;
475         case DESC_HDR_SEL0_PKEU:
476                 dev_err(dev, "PKEUISR 0x%08x_%08x\n",
477                         in_be32(priv->reg + TALITOS_PKEUISR),
478                         in_be32(priv->reg + TALITOS_PKEUISR_LO));
479                 break;
480         case DESC_HDR_SEL0_AESU:
481                 dev_err(dev, "AESUISR 0x%08x_%08x\n",
482                         in_be32(priv->reg + TALITOS_AESUISR),
483                         in_be32(priv->reg + TALITOS_AESUISR_LO));
484                 break;
485         case DESC_HDR_SEL0_CRCU:
486                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
487                         in_be32(priv->reg + TALITOS_CRCUISR),
488                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
489                 break;
490         case DESC_HDR_SEL0_KEU:
491                 dev_err(dev, "KEUISR 0x%08x_%08x\n",
492                         in_be32(priv->reg + TALITOS_KEUISR),
493                         in_be32(priv->reg + TALITOS_KEUISR_LO));
494                 break;
495         }
496
497         switch (desc->hdr & DESC_HDR_SEL1_MASK) {
498         case DESC_HDR_SEL1_MDEUA:
499         case DESC_HDR_SEL1_MDEUB:
500                 dev_err(dev, "MDEUISR 0x%08x_%08x\n",
501                         in_be32(priv->reg + TALITOS_MDEUISR),
502                         in_be32(priv->reg + TALITOS_MDEUISR_LO));
503                 break;
504         case DESC_HDR_SEL1_CRCU:
505                 dev_err(dev, "CRCUISR 0x%08x_%08x\n",
506                         in_be32(priv->reg + TALITOS_CRCUISR),
507                         in_be32(priv->reg + TALITOS_CRCUISR_LO));
508                 break;
509         }
510
511         for (i = 0; i < 8; i++)
512                 dev_err(dev, "DESCBUF 0x%08x_%08x\n",
513                         in_be32(priv->reg + TALITOS_DESCBUF(ch) + 8*i),
514                         in_be32(priv->reg + TALITOS_DESCBUF_LO(ch) + 8*i));
515 }
516
517 /*
518  * recover from error interrupts
519  */
520 static void talitos_error(unsigned long data, u32 isr, u32 isr_lo)
521 {
522         struct device *dev = (struct device *)data;
523         struct talitos_private *priv = dev_get_drvdata(dev);
524         unsigned int timeout = TALITOS_TIMEOUT;
525         int ch, error, reset_dev = 0, reset_ch = 0;
526         u32 v, v_lo;
527
528         for (ch = 0; ch < priv->num_channels; ch++) {
529                 /* skip channels without errors */
530                 if (!(isr & (1 << (ch * 2 + 1))))
531                         continue;
532
533                 error = -EINVAL;
534
535                 v = in_be32(priv->reg + TALITOS_CCPSR(ch));
536                 v_lo = in_be32(priv->reg + TALITOS_CCPSR_LO(ch));
537
538                 if (v_lo & TALITOS_CCPSR_LO_DOF) {
539                         dev_err(dev, "double fetch fifo overflow error\n");
540                         error = -EAGAIN;
541                         reset_ch = 1;
542                 }
543                 if (v_lo & TALITOS_CCPSR_LO_SOF) {
544                         /* h/w dropped descriptor */
545                         dev_err(dev, "single fetch fifo overflow error\n");
546                         error = -EAGAIN;
547                 }
548                 if (v_lo & TALITOS_CCPSR_LO_MDTE)
549                         dev_err(dev, "master data transfer error\n");
550                 if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
551                         dev_err(dev, "s/g data length zero error\n");
552                 if (v_lo & TALITOS_CCPSR_LO_FPZ)
553                         dev_err(dev, "fetch pointer zero error\n");
554                 if (v_lo & TALITOS_CCPSR_LO_IDH)
555                         dev_err(dev, "illegal descriptor header error\n");
556                 if (v_lo & TALITOS_CCPSR_LO_IEU)
557                         dev_err(dev, "invalid execution unit error\n");
558                 if (v_lo & TALITOS_CCPSR_LO_EU)
559                         report_eu_error(dev, ch, current_desc(dev, ch));
560                 if (v_lo & TALITOS_CCPSR_LO_GB)
561                         dev_err(dev, "gather boundary error\n");
562                 if (v_lo & TALITOS_CCPSR_LO_GRL)
563                         dev_err(dev, "gather return/length error\n");
564                 if (v_lo & TALITOS_CCPSR_LO_SB)
565                         dev_err(dev, "scatter boundary error\n");
566                 if (v_lo & TALITOS_CCPSR_LO_SRL)
567                         dev_err(dev, "scatter return/length error\n");
568
569                 flush_channel(dev, ch, error, reset_ch);
570
571                 if (reset_ch) {
572                         reset_channel(dev, ch);
573                 } else {
574                         setbits32(priv->reg + TALITOS_CCCR(ch),
575                                   TALITOS_CCCR_CONT);
576                         setbits32(priv->reg + TALITOS_CCCR_LO(ch), 0);
577                         while ((in_be32(priv->reg + TALITOS_CCCR(ch)) &
578                                TALITOS_CCCR_CONT) && --timeout)
579                                 cpu_relax();
580                         if (timeout == 0) {
581                                 dev_err(dev, "failed to restart channel %d\n",
582                                         ch);
583                                 reset_dev = 1;
584                         }
585                 }
586         }
587         if (reset_dev || isr & ~TALITOS_ISR_CHERR || isr_lo) {
588                 dev_err(dev, "done overflow, internal time out, or rngu error: "
589                         "ISR 0x%08x_%08x\n", isr, isr_lo);
590
591                 /* purge request queues */
592                 for (ch = 0; ch < priv->num_channels; ch++)
593                         flush_channel(dev, ch, -EIO, 1);
594
595                 /* reset and reinitialize the device */
596                 init_device(dev);
597         }
598 }
599
600 static irqreturn_t talitos_interrupt(int irq, void *data)
601 {
602         struct device *dev = data;
603         struct talitos_private *priv = dev_get_drvdata(dev);
604         u32 isr, isr_lo;
605
606         isr = in_be32(priv->reg + TALITOS_ISR);
607         isr_lo = in_be32(priv->reg + TALITOS_ISR_LO);
608         /* Acknowledge interrupt */
609         out_be32(priv->reg + TALITOS_ICR, isr);
610         out_be32(priv->reg + TALITOS_ICR_LO, isr_lo);
611
612         if (unlikely((isr & ~TALITOS_ISR_CHDONE) || isr_lo))
613                 talitos_error((unsigned long)data, isr, isr_lo);
614         else
615                 if (likely(isr & TALITOS_ISR_CHDONE)) {
616                         /* mask further done interrupts. */
617                         clrbits32(priv->reg + TALITOS_IMR, TALITOS_IMR_DONE);
618                         /* done_task will unmask done interrupts at exit */
619                         tasklet_schedule(&priv->done_task);
620                 }
621
622         return (isr || isr_lo) ? IRQ_HANDLED : IRQ_NONE;
623 }
624
625 /*
626  * hwrng
627  */
628 static int talitos_rng_data_present(struct hwrng *rng, int wait)
629 {
630         struct device *dev = (struct device *)rng->priv;
631         struct talitos_private *priv = dev_get_drvdata(dev);
632         u32 ofl;
633         int i;
634
635         for (i = 0; i < 20; i++) {
636                 ofl = in_be32(priv->reg + TALITOS_RNGUSR_LO) &
637                       TALITOS_RNGUSR_LO_OFL;
638                 if (ofl || !wait)
639                         break;
640                 udelay(10);
641         }
642
643         return !!ofl;
644 }
645
646 static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
647 {
648         struct device *dev = (struct device *)rng->priv;
649         struct talitos_private *priv = dev_get_drvdata(dev);
650
651         /* rng fifo requires 64-bit accesses */
652         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO);
653         *data = in_be32(priv->reg + TALITOS_RNGU_FIFO_LO);
654
655         return sizeof(u32);
656 }
657
658 static int talitos_rng_init(struct hwrng *rng)
659 {
660         struct device *dev = (struct device *)rng->priv;
661         struct talitos_private *priv = dev_get_drvdata(dev);
662         unsigned int timeout = TALITOS_TIMEOUT;
663
664         setbits32(priv->reg + TALITOS_RNGURCR_LO, TALITOS_RNGURCR_LO_SR);
665         while (!(in_be32(priv->reg + TALITOS_RNGUSR_LO) & TALITOS_RNGUSR_LO_RD)
666                && --timeout)
667                 cpu_relax();
668         if (timeout == 0) {
669                 dev_err(dev, "failed to reset rng hw\n");
670                 return -ENODEV;
671         }
672
673         /* start generating */
674         setbits32(priv->reg + TALITOS_RNGUDSR_LO, 0);
675
676         return 0;
677 }
678
679 static int talitos_register_rng(struct device *dev)
680 {
681         struct talitos_private *priv = dev_get_drvdata(dev);
682
683         priv->rng.name          = dev_driver_string(dev),
684         priv->rng.init          = talitos_rng_init,
685         priv->rng.data_present  = talitos_rng_data_present,
686         priv->rng.data_read     = talitos_rng_data_read,
687         priv->rng.priv          = (unsigned long)dev;
688
689         return hwrng_register(&priv->rng);
690 }
691
692 static void talitos_unregister_rng(struct device *dev)
693 {
694         struct talitos_private *priv = dev_get_drvdata(dev);
695
696         hwrng_unregister(&priv->rng);
697 }
698
699 /*
700  * crypto alg
701  */
702 #define TALITOS_CRA_PRIORITY            3000
703 #define TALITOS_MAX_KEY_SIZE            64
704 #define TALITOS_MAX_IV_LENGTH           16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
705
706 #define MD5_BLOCK_SIZE    64
707
708 struct talitos_ctx {
709         struct device *dev;
710         __be32 desc_hdr_template;
711         u8 key[TALITOS_MAX_KEY_SIZE];
712         u8 iv[TALITOS_MAX_IV_LENGTH];
713         unsigned int keylen;
714         unsigned int enckeylen;
715         unsigned int authkeylen;
716         unsigned int authsize;
717 };
718
719 #define HASH_MAX_BLOCK_SIZE             SHA512_BLOCK_SIZE
720 #define TALITOS_MDEU_MAX_CONTEXT_SIZE   TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
721
722 struct talitos_ahash_req_ctx {
723         u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
724         unsigned int hw_context_size;
725         u8 buf[HASH_MAX_BLOCK_SIZE];
726         u8 bufnext[HASH_MAX_BLOCK_SIZE];
727         unsigned int swinit;
728         unsigned int first;
729         unsigned int last;
730         unsigned int to_hash_later;
731         u64 nbuf;
732         struct scatterlist bufsl[2];
733         struct scatterlist *psrc;
734 };
735
736 static int aead_setauthsize(struct crypto_aead *authenc,
737                             unsigned int authsize)
738 {
739         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
740
741         ctx->authsize = authsize;
742
743         return 0;
744 }
745
746 static int aead_setkey(struct crypto_aead *authenc,
747                        const u8 *key, unsigned int keylen)
748 {
749         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
750         struct rtattr *rta = (void *)key;
751         struct crypto_authenc_key_param *param;
752         unsigned int authkeylen;
753         unsigned int enckeylen;
754
755         if (!RTA_OK(rta, keylen))
756                 goto badkey;
757
758         if (rta->rta_type != CRYPTO_AUTHENC_KEYA_PARAM)
759                 goto badkey;
760
761         if (RTA_PAYLOAD(rta) < sizeof(*param))
762                 goto badkey;
763
764         param = RTA_DATA(rta);
765         enckeylen = be32_to_cpu(param->enckeylen);
766
767         key += RTA_ALIGN(rta->rta_len);
768         keylen -= RTA_ALIGN(rta->rta_len);
769
770         if (keylen < enckeylen)
771                 goto badkey;
772
773         authkeylen = keylen - enckeylen;
774
775         if (keylen > TALITOS_MAX_KEY_SIZE)
776                 goto badkey;
777
778         memcpy(&ctx->key, key, keylen);
779
780         ctx->keylen = keylen;
781         ctx->enckeylen = enckeylen;
782         ctx->authkeylen = authkeylen;
783
784         return 0;
785
786 badkey:
787         crypto_aead_set_flags(authenc, CRYPTO_TFM_RES_BAD_KEY_LEN);
788         return -EINVAL;
789 }
790
791 /*
792  * talitos_edesc - s/w-extended descriptor
793  * @src_nents: number of segments in input scatterlist
794  * @dst_nents: number of segments in output scatterlist
795  * @dma_len: length of dma mapped link_tbl space
796  * @dma_link_tbl: bus physical address of link_tbl
797  * @desc: h/w descriptor
798  * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1)
799  *
800  * if decrypting (with authcheck), or either one of src_nents or dst_nents
801  * is greater than 1, an integrity check value is concatenated to the end
802  * of link_tbl data
803  */
804 struct talitos_edesc {
805         int src_nents;
806         int dst_nents;
807         int src_is_chained;
808         int dst_is_chained;
809         int dma_len;
810         dma_addr_t dma_link_tbl;
811         struct talitos_desc desc;
812         struct talitos_ptr link_tbl[0];
813 };
814
815 static int talitos_map_sg(struct device *dev, struct scatterlist *sg,
816                           unsigned int nents, enum dma_data_direction dir,
817                           int chained)
818 {
819         if (unlikely(chained))
820                 while (sg) {
821                         dma_map_sg(dev, sg, 1, dir);
822                         sg = scatterwalk_sg_next(sg);
823                 }
824         else
825                 dma_map_sg(dev, sg, nents, dir);
826         return nents;
827 }
828
829 static void talitos_unmap_sg_chain(struct device *dev, struct scatterlist *sg,
830                                    enum dma_data_direction dir)
831 {
832         while (sg) {
833                 dma_unmap_sg(dev, sg, 1, dir);
834                 sg = scatterwalk_sg_next(sg);
835         }
836 }
837
838 static void talitos_sg_unmap(struct device *dev,
839                              struct talitos_edesc *edesc,
840                              struct scatterlist *src,
841                              struct scatterlist *dst)
842 {
843         unsigned int src_nents = edesc->src_nents ? : 1;
844         unsigned int dst_nents = edesc->dst_nents ? : 1;
845
846         if (src != dst) {
847                 if (edesc->src_is_chained)
848                         talitos_unmap_sg_chain(dev, src, DMA_TO_DEVICE);
849                 else
850                         dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
851
852                 if (dst) {
853                         if (edesc->dst_is_chained)
854                                 talitos_unmap_sg_chain(dev, dst,
855                                                        DMA_FROM_DEVICE);
856                         else
857                                 dma_unmap_sg(dev, dst, dst_nents,
858                                              DMA_FROM_DEVICE);
859                 }
860         } else
861                 if (edesc->src_is_chained)
862                         talitos_unmap_sg_chain(dev, src, DMA_BIDIRECTIONAL);
863                 else
864                         dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
865 }
866
867 static void ipsec_esp_unmap(struct device *dev,
868                             struct talitos_edesc *edesc,
869                             struct aead_request *areq)
870 {
871         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6], DMA_FROM_DEVICE);
872         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[3], DMA_TO_DEVICE);
873         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
874         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[0], DMA_TO_DEVICE);
875
876         dma_unmap_sg(dev, areq->assoc, 1, DMA_TO_DEVICE);
877
878         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
879
880         if (edesc->dma_len)
881                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
882                                  DMA_BIDIRECTIONAL);
883 }
884
885 /*
886  * ipsec_esp descriptor callbacks
887  */
888 static void ipsec_esp_encrypt_done(struct device *dev,
889                                    struct talitos_desc *desc, void *context,
890                                    int err)
891 {
892         struct aead_request *areq = context;
893         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
894         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
895         struct talitos_edesc *edesc;
896         struct scatterlist *sg;
897         void *icvdata;
898
899         edesc = container_of(desc, struct talitos_edesc, desc);
900
901         ipsec_esp_unmap(dev, edesc, areq);
902
903         /* copy the generated ICV to dst */
904         if (edesc->dma_len) {
905                 icvdata = &edesc->link_tbl[edesc->src_nents +
906                                            edesc->dst_nents + 2];
907                 sg = sg_last(areq->dst, edesc->dst_nents);
908                 memcpy((char *)sg_virt(sg) + sg->length - ctx->authsize,
909                        icvdata, ctx->authsize);
910         }
911
912         kfree(edesc);
913
914         aead_request_complete(areq, err);
915 }
916
917 static void ipsec_esp_decrypt_swauth_done(struct device *dev,
918                                           struct talitos_desc *desc,
919                                           void *context, int err)
920 {
921         struct aead_request *req = context;
922         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
923         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
924         struct talitos_edesc *edesc;
925         struct scatterlist *sg;
926         void *icvdata;
927
928         edesc = container_of(desc, struct talitos_edesc, desc);
929
930         ipsec_esp_unmap(dev, edesc, req);
931
932         if (!err) {
933                 /* auth check */
934                 if (edesc->dma_len)
935                         icvdata = &edesc->link_tbl[edesc->src_nents +
936                                                    edesc->dst_nents + 2];
937                 else
938                         icvdata = &edesc->link_tbl[0];
939
940                 sg = sg_last(req->dst, edesc->dst_nents ? : 1);
941                 err = memcmp(icvdata, (char *)sg_virt(sg) + sg->length -
942                              ctx->authsize, ctx->authsize) ? -EBADMSG : 0;
943         }
944
945         kfree(edesc);
946
947         aead_request_complete(req, err);
948 }
949
950 static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
951                                           struct talitos_desc *desc,
952                                           void *context, int err)
953 {
954         struct aead_request *req = context;
955         struct talitos_edesc *edesc;
956
957         edesc = container_of(desc, struct talitos_edesc, desc);
958
959         ipsec_esp_unmap(dev, edesc, req);
960
961         /* check ICV auth status */
962         if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
963                      DESC_HDR_LO_ICCR1_PASS))
964                 err = -EBADMSG;
965
966         kfree(edesc);
967
968         aead_request_complete(req, err);
969 }
970
971 /*
972  * convert scatterlist to SEC h/w link table format
973  * stop at cryptlen bytes
974  */
975 static int sg_to_link_tbl(struct scatterlist *sg, int sg_count,
976                            int cryptlen, struct talitos_ptr *link_tbl_ptr)
977 {
978         int n_sg = sg_count;
979
980         while (n_sg--) {
981                 to_talitos_ptr(link_tbl_ptr, sg_dma_address(sg));
982                 link_tbl_ptr->len = cpu_to_be16(sg_dma_len(sg));
983                 link_tbl_ptr->j_extent = 0;
984                 link_tbl_ptr++;
985                 cryptlen -= sg_dma_len(sg);
986                 sg = scatterwalk_sg_next(sg);
987         }
988
989         /* adjust (decrease) last one (or two) entry's len to cryptlen */
990         link_tbl_ptr--;
991         while (be16_to_cpu(link_tbl_ptr->len) <= (-cryptlen)) {
992                 /* Empty this entry, and move to previous one */
993                 cryptlen += be16_to_cpu(link_tbl_ptr->len);
994                 link_tbl_ptr->len = 0;
995                 sg_count--;
996                 link_tbl_ptr--;
997         }
998         link_tbl_ptr->len = cpu_to_be16(be16_to_cpu(link_tbl_ptr->len)
999                                         + cryptlen);
1000
1001         /* tag end of link table */
1002         link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1003
1004         return sg_count;
1005 }
1006
1007 /*
1008  * fill in and submit ipsec_esp descriptor
1009  */
1010 static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
1011                      u8 *giv, u64 seq,
1012                      void (*callback) (struct device *dev,
1013                                        struct talitos_desc *desc,
1014                                        void *context, int error))
1015 {
1016         struct crypto_aead *aead = crypto_aead_reqtfm(areq);
1017         struct talitos_ctx *ctx = crypto_aead_ctx(aead);
1018         struct device *dev = ctx->dev;
1019         struct talitos_desc *desc = &edesc->desc;
1020         unsigned int cryptlen = areq->cryptlen;
1021         unsigned int authsize = ctx->authsize;
1022         unsigned int ivsize = crypto_aead_ivsize(aead);
1023         int sg_count, ret;
1024         int sg_link_tbl_len;
1025
1026         /* hmac key */
1027         map_single_talitos_ptr(dev, &desc->ptr[0], ctx->authkeylen, &ctx->key,
1028                                0, DMA_TO_DEVICE);
1029         /* hmac data */
1030         map_single_talitos_ptr(dev, &desc->ptr[1], areq->assoclen + ivsize,
1031                                sg_virt(areq->assoc), 0, DMA_TO_DEVICE);
1032         /* cipher iv */
1033         map_single_talitos_ptr(dev, &desc->ptr[2], ivsize, giv ?: areq->iv, 0,
1034                                DMA_TO_DEVICE);
1035
1036         /* cipher key */
1037         map_single_talitos_ptr(dev, &desc->ptr[3], ctx->enckeylen,
1038                                (char *)&ctx->key + ctx->authkeylen, 0,
1039                                DMA_TO_DEVICE);
1040
1041         /*
1042          * cipher in
1043          * map and adjust cipher len to aead request cryptlen.
1044          * extent is bytes of HMAC postpended to ciphertext,
1045          * typically 12 for ipsec
1046          */
1047         desc->ptr[4].len = cpu_to_be16(cryptlen);
1048         desc->ptr[4].j_extent = authsize;
1049
1050         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1051                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1052                                                            : DMA_TO_DEVICE,
1053                                   edesc->src_is_chained);
1054
1055         if (sg_count == 1) {
1056                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->src));
1057         } else {
1058                 sg_link_tbl_len = cryptlen;
1059
1060                 if (edesc->desc.hdr & DESC_HDR_MODE1_MDEU_CICV)
1061                         sg_link_tbl_len = cryptlen + authsize;
1062
1063                 sg_count = sg_to_link_tbl(areq->src, sg_count, sg_link_tbl_len,
1064                                           &edesc->link_tbl[0]);
1065                 if (sg_count > 1) {
1066                         desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1067                         to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl);
1068                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1069                                                    edesc->dma_len,
1070                                                    DMA_BIDIRECTIONAL);
1071                 } else {
1072                         /* Only one segment now, so no link tbl needed */
1073                         to_talitos_ptr(&desc->ptr[4],
1074                                        sg_dma_address(areq->src));
1075                 }
1076         }
1077
1078         /* cipher out */
1079         desc->ptr[5].len = cpu_to_be16(cryptlen);
1080         desc->ptr[5].j_extent = authsize;
1081
1082         if (areq->src != areq->dst)
1083                 sg_count = talitos_map_sg(dev, areq->dst,
1084                                           edesc->dst_nents ? : 1,
1085                                           DMA_FROM_DEVICE,
1086                                           edesc->dst_is_chained);
1087
1088         if (sg_count == 1) {
1089                 to_talitos_ptr(&desc->ptr[5], sg_dma_address(areq->dst));
1090         } else {
1091                 struct talitos_ptr *link_tbl_ptr =
1092                         &edesc->link_tbl[edesc->src_nents + 1];
1093
1094                 to_talitos_ptr(&desc->ptr[5], edesc->dma_link_tbl +
1095                                (edesc->src_nents + 1) *
1096                                sizeof(struct talitos_ptr));
1097                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1098                                           link_tbl_ptr);
1099
1100                 /* Add an entry to the link table for ICV data */
1101                 link_tbl_ptr += sg_count - 1;
1102                 link_tbl_ptr->j_extent = 0;
1103                 sg_count++;
1104                 link_tbl_ptr++;
1105                 link_tbl_ptr->j_extent = DESC_PTR_LNKTBL_RETURN;
1106                 link_tbl_ptr->len = cpu_to_be16(authsize);
1107
1108                 /* icv data follows link tables */
1109                 to_talitos_ptr(link_tbl_ptr, edesc->dma_link_tbl +
1110                                (edesc->src_nents + edesc->dst_nents + 2) *
1111                                sizeof(struct talitos_ptr));
1112                 desc->ptr[5].j_extent |= DESC_PTR_LNKTBL_JUMP;
1113                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1114                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1115         }
1116
1117         /* iv out */
1118         map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv, 0,
1119                                DMA_FROM_DEVICE);
1120
1121         ret = talitos_submit(dev, desc, callback, areq);
1122         if (ret != -EINPROGRESS) {
1123                 ipsec_esp_unmap(dev, edesc, areq);
1124                 kfree(edesc);
1125         }
1126         return ret;
1127 }
1128
1129 /*
1130  * derive number of elements in scatterlist
1131  */
1132 static int sg_count(struct scatterlist *sg_list, int nbytes, int *chained)
1133 {
1134         struct scatterlist *sg = sg_list;
1135         int sg_nents = 0;
1136
1137         *chained = 0;
1138         while (nbytes > 0) {
1139                 sg_nents++;
1140                 nbytes -= sg->length;
1141                 if (!sg_is_last(sg) && (sg + 1)->length == 0)
1142                         *chained = 1;
1143                 sg = scatterwalk_sg_next(sg);
1144         }
1145
1146         return sg_nents;
1147 }
1148
1149 /**
1150  * sg_copy_end_to_buffer - Copy end data from SG list to a linear buffer
1151  * @sgl:                 The SG list
1152  * @nents:               Number of SG entries
1153  * @buf:                 Where to copy to
1154  * @buflen:              The number of bytes to copy
1155  * @skip:                The number of bytes to skip before copying.
1156  *                       Note: skip + buflen should equal SG total size.
1157  *
1158  * Returns the number of copied bytes.
1159  *
1160  **/
1161 static size_t sg_copy_end_to_buffer(struct scatterlist *sgl, unsigned int nents,
1162                                     void *buf, size_t buflen, unsigned int skip)
1163 {
1164         unsigned int offset = 0;
1165         unsigned int boffset = 0;
1166         struct sg_mapping_iter miter;
1167         unsigned long flags;
1168         unsigned int sg_flags = SG_MITER_ATOMIC;
1169         size_t total_buffer = buflen + skip;
1170
1171         sg_flags |= SG_MITER_FROM_SG;
1172
1173         sg_miter_start(&miter, sgl, nents, sg_flags);
1174
1175         local_irq_save(flags);
1176
1177         while (sg_miter_next(&miter) && offset < total_buffer) {
1178                 unsigned int len;
1179                 unsigned int ignore;
1180
1181                 if ((offset + miter.length) > skip) {
1182                         if (offset < skip) {
1183                                 /* Copy part of this segment */
1184                                 ignore = skip - offset;
1185                                 len = miter.length - ignore;
1186                                 memcpy(buf + boffset, miter.addr + ignore, len);
1187                         } else {
1188                                 /* Copy all of this segment */
1189                                 len = miter.length;
1190                                 memcpy(buf + boffset, miter.addr, len);
1191                         }
1192                         boffset += len;
1193                 }
1194                 offset += miter.length;
1195         }
1196
1197         sg_miter_stop(&miter);
1198
1199         local_irq_restore(flags);
1200         return boffset;
1201 }
1202
1203 /*
1204  * allocate and map the extended descriptor
1205  */
1206 static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
1207                                                  struct scatterlist *src,
1208                                                  struct scatterlist *dst,
1209                                                  int hash_result,
1210                                                  unsigned int cryptlen,
1211                                                  unsigned int authsize,
1212                                                  int icv_stashing,
1213                                                  u32 cryptoflags)
1214 {
1215         struct talitos_edesc *edesc;
1216         int src_nents, dst_nents, alloc_len, dma_len;
1217         int src_chained, dst_chained = 0;
1218         gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
1219                       GFP_ATOMIC;
1220
1221         if (cryptlen + authsize > TALITOS_MAX_DATA_LEN) {
1222                 dev_err(dev, "length exceeds h/w max limit\n");
1223                 return ERR_PTR(-EINVAL);
1224         }
1225
1226         src_nents = sg_count(src, cryptlen + authsize, &src_chained);
1227         src_nents = (src_nents == 1) ? 0 : src_nents;
1228
1229         if (hash_result) {
1230                 dst_nents = 0;
1231         } else {
1232                 if (dst == src) {
1233                         dst_nents = src_nents;
1234                 } else {
1235                         dst_nents = sg_count(dst, cryptlen + authsize,
1236                                              &dst_chained);
1237                         dst_nents = (dst_nents == 1) ? 0 : dst_nents;
1238                 }
1239         }
1240
1241         /*
1242          * allocate space for base edesc plus the link tables,
1243          * allowing for two separate entries for ICV and generated ICV (+ 2),
1244          * and the ICV data itself
1245          */
1246         alloc_len = sizeof(struct talitos_edesc);
1247         if (src_nents || dst_nents) {
1248                 dma_len = (src_nents + dst_nents + 2) *
1249                                  sizeof(struct talitos_ptr) + authsize;
1250                 alloc_len += dma_len;
1251         } else {
1252                 dma_len = 0;
1253                 alloc_len += icv_stashing ? authsize : 0;
1254         }
1255
1256         edesc = kmalloc(alloc_len, GFP_DMA | flags);
1257         if (!edesc) {
1258                 dev_err(dev, "could not allocate edescriptor\n");
1259                 return ERR_PTR(-ENOMEM);
1260         }
1261
1262         edesc->src_nents = src_nents;
1263         edesc->dst_nents = dst_nents;
1264         edesc->src_is_chained = src_chained;
1265         edesc->dst_is_chained = dst_chained;
1266         edesc->dma_len = dma_len;
1267         if (dma_len)
1268                 edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
1269                                                      edesc->dma_len,
1270                                                      DMA_BIDIRECTIONAL);
1271
1272         return edesc;
1273 }
1274
1275 static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq,
1276                                               int icv_stashing)
1277 {
1278         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1279         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1280
1281         return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
1282                                    areq->cryptlen, ctx->authsize, icv_stashing,
1283                                    areq->base.flags);
1284 }
1285
1286 static int aead_encrypt(struct aead_request *req)
1287 {
1288         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1289         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1290         struct talitos_edesc *edesc;
1291
1292         /* allocate extended descriptor */
1293         edesc = aead_edesc_alloc(req, 0);
1294         if (IS_ERR(edesc))
1295                 return PTR_ERR(edesc);
1296
1297         /* set encrypt */
1298         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1299
1300         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_encrypt_done);
1301 }
1302
1303 static int aead_decrypt(struct aead_request *req)
1304 {
1305         struct crypto_aead *authenc = crypto_aead_reqtfm(req);
1306         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1307         unsigned int authsize = ctx->authsize;
1308         struct talitos_private *priv = dev_get_drvdata(ctx->dev);
1309         struct talitos_edesc *edesc;
1310         struct scatterlist *sg;
1311         void *icvdata;
1312
1313         req->cryptlen -= authsize;
1314
1315         /* allocate extended descriptor */
1316         edesc = aead_edesc_alloc(req, 1);
1317         if (IS_ERR(edesc))
1318                 return PTR_ERR(edesc);
1319
1320         if ((priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
1321             ((!edesc->src_nents && !edesc->dst_nents) ||
1322              priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
1323
1324                 /* decrypt and check the ICV */
1325                 edesc->desc.hdr = ctx->desc_hdr_template |
1326                                   DESC_HDR_DIR_INBOUND |
1327                                   DESC_HDR_MODE1_MDEU_CICV;
1328
1329                 /* reset integrity check result bits */
1330                 edesc->desc.hdr_lo = 0;
1331
1332                 return ipsec_esp(edesc, req, NULL, 0,
1333                                  ipsec_esp_decrypt_hwauth_done);
1334
1335         }
1336
1337         /* Have to check the ICV with software */
1338         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1339
1340         /* stash incoming ICV for later cmp with ICV generated by the h/w */
1341         if (edesc->dma_len)
1342                 icvdata = &edesc->link_tbl[edesc->src_nents +
1343                                            edesc->dst_nents + 2];
1344         else
1345                 icvdata = &edesc->link_tbl[0];
1346
1347         sg = sg_last(req->src, edesc->src_nents ? : 1);
1348
1349         memcpy(icvdata, (char *)sg_virt(sg) + sg->length - ctx->authsize,
1350                ctx->authsize);
1351
1352         return ipsec_esp(edesc, req, NULL, 0, ipsec_esp_decrypt_swauth_done);
1353 }
1354
1355 static int aead_givencrypt(struct aead_givcrypt_request *req)
1356 {
1357         struct aead_request *areq = &req->areq;
1358         struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
1359         struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
1360         struct talitos_edesc *edesc;
1361
1362         /* allocate extended descriptor */
1363         edesc = aead_edesc_alloc(areq, 0);
1364         if (IS_ERR(edesc))
1365                 return PTR_ERR(edesc);
1366
1367         /* set encrypt */
1368         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1369
1370         memcpy(req->giv, ctx->iv, crypto_aead_ivsize(authenc));
1371         /* avoid consecutive packets going out with same IV */
1372         *(__be64 *)req->giv ^= cpu_to_be64(req->seq);
1373
1374         return ipsec_esp(edesc, areq, req->giv, req->seq,
1375                          ipsec_esp_encrypt_done);
1376 }
1377
1378 static int ablkcipher_setkey(struct crypto_ablkcipher *cipher,
1379                              const u8 *key, unsigned int keylen)
1380 {
1381         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1382         struct ablkcipher_alg *alg = crypto_ablkcipher_alg(cipher);
1383
1384         if (keylen > TALITOS_MAX_KEY_SIZE)
1385                 goto badkey;
1386
1387         if (keylen < alg->min_keysize || keylen > alg->max_keysize)
1388                 goto badkey;
1389
1390         memcpy(&ctx->key, key, keylen);
1391         ctx->keylen = keylen;
1392
1393         return 0;
1394
1395 badkey:
1396         crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
1397         return -EINVAL;
1398 }
1399
1400 static void common_nonsnoop_unmap(struct device *dev,
1401                                   struct talitos_edesc *edesc,
1402                                   struct ablkcipher_request *areq)
1403 {
1404         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1405         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2], DMA_TO_DEVICE);
1406         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
1407
1408         talitos_sg_unmap(dev, edesc, areq->src, areq->dst);
1409
1410         if (edesc->dma_len)
1411                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1412                                  DMA_BIDIRECTIONAL);
1413 }
1414
1415 static void ablkcipher_done(struct device *dev,
1416                             struct talitos_desc *desc, void *context,
1417                             int err)
1418 {
1419         struct ablkcipher_request *areq = context;
1420         struct talitos_edesc *edesc;
1421
1422         edesc = container_of(desc, struct talitos_edesc, desc);
1423
1424         common_nonsnoop_unmap(dev, edesc, areq);
1425
1426         kfree(edesc);
1427
1428         areq->base.complete(&areq->base, err);
1429 }
1430
1431 static int common_nonsnoop(struct talitos_edesc *edesc,
1432                            struct ablkcipher_request *areq,
1433                            u8 *giv,
1434                            void (*callback) (struct device *dev,
1435                                              struct talitos_desc *desc,
1436                                              void *context, int error))
1437 {
1438         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1439         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1440         struct device *dev = ctx->dev;
1441         struct talitos_desc *desc = &edesc->desc;
1442         unsigned int cryptlen = areq->nbytes;
1443         unsigned int ivsize;
1444         int sg_count, ret;
1445
1446         /* first DWORD empty */
1447         desc->ptr[0].len = 0;
1448         to_talitos_ptr(&desc->ptr[0], 0);
1449         desc->ptr[0].j_extent = 0;
1450
1451         /* cipher iv */
1452         ivsize = crypto_ablkcipher_ivsize(cipher);
1453         map_single_talitos_ptr(dev, &desc->ptr[1], ivsize, giv ?: areq->info, 0,
1454                                DMA_TO_DEVICE);
1455
1456         /* cipher key */
1457         map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1458                                (char *)&ctx->key, 0, DMA_TO_DEVICE);
1459
1460         /*
1461          * cipher in
1462          */
1463         desc->ptr[3].len = cpu_to_be16(cryptlen);
1464         desc->ptr[3].j_extent = 0;
1465
1466         sg_count = talitos_map_sg(dev, areq->src, edesc->src_nents ? : 1,
1467                                   (areq->src == areq->dst) ? DMA_BIDIRECTIONAL
1468                                                            : DMA_TO_DEVICE,
1469                                   edesc->src_is_chained);
1470
1471         if (sg_count == 1) {
1472                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(areq->src));
1473         } else {
1474                 sg_count = sg_to_link_tbl(areq->src, sg_count, cryptlen,
1475                                           &edesc->link_tbl[0]);
1476                 if (sg_count > 1) {
1477                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1478                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1479                         dma_sync_single_for_device(dev, edesc->dma_link_tbl,
1480                                                    edesc->dma_len,
1481                                                    DMA_BIDIRECTIONAL);
1482                 } else {
1483                         /* Only one segment now, so no link tbl needed */
1484                         to_talitos_ptr(&desc->ptr[3],
1485                                        sg_dma_address(areq->src));
1486                 }
1487         }
1488
1489         /* cipher out */
1490         desc->ptr[4].len = cpu_to_be16(cryptlen);
1491         desc->ptr[4].j_extent = 0;
1492
1493         if (areq->src != areq->dst)
1494                 sg_count = talitos_map_sg(dev, areq->dst,
1495                                           edesc->dst_nents ? : 1,
1496                                           DMA_FROM_DEVICE,
1497                                           edesc->dst_is_chained);
1498
1499         if (sg_count == 1) {
1500                 to_talitos_ptr(&desc->ptr[4], sg_dma_address(areq->dst));
1501         } else {
1502                 struct talitos_ptr *link_tbl_ptr =
1503                         &edesc->link_tbl[edesc->src_nents + 1];
1504
1505                 to_talitos_ptr(&desc->ptr[4], edesc->dma_link_tbl +
1506                                               (edesc->src_nents + 1) *
1507                                               sizeof(struct talitos_ptr));
1508                 desc->ptr[4].j_extent |= DESC_PTR_LNKTBL_JUMP;
1509                 sg_count = sg_to_link_tbl(areq->dst, sg_count, cryptlen,
1510                                           link_tbl_ptr);
1511                 dma_sync_single_for_device(ctx->dev, edesc->dma_link_tbl,
1512                                            edesc->dma_len, DMA_BIDIRECTIONAL);
1513         }
1514
1515         /* iv out */
1516         map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv, 0,
1517                                DMA_FROM_DEVICE);
1518
1519         /* last DWORD empty */
1520         desc->ptr[6].len = 0;
1521         to_talitos_ptr(&desc->ptr[6], 0);
1522         desc->ptr[6].j_extent = 0;
1523
1524         ret = talitos_submit(dev, desc, callback, areq);
1525         if (ret != -EINPROGRESS) {
1526                 common_nonsnoop_unmap(dev, edesc, areq);
1527                 kfree(edesc);
1528         }
1529         return ret;
1530 }
1531
1532 static struct talitos_edesc *ablkcipher_edesc_alloc(struct ablkcipher_request *
1533                                                     areq)
1534 {
1535         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1536         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1537
1538         return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst, 0,
1539                                    areq->nbytes, 0, 0, areq->base.flags);
1540 }
1541
1542 static int ablkcipher_encrypt(struct ablkcipher_request *areq)
1543 {
1544         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1545         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1546         struct talitos_edesc *edesc;
1547
1548         /* allocate extended descriptor */
1549         edesc = ablkcipher_edesc_alloc(areq);
1550         if (IS_ERR(edesc))
1551                 return PTR_ERR(edesc);
1552
1553         /* set encrypt */
1554         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
1555
1556         return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1557 }
1558
1559 static int ablkcipher_decrypt(struct ablkcipher_request *areq)
1560 {
1561         struct crypto_ablkcipher *cipher = crypto_ablkcipher_reqtfm(areq);
1562         struct talitos_ctx *ctx = crypto_ablkcipher_ctx(cipher);
1563         struct talitos_edesc *edesc;
1564
1565         /* allocate extended descriptor */
1566         edesc = ablkcipher_edesc_alloc(areq);
1567         if (IS_ERR(edesc))
1568                 return PTR_ERR(edesc);
1569
1570         edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
1571
1572         return common_nonsnoop(edesc, areq, NULL, ablkcipher_done);
1573 }
1574
1575 static void common_nonsnoop_hash_unmap(struct device *dev,
1576                                        struct talitos_edesc *edesc,
1577                                        struct ahash_request *areq)
1578 {
1579         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1580
1581         unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
1582
1583         /* When using hashctx-in, must unmap it. */
1584         if (edesc->desc.ptr[1].len)
1585                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
1586                                          DMA_TO_DEVICE);
1587
1588         if (edesc->desc.ptr[2].len)
1589                 unmap_single_talitos_ptr(dev, &edesc->desc.ptr[2],
1590                                          DMA_TO_DEVICE);
1591
1592         talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL);
1593
1594         if (edesc->dma_len)
1595                 dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
1596                                  DMA_BIDIRECTIONAL);
1597
1598 }
1599
1600 static void ahash_done(struct device *dev,
1601                        struct talitos_desc *desc, void *context,
1602                        int err)
1603 {
1604         struct ahash_request *areq = context;
1605         struct talitos_edesc *edesc =
1606                  container_of(desc, struct talitos_edesc, desc);
1607         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1608
1609         if (!req_ctx->last && req_ctx->to_hash_later) {
1610                 /* Position any partial block for next update/final/finup */
1611                 memcpy(req_ctx->buf, req_ctx->bufnext, req_ctx->to_hash_later);
1612                 req_ctx->nbuf = req_ctx->to_hash_later;
1613         }
1614         common_nonsnoop_hash_unmap(dev, edesc, areq);
1615
1616         kfree(edesc);
1617
1618         areq->base.complete(&areq->base, err);
1619 }
1620
1621 static int common_nonsnoop_hash(struct talitos_edesc *edesc,
1622                                 struct ahash_request *areq, unsigned int length,
1623                                 void (*callback) (struct device *dev,
1624                                                   struct talitos_desc *desc,
1625                                                   void *context, int error))
1626 {
1627         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1628         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1629         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1630         struct device *dev = ctx->dev;
1631         struct talitos_desc *desc = &edesc->desc;
1632         int sg_count, ret;
1633
1634         /* first DWORD empty */
1635         desc->ptr[0] = zero_entry;
1636
1637         /* hash context in */
1638         if (!req_ctx->first || req_ctx->swinit) {
1639                 map_single_talitos_ptr(dev, &desc->ptr[1],
1640                                        req_ctx->hw_context_size,
1641                                        (char *)req_ctx->hw_context, 0,
1642                                        DMA_TO_DEVICE);
1643                 req_ctx->swinit = 0;
1644         } else {
1645                 desc->ptr[1] = zero_entry;
1646                 /* Indicate next op is not the first. */
1647                 req_ctx->first = 0;
1648         }
1649
1650         /* HMAC key */
1651         if (ctx->keylen)
1652                 map_single_talitos_ptr(dev, &desc->ptr[2], ctx->keylen,
1653                                        (char *)&ctx->key, 0, DMA_TO_DEVICE);
1654         else
1655                 desc->ptr[2] = zero_entry;
1656
1657         /*
1658          * data in
1659          */
1660         desc->ptr[3].len = cpu_to_be16(length);
1661         desc->ptr[3].j_extent = 0;
1662
1663         sg_count = talitos_map_sg(dev, req_ctx->psrc,
1664                                   edesc->src_nents ? : 1,
1665                                   DMA_TO_DEVICE,
1666                                   edesc->src_is_chained);
1667
1668         if (sg_count == 1) {
1669                 to_talitos_ptr(&desc->ptr[3], sg_dma_address(req_ctx->psrc));
1670         } else {
1671                 sg_count = sg_to_link_tbl(req_ctx->psrc, sg_count, length,
1672                                           &edesc->link_tbl[0]);
1673                 if (sg_count > 1) {
1674                         desc->ptr[3].j_extent |= DESC_PTR_LNKTBL_JUMP;
1675                         to_talitos_ptr(&desc->ptr[3], edesc->dma_link_tbl);
1676                         dma_sync_single_for_device(ctx->dev,
1677                                                    edesc->dma_link_tbl,
1678                                                    edesc->dma_len,
1679                                                    DMA_BIDIRECTIONAL);
1680                 } else {
1681                         /* Only one segment now, so no link tbl needed */
1682                         to_talitos_ptr(&desc->ptr[3],
1683                                        sg_dma_address(req_ctx->psrc));
1684                 }
1685         }
1686
1687         /* fifth DWORD empty */
1688         desc->ptr[4] = zero_entry;
1689
1690         /* hash/HMAC out -or- hash context out */
1691         if (req_ctx->last)
1692                 map_single_talitos_ptr(dev, &desc->ptr[5],
1693                                        crypto_ahash_digestsize(tfm),
1694                                        areq->result, 0, DMA_FROM_DEVICE);
1695         else
1696                 map_single_talitos_ptr(dev, &desc->ptr[5],
1697                                        req_ctx->hw_context_size,
1698                                        req_ctx->hw_context, 0, DMA_FROM_DEVICE);
1699
1700         /* last DWORD empty */
1701         desc->ptr[6] = zero_entry;
1702
1703         ret = talitos_submit(dev, desc, callback, areq);
1704         if (ret != -EINPROGRESS) {
1705                 common_nonsnoop_hash_unmap(dev, edesc, areq);
1706                 kfree(edesc);
1707         }
1708         return ret;
1709 }
1710
1711 static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
1712                                                unsigned int nbytes)
1713 {
1714         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1715         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1716         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1717
1718         return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, 1,
1719                                    nbytes, 0, 0, areq->base.flags);
1720 }
1721
1722 static int ahash_init(struct ahash_request *areq)
1723 {
1724         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1725         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1726
1727         /* Initialize the context */
1728         req_ctx->nbuf = 0;
1729         req_ctx->first = 1; /* first indicates h/w must init its context */
1730         req_ctx->swinit = 0; /* assume h/w init of context */
1731         req_ctx->hw_context_size =
1732                 (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
1733                         ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
1734                         : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
1735
1736         return 0;
1737 }
1738
1739 /*
1740  * on h/w without explicit sha224 support, we initialize h/w context
1741  * manually with sha224 constants, and tell it to run sha256.
1742  */
1743 static int ahash_init_sha224_swinit(struct ahash_request *areq)
1744 {
1745         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1746
1747         ahash_init(areq);
1748         req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
1749
1750         req_ctx->hw_context[0] = cpu_to_be32(SHA224_H0);
1751         req_ctx->hw_context[1] = cpu_to_be32(SHA224_H1);
1752         req_ctx->hw_context[2] = cpu_to_be32(SHA224_H2);
1753         req_ctx->hw_context[3] = cpu_to_be32(SHA224_H3);
1754         req_ctx->hw_context[4] = cpu_to_be32(SHA224_H4);
1755         req_ctx->hw_context[5] = cpu_to_be32(SHA224_H5);
1756         req_ctx->hw_context[6] = cpu_to_be32(SHA224_H6);
1757         req_ctx->hw_context[7] = cpu_to_be32(SHA224_H7);
1758
1759         /* init 64-bit count */
1760         req_ctx->hw_context[8] = 0;
1761         req_ctx->hw_context[9] = 0;
1762
1763         return 0;
1764 }
1765
1766 static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
1767 {
1768         struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
1769         struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
1770         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1771         struct talitos_edesc *edesc;
1772         unsigned int blocksize =
1773                         crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
1774         unsigned int nbytes_to_hash;
1775         unsigned int to_hash_later;
1776         unsigned int nsg;
1777         int chained;
1778
1779         if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
1780                 /* Buffer up to one whole block */
1781                 sg_copy_to_buffer(areq->src,
1782                                   sg_count(areq->src, nbytes, &chained),
1783                                   req_ctx->buf + req_ctx->nbuf, nbytes);
1784                 req_ctx->nbuf += nbytes;
1785                 return 0;
1786         }
1787
1788         /* At least (blocksize + 1) bytes are available to hash */
1789         nbytes_to_hash = nbytes + req_ctx->nbuf;
1790         to_hash_later = nbytes_to_hash & (blocksize - 1);
1791
1792         if (req_ctx->last)
1793                 to_hash_later = 0;
1794         else if (to_hash_later)
1795                 /* There is a partial block. Hash the full block(s) now */
1796                 nbytes_to_hash -= to_hash_later;
1797         else {
1798                 /* Keep one block buffered */
1799                 nbytes_to_hash -= blocksize;
1800                 to_hash_later = blocksize;
1801         }
1802
1803         /* Chain in any previously buffered data */
1804         if (req_ctx->nbuf) {
1805                 nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
1806                 sg_init_table(req_ctx->bufsl, nsg);
1807                 sg_set_buf(req_ctx->bufsl, req_ctx->buf, req_ctx->nbuf);
1808                 if (nsg > 1)
1809                         scatterwalk_sg_chain(req_ctx->bufsl, 2, areq->src);
1810                 req_ctx->psrc = req_ctx->bufsl;
1811         } else
1812                 req_ctx->psrc = areq->src;
1813
1814         if (to_hash_later) {
1815                 int nents = sg_count(areq->src, nbytes, &chained);
1816                 sg_copy_end_to_buffer(areq->src, nents,
1817                                       req_ctx->bufnext,
1818                                       to_hash_later,
1819                                       nbytes - to_hash_later);
1820         }
1821         req_ctx->to_hash_later = to_hash_later;
1822
1823         /* Allocate extended descriptor */
1824         edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
1825         if (IS_ERR(edesc))
1826                 return PTR_ERR(edesc);
1827
1828         edesc->desc.hdr = ctx->desc_hdr_template;
1829
1830         /* On last one, request SEC to pad; otherwise continue */
1831         if (req_ctx->last)
1832                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
1833         else
1834                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
1835
1836         /* request SEC to INIT hash. */
1837         if (req_ctx->first && !req_ctx->swinit)
1838                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
1839
1840         /* When the tfm context has a keylen, it's an HMAC.
1841          * A first or last (ie. not middle) descriptor must request HMAC.
1842          */
1843         if (ctx->keylen && (req_ctx->first || req_ctx->last))
1844                 edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
1845
1846         return common_nonsnoop_hash(edesc, areq, nbytes_to_hash,
1847                                     ahash_done);
1848 }
1849
1850 static int ahash_update(struct ahash_request *areq)
1851 {
1852         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1853
1854         req_ctx->last = 0;
1855
1856         return ahash_process_req(areq, areq->nbytes);
1857 }
1858
1859 static int ahash_final(struct ahash_request *areq)
1860 {
1861         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1862
1863         req_ctx->last = 1;
1864
1865         return ahash_process_req(areq, 0);
1866 }
1867
1868 static int ahash_finup(struct ahash_request *areq)
1869 {
1870         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1871
1872         req_ctx->last = 1;
1873
1874         return ahash_process_req(areq, areq->nbytes);
1875 }
1876
1877 static int ahash_digest(struct ahash_request *areq)
1878 {
1879         struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
1880         struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
1881
1882         ahash->init(areq);
1883         req_ctx->last = 1;
1884
1885         return ahash_process_req(areq, areq->nbytes);
1886 }
1887
1888 struct talitos_alg_template {
1889         u32 type;
1890         union {
1891                 struct crypto_alg crypto;
1892                 struct ahash_alg hash;
1893         } alg;
1894         __be32 desc_hdr_template;
1895 };
1896
1897 static struct talitos_alg_template driver_algs[] = {
1898         /* AEAD algorithms.  These use a single-pass ipsec_esp descriptor */
1899         {       .type = CRYPTO_ALG_TYPE_AEAD,
1900                 .alg.crypto = {
1901                         .cra_name = "authenc(hmac(sha1),cbc(aes))",
1902                         .cra_driver_name = "authenc-hmac-sha1-cbc-aes-talitos",
1903                         .cra_blocksize = AES_BLOCK_SIZE,
1904                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1905                         .cra_type = &crypto_aead_type,
1906                         .cra_aead = {
1907                                 .setkey = aead_setkey,
1908                                 .setauthsize = aead_setauthsize,
1909                                 .encrypt = aead_encrypt,
1910                                 .decrypt = aead_decrypt,
1911                                 .givencrypt = aead_givencrypt,
1912                                 .geniv = "<built-in>",
1913                                 .ivsize = AES_BLOCK_SIZE,
1914                                 .maxauthsize = SHA1_DIGEST_SIZE,
1915                         }
1916                 },
1917                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1918                                      DESC_HDR_SEL0_AESU |
1919                                      DESC_HDR_MODE0_AESU_CBC |
1920                                      DESC_HDR_SEL1_MDEUA |
1921                                      DESC_HDR_MODE1_MDEU_INIT |
1922                                      DESC_HDR_MODE1_MDEU_PAD |
1923                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1924         },
1925         {       .type = CRYPTO_ALG_TYPE_AEAD,
1926                 .alg.crypto = {
1927                         .cra_name = "authenc(hmac(sha1),cbc(des3_ede))",
1928                         .cra_driver_name = "authenc-hmac-sha1-cbc-3des-talitos",
1929                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1930                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1931                         .cra_type = &crypto_aead_type,
1932                         .cra_aead = {
1933                                 .setkey = aead_setkey,
1934                                 .setauthsize = aead_setauthsize,
1935                                 .encrypt = aead_encrypt,
1936                                 .decrypt = aead_decrypt,
1937                                 .givencrypt = aead_givencrypt,
1938                                 .geniv = "<built-in>",
1939                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1940                                 .maxauthsize = SHA1_DIGEST_SIZE,
1941                         }
1942                 },
1943                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1944                                      DESC_HDR_SEL0_DEU |
1945                                      DESC_HDR_MODE0_DEU_CBC |
1946                                      DESC_HDR_MODE0_DEU_3DES |
1947                                      DESC_HDR_SEL1_MDEUA |
1948                                      DESC_HDR_MODE1_MDEU_INIT |
1949                                      DESC_HDR_MODE1_MDEU_PAD |
1950                                      DESC_HDR_MODE1_MDEU_SHA1_HMAC,
1951         },
1952         {       .type = CRYPTO_ALG_TYPE_AEAD,
1953                 .alg.crypto = {
1954                         .cra_name = "authenc(hmac(sha256),cbc(aes))",
1955                         .cra_driver_name = "authenc-hmac-sha256-cbc-aes-talitos",
1956                         .cra_blocksize = AES_BLOCK_SIZE,
1957                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1958                         .cra_type = &crypto_aead_type,
1959                         .cra_aead = {
1960                                 .setkey = aead_setkey,
1961                                 .setauthsize = aead_setauthsize,
1962                                 .encrypt = aead_encrypt,
1963                                 .decrypt = aead_decrypt,
1964                                 .givencrypt = aead_givencrypt,
1965                                 .geniv = "<built-in>",
1966                                 .ivsize = AES_BLOCK_SIZE,
1967                                 .maxauthsize = SHA256_DIGEST_SIZE,
1968                         }
1969                 },
1970                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1971                                      DESC_HDR_SEL0_AESU |
1972                                      DESC_HDR_MODE0_AESU_CBC |
1973                                      DESC_HDR_SEL1_MDEUA |
1974                                      DESC_HDR_MODE1_MDEU_INIT |
1975                                      DESC_HDR_MODE1_MDEU_PAD |
1976                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
1977         },
1978         {       .type = CRYPTO_ALG_TYPE_AEAD,
1979                 .alg.crypto = {
1980                         .cra_name = "authenc(hmac(sha256),cbc(des3_ede))",
1981                         .cra_driver_name = "authenc-hmac-sha256-cbc-3des-talitos",
1982                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
1983                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
1984                         .cra_type = &crypto_aead_type,
1985                         .cra_aead = {
1986                                 .setkey = aead_setkey,
1987                                 .setauthsize = aead_setauthsize,
1988                                 .encrypt = aead_encrypt,
1989                                 .decrypt = aead_decrypt,
1990                                 .givencrypt = aead_givencrypt,
1991                                 .geniv = "<built-in>",
1992                                 .ivsize = DES3_EDE_BLOCK_SIZE,
1993                                 .maxauthsize = SHA256_DIGEST_SIZE,
1994                         }
1995                 },
1996                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
1997                                      DESC_HDR_SEL0_DEU |
1998                                      DESC_HDR_MODE0_DEU_CBC |
1999                                      DESC_HDR_MODE0_DEU_3DES |
2000                                      DESC_HDR_SEL1_MDEUA |
2001                                      DESC_HDR_MODE1_MDEU_INIT |
2002                                      DESC_HDR_MODE1_MDEU_PAD |
2003                                      DESC_HDR_MODE1_MDEU_SHA256_HMAC,
2004         },
2005         {       .type = CRYPTO_ALG_TYPE_AEAD,
2006                 .alg.crypto = {
2007                         .cra_name = "authenc(hmac(md5),cbc(aes))",
2008                         .cra_driver_name = "authenc-hmac-md5-cbc-aes-talitos",
2009                         .cra_blocksize = AES_BLOCK_SIZE,
2010                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2011                         .cra_type = &crypto_aead_type,
2012                         .cra_aead = {
2013                                 .setkey = aead_setkey,
2014                                 .setauthsize = aead_setauthsize,
2015                                 .encrypt = aead_encrypt,
2016                                 .decrypt = aead_decrypt,
2017                                 .givencrypt = aead_givencrypt,
2018                                 .geniv = "<built-in>",
2019                                 .ivsize = AES_BLOCK_SIZE,
2020                                 .maxauthsize = MD5_DIGEST_SIZE,
2021                         }
2022                 },
2023                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2024                                      DESC_HDR_SEL0_AESU |
2025                                      DESC_HDR_MODE0_AESU_CBC |
2026                                      DESC_HDR_SEL1_MDEUA |
2027                                      DESC_HDR_MODE1_MDEU_INIT |
2028                                      DESC_HDR_MODE1_MDEU_PAD |
2029                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2030         },
2031         {       .type = CRYPTO_ALG_TYPE_AEAD,
2032                 .alg.crypto = {
2033                         .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
2034                         .cra_driver_name = "authenc-hmac-md5-cbc-3des-talitos",
2035                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2036                         .cra_flags = CRYPTO_ALG_TYPE_AEAD | CRYPTO_ALG_ASYNC,
2037                         .cra_type = &crypto_aead_type,
2038                         .cra_aead = {
2039                                 .setkey = aead_setkey,
2040                                 .setauthsize = aead_setauthsize,
2041                                 .encrypt = aead_encrypt,
2042                                 .decrypt = aead_decrypt,
2043                                 .givencrypt = aead_givencrypt,
2044                                 .geniv = "<built-in>",
2045                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2046                                 .maxauthsize = MD5_DIGEST_SIZE,
2047                         }
2048                 },
2049                 .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
2050                                      DESC_HDR_SEL0_DEU |
2051                                      DESC_HDR_MODE0_DEU_CBC |
2052                                      DESC_HDR_MODE0_DEU_3DES |
2053                                      DESC_HDR_SEL1_MDEUA |
2054                                      DESC_HDR_MODE1_MDEU_INIT |
2055                                      DESC_HDR_MODE1_MDEU_PAD |
2056                                      DESC_HDR_MODE1_MDEU_MD5_HMAC,
2057         },
2058         /* ABLKCIPHER algorithms. */
2059         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2060                 .alg.crypto = {
2061                         .cra_name = "cbc(aes)",
2062                         .cra_driver_name = "cbc-aes-talitos",
2063                         .cra_blocksize = AES_BLOCK_SIZE,
2064                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2065                                      CRYPTO_ALG_ASYNC,
2066                         .cra_type = &crypto_ablkcipher_type,
2067                         .cra_ablkcipher = {
2068                                 .setkey = ablkcipher_setkey,
2069                                 .encrypt = ablkcipher_encrypt,
2070                                 .decrypt = ablkcipher_decrypt,
2071                                 .geniv = "eseqiv",
2072                                 .min_keysize = AES_MIN_KEY_SIZE,
2073                                 .max_keysize = AES_MAX_KEY_SIZE,
2074                                 .ivsize = AES_BLOCK_SIZE,
2075                         }
2076                 },
2077                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2078                                      DESC_HDR_SEL0_AESU |
2079                                      DESC_HDR_MODE0_AESU_CBC,
2080         },
2081         {       .type = CRYPTO_ALG_TYPE_ABLKCIPHER,
2082                 .alg.crypto = {
2083                         .cra_name = "cbc(des3_ede)",
2084                         .cra_driver_name = "cbc-3des-talitos",
2085                         .cra_blocksize = DES3_EDE_BLOCK_SIZE,
2086                         .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
2087                                      CRYPTO_ALG_ASYNC,
2088                         .cra_type = &crypto_ablkcipher_type,
2089                         .cra_ablkcipher = {
2090                                 .setkey = ablkcipher_setkey,
2091                                 .encrypt = ablkcipher_encrypt,
2092                                 .decrypt = ablkcipher_decrypt,
2093                                 .geniv = "eseqiv",
2094                                 .min_keysize = DES3_EDE_KEY_SIZE,
2095                                 .max_keysize = DES3_EDE_KEY_SIZE,
2096                                 .ivsize = DES3_EDE_BLOCK_SIZE,
2097                         }
2098                 },
2099                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2100                                      DESC_HDR_SEL0_DEU |
2101                                      DESC_HDR_MODE0_DEU_CBC |
2102                                      DESC_HDR_MODE0_DEU_3DES,
2103         },
2104         /* AHASH algorithms. */
2105         {       .type = CRYPTO_ALG_TYPE_AHASH,
2106                 .alg.hash = {
2107                         .init = ahash_init,
2108                         .update = ahash_update,
2109                         .final = ahash_final,
2110                         .finup = ahash_finup,
2111                         .digest = ahash_digest,
2112                         .halg.digestsize = MD5_DIGEST_SIZE,
2113                         .halg.base = {
2114                                 .cra_name = "md5",
2115                                 .cra_driver_name = "md5-talitos",
2116                                 .cra_blocksize = MD5_BLOCK_SIZE,
2117                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2118                                              CRYPTO_ALG_ASYNC,
2119                                 .cra_type = &crypto_ahash_type
2120                         }
2121                 },
2122                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2123                                      DESC_HDR_SEL0_MDEUA |
2124                                      DESC_HDR_MODE0_MDEU_MD5,
2125         },
2126         {       .type = CRYPTO_ALG_TYPE_AHASH,
2127                 .alg.hash = {
2128                         .init = ahash_init,
2129                         .update = ahash_update,
2130                         .final = ahash_final,
2131                         .finup = ahash_finup,
2132                         .digest = ahash_digest,
2133                         .halg.digestsize = SHA1_DIGEST_SIZE,
2134                         .halg.base = {
2135                                 .cra_name = "sha1",
2136                                 .cra_driver_name = "sha1-talitos",
2137                                 .cra_blocksize = SHA1_BLOCK_SIZE,
2138                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2139                                              CRYPTO_ALG_ASYNC,
2140                                 .cra_type = &crypto_ahash_type
2141                         }
2142                 },
2143                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2144                                      DESC_HDR_SEL0_MDEUA |
2145                                      DESC_HDR_MODE0_MDEU_SHA1,
2146         },
2147         {       .type = CRYPTO_ALG_TYPE_AHASH,
2148                 .alg.hash = {
2149                         .init = ahash_init,
2150                         .update = ahash_update,
2151                         .final = ahash_final,
2152                         .finup = ahash_finup,
2153                         .digest = ahash_digest,
2154                         .halg.digestsize = SHA224_DIGEST_SIZE,
2155                         .halg.base = {
2156                                 .cra_name = "sha224",
2157                                 .cra_driver_name = "sha224-talitos",
2158                                 .cra_blocksize = SHA224_BLOCK_SIZE,
2159                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2160                                              CRYPTO_ALG_ASYNC,
2161                                 .cra_type = &crypto_ahash_type
2162                         }
2163                 },
2164                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2165                                      DESC_HDR_SEL0_MDEUA |
2166                                      DESC_HDR_MODE0_MDEU_SHA224,
2167         },
2168         {       .type = CRYPTO_ALG_TYPE_AHASH,
2169                 .alg.hash = {
2170                         .init = ahash_init,
2171                         .update = ahash_update,
2172                         .final = ahash_final,
2173                         .finup = ahash_finup,
2174                         .digest = ahash_digest,
2175                         .halg.digestsize = SHA256_DIGEST_SIZE,
2176                         .halg.base = {
2177                                 .cra_name = "sha256",
2178                                 .cra_driver_name = "sha256-talitos",
2179                                 .cra_blocksize = SHA256_BLOCK_SIZE,
2180                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2181                                              CRYPTO_ALG_ASYNC,
2182                                 .cra_type = &crypto_ahash_type
2183                         }
2184                 },
2185                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2186                                      DESC_HDR_SEL0_MDEUA |
2187                                      DESC_HDR_MODE0_MDEU_SHA256,
2188         },
2189         {       .type = CRYPTO_ALG_TYPE_AHASH,
2190                 .alg.hash = {
2191                         .init = ahash_init,
2192                         .update = ahash_update,
2193                         .final = ahash_final,
2194                         .finup = ahash_finup,
2195                         .digest = ahash_digest,
2196                         .halg.digestsize = SHA384_DIGEST_SIZE,
2197                         .halg.base = {
2198                                 .cra_name = "sha384",
2199                                 .cra_driver_name = "sha384-talitos",
2200                                 .cra_blocksize = SHA384_BLOCK_SIZE,
2201                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2202                                              CRYPTO_ALG_ASYNC,
2203                                 .cra_type = &crypto_ahash_type
2204                         }
2205                 },
2206                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2207                                      DESC_HDR_SEL0_MDEUB |
2208                                      DESC_HDR_MODE0_MDEUB_SHA384,
2209         },
2210         {       .type = CRYPTO_ALG_TYPE_AHASH,
2211                 .alg.hash = {
2212                         .init = ahash_init,
2213                         .update = ahash_update,
2214                         .final = ahash_final,
2215                         .finup = ahash_finup,
2216                         .digest = ahash_digest,
2217                         .halg.digestsize = SHA512_DIGEST_SIZE,
2218                         .halg.base = {
2219                                 .cra_name = "sha512",
2220                                 .cra_driver_name = "sha512-talitos",
2221                                 .cra_blocksize = SHA512_BLOCK_SIZE,
2222                                 .cra_flags = CRYPTO_ALG_TYPE_AHASH |
2223                                              CRYPTO_ALG_ASYNC,
2224                                 .cra_type = &crypto_ahash_type
2225                         }
2226                 },
2227                 .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2228                                      DESC_HDR_SEL0_MDEUB |
2229                                      DESC_HDR_MODE0_MDEUB_SHA512,
2230         },
2231 };
2232
2233 struct talitos_crypto_alg {
2234         struct list_head entry;
2235         struct device *dev;
2236         struct talitos_alg_template algt;
2237 };
2238
2239 static int talitos_cra_init(struct crypto_tfm *tfm)
2240 {
2241         struct crypto_alg *alg = tfm->__crt_alg;
2242         struct talitos_crypto_alg *talitos_alg;
2243         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2244
2245         if ((alg->cra_flags & CRYPTO_ALG_TYPE_MASK) == CRYPTO_ALG_TYPE_AHASH)
2246                 talitos_alg = container_of(__crypto_ahash_alg(alg),
2247                                            struct talitos_crypto_alg,
2248                                            algt.alg.hash);
2249         else
2250                 talitos_alg = container_of(alg, struct talitos_crypto_alg,
2251                                            algt.alg.crypto);
2252
2253         /* update context with ptr to dev */
2254         ctx->dev = talitos_alg->dev;
2255
2256         /* copy descriptor header template value */
2257         ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
2258
2259         return 0;
2260 }
2261
2262 static int talitos_cra_init_aead(struct crypto_tfm *tfm)
2263 {
2264         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2265
2266         talitos_cra_init(tfm);
2267
2268         /* random first IV */
2269         get_random_bytes(ctx->iv, TALITOS_MAX_IV_LENGTH);
2270
2271         return 0;
2272 }
2273
2274 static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
2275 {
2276         struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
2277
2278         talitos_cra_init(tfm);
2279
2280         ctx->keylen = 0;
2281         crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
2282                                  sizeof(struct talitos_ahash_req_ctx));
2283
2284         return 0;
2285 }
2286
2287 /*
2288  * given the alg's descriptor header template, determine whether descriptor
2289  * type and primary/secondary execution units required match the hw
2290  * capabilities description provided in the device tree node.
2291  */
2292 static int hw_supports(struct device *dev, __be32 desc_hdr_template)
2293 {
2294         struct talitos_private *priv = dev_get_drvdata(dev);
2295         int ret;
2296
2297         ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
2298               (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
2299
2300         if (SECONDARY_EU(desc_hdr_template))
2301                 ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
2302                               & priv->exec_units);
2303
2304         return ret;
2305 }
2306
2307 static int talitos_remove(struct of_device *ofdev)
2308 {
2309         struct device *dev = &ofdev->dev;
2310         struct talitos_private *priv = dev_get_drvdata(dev);
2311         struct talitos_crypto_alg *t_alg, *n;
2312         int i;
2313
2314         list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
2315                 switch (t_alg->algt.type) {
2316                 case CRYPTO_ALG_TYPE_ABLKCIPHER:
2317                 case CRYPTO_ALG_TYPE_AEAD:
2318                         crypto_unregister_alg(&t_alg->algt.alg.crypto);
2319                         break;
2320                 case CRYPTO_ALG_TYPE_AHASH:
2321                         crypto_unregister_ahash(&t_alg->algt.alg.hash);
2322                         break;
2323                 }
2324                 list_del(&t_alg->entry);
2325                 kfree(t_alg);
2326         }
2327
2328         if (hw_supports(dev, DESC_HDR_SEL0_RNG))
2329                 talitos_unregister_rng(dev);
2330
2331         for (i = 0; i < priv->num_channels; i++)
2332                 if (priv->chan[i].fifo)
2333                         kfree(priv->chan[i].fifo);
2334
2335         kfree(priv->chan);
2336
2337         if (priv->irq != NO_IRQ) {
2338                 free_irq(priv->irq, dev);
2339                 irq_dispose_mapping(priv->irq);
2340         }
2341
2342         tasklet_kill(&priv->done_task);
2343
2344         iounmap(priv->reg);
2345
2346         dev_set_drvdata(dev, NULL);
2347
2348         kfree(priv);
2349
2350         return 0;
2351 }
2352
2353 static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
2354                                                     struct talitos_alg_template
2355                                                            *template)
2356 {
2357         struct talitos_private *priv = dev_get_drvdata(dev);
2358         struct talitos_crypto_alg *t_alg;
2359         struct crypto_alg *alg;
2360
2361         t_alg = kzalloc(sizeof(struct talitos_crypto_alg), GFP_KERNEL);
2362         if (!t_alg)
2363                 return ERR_PTR(-ENOMEM);
2364
2365         t_alg->algt = *template;
2366
2367         switch (t_alg->algt.type) {
2368         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2369                 alg = &t_alg->algt.alg.crypto;
2370                 alg->cra_init = talitos_cra_init;
2371                 break;
2372         case CRYPTO_ALG_TYPE_AEAD:
2373                 alg = &t_alg->algt.alg.crypto;
2374                 alg->cra_init = talitos_cra_init_aead;
2375                 break;
2376         case CRYPTO_ALG_TYPE_AHASH:
2377                 alg = &t_alg->algt.alg.hash.halg.base;
2378                 alg->cra_init = talitos_cra_init_ahash;
2379                 if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
2380                     !strcmp(alg->cra_name, "sha224")) {
2381                         t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
2382                         t_alg->algt.desc_hdr_template =
2383                                         DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
2384                                         DESC_HDR_SEL0_MDEUA |
2385                                         DESC_HDR_MODE0_MDEU_SHA256;
2386                 }
2387                 break;
2388         }
2389
2390         alg->cra_module = THIS_MODULE;
2391         alg->cra_priority = TALITOS_CRA_PRIORITY;
2392         alg->cra_alignmask = 0;
2393         alg->cra_ctxsize = sizeof(struct talitos_ctx);
2394
2395         t_alg->dev = dev;
2396
2397         return t_alg;
2398 }
2399
2400 static int talitos_probe(struct of_device *ofdev,
2401                          const struct of_device_id *match)
2402 {
2403         struct device *dev = &ofdev->dev;
2404         struct device_node *np = ofdev->dev.of_node;
2405         struct talitos_private *priv;
2406         const unsigned int *prop;
2407         int i, err;
2408
2409         priv = kzalloc(sizeof(struct talitos_private), GFP_KERNEL);
2410         if (!priv)
2411                 return -ENOMEM;
2412
2413         dev_set_drvdata(dev, priv);
2414
2415         priv->ofdev = ofdev;
2416
2417         tasklet_init(&priv->done_task, talitos_done, (unsigned long)dev);
2418
2419         INIT_LIST_HEAD(&priv->alg_list);
2420
2421         priv->irq = irq_of_parse_and_map(np, 0);
2422
2423         if (priv->irq == NO_IRQ) {
2424                 dev_err(dev, "failed to map irq\n");
2425                 err = -EINVAL;
2426                 goto err_out;
2427         }
2428
2429         /* get the irq line */
2430         err = request_irq(priv->irq, talitos_interrupt, 0,
2431                           dev_driver_string(dev), dev);
2432         if (err) {
2433                 dev_err(dev, "failed to request irq %d\n", priv->irq);
2434                 irq_dispose_mapping(priv->irq);
2435                 priv->irq = NO_IRQ;
2436                 goto err_out;
2437         }
2438
2439         priv->reg = of_iomap(np, 0);
2440         if (!priv->reg) {
2441                 dev_err(dev, "failed to of_iomap\n");
2442                 err = -ENOMEM;
2443                 goto err_out;
2444         }
2445
2446         /* get SEC version capabilities from device tree */
2447         prop = of_get_property(np, "fsl,num-channels", NULL);
2448         if (prop)
2449                 priv->num_channels = *prop;
2450
2451         prop = of_get_property(np, "fsl,channel-fifo-len", NULL);
2452         if (prop)
2453                 priv->chfifo_len = *prop;
2454
2455         prop = of_get_property(np, "fsl,exec-units-mask", NULL);
2456         if (prop)
2457                 priv->exec_units = *prop;
2458
2459         prop = of_get_property(np, "fsl,descriptor-types-mask", NULL);
2460         if (prop)
2461                 priv->desc_types = *prop;
2462
2463         if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
2464             !priv->exec_units || !priv->desc_types) {
2465                 dev_err(dev, "invalid property data in device tree node\n");
2466                 err = -EINVAL;
2467                 goto err_out;
2468         }
2469
2470         if (of_device_is_compatible(np, "fsl,sec3.0"))
2471                 priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
2472
2473         if (of_device_is_compatible(np, "fsl,sec2.1"))
2474                 priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
2475                                   TALITOS_FTR_SHA224_HWINIT;
2476
2477         priv->chan = kzalloc(sizeof(struct talitos_channel) *
2478                              priv->num_channels, GFP_KERNEL);
2479         if (!priv->chan) {
2480                 dev_err(dev, "failed to allocate channel management space\n");
2481                 err = -ENOMEM;
2482                 goto err_out;
2483         }
2484
2485         for (i = 0; i < priv->num_channels; i++) {
2486                 spin_lock_init(&priv->chan[i].head_lock);
2487                 spin_lock_init(&priv->chan[i].tail_lock);
2488         }
2489
2490         priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
2491
2492         for (i = 0; i < priv->num_channels; i++) {
2493                 priv->chan[i].fifo = kzalloc(sizeof(struct talitos_request) *
2494                                              priv->fifo_len, GFP_KERNEL);
2495                 if (!priv->chan[i].fifo) {
2496                         dev_err(dev, "failed to allocate request fifo %d\n", i);
2497                         err = -ENOMEM;
2498                         goto err_out;
2499                 }
2500         }
2501
2502         for (i = 0; i < priv->num_channels; i++)
2503                 atomic_set(&priv->chan[i].submit_count,
2504                            -(priv->chfifo_len - 1));
2505
2506         dma_set_mask(dev, DMA_BIT_MASK(36));
2507
2508         /* reset and initialize the h/w */
2509         err = init_device(dev);
2510         if (err) {
2511                 dev_err(dev, "failed to initialize device\n");
2512                 goto err_out;
2513         }
2514
2515         /* register the RNG, if available */
2516         if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
2517                 err = talitos_register_rng(dev);
2518                 if (err) {
2519                         dev_err(dev, "failed to register hwrng: %d\n", err);
2520                         goto err_out;
2521                 } else
2522                         dev_info(dev, "hwrng\n");
2523         }
2524
2525         /* register crypto algorithms the device supports */
2526         for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
2527                 if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
2528                         struct talitos_crypto_alg *t_alg;
2529                         char *name = NULL;
2530
2531                         t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
2532                         if (IS_ERR(t_alg)) {
2533                                 err = PTR_ERR(t_alg);
2534                                 goto err_out;
2535                         }
2536
2537                         switch (t_alg->algt.type) {
2538                         case CRYPTO_ALG_TYPE_ABLKCIPHER:
2539                         case CRYPTO_ALG_TYPE_AEAD:
2540                                 err = crypto_register_alg(
2541                                                 &t_alg->algt.alg.crypto);
2542                                 name = t_alg->algt.alg.crypto.cra_driver_name;
2543                                 break;
2544                         case CRYPTO_ALG_TYPE_AHASH:
2545                                 err = crypto_register_ahash(
2546                                                 &t_alg->algt.alg.hash);
2547                                 name =
2548                                  t_alg->algt.alg.hash.halg.base.cra_driver_name;
2549                                 break;
2550                         }
2551                         if (err) {
2552                                 dev_err(dev, "%s alg registration failed\n",
2553                                         name);
2554                                 kfree(t_alg);
2555                         } else {
2556                                 list_add_tail(&t_alg->entry, &priv->alg_list);
2557                                 dev_info(dev, "%s\n", name);
2558                         }
2559                 }
2560         }
2561
2562         return 0;
2563
2564 err_out:
2565         talitos_remove(ofdev);
2566
2567         return err;
2568 }
2569
2570 static const struct of_device_id talitos_match[] = {
2571         {
2572                 .compatible = "fsl,sec2.0",
2573         },
2574         {},
2575 };
2576 MODULE_DEVICE_TABLE(of, talitos_match);
2577
2578 static struct of_platform_driver talitos_driver = {
2579         .driver = {
2580                 .name = "talitos",
2581                 .owner = THIS_MODULE,
2582                 .of_match_table = talitos_match,
2583         },
2584         .probe = talitos_probe,
2585         .remove = talitos_remove,
2586 };
2587
2588 static int __init talitos_init(void)
2589 {
2590         return of_register_platform_driver(&talitos_driver);
2591 }
2592 module_init(talitos_init);
2593
2594 static void __exit talitos_exit(void)
2595 {
2596         of_unregister_platform_driver(&talitos_driver);
2597 }
2598 module_exit(talitos_exit);
2599
2600 MODULE_LICENSE("GPL");
2601 MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
2602 MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");