config: tegra3: enable /dev mount with ACL
[linux-2.6.git] / drivers / cpufreq / maple-cpufreq.c
1 /*
2  *  Copyright (C) 2011 Dmitry Eremin-Solenikov
3  *  Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
4  *  and                       Markus Demleitner <msdemlei@cl.uni-heidelberg.de>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This driver adds basic cpufreq support for SMU & 970FX based G5 Macs,
11  * that is iMac G5 and latest single CPU desktop.
12  */
13
14 #undef DEBUG
15
16 #include <linux/module.h>
17 #include <linux/types.h>
18 #include <linux/errno.h>
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/sched.h>
22 #include <linux/cpufreq.h>
23 #include <linux/init.h>
24 #include <linux/completion.h>
25 #include <linux/mutex.h>
26 #include <linux/time.h>
27 #include <linux/of.h>
28
29 #define DBG(fmt...) pr_debug(fmt)
30
31 /* see 970FX user manual */
32
33 #define SCOM_PCR 0x0aa001                       /* PCR scom addr */
34
35 #define PCR_HILO_SELECT         0x80000000U     /* 1 = PCR, 0 = PCRH */
36 #define PCR_SPEED_FULL          0x00000000U     /* 1:1 speed value */
37 #define PCR_SPEED_HALF          0x00020000U     /* 1:2 speed value */
38 #define PCR_SPEED_QUARTER       0x00040000U     /* 1:4 speed value */
39 #define PCR_SPEED_MASK          0x000e0000U     /* speed mask */
40 #define PCR_SPEED_SHIFT         17
41 #define PCR_FREQ_REQ_VALID      0x00010000U     /* freq request valid */
42 #define PCR_VOLT_REQ_VALID      0x00008000U     /* volt request valid */
43 #define PCR_TARGET_TIME_MASK    0x00006000U     /* target time */
44 #define PCR_STATLAT_MASK        0x00001f00U     /* STATLAT value */
45 #define PCR_SNOOPLAT_MASK       0x000000f0U     /* SNOOPLAT value */
46 #define PCR_SNOOPACC_MASK       0x0000000fU     /* SNOOPACC value */
47
48 #define SCOM_PSR 0x408001                       /* PSR scom addr */
49 /* warning: PSR is a 64 bits register */
50 #define PSR_CMD_RECEIVED        0x2000000000000000U   /* command received */
51 #define PSR_CMD_COMPLETED       0x1000000000000000U   /* command completed */
52 #define PSR_CUR_SPEED_MASK      0x0300000000000000U   /* current speed */
53 #define PSR_CUR_SPEED_SHIFT     (56)
54
55 /*
56  * The G5 only supports two frequencies (Quarter speed is not supported)
57  */
58 #define CPUFREQ_HIGH                  0
59 #define CPUFREQ_LOW                   1
60
61 static struct cpufreq_frequency_table maple_cpu_freqs[] = {
62         {CPUFREQ_HIGH,          0},
63         {CPUFREQ_LOW,           0},
64         {0,                     CPUFREQ_TABLE_END},
65 };
66
67 static struct freq_attr *maple_cpu_freqs_attr[] = {
68         &cpufreq_freq_attr_scaling_available_freqs,
69         NULL,
70 };
71
72 /* Power mode data is an array of the 32 bits PCR values to use for
73  * the various frequencies, retrieved from the device-tree
74  */
75 static int maple_pmode_cur;
76
77 static DEFINE_MUTEX(maple_switch_mutex);
78
79 static const u32 *maple_pmode_data;
80 static int maple_pmode_max;
81
82 /*
83  * SCOM based frequency switching for 970FX rev3
84  */
85 static int maple_scom_switch_freq(int speed_mode)
86 {
87         unsigned long flags;
88         int to;
89
90         local_irq_save(flags);
91
92         /* Clear PCR high */
93         scom970_write(SCOM_PCR, 0);
94         /* Clear PCR low */
95         scom970_write(SCOM_PCR, PCR_HILO_SELECT | 0);
96         /* Set PCR low */
97         scom970_write(SCOM_PCR, PCR_HILO_SELECT |
98                       maple_pmode_data[speed_mode]);
99
100         /* Wait for completion */
101         for (to = 0; to < 10; to++) {
102                 unsigned long psr = scom970_read(SCOM_PSR);
103
104                 if ((psr & PSR_CMD_RECEIVED) == 0 &&
105                     (((psr >> PSR_CUR_SPEED_SHIFT) ^
106                       (maple_pmode_data[speed_mode] >> PCR_SPEED_SHIFT)) & 0x3)
107                     == 0)
108                         break;
109                 if (psr & PSR_CMD_COMPLETED)
110                         break;
111                 udelay(100);
112         }
113
114         local_irq_restore(flags);
115
116         maple_pmode_cur = speed_mode;
117         ppc_proc_freq = maple_cpu_freqs[speed_mode].frequency * 1000ul;
118
119         return 0;
120 }
121
122 static int maple_scom_query_freq(void)
123 {
124         unsigned long psr = scom970_read(SCOM_PSR);
125         int i;
126
127         for (i = 0; i <= maple_pmode_max; i++)
128                 if ((((psr >> PSR_CUR_SPEED_SHIFT) ^
129                       (maple_pmode_data[i] >> PCR_SPEED_SHIFT)) & 0x3) == 0)
130                         break;
131         return i;
132 }
133
134 /*
135  * Common interface to the cpufreq core
136  */
137
138 static int maple_cpufreq_verify(struct cpufreq_policy *policy)
139 {
140         return cpufreq_frequency_table_verify(policy, maple_cpu_freqs);
141 }
142
143 static int maple_cpufreq_target(struct cpufreq_policy *policy,
144         unsigned int target_freq, unsigned int relation)
145 {
146         unsigned int newstate = 0;
147         struct cpufreq_freqs freqs;
148         int rc;
149
150         if (cpufreq_frequency_table_target(policy, maple_cpu_freqs,
151                         target_freq, relation, &newstate))
152                 return -EINVAL;
153
154         if (maple_pmode_cur == newstate)
155                 return 0;
156
157         mutex_lock(&maple_switch_mutex);
158
159         freqs.old = maple_cpu_freqs[maple_pmode_cur].frequency;
160         freqs.new = maple_cpu_freqs[newstate].frequency;
161         freqs.cpu = 0;
162
163         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
164         rc = maple_scom_switch_freq(newstate);
165         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
166
167         mutex_unlock(&maple_switch_mutex);
168
169         return rc;
170 }
171
172 static unsigned int maple_cpufreq_get_speed(unsigned int cpu)
173 {
174         return maple_cpu_freqs[maple_pmode_cur].frequency;
175 }
176
177 static int maple_cpufreq_cpu_init(struct cpufreq_policy *policy)
178 {
179         policy->cpuinfo.transition_latency = 12000;
180         policy->cur = maple_cpu_freqs[maple_scom_query_freq()].frequency;
181         /* secondary CPUs are tied to the primary one by the
182          * cpufreq core if in the secondary policy we tell it that
183          * it actually must be one policy together with all others. */
184         cpumask_copy(policy->cpus, cpu_online_mask);
185         cpufreq_frequency_table_get_attr(maple_cpu_freqs, policy->cpu);
186
187         return cpufreq_frequency_table_cpuinfo(policy,
188                 maple_cpu_freqs);
189 }
190
191
192 static struct cpufreq_driver maple_cpufreq_driver = {
193         .name           = "maple",
194         .owner          = THIS_MODULE,
195         .flags          = CPUFREQ_CONST_LOOPS,
196         .init           = maple_cpufreq_cpu_init,
197         .verify         = maple_cpufreq_verify,
198         .target         = maple_cpufreq_target,
199         .get            = maple_cpufreq_get_speed,
200         .attr           = maple_cpu_freqs_attr,
201 };
202
203 static int __init maple_cpufreq_init(void)
204 {
205         struct device_node *cpus;
206         struct device_node *cpunode;
207         unsigned int psize;
208         unsigned long max_freq;
209         const u32 *valp;
210         u32 pvr_hi;
211         int rc = -ENODEV;
212
213         /*
214          * Behave here like powermac driver which checks machine compatibility
215          * to ease merging of two drivers in future.
216          */
217         if (!of_machine_is_compatible("Momentum,Maple") &&
218             !of_machine_is_compatible("Momentum,Apache"))
219                 return 0;
220
221         cpus = of_find_node_by_path("/cpus");
222         if (cpus == NULL) {
223                 DBG("No /cpus node !\n");
224                 return -ENODEV;
225         }
226
227         /* Get first CPU node */
228         for (cpunode = NULL;
229              (cpunode = of_get_next_child(cpus, cpunode)) != NULL;) {
230                 const u32 *reg = of_get_property(cpunode, "reg", NULL);
231                 if (reg == NULL || (*reg) != 0)
232                         continue;
233                 if (!strcmp(cpunode->type, "cpu"))
234                         break;
235         }
236         if (cpunode == NULL) {
237                 printk(KERN_ERR "cpufreq: Can't find any CPU 0 node\n");
238                 goto bail_cpus;
239         }
240
241         /* Check 970FX for now */
242         /* we actually don't care on which CPU to access PVR */
243         pvr_hi = PVR_VER(mfspr(SPRN_PVR));
244         if (pvr_hi != 0x3c && pvr_hi != 0x44) {
245                 printk(KERN_ERR "cpufreq: Unsupported CPU version (%x)\n",
246                                 pvr_hi);
247                 goto bail_noprops;
248         }
249
250         /* Look for the powertune data in the device-tree */
251         /*
252          * On Maple this property is provided by PIBS in dual-processor config,
253          * not provided by PIBS in CPU0 config and also not provided by SLOF,
254          * so YMMV
255          */
256         maple_pmode_data = of_get_property(cpunode, "power-mode-data", &psize);
257         if (!maple_pmode_data) {
258                 DBG("No power-mode-data !\n");
259                 goto bail_noprops;
260         }
261         maple_pmode_max = psize / sizeof(u32) - 1;
262
263         /*
264          * From what I see, clock-frequency is always the maximal frequency.
265          * The current driver can not slew sysclk yet, so we really only deal
266          * with powertune steps for now. We also only implement full freq and
267          * half freq in this version. So far, I haven't yet seen a machine
268          * supporting anything else.
269          */
270         valp = of_get_property(cpunode, "clock-frequency", NULL);
271         if (!valp)
272                 return -ENODEV;
273         max_freq = (*valp)/1000;
274         maple_cpu_freqs[0].frequency = max_freq;
275         maple_cpu_freqs[1].frequency = max_freq/2;
276
277         /* Force apply current frequency to make sure everything is in
278          * sync (voltage is right for example). Firmware may leave us with
279          * a strange setting ...
280          */
281         msleep(10);
282         maple_pmode_cur = -1;
283         maple_scom_switch_freq(maple_scom_query_freq());
284
285         printk(KERN_INFO "Registering Maple CPU frequency driver\n");
286         printk(KERN_INFO "Low: %d Mhz, High: %d Mhz, Cur: %d MHz\n",
287                 maple_cpu_freqs[1].frequency/1000,
288                 maple_cpu_freqs[0].frequency/1000,
289                 maple_cpu_freqs[maple_pmode_cur].frequency/1000);
290
291         rc = cpufreq_register_driver(&maple_cpufreq_driver);
292
293         of_node_put(cpunode);
294         of_node_put(cpus);
295
296         return rc;
297
298 bail_noprops:
299         of_node_put(cpunode);
300 bail_cpus:
301         of_node_put(cpus);
302
303         return rc;
304 }
305
306 module_init(maple_cpufreq_init);
307
308
309 MODULE_LICENSE("GPL");