sh: Disable IRQ balancing for timer and IPI IRQs.
[linux-2.6.git] / drivers / clocksource / sh_mtu2.c
1 /*
2  * SuperH Timer Support - MTU2
3  *
4  *  Copyright (C) 2009 Magnus Damm
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, write to the Free Software
17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
18  */
19
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/interrupt.h>
24 #include <linux/ioport.h>
25 #include <linux/delay.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/irq.h>
29 #include <linux/err.h>
30 #include <linux/clockchips.h>
31 #include <linux/sh_timer.h>
32
33 struct sh_mtu2_priv {
34         void __iomem *mapbase;
35         struct clk *clk;
36         struct irqaction irqaction;
37         struct platform_device *pdev;
38         unsigned long rate;
39         unsigned long periodic;
40         struct clock_event_device ced;
41 };
42
43 static DEFINE_SPINLOCK(sh_mtu2_lock);
44
45 #define TSTR -1 /* shared register */
46 #define TCR  0 /* channel register */
47 #define TMDR 1 /* channel register */
48 #define TIOR 2 /* channel register */
49 #define TIER 3 /* channel register */
50 #define TSR  4 /* channel register */
51 #define TCNT 5 /* channel register */
52 #define TGR  6 /* channel register */
53
54 static unsigned long mtu2_reg_offs[] = {
55         [TCR] = 0,
56         [TMDR] = 1,
57         [TIOR] = 2,
58         [TIER] = 4,
59         [TSR] = 5,
60         [TCNT] = 6,
61         [TGR] = 8,
62 };
63
64 static inline unsigned long sh_mtu2_read(struct sh_mtu2_priv *p, int reg_nr)
65 {
66         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
67         void __iomem *base = p->mapbase;
68         unsigned long offs;
69
70         if (reg_nr == TSTR)
71                 return ioread8(base + cfg->channel_offset);
72
73         offs = mtu2_reg_offs[reg_nr];
74
75         if ((reg_nr == TCNT) || (reg_nr == TGR))
76                 return ioread16(base + offs);
77         else
78                 return ioread8(base + offs);
79 }
80
81 static inline void sh_mtu2_write(struct sh_mtu2_priv *p, int reg_nr,
82                                 unsigned long value)
83 {
84         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
85         void __iomem *base = p->mapbase;
86         unsigned long offs;
87
88         if (reg_nr == TSTR) {
89                 iowrite8(value, base + cfg->channel_offset);
90                 return;
91         }
92
93         offs = mtu2_reg_offs[reg_nr];
94
95         if ((reg_nr == TCNT) || (reg_nr == TGR))
96                 iowrite16(value, base + offs);
97         else
98                 iowrite8(value, base + offs);
99 }
100
101 static void sh_mtu2_start_stop_ch(struct sh_mtu2_priv *p, int start)
102 {
103         struct sh_timer_config *cfg = p->pdev->dev.platform_data;
104         unsigned long flags, value;
105
106         /* start stop register shared by multiple timer channels */
107         spin_lock_irqsave(&sh_mtu2_lock, flags);
108         value = sh_mtu2_read(p, TSTR);
109
110         if (start)
111                 value |= 1 << cfg->timer_bit;
112         else
113                 value &= ~(1 << cfg->timer_bit);
114
115         sh_mtu2_write(p, TSTR, value);
116         spin_unlock_irqrestore(&sh_mtu2_lock, flags);
117 }
118
119 static int sh_mtu2_enable(struct sh_mtu2_priv *p)
120 {
121         int ret;
122
123         /* enable clock */
124         ret = clk_enable(p->clk);
125         if (ret) {
126                 dev_err(&p->pdev->dev, "cannot enable clock\n");
127                 return ret;
128         }
129
130         /* make sure channel is disabled */
131         sh_mtu2_start_stop_ch(p, 0);
132
133         p->rate = clk_get_rate(p->clk) / 64;
134         p->periodic = (p->rate + HZ/2) / HZ;
135
136         /* "Periodic Counter Operation" */
137         sh_mtu2_write(p, TCR, 0x23); /* TGRA clear, divide clock by 64 */
138         sh_mtu2_write(p, TIOR, 0);
139         sh_mtu2_write(p, TGR, p->periodic);
140         sh_mtu2_write(p, TCNT, 0);
141         sh_mtu2_write(p, TMDR, 0);
142         sh_mtu2_write(p, TIER, 0x01);
143
144         /* enable channel */
145         sh_mtu2_start_stop_ch(p, 1);
146
147         return 0;
148 }
149
150 static void sh_mtu2_disable(struct sh_mtu2_priv *p)
151 {
152         /* disable channel */
153         sh_mtu2_start_stop_ch(p, 0);
154
155         /* stop clock */
156         clk_disable(p->clk);
157 }
158
159 static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id)
160 {
161         struct sh_mtu2_priv *p = dev_id;
162
163         /* acknowledge interrupt */
164         sh_mtu2_read(p, TSR);
165         sh_mtu2_write(p, TSR, 0xfe);
166
167         /* notify clockevent layer */
168         p->ced.event_handler(&p->ced);
169         return IRQ_HANDLED;
170 }
171
172 static struct sh_mtu2_priv *ced_to_sh_mtu2(struct clock_event_device *ced)
173 {
174         return container_of(ced, struct sh_mtu2_priv, ced);
175 }
176
177 static void sh_mtu2_clock_event_mode(enum clock_event_mode mode,
178                                     struct clock_event_device *ced)
179 {
180         struct sh_mtu2_priv *p = ced_to_sh_mtu2(ced);
181         int disabled = 0;
182
183         /* deal with old setting first */
184         switch (ced->mode) {
185         case CLOCK_EVT_MODE_PERIODIC:
186                 sh_mtu2_disable(p);
187                 disabled = 1;
188                 break;
189         default:
190                 break;
191         }
192
193         switch (mode) {
194         case CLOCK_EVT_MODE_PERIODIC:
195                 dev_info(&p->pdev->dev, "used for periodic clock events\n");
196                 sh_mtu2_enable(p);
197                 break;
198         case CLOCK_EVT_MODE_UNUSED:
199                 if (!disabled)
200                         sh_mtu2_disable(p);
201                 break;
202         case CLOCK_EVT_MODE_SHUTDOWN:
203         default:
204                 break;
205         }
206 }
207
208 static void sh_mtu2_register_clockevent(struct sh_mtu2_priv *p,
209                                        char *name, unsigned long rating)
210 {
211         struct clock_event_device *ced = &p->ced;
212         int ret;
213
214         memset(ced, 0, sizeof(*ced));
215
216         ced->name = name;
217         ced->features = CLOCK_EVT_FEAT_PERIODIC;
218         ced->rating = rating;
219         ced->cpumask = cpumask_of(0);
220         ced->set_mode = sh_mtu2_clock_event_mode;
221
222         dev_info(&p->pdev->dev, "used for clock events\n");
223         clockevents_register_device(ced);
224
225         ret = setup_irq(p->irqaction.irq, &p->irqaction);
226         if (ret) {
227                 dev_err(&p->pdev->dev, "failed to request irq %d\n",
228                         p->irqaction.irq);
229                 return;
230         }
231 }
232
233 static int sh_mtu2_register(struct sh_mtu2_priv *p, char *name,
234                             unsigned long clockevent_rating)
235 {
236         if (clockevent_rating)
237                 sh_mtu2_register_clockevent(p, name, clockevent_rating);
238
239         return 0;
240 }
241
242 static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
243 {
244         struct sh_timer_config *cfg = pdev->dev.platform_data;
245         struct resource *res;
246         int irq, ret;
247         ret = -ENXIO;
248
249         memset(p, 0, sizeof(*p));
250         p->pdev = pdev;
251
252         if (!cfg) {
253                 dev_err(&p->pdev->dev, "missing platform data\n");
254                 goto err0;
255         }
256
257         platform_set_drvdata(pdev, p);
258
259         res = platform_get_resource(p->pdev, IORESOURCE_MEM, 0);
260         if (!res) {
261                 dev_err(&p->pdev->dev, "failed to get I/O memory\n");
262                 goto err0;
263         }
264
265         irq = platform_get_irq(p->pdev, 0);
266         if (irq < 0) {
267                 dev_err(&p->pdev->dev, "failed to get irq\n");
268                 goto err0;
269         }
270
271         /* map memory, let mapbase point to our channel */
272         p->mapbase = ioremap_nocache(res->start, resource_size(res));
273         if (p->mapbase == NULL) {
274                 dev_err(&p->pdev->dev, "failed to remap I/O memory\n");
275                 goto err0;
276         }
277
278         /* setup data for setup_irq() (too early for request_irq()) */
279         p->irqaction.name = dev_name(&p->pdev->dev);
280         p->irqaction.handler = sh_mtu2_interrupt;
281         p->irqaction.dev_id = p;
282         p->irqaction.irq = irq;
283         p->irqaction.flags = IRQF_DISABLED | IRQF_TIMER | \
284                              IRQF_IRQPOLL  | IRQF_NOBALANCING;
285
286         /* get hold of clock */
287         p->clk = clk_get(&p->pdev->dev, "mtu2_fck");
288         if (IS_ERR(p->clk)) {
289                 dev_warn(&p->pdev->dev, "using deprecated clock lookup\n");
290                 p->clk = clk_get(&p->pdev->dev, cfg->clk);
291                 if (IS_ERR(p->clk)) {
292                         dev_err(&p->pdev->dev, "cannot get clock\n");
293                         ret = PTR_ERR(p->clk);
294                         goto err1;
295                 }
296         }
297
298         return sh_mtu2_register(p, (char *)dev_name(&p->pdev->dev),
299                                 cfg->clockevent_rating);
300  err1:
301         iounmap(p->mapbase);
302  err0:
303         return ret;
304 }
305
306 static int __devinit sh_mtu2_probe(struct platform_device *pdev)
307 {
308         struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
309         int ret;
310
311         if (p) {
312                 dev_info(&pdev->dev, "kept as earlytimer\n");
313                 return 0;
314         }
315
316         p = kmalloc(sizeof(*p), GFP_KERNEL);
317         if (p == NULL) {
318                 dev_err(&pdev->dev, "failed to allocate driver data\n");
319                 return -ENOMEM;
320         }
321
322         ret = sh_mtu2_setup(p, pdev);
323         if (ret) {
324                 kfree(p);
325                 platform_set_drvdata(pdev, NULL);
326         }
327         return ret;
328 }
329
330 static int __devexit sh_mtu2_remove(struct platform_device *pdev)
331 {
332         return -EBUSY; /* cannot unregister clockevent */
333 }
334
335 static struct platform_driver sh_mtu2_device_driver = {
336         .probe          = sh_mtu2_probe,
337         .remove         = __devexit_p(sh_mtu2_remove),
338         .driver         = {
339                 .name   = "sh_mtu2",
340         }
341 };
342
343 static int __init sh_mtu2_init(void)
344 {
345         return platform_driver_register(&sh_mtu2_device_driver);
346 }
347
348 static void __exit sh_mtu2_exit(void)
349 {
350         platform_driver_unregister(&sh_mtu2_device_driver);
351 }
352
353 early_platform_init("earlytimer", &sh_mtu2_device_driver);
354 module_init(sh_mtu2_init);
355 module_exit(sh_mtu2_exit);
356
357 MODULE_AUTHOR("Magnus Damm");
358 MODULE_DESCRIPTION("SuperH MTU2 Timer Driver");
359 MODULE_LICENSE("GPL v2");