drivers/char/drm/via_dmablit.c

   1 /* via_dmablit.c -- PCI DMA BitBlt support for the VIA Unichrome/Pro
   2  *
   3  * Copyright (C) 2005 Thomas Hellstrom, All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Thomas Hellstrom.
  26  *    Partially based on code obtained from Digeo Inc.
  27  */
  28
  29
  30 /*
  31  * Unmaps the DMA mappings.
  32  * FIXME: Is this a NoOp on x86? Also
  33  * FIXME: What happens if this one is called and a pending blit has previously done
  34  * the same DMA mappings?
  35  */
  36
  37 #include "drmP.h"
  38 #include "via_drm.h"
  39 #include "via_drv.h"
  40 #include "via_dmablit.h"
  41
  42 #include <linux/pagemap.h>
  43
  44 #define VIA_PGDN(x)          (((unsigned long)(x)) & PAGE_MASK)
  45 #define VIA_PGOFF(x)        (((unsigned long)(x)) & ~PAGE_MASK)
  46 #define VIA_PFN(x)            ((unsigned long)(x) >> PAGE_SHIFT)
  47
  48 typedef struct _drm_via_descriptor {
  49         uint32_t mem_addr;
  50         uint32_t dev_addr;
  51         uint32_t size;
  52         uint32_t next;
  53 } drm_via_descriptor_t;
  54
  55
  56 /*
  57  * Unmap a DMA mapping.
  58  */
  59
  60
  61
  62 static void
  63 via_unmap_blit_from_device(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
  64 {
  65         int num_desc = vsg->num_desc;
  66         unsigned cur_descriptor_page = num_desc / vsg->descriptors_per_page;
  67         unsigned descriptor_this_page = num_desc % vsg->descriptors_per_page;
  68         drm_via_descriptor_t *desc_ptr = vsg->desc_pages[cur_descriptor_page] +
  69                 descriptor_this_page;
  70         dma_addr_t next = vsg->chain_start;
  71
  72         while(num_desc--) {
  73                 if (descriptor_this_page-- == 0) {
  74                         cur_descriptor_page--;
  75                         descriptor_this_page = vsg->descriptors_per_page - 1;
  76                         desc_ptr = vsg->desc_pages[cur_descriptor_page] +
  77                                 descriptor_this_page;
  78                 }
  79                 dma_unmap_single(&pdev->dev, next, sizeof(*desc_ptr), DMA_TO_DEVICE);
  80                 dma_unmap_page(&pdev->dev, desc_ptr->mem_addr, desc_ptr->size, vsg->direction);
  81                 next = (dma_addr_t) desc_ptr->next;
  82                 desc_ptr--;
  83         }
  84 }
  85
  86 /*
  87  * If mode = 0, count how many descriptors are needed.
  88  * If mode = 1, Map the DMA pages for the device, put together and map also the descriptors.
  89  * Descriptors are run in reverse order by the hardware because we are not allowed to update the
  90  * 'next' field without syncing calls when the descriptor is already mapped.
  91  */
  92
  93 static void
  94 via_map_blit_for_device(struct pci_dev *pdev,
  95                    const drm_via_dmablit_t *xfer,
  96                    drm_via_sg_info_t *vsg,
  97                    int mode)
  98 {
  99         unsigned cur_descriptor_page = 0;
 100         unsigned num_descriptors_this_page = 0;
 101         unsigned char *mem_addr = xfer->mem_addr;
 102         unsigned char *cur_mem;
 103         unsigned char *first_addr = (unsigned char *)VIA_PGDN(mem_addr);
 104         uint32_t fb_addr = xfer->fb_addr;
 105         uint32_t cur_fb;
 106         unsigned long line_len;
 107         unsigned remaining_len;
 108         int num_desc = 0;
 109         int cur_line;
 110         dma_addr_t next = 0 | VIA_DMA_DPR_EC;
 111         drm_via_descriptor_t *desc_ptr = NULL;
 112
 113         if (mode == 1)
 114                 desc_ptr = vsg->desc_pages[cur_descriptor_page];
 115
 116         for (cur_line = 0; cur_line < xfer->num_lines; ++cur_line) {
 117
 118                 line_len = xfer->line_length;
 119                 cur_fb = fb_addr;
 120                 cur_mem = mem_addr;
 121
 122                 while (line_len > 0) {
 123
 124                         remaining_len = min(PAGE_SIZE-VIA_PGOFF(cur_mem), line_len);
 125                         line_len -= remaining_len;
 126
 127                         if (mode == 1) {
 128                                 desc_ptr->mem_addr =
 129                                         dma_map_page(&pdev->dev,
 130                                                      vsg->pages[VIA_PFN(cur_mem) -
 131                                                                 VIA_PFN(first_addr)],
 132                                                      VIA_PGOFF(cur_mem), remaining_len,
 133                                                      vsg->direction);
 134                                 desc_ptr->dev_addr = cur_fb;
 135
 136                                 desc_ptr->size = remaining_len;
 137                                 desc_ptr->next = (uint32_t) next;
 138                                 next = dma_map_single(&pdev->dev, desc_ptr, sizeof(*desc_ptr),
 139                                                       DMA_TO_DEVICE);
 140                                 desc_ptr++;
 141                                 if (++num_descriptors_this_page >= vsg->descriptors_per_page) {
 142                                         num_descriptors_this_page = 0;
 143                                         desc_ptr = vsg->desc_pages[++cur_descriptor_page];
 144                                 }
 145                         }
 146
 147                         num_desc++;
 148                         cur_mem += remaining_len;
 149                         cur_fb += remaining_len;
 150                 }
 151
 152                 mem_addr += xfer->mem_stride;
 153                 fb_addr += xfer->fb_stride;
 154         }
 155
 156         if (mode == 1) {
 157                 vsg->chain_start = next;
 158                 vsg->state = dr_via_device_mapped;
 159         }
 160         vsg->num_desc = num_desc;
 161 }
 162
 163 /*
 164  * Function that frees up all resources for a blit. It is usable even if the
 165  * blit info has only been partially built as long as the status enum is consistent
 166  * with the actual status of the used resources.
 167  */
 168
 169
 170 static void
 171 via_free_sg_info(struct pci_dev *pdev, drm_via_sg_info_t *vsg)
 172 {
 173         struct page *page;
 174         int i;
 175
 176         switch(vsg->state) {
 177         case dr_via_device_mapped:
 178                 via_unmap_blit_from_device(pdev, vsg);
 179         case dr_via_desc_pages_alloc:
 180                 for (i=0; i<vsg->num_desc_pages; ++i) {
 181                         if (vsg->desc_pages[i] != NULL)
 182                           free_page((unsigned long)vsg->desc_pages[i]);
 183                 }
 184                 kfree(vsg->desc_pages);
 185         case dr_via_pages_locked:
 186                 for (i=0; i<vsg->num_pages; ++i) {
 187                         if ( NULL != (page = vsg->pages[i])) {
 188                                 if (! PageReserved(page) && (DMA_FROM_DEVICE == vsg->direction))
 189                                         SetPageDirty(page);
 190                                 page_cache_release(page);
 191                         }
 192                 }
 193         case dr_via_pages_alloc:
 194                 vfree(vsg->pages);
 195         default:
 196                 vsg->state = dr_via_sg_init;
 197         }
 198         if (vsg->bounce_buffer) {
 199                 vfree(vsg->bounce_buffer);
 200                 vsg->bounce_buffer = NULL;
 201         }
 202         vsg->free_on_sequence = 0;
 203 }
 204
 205 /*
 206  * Fire a blit engine.
 207  */
 208
 209 static void
 210 via_fire_dmablit(drm_device_t *dev, drm_via_sg_info_t *vsg, int engine)
 211 {
 212         drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
 213
 214         VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0);
 215         VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0);
 216         VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD |
 217                   VIA_DMA_CSR_DE);
 218         VIA_WRITE(VIA_PCI_DMA_MR0  + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
 219         VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0);
 220         VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
 221         VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
 222 }
 223
 224 /*
 225  * Obtain a page pointer array and lock all pages into system memory. A segmentation violation will
 226  * occur here if the calling user does not have access to the submitted address.
 227  */
 228
 229 static int
 230 via_lock_all_dma_pages(drm_via_sg_info_t *vsg,  drm_via_dmablit_t *xfer)
 231 {
 232         int ret;
 233         unsigned long first_pfn = VIA_PFN(xfer->mem_addr);
 234         vsg->num_pages = VIA_PFN(xfer->mem_addr + (xfer->num_lines * xfer->mem_stride -1)) -
 235                 first_pfn + 1;
 236
 237         if (NULL == (vsg->pages = vmalloc(sizeof(struct page *) * vsg->num_pages)))
 238                 return DRM_ERR(ENOMEM);
 239         memset(vsg->pages, 0, sizeof(struct page *) * vsg->num_pages);
 240         down_read(&current->mm->mmap_sem);
 241         ret = get_user_pages(current, current->mm,
 242                              (unsigned long)xfer->mem_addr,
 243                              vsg->num_pages,
 244                              (vsg->direction == DMA_FROM_DEVICE),
 245                              0, vsg->pages, NULL);
 246
 247         up_read(&current->mm->mmap_sem);
 248         if (ret != vsg->num_pages) {
 249                 if (ret < 0)
 250                         return ret;
 251                 vsg->state = dr_via_pages_locked;
 252                 return DRM_ERR(EINVAL);
 253         }
 254         vsg->state = dr_via_pages_locked;
 255         DRM_DEBUG("DMA pages locked\n");
 256         return 0;
 257 }
 258
 259 /*
 260  * Allocate DMA capable memory for the blit descriptor chain, and an array that keeps track of the
 261  * pages we allocate. We don't want to use kmalloc for the descriptor chain because it may be
 262  * quite large for some blits, and pages don't need to be contingous.
 263  */
 264
 265 static int
 266 via_alloc_desc_pages(drm_via_sg_info_t *vsg)
 267 {
 268         int i;
 269
 270         vsg->descriptors_per_page = PAGE_SIZE / sizeof( drm_via_descriptor_t);
 271         vsg->num_desc_pages = (vsg->num_desc + vsg->descriptors_per_page - 1) /
 272                 vsg->descriptors_per_page;
 273
 274         if (NULL ==  (vsg->desc_pages = kmalloc(sizeof(void *) * vsg->num_desc_pages, GFP_KERNEL)))
 275                 return DRM_ERR(ENOMEM);
 276
 277         memset(vsg->desc_pages, 0, sizeof(void *) * vsg->num_desc_pages);
 278         vsg->state = dr_via_desc_pages_alloc;
 279         for (i=0; i<vsg->num_desc_pages; ++i) {
 280                 if (NULL == (vsg->desc_pages[i] =
 281                              (drm_via_descriptor_t *) __get_free_page(GFP_KERNEL)))
 282                         return DRM_ERR(ENOMEM);
 283         }
 284         DRM_DEBUG("Allocated %d pages for %d descriptors.\n", vsg->num_desc_pages,
 285                   vsg->num_desc);
 286         return 0;
 287 }
 288
 289 static void
 290 via_abort_dmablit(drm_device_t *dev, int engine)
 291 {
 292         drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
 293
 294         VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA);
 295 }
 296
 297 static void
 298 via_dmablit_engine_off(drm_device_t *dev, int engine)
 299 {
 300         drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
 301
 302         VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD);
 303 }
 304
 305
 306
 307 /*
 308  * The dmablit part of the IRQ handler. Trying to do only reasonably fast things here.
 309  * The rest, like unmapping and freeing memory for done blits is done in a separate workqueue
 310  * task. Basically the task of the interrupt handler is to submit a new blit to the engine, while
 311  * the workqueue task takes care of processing associated with the old blit.
 312  */
 313
 314 void
 315 via_dmablit_handler(drm_device_t *dev, int engine, int from_irq)
 316 {
 317         drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
 318         drm_via_blitq_t *blitq = dev_priv->blit_queues + engine;
 319         int cur;
 320         int done_transfer;
 321         unsigned long irqsave=0;
 322         uint32_t status = 0;
 323
 324         DRM_DEBUG("DMA blit handler called. engine = %d, from_irq = %d, blitq = 0x%lx\n",
 325                   engine, from_irq, (unsigned long) blitq);
 326
 327         if (from_irq) {
 328                 spin_lock(&blitq->blit_lock);
 329         } else {
 330                 spin_lock_irqsave(&blitq->blit_lock, irqsave);
 331         }
 332
 333         done_transfer = blitq->is_active &&
 334           (( status = VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04)) & VIA_DMA_CSR_TD);
 335         done_transfer = done_transfer || ( blitq->aborting && !(status & VIA_DMA_CSR_DE));
 336
 337         cur = blitq->cur;
 338         if (done_transfer) {
 339
 340                 blitq->blits[cur]->aborted = blitq->aborting;
 341                 blitq->done_blit_handle++;
 342                 DRM_WAKEUP(blitq->blit_queue + cur);
 343
 344                 cur++;
 345                 if (cur >= VIA_NUM_BLIT_SLOTS)
 346                         cur = 0;
 347                 blitq->cur = cur;
 348
 349                 /*
 350                  * Clear transfer done flag.
 351                  */
 352
 353                 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04,  VIA_DMA_CSR_TD);
 354
 355                 blitq->is_active = 0;
 356                 blitq->aborting = 0;
 357                 schedule_work(&blitq->wq);
 358
 359         } else if (blitq->is_active && time_after_eq(jiffies, blitq->end)) {
 360
 361                 /*
 362                  * Abort transfer after one second.
 363                  */
 364
 365                 via_abort_dmablit(dev, engine);
 366                 blitq->aborting = 1;
 367                 blitq->end = jiffies + DRM_HZ;
 368         }
 369
 370         if (!blitq->is_active) {
 371                 if (blitq->num_outstanding) {
 372                         via_fire_dmablit(dev, blitq->blits[cur], engine);
 373                         blitq->is_active = 1;
 374                         blitq->cur = cur;
 375                         blitq->num_outstanding--;
 376                         blitq->end = jiffies + DRM_HZ;
 377                         if (!timer_pending(&blitq->poll_timer)) {
 378                                 blitq->poll_timer.expires = jiffies+1;
 379                                 add_timer(&blitq->poll_timer);
 380                         }
 381                 } else {
 382                         if (timer_pending(&blitq->poll_timer)) {
 383                                 del_timer(&blitq->poll_timer);
 384                         }
 385                         via_dmablit_engine_off(dev, engine);
 386                 }
 387         }
 388
 389         if (from_irq) {
 390                 spin_unlock(&blitq->blit_lock);
 391         } else {
 392                 spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
 393         }
 394 }
 395
 396
 397
 398 /*
 399  * Check whether this blit is still active, performing necessary locking.
 400  */
 401
 402 static int
 403 via_dmablit_active(drm_via_blitq_t *blitq, int engine, uint32_t handle, wait_queue_head_t **queue)
 404 {
 405         unsigned long irqsave;
 406         uint32_t slot;
 407         int active;
 408
 409         spin_lock_irqsave(&blitq->blit_lock, irqsave);
 410
 411         /*
 412          * Allow for handle wraparounds.
 413          */
 414
 415         active = ((blitq->done_blit_handle - handle) > (1 << 23)) &&
 416                 ((blitq->cur_blit_handle - handle) <= (1 << 23));
 417
 418         if (queue && active) {
 419                 slot = handle - blitq->done_blit_handle + blitq->cur -1;
 420                 if (slot >= VIA_NUM_BLIT_SLOTS) {
 421                         slot -= VIA_NUM_BLIT_SLOTS;
 422                 }
 423                 *queue = blitq->blit_queue + slot;
 424         }
 425
 426         spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
 427
 428         return active;
 429 }
 430
 431 /*
 432  * Sync. Wait for at least three seconds for the blit to be performed.
 433  */
 434
 435 static int
 436 via_dmablit_sync(drm_device_t *dev, uint32_t handle, int engine)
 437 {
 438
 439         drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
 440         drm_via_blitq_t *blitq = dev_priv->blit_queues + engine;
 441         wait_queue_head_t *queue;
 442         int ret = 0;
 443
 444         if (via_dmablit_active(blitq, engine, handle, &queue)) {
 445                 DRM_WAIT_ON(ret, *queue, 3 * DRM_HZ,
 446                             !via_dmablit_active(blitq, engine, handle, NULL));
 447         }
 448         DRM_DEBUG("DMA blit sync handle 0x%x engine %d returned %d\n",
 449                   handle, engine, ret);
 450
 451         return ret;
 452 }
 453
 454
 455 /*
 456  * A timer that regularly polls the blit engine in cases where we don't have interrupts:
 457  * a) Broken hardware (typically those that don't have any video capture facility).
 458  * b) Blit abort. The hardware doesn't send an interrupt when a blit is aborted.
 459  * The timer and hardware IRQ's can and do work in parallel. If the hardware has
 460  * irqs, it will shorten the latency somewhat.
 461  */
 462
 463
 464
 465 static void
 466 via_dmablit_timer(unsigned long data)
 467 {
 468         drm_via_blitq_t *blitq = (drm_via_blitq_t *) data;
 469         drm_device_t *dev = blitq->dev;
 470         int engine = (int)
 471                 (blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues);
 472
 473         DRM_DEBUG("Polling timer called for engine %d, jiffies %lu\n", engine,
 474                   (unsigned long) jiffies);
 475
 476         via_dmablit_handler(dev, engine, 0);
 477
 478         if (!timer_pending(&blitq->poll_timer)) {
 479                 blitq->poll_timer.expires = jiffies+1;
 480                 add_timer(&blitq->poll_timer);
 481
 482                /*
 483                 * Rerun handler to delete timer if engines are off, and
 484                 * to shorten abort latency. This is a little nasty.
 485                 */
 486
 487                via_dmablit_handler(dev, engine, 0);
 488
 489         }
 490 }
 491
 492
 493
 494
 495 /*
 496  * Workqueue task that frees data and mappings associated with a blit.
 497  * Also wakes up waiting processes. Each of these tasks handles one
 498  * blit engine only and may not be called on each interrupt.
 499  */
 500
 501
 502 static void
 503 via_dmablit_workqueue(struct work_struct *work)
 504 {
 505         drm_via_blitq_t *blitq = container_of(work, drm_via_blitq_t, wq);
 506         drm_device_t *dev = blitq->dev;
 507         unsigned long irqsave;
 508         drm_via_sg_info_t *cur_sg;
 509         int cur_released;
 510
 511
 512         DRM_DEBUG("Workqueue task called for blit engine %ld\n",(unsigned long)
 513                   (blitq - ((drm_via_private_t *)dev->dev_private)->blit_queues));
 514
 515         spin_lock_irqsave(&blitq->blit_lock, irqsave);
 516
 517         while(blitq->serviced != blitq->cur) {
 518
 519                 cur_released = blitq->serviced++;
 520
 521                 DRM_DEBUG("Releasing blit slot %d\n", cur_released);
 522
 523                 if (blitq->serviced >= VIA_NUM_BLIT_SLOTS)
 524                         blitq->serviced = 0;
 525
 526                 cur_sg = blitq->blits[cur_released];
 527                 blitq->num_free++;
 528
 529                 spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
 530
 531                 DRM_WAKEUP(&blitq->busy_queue);
 532
 533                 via_free_sg_info(dev->pdev, cur_sg);
 534                 kfree(cur_sg);
 535
 536                 spin_lock_irqsave(&blitq->blit_lock, irqsave);
 537         }
 538
 539         spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
 540 }
 541
 542
 543 /*
 544  * Init all blit engines. Currently we use two, but some hardware have 4.
 545  */
 546
 547
 548 void
 549 via_init_dmablit(drm_device_t *dev)
 550 {
 551         int i,j;
 552         drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
 553         drm_via_blitq_t *blitq;
 554
 555         pci_set_master(dev->pdev);
 556
 557         for (i=0; i< VIA_NUM_BLIT_ENGINES; ++i) {
 558                 blitq = dev_priv->blit_queues + i;
 559                 blitq->dev = dev;
 560                 blitq->cur_blit_handle = 0;
 561                 blitq->done_blit_handle = 0;
 562                 blitq->head = 0;
 563                 blitq->cur = 0;
 564                 blitq->serviced = 0;
 565                 blitq->num_free = VIA_NUM_BLIT_SLOTS;
 566                 blitq->num_outstanding = 0;
 567                 blitq->is_active = 0;
 568                 blitq->aborting = 0;
 569                 spin_lock_init(&blitq->blit_lock);
 570                 for (j=0; j<VIA_NUM_BLIT_SLOTS; ++j) {
 571                         DRM_INIT_WAITQUEUE(blitq->blit_queue + j);
 572                 }
 573                 DRM_INIT_WAITQUEUE(&blitq->busy_queue);
 574                 INIT_WORK(&blitq->wq, via_dmablit_workqueue);
 575                 init_timer(&blitq->poll_timer);
 576                 blitq->poll_timer.function = &via_dmablit_timer;
 577                 blitq->poll_timer.data = (unsigned long) blitq;
 578         }
 579 }
 580
 581 /*
 582  * Build all info and do all mappings required for a blit.
 583  */
 584
 585
 586 static int
 587 via_build_sg_info(drm_device_t *dev, drm_via_sg_info_t *vsg, drm_via_dmablit_t *xfer)
 588 {
 589         int draw = xfer->to_fb;
 590         int ret = 0;
 591
 592         vsg->direction = (draw) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
 593         vsg->bounce_buffer = NULL;
 594
 595         vsg->state = dr_via_sg_init;
 596
 597         if (xfer->num_lines <= 0 || xfer->line_length <= 0) {
 598                 DRM_ERROR("Zero size bitblt.\n");
 599                 return DRM_ERR(EINVAL);
 600         }
 601
 602         /*
 603          * Below check is a driver limitation, not a hardware one. We
 604          * don't want to lock unused pages, and don't want to incoporate the
 605          * extra logic of avoiding them. Make sure there are no.
 606          * (Not a big limitation anyway.)
 607          */
 608
 609         if ((xfer->mem_stride - xfer->line_length) >= PAGE_SIZE) {
 610                 DRM_ERROR("Too large system memory stride. Stride: %d, "
 611                           "Length: %d\n", xfer->mem_stride, xfer->line_length);
 612                 return DRM_ERR(EINVAL);
 613         }
 614
 615         if ((xfer->mem_stride == xfer->line_length) &&
 616            (xfer->fb_stride == xfer->line_length)) {
 617                 xfer->mem_stride *= xfer->num_lines;
 618                 xfer->line_length = xfer->mem_stride;
 619                 xfer->fb_stride = xfer->mem_stride;
 620                 xfer->num_lines = 1;
 621         }
 622
 623         /*
 624          * Don't lock an arbitrary large number of pages, since that causes a
 625          * DOS security hole.
 626          */
 627
 628         if (xfer->num_lines > 2048 || (xfer->num_lines*xfer->mem_stride > (2048*2048*4))) {
 629                 DRM_ERROR("Too large PCI DMA bitblt.\n");
 630                 return DRM_ERR(EINVAL);
 631         }
 632
 633         /*
 634          * we allow a negative fb stride to allow flipping of images in
 635          * transfer.
 636          */
 637
 638         if (xfer->mem_stride < xfer->line_length ||
 639                 abs(xfer->fb_stride) < xfer->line_length) {
 640                 DRM_ERROR("Invalid frame-buffer / memory stride.\n");
 641                 return DRM_ERR(EINVAL);
 642         }
 643
 644         /*
 645          * A hardware bug seems to be worked around if system memory addresses start on
 646          * 16 byte boundaries. This seems a bit restrictive however. VIA is contacted
 647          * about this. Meanwhile, impose the following restrictions:
 648          */
 649
 650 #ifdef VIA_BUGFREE
 651         if ((((unsigned long)xfer->mem_addr & 3) != ((unsigned long)xfer->fb_addr & 3)) ||
 652             ((xfer->num_lines > 1) && ((xfer->mem_stride & 3) != (xfer->fb_stride & 3)))) {
 653                 DRM_ERROR("Invalid DRM bitblt alignment.\n");
 654                 return DRM_ERR(EINVAL);
 655         }
 656 #else
 657         if ((((unsigned long)xfer->mem_addr & 15) ||
 658               ((unsigned long)xfer->fb_addr & 3)) ||
 659            ((xfer->num_lines > 1) &&
 660            ((xfer->mem_stride & 15) || (xfer->fb_stride & 3)))) {
 661                 DRM_ERROR("Invalid DRM bitblt alignment.\n");
 662                 return DRM_ERR(EINVAL);
 663         }
 664 #endif
 665
 666         if (0 != (ret = via_lock_all_dma_pages(vsg, xfer))) {
 667                 DRM_ERROR("Could not lock DMA pages.\n");
 668                 via_free_sg_info(dev->pdev, vsg);
 669                 return ret;
 670         }
 671
 672         via_map_blit_for_device(dev->pdev, xfer, vsg, 0);
 673         if (0 != (ret = via_alloc_desc_pages(vsg))) {
 674                 DRM_ERROR("Could not allocate DMA descriptor pages.\n");
 675                 via_free_sg_info(dev->pdev, vsg);
 676                 return ret;
 677         }
 678         via_map_blit_for_device(dev->pdev, xfer, vsg, 1);
 679
 680         return 0;
 681 }
 682
 683
 684 /*
 685  * Reserve one free slot in the blit queue. Will wait for one second for one
 686  * to become available. Otherwise -EBUSY is returned.
 687  */
 688
 689 static int
 690 via_dmablit_grab_slot(drm_via_blitq_t *blitq, int engine)
 691 {
 692         int ret=0;
 693         unsigned long irqsave;
 694
 695         DRM_DEBUG("Num free is %d\n", blitq->num_free);
 696         spin_lock_irqsave(&blitq->blit_lock, irqsave);
 697         while(blitq->num_free == 0) {
 698                 spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
 699
 700                 DRM_WAIT_ON(ret, blitq->busy_queue, DRM_HZ, blitq->num_free > 0);
 701                 if (ret) {
 702                         return (DRM_ERR(EINTR) == ret) ? DRM_ERR(EAGAIN) : ret;
 703                 }
 704
 705                 spin_lock_irqsave(&blitq->blit_lock, irqsave);
 706         }
 707
 708         blitq->num_free--;
 709         spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
 710
 711         return 0;
 712 }
 713
 714 /*
 715  * Hand back a free slot if we changed our mind.
 716  */
 717
 718 static void
 719 via_dmablit_release_slot(drm_via_blitq_t *blitq)
 720 {
 721         unsigned long irqsave;
 722
 723         spin_lock_irqsave(&blitq->blit_lock, irqsave);
 724         blitq->num_free++;
 725         spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
 726         DRM_WAKEUP( &blitq->busy_queue );
 727 }
 728
 729 /*
 730  * Grab a free slot. Build blit info and queue a blit.
 731  */
 732
 733
 734 static int
 735 via_dmablit(drm_device_t *dev, drm_via_dmablit_t *xfer)
 736 {
 737         drm_via_private_t *dev_priv = (drm_via_private_t *)dev->dev_private;
 738         drm_via_sg_info_t *vsg;
 739         drm_via_blitq_t *blitq;
 740         int ret;
 741         int engine;
 742         unsigned long irqsave;
 743
 744         if (dev_priv == NULL) {
 745                 DRM_ERROR("Called without initialization.\n");
 746                 return DRM_ERR(EINVAL);
 747         }
 748
 749         engine = (xfer->to_fb) ? 0 : 1;
 750         blitq = dev_priv->blit_queues + engine;
 751         if (0 != (ret = via_dmablit_grab_slot(blitq, engine))) {
 752                 return ret;
 753         }
 754         if (NULL == (vsg = kmalloc(sizeof(*vsg), GFP_KERNEL))) {
 755                 via_dmablit_release_slot(blitq);
 756                 return DRM_ERR(ENOMEM);
 757         }
 758         if (0 != (ret = via_build_sg_info(dev, vsg, xfer))) {
 759                 via_dmablit_release_slot(blitq);
 760                 kfree(vsg);
 761                 return ret;
 762         }
 763         spin_lock_irqsave(&blitq->blit_lock, irqsave);
 764
 765         blitq->blits[blitq->head++] = vsg;
 766         if (blitq->head >= VIA_NUM_BLIT_SLOTS)
 767                 blitq->head = 0;
 768         blitq->num_outstanding++;
 769         xfer->sync.sync_handle = ++blitq->cur_blit_handle;
 770
 771         spin_unlock_irqrestore(&blitq->blit_lock, irqsave);
 772         xfer->sync.engine = engine;
 773
 774         via_dmablit_handler(dev, engine, 0);
 775
 776         return 0;
 777 }
 778
 779 /*
 780  * Sync on a previously submitted blit. Note that the X server use signals extensively, and
 781  * that there is a very big probability that this IOCTL will be interrupted by a signal. In that
 782  * case it returns with -EAGAIN for the signal to be delivered.
 783  * The caller should then reissue the IOCTL. This is similar to what is being done for drmGetLock().
 784  */
 785
 786 int
 787 via_dma_blit_sync( DRM_IOCTL_ARGS )
 788 {
 789         drm_via_blitsync_t sync;
 790         int err;
 791         DRM_DEVICE;
 792
 793         DRM_COPY_FROM_USER_IOCTL(sync, (drm_via_blitsync_t *)data, sizeof(sync));
 794
 795         if (sync.engine >= VIA_NUM_BLIT_ENGINES)
 796                 return DRM_ERR(EINVAL);
 797
 798         err = via_dmablit_sync(dev, sync.sync_handle, sync.engine);
 799
 800         if (DRM_ERR(EINTR) == err)
 801                 err = DRM_ERR(EAGAIN);
 802
 803         return err;
 804 }
 805
 806
 807 /*
 808  * Queue a blit and hand back a handle to be used for sync. This IOCTL may be interrupted by a signal
 809  * while waiting for a free slot in the blit queue. In that case it returns with -EAGAIN and should
 810  * be reissued. See the above IOCTL code.
 811  */
 812
 813 int
 814 via_dma_blit( DRM_IOCTL_ARGS )
 815 {
 816         drm_via_dmablit_t xfer;
 817         int err;
 818         DRM_DEVICE;
 819
 820         DRM_COPY_FROM_USER_IOCTL(xfer, (drm_via_dmablit_t __user *)data, sizeof(xfer));
 821
 822         err = via_dmablit(dev, &xfer);
 823
 824         DRM_COPY_TO_USER_IOCTL((void __user *)data, xfer, sizeof(xfer));
 825
 826         return err;
 827 }