[PATCH] mark struct file_operations const 3
[linux-2.6.git] / drivers / char / drm / i830_dma.c
1 /* i830_dma.c -- DMA support for the I830 -*- linux-c -*-
2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3  *
4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28  *          Jeff Hartmann <jhartmann@valinux.com>
29  *          Keith Whitwell <keith@tungstengraphics.com>
30  *          Abraham vd Merwe <abraham@2d3d.co.za>
31  *
32  */
33
34 #include "drmP.h"
35 #include "drm.h"
36 #include "i830_drm.h"
37 #include "i830_drv.h"
38 #include <linux/interrupt.h>    /* For task queue support */
39 #include <linux/pagemap.h>      /* For FASTCALL on unlock_page() */
40 #include <linux/delay.h>
41 #include <asm/uaccess.h>
42
43 #define I830_BUF_FREE           2
44 #define I830_BUF_CLIENT         1
45 #define I830_BUF_HARDWARE       0
46
47 #define I830_BUF_UNMAPPED 0
48 #define I830_BUF_MAPPED   1
49
50 static drm_buf_t *i830_freelist_get(drm_device_t * dev)
51 {
52         drm_device_dma_t *dma = dev->dma;
53         int i;
54         int used;
55
56         /* Linear search might not be the best solution */
57
58         for (i = 0; i < dma->buf_count; i++) {
59                 drm_buf_t *buf = dma->buflist[i];
60                 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
61                 /* In use is already a pointer */
62                 used = cmpxchg(buf_priv->in_use, I830_BUF_FREE,
63                                I830_BUF_CLIENT);
64                 if (used == I830_BUF_FREE) {
65                         return buf;
66                 }
67         }
68         return NULL;
69 }
70
71 /* This should only be called if the buffer is not sent to the hardware
72  * yet, the hardware updates in use for us once its on the ring buffer.
73  */
74
75 static int i830_freelist_put(drm_device_t * dev, drm_buf_t * buf)
76 {
77         drm_i830_buf_priv_t *buf_priv = buf->dev_private;
78         int used;
79
80         /* In use is already a pointer */
81         used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE);
82         if (used != I830_BUF_CLIENT) {
83                 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
84                 return -EINVAL;
85         }
86
87         return 0;
88 }
89
90 static int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
91 {
92         drm_file_t *priv = filp->private_data;
93         drm_device_t *dev;
94         drm_i830_private_t *dev_priv;
95         drm_buf_t *buf;
96         drm_i830_buf_priv_t *buf_priv;
97
98         lock_kernel();
99         dev = priv->head->dev;
100         dev_priv = dev->dev_private;
101         buf = dev_priv->mmap_buffer;
102         buf_priv = buf->dev_private;
103
104         vma->vm_flags |= (VM_IO | VM_DONTCOPY);
105         vma->vm_file = filp;
106
107         buf_priv->currently_mapped = I830_BUF_MAPPED;
108         unlock_kernel();
109
110         if (io_remap_pfn_range(vma, vma->vm_start,
111                                vma->vm_pgoff,
112                                vma->vm_end - vma->vm_start, vma->vm_page_prot))
113                 return -EAGAIN;
114         return 0;
115 }
116
117 static const struct file_operations i830_buffer_fops = {
118         .open = drm_open,
119         .release = drm_release,
120         .ioctl = drm_ioctl,
121         .mmap = i830_mmap_buffers,
122         .fasync = drm_fasync,
123 };
124
125 static int i830_map_buffer(drm_buf_t * buf, struct file *filp)
126 {
127         drm_file_t *priv = filp->private_data;
128         drm_device_t *dev = priv->head->dev;
129         drm_i830_buf_priv_t *buf_priv = buf->dev_private;
130         drm_i830_private_t *dev_priv = dev->dev_private;
131         const struct file_operations *old_fops;
132         unsigned long virtual;
133         int retcode = 0;
134
135         if (buf_priv->currently_mapped == I830_BUF_MAPPED)
136                 return -EINVAL;
137
138         down_write(&current->mm->mmap_sem);
139         old_fops = filp->f_op;
140         filp->f_op = &i830_buffer_fops;
141         dev_priv->mmap_buffer = buf;
142         virtual = do_mmap(filp, 0, buf->total, PROT_READ | PROT_WRITE,
143                           MAP_SHARED, buf->bus_address);
144         dev_priv->mmap_buffer = NULL;
145         filp->f_op = old_fops;
146         if (IS_ERR((void *)virtual)) {  /* ugh */
147                 /* Real error */
148                 DRM_ERROR("mmap error\n");
149                 retcode = PTR_ERR((void *)virtual);
150                 buf_priv->virtual = NULL;
151         } else {
152                 buf_priv->virtual = (void __user *)virtual;
153         }
154         up_write(&current->mm->mmap_sem);
155
156         return retcode;
157 }
158
159 static int i830_unmap_buffer(drm_buf_t * buf)
160 {
161         drm_i830_buf_priv_t *buf_priv = buf->dev_private;
162         int retcode = 0;
163
164         if (buf_priv->currently_mapped != I830_BUF_MAPPED)
165                 return -EINVAL;
166
167         down_write(&current->mm->mmap_sem);
168         retcode = do_munmap(current->mm,
169                             (unsigned long)buf_priv->virtual,
170                             (size_t) buf->total);
171         up_write(&current->mm->mmap_sem);
172
173         buf_priv->currently_mapped = I830_BUF_UNMAPPED;
174         buf_priv->virtual = NULL;
175
176         return retcode;
177 }
178
179 static int i830_dma_get_buffer(drm_device_t * dev, drm_i830_dma_t * d,
180                                struct file *filp)
181 {
182         drm_buf_t *buf;
183         drm_i830_buf_priv_t *buf_priv;
184         int retcode = 0;
185
186         buf = i830_freelist_get(dev);
187         if (!buf) {
188                 retcode = -ENOMEM;
189                 DRM_DEBUG("retcode=%d\n", retcode);
190                 return retcode;
191         }
192
193         retcode = i830_map_buffer(buf, filp);
194         if (retcode) {
195                 i830_freelist_put(dev, buf);
196                 DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
197                 return retcode;
198         }
199         buf->filp = filp;
200         buf_priv = buf->dev_private;
201         d->granted = 1;
202         d->request_idx = buf->idx;
203         d->request_size = buf->total;
204         d->virtual = buf_priv->virtual;
205
206         return retcode;
207 }
208
209 static int i830_dma_cleanup(drm_device_t * dev)
210 {
211         drm_device_dma_t *dma = dev->dma;
212
213         /* Make sure interrupts are disabled here because the uninstall ioctl
214          * may not have been called from userspace and after dev_private
215          * is freed, it's too late.
216          */
217         if (dev->irq_enabled)
218                 drm_irq_uninstall(dev);
219
220         if (dev->dev_private) {
221                 int i;
222                 drm_i830_private_t *dev_priv =
223                     (drm_i830_private_t *) dev->dev_private;
224
225                 if (dev_priv->ring.virtual_start) {
226                         drm_core_ioremapfree(&dev_priv->ring.map, dev);
227                 }
228                 if (dev_priv->hw_status_page) {
229                         pci_free_consistent(dev->pdev, PAGE_SIZE,
230                                             dev_priv->hw_status_page,
231                                             dev_priv->dma_status_page);
232                         /* Need to rewrite hardware status page */
233                         I830_WRITE(0x02080, 0x1ffff000);
234                 }
235
236                 drm_free(dev->dev_private, sizeof(drm_i830_private_t),
237                          DRM_MEM_DRIVER);
238                 dev->dev_private = NULL;
239
240                 for (i = 0; i < dma->buf_count; i++) {
241                         drm_buf_t *buf = dma->buflist[i];
242                         drm_i830_buf_priv_t *buf_priv = buf->dev_private;
243                         if (buf_priv->kernel_virtual && buf->total)
244                                 drm_core_ioremapfree(&buf_priv->map, dev);
245                 }
246         }
247         return 0;
248 }
249
250 int i830_wait_ring(drm_device_t * dev, int n, const char *caller)
251 {
252         drm_i830_private_t *dev_priv = dev->dev_private;
253         drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
254         int iters = 0;
255         unsigned long end;
256         unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
257
258         end = jiffies + (HZ * 3);
259         while (ring->space < n) {
260                 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
261                 ring->space = ring->head - (ring->tail + 8);
262                 if (ring->space < 0)
263                         ring->space += ring->Size;
264
265                 if (ring->head != last_head) {
266                         end = jiffies + (HZ * 3);
267                         last_head = ring->head;
268                 }
269
270                 iters++;
271                 if (time_before(end, jiffies)) {
272                         DRM_ERROR("space: %d wanted %d\n", ring->space, n);
273                         DRM_ERROR("lockup\n");
274                         goto out_wait_ring;
275                 }
276                 udelay(1);
277                 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
278         }
279
280       out_wait_ring:
281         return iters;
282 }
283
284 static void i830_kernel_lost_context(drm_device_t * dev)
285 {
286         drm_i830_private_t *dev_priv = dev->dev_private;
287         drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
288
289         ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
290         ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
291         ring->space = ring->head - (ring->tail + 8);
292         if (ring->space < 0)
293                 ring->space += ring->Size;
294
295         if (ring->head == ring->tail)
296                 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY;
297 }
298
299 static int i830_freelist_init(drm_device_t * dev, drm_i830_private_t * dev_priv)
300 {
301         drm_device_dma_t *dma = dev->dma;
302         int my_idx = 36;
303         u32 *hw_status = (u32 *) (dev_priv->hw_status_page + my_idx);
304         int i;
305
306         if (dma->buf_count > 1019) {
307                 /* Not enough space in the status page for the freelist */
308                 return -EINVAL;
309         }
310
311         for (i = 0; i < dma->buf_count; i++) {
312                 drm_buf_t *buf = dma->buflist[i];
313                 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
314
315                 buf_priv->in_use = hw_status++;
316                 buf_priv->my_use_idx = my_idx;
317                 my_idx += 4;
318
319                 *buf_priv->in_use = I830_BUF_FREE;
320
321                 buf_priv->map.offset = buf->bus_address;
322                 buf_priv->map.size = buf->total;
323                 buf_priv->map.type = _DRM_AGP;
324                 buf_priv->map.flags = 0;
325                 buf_priv->map.mtrr = 0;
326
327                 drm_core_ioremap(&buf_priv->map, dev);
328                 buf_priv->kernel_virtual = buf_priv->map.handle;
329         }
330         return 0;
331 }
332
333 static int i830_dma_initialize(drm_device_t * dev,
334                                drm_i830_private_t * dev_priv,
335                                drm_i830_init_t * init)
336 {
337         struct list_head *list;
338
339         memset(dev_priv, 0, sizeof(drm_i830_private_t));
340
341         list_for_each(list, &dev->maplist->head) {
342                 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
343                 if (r_list->map &&
344                     r_list->map->type == _DRM_SHM &&
345                     r_list->map->flags & _DRM_CONTAINS_LOCK) {
346                         dev_priv->sarea_map = r_list->map;
347                         break;
348                 }
349         }
350
351         if (!dev_priv->sarea_map) {
352                 dev->dev_private = (void *)dev_priv;
353                 i830_dma_cleanup(dev);
354                 DRM_ERROR("can not find sarea!\n");
355                 return -EINVAL;
356         }
357         dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
358         if (!dev_priv->mmio_map) {
359                 dev->dev_private = (void *)dev_priv;
360                 i830_dma_cleanup(dev);
361                 DRM_ERROR("can not find mmio map!\n");
362                 return -EINVAL;
363         }
364         dev->agp_buffer_token = init->buffers_offset;
365         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
366         if (!dev->agp_buffer_map) {
367                 dev->dev_private = (void *)dev_priv;
368                 i830_dma_cleanup(dev);
369                 DRM_ERROR("can not find dma buffer map!\n");
370                 return -EINVAL;
371         }
372
373         dev_priv->sarea_priv = (drm_i830_sarea_t *)
374             ((u8 *) dev_priv->sarea_map->handle + init->sarea_priv_offset);
375
376         dev_priv->ring.Start = init->ring_start;
377         dev_priv->ring.End = init->ring_end;
378         dev_priv->ring.Size = init->ring_size;
379
380         dev_priv->ring.map.offset = dev->agp->base + init->ring_start;
381         dev_priv->ring.map.size = init->ring_size;
382         dev_priv->ring.map.type = _DRM_AGP;
383         dev_priv->ring.map.flags = 0;
384         dev_priv->ring.map.mtrr = 0;
385
386         drm_core_ioremap(&dev_priv->ring.map, dev);
387
388         if (dev_priv->ring.map.handle == NULL) {
389                 dev->dev_private = (void *)dev_priv;
390                 i830_dma_cleanup(dev);
391                 DRM_ERROR("can not ioremap virtual address for"
392                           " ring buffer\n");
393                 return DRM_ERR(ENOMEM);
394         }
395
396         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
397
398         dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
399
400         dev_priv->w = init->w;
401         dev_priv->h = init->h;
402         dev_priv->pitch = init->pitch;
403         dev_priv->back_offset = init->back_offset;
404         dev_priv->depth_offset = init->depth_offset;
405         dev_priv->front_offset = init->front_offset;
406
407         dev_priv->front_di1 = init->front_offset | init->pitch_bits;
408         dev_priv->back_di1 = init->back_offset | init->pitch_bits;
409         dev_priv->zi1 = init->depth_offset | init->pitch_bits;
410
411         DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1);
412         DRM_DEBUG("back_offset %x\n", dev_priv->back_offset);
413         DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1);
414         DRM_DEBUG("pitch_bits %x\n", init->pitch_bits);
415
416         dev_priv->cpp = init->cpp;
417         /* We are using separate values as placeholders for mechanisms for
418          * private backbuffer/depthbuffer usage.
419          */
420
421         dev_priv->back_pitch = init->back_pitch;
422         dev_priv->depth_pitch = init->depth_pitch;
423         dev_priv->do_boxes = 0;
424         dev_priv->use_mi_batchbuffer_start = 0;
425
426         /* Program Hardware Status Page */
427         dev_priv->hw_status_page =
428             pci_alloc_consistent(dev->pdev, PAGE_SIZE,
429                                  &dev_priv->dma_status_page);
430         if (!dev_priv->hw_status_page) {
431                 dev->dev_private = (void *)dev_priv;
432                 i830_dma_cleanup(dev);
433                 DRM_ERROR("Can not allocate hardware status page\n");
434                 return -ENOMEM;
435         }
436         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
437         DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
438
439         I830_WRITE(0x02080, dev_priv->dma_status_page);
440         DRM_DEBUG("Enabled hardware status page\n");
441
442         /* Now we need to init our freelist */
443         if (i830_freelist_init(dev, dev_priv) != 0) {
444                 dev->dev_private = (void *)dev_priv;
445                 i830_dma_cleanup(dev);
446                 DRM_ERROR("Not enough space in the status page for"
447                           " the freelist\n");
448                 return -ENOMEM;
449         }
450         dev->dev_private = (void *)dev_priv;
451
452         return 0;
453 }
454
455 static int i830_dma_init(struct inode *inode, struct file *filp,
456                          unsigned int cmd, unsigned long arg)
457 {
458         drm_file_t *priv = filp->private_data;
459         drm_device_t *dev = priv->head->dev;
460         drm_i830_private_t *dev_priv;
461         drm_i830_init_t init;
462         int retcode = 0;
463
464         if (copy_from_user(&init, (void *__user)arg, sizeof(init)))
465                 return -EFAULT;
466
467         switch (init.func) {
468         case I830_INIT_DMA:
469                 dev_priv = drm_alloc(sizeof(drm_i830_private_t),
470                                      DRM_MEM_DRIVER);
471                 if (dev_priv == NULL)
472                         return -ENOMEM;
473                 retcode = i830_dma_initialize(dev, dev_priv, &init);
474                 break;
475         case I830_CLEANUP_DMA:
476                 retcode = i830_dma_cleanup(dev);
477                 break;
478         default:
479                 retcode = -EINVAL;
480                 break;
481         }
482
483         return retcode;
484 }
485
486 #define GFX_OP_STIPPLE           ((0x3<<29)|(0x1d<<24)|(0x83<<16))
487 #define ST1_ENABLE               (1<<16)
488 #define ST1_MASK                 (0xffff)
489
490 /* Most efficient way to verify state for the i830 is as it is
491  * emitted.  Non-conformant state is silently dropped.
492  */
493 static void i830EmitContextVerified(drm_device_t * dev, unsigned int *code)
494 {
495         drm_i830_private_t *dev_priv = dev->dev_private;
496         int i, j = 0;
497         unsigned int tmp;
498         RING_LOCALS;
499
500         BEGIN_LP_RING(I830_CTX_SETUP_SIZE + 4);
501
502         for (i = 0; i < I830_CTXREG_BLENDCOLR0; i++) {
503                 tmp = code[i];
504                 if ((tmp & (7 << 29)) == CMD_3D &&
505                     (tmp & (0x1f << 24)) < (0x1d << 24)) {
506                         OUT_RING(tmp);
507                         j++;
508                 } else {
509                         DRM_ERROR("Skipping %d\n", i);
510                 }
511         }
512
513         OUT_RING(STATE3D_CONST_BLEND_COLOR_CMD);
514         OUT_RING(code[I830_CTXREG_BLENDCOLR]);
515         j += 2;
516
517         for (i = I830_CTXREG_VF; i < I830_CTXREG_MCSB0; i++) {
518                 tmp = code[i];
519                 if ((tmp & (7 << 29)) == CMD_3D &&
520                     (tmp & (0x1f << 24)) < (0x1d << 24)) {
521                         OUT_RING(tmp);
522                         j++;
523                 } else {
524                         DRM_ERROR("Skipping %d\n", i);
525                 }
526         }
527
528         OUT_RING(STATE3D_MAP_COORD_SETBIND_CMD);
529         OUT_RING(code[I830_CTXREG_MCSB1]);
530         j += 2;
531
532         if (j & 1)
533                 OUT_RING(0);
534
535         ADVANCE_LP_RING();
536 }
537
538 static void i830EmitTexVerified(drm_device_t * dev, unsigned int *code)
539 {
540         drm_i830_private_t *dev_priv = dev->dev_private;
541         int i, j = 0;
542         unsigned int tmp;
543         RING_LOCALS;
544
545         if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO ||
546             (code[I830_TEXREG_MI0] & ~(0xf * LOAD_TEXTURE_MAP0)) ==
547             (STATE3D_LOAD_STATE_IMMEDIATE_2 | 4)) {
548
549                 BEGIN_LP_RING(I830_TEX_SETUP_SIZE);
550
551                 OUT_RING(code[I830_TEXREG_MI0]);        /* TM0LI */
552                 OUT_RING(code[I830_TEXREG_MI1]);        /* TM0S0 */
553                 OUT_RING(code[I830_TEXREG_MI2]);        /* TM0S1 */
554                 OUT_RING(code[I830_TEXREG_MI3]);        /* TM0S2 */
555                 OUT_RING(code[I830_TEXREG_MI4]);        /* TM0S3 */
556                 OUT_RING(code[I830_TEXREG_MI5]);        /* TM0S4 */
557
558                 for (i = 6; i < I830_TEX_SETUP_SIZE; i++) {
559                         tmp = code[i];
560                         OUT_RING(tmp);
561                         j++;
562                 }
563
564                 if (j & 1)
565                         OUT_RING(0);
566
567                 ADVANCE_LP_RING();
568         } else
569                 printk("rejected packet %x\n", code[0]);
570 }
571
572 static void i830EmitTexBlendVerified(drm_device_t * dev,
573                                      unsigned int *code, unsigned int num)
574 {
575         drm_i830_private_t *dev_priv = dev->dev_private;
576         int i, j = 0;
577         unsigned int tmp;
578         RING_LOCALS;
579
580         if (!num)
581                 return;
582
583         BEGIN_LP_RING(num + 1);
584
585         for (i = 0; i < num; i++) {
586                 tmp = code[i];
587                 OUT_RING(tmp);
588                 j++;
589         }
590
591         if (j & 1)
592                 OUT_RING(0);
593
594         ADVANCE_LP_RING();
595 }
596
597 static void i830EmitTexPalette(drm_device_t * dev,
598                                unsigned int *palette, int number, int is_shared)
599 {
600         drm_i830_private_t *dev_priv = dev->dev_private;
601         int i;
602         RING_LOCALS;
603
604         return;
605
606         BEGIN_LP_RING(258);
607
608         if (is_shared == 1) {
609                 OUT_RING(CMD_OP_MAP_PALETTE_LOAD |
610                          MAP_PALETTE_NUM(0) | MAP_PALETTE_BOTH);
611         } else {
612                 OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number));
613         }
614         for (i = 0; i < 256; i++) {
615                 OUT_RING(palette[i]);
616         }
617         OUT_RING(0);
618         /* KW:  WHERE IS THE ADVANCE_LP_RING?  This is effectively a noop!
619          */
620 }
621
622 /* Need to do some additional checking when setting the dest buffer.
623  */
624 static void i830EmitDestVerified(drm_device_t * dev, unsigned int *code)
625 {
626         drm_i830_private_t *dev_priv = dev->dev_private;
627         unsigned int tmp;
628         RING_LOCALS;
629
630         BEGIN_LP_RING(I830_DEST_SETUP_SIZE + 10);
631
632         tmp = code[I830_DESTREG_CBUFADDR];
633         if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
634                 if (((int)outring) & 8) {
635                         OUT_RING(0);
636                         OUT_RING(0);
637                 }
638
639                 OUT_RING(CMD_OP_DESTBUFFER_INFO);
640                 OUT_RING(BUF_3D_ID_COLOR_BACK |
641                          BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) |
642                          BUF_3D_USE_FENCE);
643                 OUT_RING(tmp);
644                 OUT_RING(0);
645
646                 OUT_RING(CMD_OP_DESTBUFFER_INFO);
647                 OUT_RING(BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE |
648                          BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp));
649                 OUT_RING(dev_priv->zi1);
650                 OUT_RING(0);
651         } else {
652                 DRM_ERROR("bad di1 %x (allow %x or %x)\n",
653                           tmp, dev_priv->front_di1, dev_priv->back_di1);
654         }
655
656         /* invarient:
657          */
658
659         OUT_RING(GFX_OP_DESTBUFFER_VARS);
660         OUT_RING(code[I830_DESTREG_DV1]);
661
662         OUT_RING(GFX_OP_DRAWRECT_INFO);
663         OUT_RING(code[I830_DESTREG_DR1]);
664         OUT_RING(code[I830_DESTREG_DR2]);
665         OUT_RING(code[I830_DESTREG_DR3]);
666         OUT_RING(code[I830_DESTREG_DR4]);
667
668         /* Need to verify this */
669         tmp = code[I830_DESTREG_SENABLE];
670         if ((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) {
671                 OUT_RING(tmp);
672         } else {
673                 DRM_ERROR("bad scissor enable\n");
674                 OUT_RING(0);
675         }
676
677         OUT_RING(GFX_OP_SCISSOR_RECT);
678         OUT_RING(code[I830_DESTREG_SR1]);
679         OUT_RING(code[I830_DESTREG_SR2]);
680         OUT_RING(0);
681
682         ADVANCE_LP_RING();
683 }
684
685 static void i830EmitStippleVerified(drm_device_t * dev, unsigned int *code)
686 {
687         drm_i830_private_t *dev_priv = dev->dev_private;
688         RING_LOCALS;
689
690         BEGIN_LP_RING(2);
691         OUT_RING(GFX_OP_STIPPLE);
692         OUT_RING(code[1]);
693         ADVANCE_LP_RING();
694 }
695
696 static void i830EmitState(drm_device_t * dev)
697 {
698         drm_i830_private_t *dev_priv = dev->dev_private;
699         drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
700         unsigned int dirty = sarea_priv->dirty;
701
702         DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
703
704         if (dirty & I830_UPLOAD_BUFFERS) {
705                 i830EmitDestVerified(dev, sarea_priv->BufferState);
706                 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS;
707         }
708
709         if (dirty & I830_UPLOAD_CTX) {
710                 i830EmitContextVerified(dev, sarea_priv->ContextState);
711                 sarea_priv->dirty &= ~I830_UPLOAD_CTX;
712         }
713
714         if (dirty & I830_UPLOAD_TEX0) {
715                 i830EmitTexVerified(dev, sarea_priv->TexState[0]);
716                 sarea_priv->dirty &= ~I830_UPLOAD_TEX0;
717         }
718
719         if (dirty & I830_UPLOAD_TEX1) {
720                 i830EmitTexVerified(dev, sarea_priv->TexState[1]);
721                 sarea_priv->dirty &= ~I830_UPLOAD_TEX1;
722         }
723
724         if (dirty & I830_UPLOAD_TEXBLEND0) {
725                 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[0],
726                                          sarea_priv->TexBlendStateWordsUsed[0]);
727                 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0;
728         }
729
730         if (dirty & I830_UPLOAD_TEXBLEND1) {
731                 i830EmitTexBlendVerified(dev, sarea_priv->TexBlendState[1],
732                                          sarea_priv->TexBlendStateWordsUsed[1]);
733                 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1;
734         }
735
736         if (dirty & I830_UPLOAD_TEX_PALETTE_SHARED) {
737                 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1);
738         } else {
739                 if (dirty & I830_UPLOAD_TEX_PALETTE_N(0)) {
740                         i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0);
741                         sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0);
742                 }
743                 if (dirty & I830_UPLOAD_TEX_PALETTE_N(1)) {
744                         i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0);
745                         sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1);
746                 }
747
748                 /* 1.3:
749                  */
750 #if 0
751                 if (dirty & I830_UPLOAD_TEX_PALETTE_N(2)) {
752                         i830EmitTexPalette(dev, sarea_priv->Palette2[0], 0, 0);
753                         sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
754                 }
755                 if (dirty & I830_UPLOAD_TEX_PALETTE_N(3)) {
756                         i830EmitTexPalette(dev, sarea_priv->Palette2[1], 1, 0);
757                         sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
758                 }
759 #endif
760         }
761
762         /* 1.3:
763          */
764         if (dirty & I830_UPLOAD_STIPPLE) {
765                 i830EmitStippleVerified(dev, sarea_priv->StippleState);
766                 sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE;
767         }
768
769         if (dirty & I830_UPLOAD_TEX2) {
770                 i830EmitTexVerified(dev, sarea_priv->TexState2);
771                 sarea_priv->dirty &= ~I830_UPLOAD_TEX2;
772         }
773
774         if (dirty & I830_UPLOAD_TEX3) {
775                 i830EmitTexVerified(dev, sarea_priv->TexState3);
776                 sarea_priv->dirty &= ~I830_UPLOAD_TEX3;
777         }
778
779         if (dirty & I830_UPLOAD_TEXBLEND2) {
780                 i830EmitTexBlendVerified(dev,
781                                          sarea_priv->TexBlendState2,
782                                          sarea_priv->TexBlendStateWordsUsed2);
783
784                 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2;
785         }
786
787         if (dirty & I830_UPLOAD_TEXBLEND3) {
788                 i830EmitTexBlendVerified(dev,
789                                          sarea_priv->TexBlendState3,
790                                          sarea_priv->TexBlendStateWordsUsed3);
791                 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3;
792         }
793 }
794
795 /* ================================================================
796  * Performance monitoring functions
797  */
798
799 static void i830_fill_box(drm_device_t * dev,
800                           int x, int y, int w, int h, int r, int g, int b)
801 {
802         drm_i830_private_t *dev_priv = dev->dev_private;
803         u32 color;
804         unsigned int BR13, CMD;
805         RING_LOCALS;
806
807         BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1 << 24);
808         CMD = XY_COLOR_BLT_CMD;
809         x += dev_priv->sarea_priv->boxes[0].x1;
810         y += dev_priv->sarea_priv->boxes[0].y1;
811
812         if (dev_priv->cpp == 4) {
813                 BR13 |= (1 << 25);
814                 CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
815                 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
816         } else {
817                 color = (((r & 0xf8) << 8) |
818                          ((g & 0xfc) << 3) | ((b & 0xf8) >> 3));
819         }
820
821         BEGIN_LP_RING(6);
822         OUT_RING(CMD);
823         OUT_RING(BR13);
824         OUT_RING((y << 16) | x);
825         OUT_RING(((y + h) << 16) | (x + w));
826
827         if (dev_priv->current_page == 1) {
828                 OUT_RING(dev_priv->front_offset);
829         } else {
830                 OUT_RING(dev_priv->back_offset);
831         }
832
833         OUT_RING(color);
834         ADVANCE_LP_RING();
835 }
836
837 static void i830_cp_performance_boxes(drm_device_t * dev)
838 {
839         drm_i830_private_t *dev_priv = dev->dev_private;
840
841         /* Purple box for page flipping
842          */
843         if (dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP)
844                 i830_fill_box(dev, 4, 4, 8, 8, 255, 0, 255);
845
846         /* Red box if we have to wait for idle at any point
847          */
848         if (dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT)
849                 i830_fill_box(dev, 16, 4, 8, 8, 255, 0, 0);
850
851         /* Blue box: lost context?
852          */
853         if (dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT)
854                 i830_fill_box(dev, 28, 4, 8, 8, 0, 0, 255);
855
856         /* Yellow box for texture swaps
857          */
858         if (dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD)
859                 i830_fill_box(dev, 40, 4, 8, 8, 255, 255, 0);
860
861         /* Green box if hardware never idles (as far as we can tell)
862          */
863         if (!(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY))
864                 i830_fill_box(dev, 64, 4, 8, 8, 0, 255, 0);
865
866         /* Draw bars indicating number of buffers allocated
867          * (not a great measure, easily confused)
868          */
869         if (dev_priv->dma_used) {
870                 int bar = dev_priv->dma_used / 10240;
871                 if (bar > 100)
872                         bar = 100;
873                 if (bar < 1)
874                         bar = 1;
875                 i830_fill_box(dev, 4, 16, bar, 4, 196, 128, 128);
876                 dev_priv->dma_used = 0;
877         }
878
879         dev_priv->sarea_priv->perf_boxes = 0;
880 }
881
882 static void i830_dma_dispatch_clear(drm_device_t * dev, int flags,
883                                     unsigned int clear_color,
884                                     unsigned int clear_zval,
885                                     unsigned int clear_depthmask)
886 {
887         drm_i830_private_t *dev_priv = dev->dev_private;
888         drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
889         int nbox = sarea_priv->nbox;
890         drm_clip_rect_t *pbox = sarea_priv->boxes;
891         int pitch = dev_priv->pitch;
892         int cpp = dev_priv->cpp;
893         int i;
894         unsigned int BR13, CMD, D_CMD;
895         RING_LOCALS;
896
897         if (dev_priv->current_page == 1) {
898                 unsigned int tmp = flags;
899
900                 flags &= ~(I830_FRONT | I830_BACK);
901                 if (tmp & I830_FRONT)
902                         flags |= I830_BACK;
903                 if (tmp & I830_BACK)
904                         flags |= I830_FRONT;
905         }
906
907         i830_kernel_lost_context(dev);
908
909         switch (cpp) {
910         case 2:
911                 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
912                 D_CMD = CMD = XY_COLOR_BLT_CMD;
913                 break;
914         case 4:
915                 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24) | (1 << 25);
916                 CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA |
917                        XY_COLOR_BLT_WRITE_RGB);
918                 D_CMD = XY_COLOR_BLT_CMD;
919                 if (clear_depthmask & 0x00ffffff)
920                         D_CMD |= XY_COLOR_BLT_WRITE_RGB;
921                 if (clear_depthmask & 0xff000000)
922                         D_CMD |= XY_COLOR_BLT_WRITE_ALPHA;
923                 break;
924         default:
925                 BR13 = (0xF0 << 16) | (pitch * cpp) | (1 << 24);
926                 D_CMD = CMD = XY_COLOR_BLT_CMD;
927                 break;
928         }
929
930         if (nbox > I830_NR_SAREA_CLIPRECTS)
931                 nbox = I830_NR_SAREA_CLIPRECTS;
932
933         for (i = 0; i < nbox; i++, pbox++) {
934                 if (pbox->x1 > pbox->x2 ||
935                     pbox->y1 > pbox->y2 ||
936                     pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
937                         continue;
938
939                 if (flags & I830_FRONT) {
940                         DRM_DEBUG("clear front\n");
941                         BEGIN_LP_RING(6);
942                         OUT_RING(CMD);
943                         OUT_RING(BR13);
944                         OUT_RING((pbox->y1 << 16) | pbox->x1);
945                         OUT_RING((pbox->y2 << 16) | pbox->x2);
946                         OUT_RING(dev_priv->front_offset);
947                         OUT_RING(clear_color);
948                         ADVANCE_LP_RING();
949                 }
950
951                 if (flags & I830_BACK) {
952                         DRM_DEBUG("clear back\n");
953                         BEGIN_LP_RING(6);
954                         OUT_RING(CMD);
955                         OUT_RING(BR13);
956                         OUT_RING((pbox->y1 << 16) | pbox->x1);
957                         OUT_RING((pbox->y2 << 16) | pbox->x2);
958                         OUT_RING(dev_priv->back_offset);
959                         OUT_RING(clear_color);
960                         ADVANCE_LP_RING();
961                 }
962
963                 if (flags & I830_DEPTH) {
964                         DRM_DEBUG("clear depth\n");
965                         BEGIN_LP_RING(6);
966                         OUT_RING(D_CMD);
967                         OUT_RING(BR13);
968                         OUT_RING((pbox->y1 << 16) | pbox->x1);
969                         OUT_RING((pbox->y2 << 16) | pbox->x2);
970                         OUT_RING(dev_priv->depth_offset);
971                         OUT_RING(clear_zval);
972                         ADVANCE_LP_RING();
973                 }
974         }
975 }
976
977 static void i830_dma_dispatch_swap(drm_device_t * dev)
978 {
979         drm_i830_private_t *dev_priv = dev->dev_private;
980         drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
981         int nbox = sarea_priv->nbox;
982         drm_clip_rect_t *pbox = sarea_priv->boxes;
983         int pitch = dev_priv->pitch;
984         int cpp = dev_priv->cpp;
985         int i;
986         unsigned int CMD, BR13;
987         RING_LOCALS;
988
989         DRM_DEBUG("swapbuffers\n");
990
991         i830_kernel_lost_context(dev);
992
993         if (dev_priv->do_boxes)
994                 i830_cp_performance_boxes(dev);
995
996         switch (cpp) {
997         case 2:
998                 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
999                 CMD = XY_SRC_COPY_BLT_CMD;
1000                 break;
1001         case 4:
1002                 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24) | (1 << 25);
1003                 CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
1004                        XY_SRC_COPY_BLT_WRITE_RGB);
1005                 break;
1006         default:
1007                 BR13 = (pitch * cpp) | (0xCC << 16) | (1 << 24);
1008                 CMD = XY_SRC_COPY_BLT_CMD;
1009                 break;
1010         }
1011
1012         if (nbox > I830_NR_SAREA_CLIPRECTS)
1013                 nbox = I830_NR_SAREA_CLIPRECTS;
1014
1015         for (i = 0; i < nbox; i++, pbox++) {
1016                 if (pbox->x1 > pbox->x2 ||
1017                     pbox->y1 > pbox->y2 ||
1018                     pbox->x2 > dev_priv->w || pbox->y2 > dev_priv->h)
1019                         continue;
1020
1021                 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
1022                           pbox->x1, pbox->y1, pbox->x2, pbox->y2);
1023
1024                 BEGIN_LP_RING(8);
1025                 OUT_RING(CMD);
1026                 OUT_RING(BR13);
1027                 OUT_RING((pbox->y1 << 16) | pbox->x1);
1028                 OUT_RING((pbox->y2 << 16) | pbox->x2);
1029
1030                 if (dev_priv->current_page == 0)
1031                         OUT_RING(dev_priv->front_offset);
1032                 else
1033                         OUT_RING(dev_priv->back_offset);
1034
1035                 OUT_RING((pbox->y1 << 16) | pbox->x1);
1036                 OUT_RING(BR13 & 0xffff);
1037
1038                 if (dev_priv->current_page == 0)
1039                         OUT_RING(dev_priv->back_offset);
1040                 else
1041                         OUT_RING(dev_priv->front_offset);
1042
1043                 ADVANCE_LP_RING();
1044         }
1045 }
1046
1047 static void i830_dma_dispatch_flip(drm_device_t * dev)
1048 {
1049         drm_i830_private_t *dev_priv = dev->dev_private;
1050         RING_LOCALS;
1051
1052         DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
1053                   __FUNCTION__,
1054                   dev_priv->current_page,
1055                   dev_priv->sarea_priv->pf_current_page);
1056
1057         i830_kernel_lost_context(dev);
1058
1059         if (dev_priv->do_boxes) {
1060                 dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP;
1061                 i830_cp_performance_boxes(dev);
1062         }
1063
1064         BEGIN_LP_RING(2);
1065         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1066         OUT_RING(0);
1067         ADVANCE_LP_RING();
1068
1069         BEGIN_LP_RING(6);
1070         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
1071         OUT_RING(0);
1072         if (dev_priv->current_page == 0) {
1073                 OUT_RING(dev_priv->back_offset);
1074                 dev_priv->current_page = 1;
1075         } else {
1076                 OUT_RING(dev_priv->front_offset);
1077                 dev_priv->current_page = 0;
1078         }
1079         OUT_RING(0);
1080         ADVANCE_LP_RING();
1081
1082         BEGIN_LP_RING(2);
1083         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
1084         OUT_RING(0);
1085         ADVANCE_LP_RING();
1086
1087         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1088 }
1089
1090 static void i830_dma_dispatch_vertex(drm_device_t * dev,
1091                                      drm_buf_t * buf, int discard, int used)
1092 {
1093         drm_i830_private_t *dev_priv = dev->dev_private;
1094         drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1095         drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
1096         drm_clip_rect_t *box = sarea_priv->boxes;
1097         int nbox = sarea_priv->nbox;
1098         unsigned long address = (unsigned long)buf->bus_address;
1099         unsigned long start = address - dev->agp->base;
1100         int i = 0, u;
1101         RING_LOCALS;
1102
1103         i830_kernel_lost_context(dev);
1104
1105         if (nbox > I830_NR_SAREA_CLIPRECTS)
1106                 nbox = I830_NR_SAREA_CLIPRECTS;
1107
1108         if (discard) {
1109                 u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1110                             I830_BUF_HARDWARE);
1111                 if (u != I830_BUF_CLIENT) {
1112                         DRM_DEBUG("xxxx 2\n");
1113                 }
1114         }
1115
1116         if (used > 4 * 1023)
1117                 used = 0;
1118
1119         if (sarea_priv->dirty)
1120                 i830EmitState(dev);
1121
1122         DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
1123                   address, used, nbox);
1124
1125         dev_priv->counter++;
1126         DRM_DEBUG("dispatch counter : %ld\n", dev_priv->counter);
1127         DRM_DEBUG("i830_dma_dispatch\n");
1128         DRM_DEBUG("start : %lx\n", start);
1129         DRM_DEBUG("used : %d\n", used);
1130         DRM_DEBUG("start + used - 4 : %ld\n", start + used - 4);
1131
1132         if (buf_priv->currently_mapped == I830_BUF_MAPPED) {
1133                 u32 *vp = buf_priv->kernel_virtual;
1134
1135                 vp[0] = (GFX_OP_PRIMITIVE |
1136                          sarea_priv->vertex_prim | ((used / 4) - 2));
1137
1138                 if (dev_priv->use_mi_batchbuffer_start) {
1139                         vp[used / 4] = MI_BATCH_BUFFER_END;
1140                         used += 4;
1141                 }
1142
1143                 if (used & 4) {
1144                         vp[used / 4] = 0;
1145                         used += 4;
1146                 }
1147
1148                 i830_unmap_buffer(buf);
1149         }
1150
1151         if (used) {
1152                 do {
1153                         if (i < nbox) {
1154                                 BEGIN_LP_RING(6);
1155                                 OUT_RING(GFX_OP_DRAWRECT_INFO);
1156                                 OUT_RING(sarea_priv->
1157                                          BufferState[I830_DESTREG_DR1]);
1158                                 OUT_RING(box[i].x1 | (box[i].y1 << 16));
1159                                 OUT_RING(box[i].x2 | (box[i].y2 << 16));
1160                                 OUT_RING(sarea_priv->
1161                                          BufferState[I830_DESTREG_DR4]);
1162                                 OUT_RING(0);
1163                                 ADVANCE_LP_RING();
1164                         }
1165
1166                         if (dev_priv->use_mi_batchbuffer_start) {
1167                                 BEGIN_LP_RING(2);
1168                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
1169                                 OUT_RING(start | MI_BATCH_NON_SECURE);
1170                                 ADVANCE_LP_RING();
1171                         } else {
1172                                 BEGIN_LP_RING(4);
1173                                 OUT_RING(MI_BATCH_BUFFER);
1174                                 OUT_RING(start | MI_BATCH_NON_SECURE);
1175                                 OUT_RING(start + used - 4);
1176                                 OUT_RING(0);
1177                                 ADVANCE_LP_RING();
1178                         }
1179
1180                 } while (++i < nbox);
1181         }
1182
1183         if (discard) {
1184                 dev_priv->counter++;
1185
1186                 (void)cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1187                               I830_BUF_HARDWARE);
1188
1189                 BEGIN_LP_RING(8);
1190                 OUT_RING(CMD_STORE_DWORD_IDX);
1191                 OUT_RING(20);
1192                 OUT_RING(dev_priv->counter);
1193                 OUT_RING(CMD_STORE_DWORD_IDX);
1194                 OUT_RING(buf_priv->my_use_idx);
1195                 OUT_RING(I830_BUF_FREE);
1196                 OUT_RING(CMD_REPORT_HEAD);
1197                 OUT_RING(0);
1198                 ADVANCE_LP_RING();
1199         }
1200 }
1201
1202 static void i830_dma_quiescent(drm_device_t * dev)
1203 {
1204         drm_i830_private_t *dev_priv = dev->dev_private;
1205         RING_LOCALS;
1206
1207         i830_kernel_lost_context(dev);
1208
1209         BEGIN_LP_RING(4);
1210         OUT_RING(INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE);
1211         OUT_RING(CMD_REPORT_HEAD);
1212         OUT_RING(0);
1213         OUT_RING(0);
1214         ADVANCE_LP_RING();
1215
1216         i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
1217 }
1218
1219 static int i830_flush_queue(drm_device_t * dev)
1220 {
1221         drm_i830_private_t *dev_priv = dev->dev_private;
1222         drm_device_dma_t *dma = dev->dma;
1223         int i, ret = 0;
1224         RING_LOCALS;
1225
1226         i830_kernel_lost_context(dev);
1227
1228         BEGIN_LP_RING(2);
1229         OUT_RING(CMD_REPORT_HEAD);
1230         OUT_RING(0);
1231         ADVANCE_LP_RING();
1232
1233         i830_wait_ring(dev, dev_priv->ring.Size - 8, __FUNCTION__);
1234
1235         for (i = 0; i < dma->buf_count; i++) {
1236                 drm_buf_t *buf = dma->buflist[i];
1237                 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1238
1239                 int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE,
1240                                    I830_BUF_FREE);
1241
1242                 if (used == I830_BUF_HARDWARE)
1243                         DRM_DEBUG("reclaimed from HARDWARE\n");
1244                 if (used == I830_BUF_CLIENT)
1245                         DRM_DEBUG("still on client\n");
1246         }
1247
1248         return ret;
1249 }
1250
1251 /* Must be called with the lock held */
1252 static void i830_reclaim_buffers(drm_device_t * dev, struct file *filp)
1253 {
1254         drm_device_dma_t *dma = dev->dma;
1255         int i;
1256
1257         if (!dma)
1258                 return;
1259         if (!dev->dev_private)
1260                 return;
1261         if (!dma->buflist)
1262                 return;
1263
1264         i830_flush_queue(dev);
1265
1266         for (i = 0; i < dma->buf_count; i++) {
1267                 drm_buf_t *buf = dma->buflist[i];
1268                 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1269
1270                 if (buf->filp == filp && buf_priv) {
1271                         int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1272                                            I830_BUF_FREE);
1273
1274                         if (used == I830_BUF_CLIENT)
1275                                 DRM_DEBUG("reclaimed from client\n");
1276                         if (buf_priv->currently_mapped == I830_BUF_MAPPED)
1277                                 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
1278                 }
1279         }
1280 }
1281
1282 static int i830_flush_ioctl(struct inode *inode, struct file *filp,
1283                             unsigned int cmd, unsigned long arg)
1284 {
1285         drm_file_t *priv = filp->private_data;
1286         drm_device_t *dev = priv->head->dev;
1287
1288         LOCK_TEST_WITH_RETURN(dev, filp);
1289
1290         i830_flush_queue(dev);
1291         return 0;
1292 }
1293
1294 static int i830_dma_vertex(struct inode *inode, struct file *filp,
1295                            unsigned int cmd, unsigned long arg)
1296 {
1297         drm_file_t *priv = filp->private_data;
1298         drm_device_t *dev = priv->head->dev;
1299         drm_device_dma_t *dma = dev->dma;
1300         drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1301         u32 *hw_status = dev_priv->hw_status_page;
1302         drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1303             dev_priv->sarea_priv;
1304         drm_i830_vertex_t vertex;
1305
1306         if (copy_from_user
1307             (&vertex, (drm_i830_vertex_t __user *) arg, sizeof(vertex)))
1308                 return -EFAULT;
1309
1310         LOCK_TEST_WITH_RETURN(dev, filp);
1311
1312         DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
1313                   vertex.idx, vertex.used, vertex.discard);
1314
1315         if (vertex.idx < 0 || vertex.idx > dma->buf_count)
1316                 return -EINVAL;
1317
1318         i830_dma_dispatch_vertex(dev,
1319                                  dma->buflist[vertex.idx],
1320                                  vertex.discard, vertex.used);
1321
1322         sarea_priv->last_enqueue = dev_priv->counter - 1;
1323         sarea_priv->last_dispatch = (int)hw_status[5];
1324
1325         return 0;
1326 }
1327
1328 static int i830_clear_bufs(struct inode *inode, struct file *filp,
1329                            unsigned int cmd, unsigned long arg)
1330 {
1331         drm_file_t *priv = filp->private_data;
1332         drm_device_t *dev = priv->head->dev;
1333         drm_i830_clear_t clear;
1334
1335         if (copy_from_user
1336             (&clear, (drm_i830_clear_t __user *) arg, sizeof(clear)))
1337                 return -EFAULT;
1338
1339         LOCK_TEST_WITH_RETURN(dev, filp);
1340
1341         /* GH: Someone's doing nasty things... */
1342         if (!dev->dev_private) {
1343                 return -EINVAL;
1344         }
1345
1346         i830_dma_dispatch_clear(dev, clear.flags,
1347                                 clear.clear_color,
1348                                 clear.clear_depth, clear.clear_depthmask);
1349         return 0;
1350 }
1351
1352 static int i830_swap_bufs(struct inode *inode, struct file *filp,
1353                           unsigned int cmd, unsigned long arg)
1354 {
1355         drm_file_t *priv = filp->private_data;
1356         drm_device_t *dev = priv->head->dev;
1357
1358         DRM_DEBUG("i830_swap_bufs\n");
1359
1360         LOCK_TEST_WITH_RETURN(dev, filp);
1361
1362         i830_dma_dispatch_swap(dev);
1363         return 0;
1364 }
1365
1366 /* Not sure why this isn't set all the time:
1367  */
1368 static void i830_do_init_pageflip(drm_device_t * dev)
1369 {
1370         drm_i830_private_t *dev_priv = dev->dev_private;
1371
1372         DRM_DEBUG("%s\n", __FUNCTION__);
1373         dev_priv->page_flipping = 1;
1374         dev_priv->current_page = 0;
1375         dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1376 }
1377
1378 static int i830_do_cleanup_pageflip(drm_device_t * dev)
1379 {
1380         drm_i830_private_t *dev_priv = dev->dev_private;
1381
1382         DRM_DEBUG("%s\n", __FUNCTION__);
1383         if (dev_priv->current_page != 0)
1384                 i830_dma_dispatch_flip(dev);
1385
1386         dev_priv->page_flipping = 0;
1387         return 0;
1388 }
1389
1390 static int i830_flip_bufs(struct inode *inode, struct file *filp,
1391                           unsigned int cmd, unsigned long arg)
1392 {
1393         drm_file_t *priv = filp->private_data;
1394         drm_device_t *dev = priv->head->dev;
1395         drm_i830_private_t *dev_priv = dev->dev_private;
1396
1397         DRM_DEBUG("%s\n", __FUNCTION__);
1398
1399         LOCK_TEST_WITH_RETURN(dev, filp);
1400
1401         if (!dev_priv->page_flipping)
1402                 i830_do_init_pageflip(dev);
1403
1404         i830_dma_dispatch_flip(dev);
1405         return 0;
1406 }
1407
1408 static int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd,
1409                        unsigned long arg)
1410 {
1411         drm_file_t *priv = filp->private_data;
1412         drm_device_t *dev = priv->head->dev;
1413         drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1414         u32 *hw_status = dev_priv->hw_status_page;
1415         drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1416             dev_priv->sarea_priv;
1417
1418         sarea_priv->last_dispatch = (int)hw_status[5];
1419         return 0;
1420 }
1421
1422 static int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
1423                        unsigned long arg)
1424 {
1425         drm_file_t *priv = filp->private_data;
1426         drm_device_t *dev = priv->head->dev;
1427         int retcode = 0;
1428         drm_i830_dma_t d;
1429         drm_i830_private_t *dev_priv = (drm_i830_private_t *) dev->dev_private;
1430         u32 *hw_status = dev_priv->hw_status_page;
1431         drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1432             dev_priv->sarea_priv;
1433
1434         DRM_DEBUG("getbuf\n");
1435         if (copy_from_user(&d, (drm_i830_dma_t __user *) arg, sizeof(d)))
1436                 return -EFAULT;
1437
1438         LOCK_TEST_WITH_RETURN(dev, filp);
1439
1440         d.granted = 0;
1441
1442         retcode = i830_dma_get_buffer(dev, &d, filp);
1443
1444         DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
1445                   current->pid, retcode, d.granted);
1446
1447         if (copy_to_user((drm_dma_t __user *) arg, &d, sizeof(d)))
1448                 return -EFAULT;
1449         sarea_priv->last_dispatch = (int)hw_status[5];
1450
1451         return retcode;
1452 }
1453
1454 static int i830_copybuf(struct inode *inode,
1455                         struct file *filp, unsigned int cmd, unsigned long arg)
1456 {
1457         /* Never copy - 2.4.x doesn't need it */
1458         return 0;
1459 }
1460
1461 static int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
1462                        unsigned long arg)
1463 {
1464         return 0;
1465 }
1466
1467 static int i830_getparam(struct inode *inode, struct file *filp,
1468                          unsigned int cmd, unsigned long arg)
1469 {
1470         drm_file_t *priv = filp->private_data;
1471         drm_device_t *dev = priv->head->dev;
1472         drm_i830_private_t *dev_priv = dev->dev_private;
1473         drm_i830_getparam_t param;
1474         int value;
1475
1476         if (!dev_priv) {
1477                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1478                 return -EINVAL;
1479         }
1480
1481         if (copy_from_user
1482             (&param, (drm_i830_getparam_t __user *) arg, sizeof(param)))
1483                 return -EFAULT;
1484
1485         switch (param.param) {
1486         case I830_PARAM_IRQ_ACTIVE:
1487                 value = dev->irq_enabled;
1488                 break;
1489         default:
1490                 return -EINVAL;
1491         }
1492
1493         if (copy_to_user(param.value, &value, sizeof(int))) {
1494                 DRM_ERROR("copy_to_user\n");
1495                 return -EFAULT;
1496         }
1497
1498         return 0;
1499 }
1500
1501 static int i830_setparam(struct inode *inode, struct file *filp,
1502                          unsigned int cmd, unsigned long arg)
1503 {
1504         drm_file_t *priv = filp->private_data;
1505         drm_device_t *dev = priv->head->dev;
1506         drm_i830_private_t *dev_priv = dev->dev_private;
1507         drm_i830_setparam_t param;
1508
1509         if (!dev_priv) {
1510                 DRM_ERROR("%s called with no initialization\n", __FUNCTION__);
1511                 return -EINVAL;
1512         }
1513
1514         if (copy_from_user
1515             (&param, (drm_i830_setparam_t __user *) arg, sizeof(param)))
1516                 return -EFAULT;
1517
1518         switch (param.param) {
1519         case I830_SETPARAM_USE_MI_BATCHBUFFER_START:
1520                 dev_priv->use_mi_batchbuffer_start = param.value;
1521                 break;
1522         default:
1523                 return -EINVAL;
1524         }
1525
1526         return 0;
1527 }
1528
1529 int i830_driver_load(drm_device_t *dev, unsigned long flags)
1530 {
1531         /* i830 has 4 more counters */
1532         dev->counters += 4;
1533         dev->types[6] = _DRM_STAT_IRQ;
1534         dev->types[7] = _DRM_STAT_PRIMARY;
1535         dev->types[8] = _DRM_STAT_SECONDARY;
1536         dev->types[9] = _DRM_STAT_DMA;
1537
1538         return 0;
1539 }
1540
1541 void i830_driver_lastclose(drm_device_t * dev)
1542 {
1543         i830_dma_cleanup(dev);
1544 }
1545
1546 void i830_driver_preclose(drm_device_t * dev, DRMFILE filp)
1547 {
1548         if (dev->dev_private) {
1549                 drm_i830_private_t *dev_priv = dev->dev_private;
1550                 if (dev_priv->page_flipping) {
1551                         i830_do_cleanup_pageflip(dev);
1552                 }
1553         }
1554 }
1555
1556 void i830_driver_reclaim_buffers_locked(drm_device_t * dev, struct file *filp)
1557 {
1558         i830_reclaim_buffers(dev, filp);
1559 }
1560
1561 int i830_driver_dma_quiescent(drm_device_t * dev)
1562 {
1563         i830_dma_quiescent(dev);
1564         return 0;
1565 }
1566
1567 drm_ioctl_desc_t i830_ioctls[] = {
1568         [DRM_IOCTL_NR(DRM_I830_INIT)] = {i830_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY},
1569         [DRM_IOCTL_NR(DRM_I830_VERTEX)] = {i830_dma_vertex, DRM_AUTH},
1570         [DRM_IOCTL_NR(DRM_I830_CLEAR)] = {i830_clear_bufs, DRM_AUTH},
1571         [DRM_IOCTL_NR(DRM_I830_FLUSH)] = {i830_flush_ioctl, DRM_AUTH},
1572         [DRM_IOCTL_NR(DRM_I830_GETAGE)] = {i830_getage, DRM_AUTH},
1573         [DRM_IOCTL_NR(DRM_I830_GETBUF)] = {i830_getbuf, DRM_AUTH},
1574         [DRM_IOCTL_NR(DRM_I830_SWAP)] = {i830_swap_bufs, DRM_AUTH},
1575         [DRM_IOCTL_NR(DRM_I830_COPY)] = {i830_copybuf, DRM_AUTH},
1576         [DRM_IOCTL_NR(DRM_I830_DOCOPY)] = {i830_docopy, DRM_AUTH},
1577         [DRM_IOCTL_NR(DRM_I830_FLIP)] = {i830_flip_bufs, DRM_AUTH},
1578         [DRM_IOCTL_NR(DRM_I830_IRQ_EMIT)] = {i830_irq_emit, DRM_AUTH},
1579         [DRM_IOCTL_NR(DRM_I830_IRQ_WAIT)] = {i830_irq_wait, DRM_AUTH},
1580         [DRM_IOCTL_NR(DRM_I830_GETPARAM)] = {i830_getparam, DRM_AUTH},
1581         [DRM_IOCTL_NR(DRM_I830_SETPARAM)] = {i830_setparam, DRM_AUTH}
1582 };
1583
1584 int i830_max_ioctl = DRM_ARRAY_SIZE(i830_ioctls);
1585
1586 /**
1587  * Determine if the device really is AGP or not.
1588  *
1589  * All Intel graphics chipsets are treated as AGP, even if they are really
1590  * PCI-e.
1591  *
1592  * \param dev   The device to be tested.
1593  *
1594  * \returns
1595  * A value of 1 is always retured to indictate every i8xx is AGP.
1596  */
1597 int i830_driver_device_is_agp(drm_device_t * dev)
1598 {
1599         return 1;
1600 }