cciss: Fix scsi tape io with more than 255 scatter gather elements
[linux-2.6.git] / drivers / block / nvme.c
1 /*
2  * NVM Express device driver
3  * Copyright (c) 2011, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  */
18
19 #include <linux/nvme.h>
20 #include <linux/bio.h>
21 #include <linux/bitops.h>
22 #include <linux/blkdev.h>
23 #include <linux/delay.h>
24 #include <linux/errno.h>
25 #include <linux/fs.h>
26 #include <linux/genhd.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kthread.h>
33 #include <linux/kernel.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/version.h>
43
44 #include <asm-generic/io-64-nonatomic-lo-hi.h>
45
46 #define NVME_Q_DEPTH 1024
47 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
48 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
49 #define NVME_MINORS 64
50 #define NVME_IO_TIMEOUT (5 * HZ)
51 #define ADMIN_TIMEOUT   (60 * HZ)
52
53 static int nvme_major;
54 module_param(nvme_major, int, 0);
55
56 static int use_threaded_interrupts;
57 module_param(use_threaded_interrupts, int, 0);
58
59 static DEFINE_SPINLOCK(dev_list_lock);
60 static LIST_HEAD(dev_list);
61 static struct task_struct *nvme_thread;
62
63 /*
64  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
65  */
66 struct nvme_dev {
67         struct list_head node;
68         struct nvme_queue **queues;
69         u32 __iomem *dbs;
70         struct pci_dev *pci_dev;
71         struct dma_pool *prp_page_pool;
72         struct dma_pool *prp_small_pool;
73         int instance;
74         int queue_count;
75         int db_stride;
76         u32 ctrl_config;
77         struct msix_entry *entry;
78         struct nvme_bar __iomem *bar;
79         struct list_head namespaces;
80         char serial[20];
81         char model[40];
82         char firmware_rev[8];
83 };
84
85 /*
86  * An NVM Express namespace is equivalent to a SCSI LUN
87  */
88 struct nvme_ns {
89         struct list_head list;
90
91         struct nvme_dev *dev;
92         struct request_queue *queue;
93         struct gendisk *disk;
94
95         int ns_id;
96         int lba_shift;
97 };
98
99 /*
100  * An NVM Express queue.  Each device has at least two (one for admin
101  * commands and one for I/O commands).
102  */
103 struct nvme_queue {
104         struct device *q_dmadev;
105         struct nvme_dev *dev;
106         spinlock_t q_lock;
107         struct nvme_command *sq_cmds;
108         volatile struct nvme_completion *cqes;
109         dma_addr_t sq_dma_addr;
110         dma_addr_t cq_dma_addr;
111         wait_queue_head_t sq_full;
112         wait_queue_t sq_cong_wait;
113         struct bio_list sq_cong;
114         u32 __iomem *q_db;
115         u16 q_depth;
116         u16 cq_vector;
117         u16 sq_head;
118         u16 sq_tail;
119         u16 cq_head;
120         u16 cq_phase;
121         unsigned long cmdid_data[];
122 };
123
124 /*
125  * Check we didin't inadvertently grow the command struct
126  */
127 static inline void _nvme_check_size(void)
128 {
129         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
130         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
131         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
132         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
133         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
134         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
135         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
136         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
137         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
138 }
139
140 typedef void (*nvme_completion_fn)(struct nvme_dev *, void *,
141                                                 struct nvme_completion *);
142
143 struct nvme_cmd_info {
144         nvme_completion_fn fn;
145         void *ctx;
146         unsigned long timeout;
147 };
148
149 static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
150 {
151         return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
152 }
153
154 /**
155  * alloc_cmdid() - Allocate a Command ID
156  * @nvmeq: The queue that will be used for this command
157  * @ctx: A pointer that will be passed to the handler
158  * @handler: The function to call on completion
159  *
160  * Allocate a Command ID for a queue.  The data passed in will
161  * be passed to the completion handler.  This is implemented by using
162  * the bottom two bits of the ctx pointer to store the handler ID.
163  * Passing in a pointer that's not 4-byte aligned will cause a BUG.
164  * We can change this if it becomes a problem.
165  *
166  * May be called with local interrupts disabled and the q_lock held,
167  * or with interrupts enabled and no locks held.
168  */
169 static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
170                                 nvme_completion_fn handler, unsigned timeout)
171 {
172         int depth = nvmeq->q_depth - 1;
173         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
174         int cmdid;
175
176         do {
177                 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
178                 if (cmdid >= depth)
179                         return -EBUSY;
180         } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
181
182         info[cmdid].fn = handler;
183         info[cmdid].ctx = ctx;
184         info[cmdid].timeout = jiffies + timeout;
185         return cmdid;
186 }
187
188 static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
189                                 nvme_completion_fn handler, unsigned timeout)
190 {
191         int cmdid;
192         wait_event_killable(nvmeq->sq_full,
193                 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
194         return (cmdid < 0) ? -EINTR : cmdid;
195 }
196
197 /* Special values must be less than 0x1000 */
198 #define CMD_CTX_BASE            ((void *)POISON_POINTER_DELTA)
199 #define CMD_CTX_CANCELLED       (0x30C + CMD_CTX_BASE)
200 #define CMD_CTX_COMPLETED       (0x310 + CMD_CTX_BASE)
201 #define CMD_CTX_INVALID         (0x314 + CMD_CTX_BASE)
202 #define CMD_CTX_FLUSH           (0x318 + CMD_CTX_BASE)
203
204 static void special_completion(struct nvme_dev *dev, void *ctx,
205                                                 struct nvme_completion *cqe)
206 {
207         if (ctx == CMD_CTX_CANCELLED)
208                 return;
209         if (ctx == CMD_CTX_FLUSH)
210                 return;
211         if (ctx == CMD_CTX_COMPLETED) {
212                 dev_warn(&dev->pci_dev->dev,
213                                 "completed id %d twice on queue %d\n",
214                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
215                 return;
216         }
217         if (ctx == CMD_CTX_INVALID) {
218                 dev_warn(&dev->pci_dev->dev,
219                                 "invalid id %d completed on queue %d\n",
220                                 cqe->command_id, le16_to_cpup(&cqe->sq_id));
221                 return;
222         }
223
224         dev_warn(&dev->pci_dev->dev, "Unknown special completion %p\n", ctx);
225 }
226
227 /*
228  * Called with local interrupts disabled and the q_lock held.  May not sleep.
229  */
230 static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
231                                                 nvme_completion_fn *fn)
232 {
233         void *ctx;
234         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
235
236         if (cmdid >= nvmeq->q_depth) {
237                 *fn = special_completion;
238                 return CMD_CTX_INVALID;
239         }
240         *fn = info[cmdid].fn;
241         ctx = info[cmdid].ctx;
242         info[cmdid].fn = special_completion;
243         info[cmdid].ctx = CMD_CTX_COMPLETED;
244         clear_bit(cmdid, nvmeq->cmdid_data);
245         wake_up(&nvmeq->sq_full);
246         return ctx;
247 }
248
249 static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
250                                                 nvme_completion_fn *fn)
251 {
252         void *ctx;
253         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
254         if (fn)
255                 *fn = info[cmdid].fn;
256         ctx = info[cmdid].ctx;
257         info[cmdid].fn = special_completion;
258         info[cmdid].ctx = CMD_CTX_CANCELLED;
259         return ctx;
260 }
261
262 static struct nvme_queue *get_nvmeq(struct nvme_dev *dev)
263 {
264         return dev->queues[get_cpu() + 1];
265 }
266
267 static void put_nvmeq(struct nvme_queue *nvmeq)
268 {
269         put_cpu();
270 }
271
272 /**
273  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
274  * @nvmeq: The queue to use
275  * @cmd: The command to send
276  *
277  * Safe to use from interrupt context
278  */
279 static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
280 {
281         unsigned long flags;
282         u16 tail;
283         spin_lock_irqsave(&nvmeq->q_lock, flags);
284         tail = nvmeq->sq_tail;
285         memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
286         if (++tail == nvmeq->q_depth)
287                 tail = 0;
288         writel(tail, nvmeq->q_db);
289         nvmeq->sq_tail = tail;
290         spin_unlock_irqrestore(&nvmeq->q_lock, flags);
291
292         return 0;
293 }
294
295 /*
296  * The nvme_iod describes the data in an I/O, including the list of PRP
297  * entries.  You can't see it in this data structure because C doesn't let
298  * me express that.  Use nvme_alloc_iod to ensure there's enough space
299  * allocated to store the PRP list.
300  */
301 struct nvme_iod {
302         void *private;          /* For the use of the submitter of the I/O */
303         int npages;             /* In the PRP list. 0 means small pool in use */
304         int offset;             /* Of PRP list */
305         int nents;              /* Used in scatterlist */
306         int length;             /* Of data, in bytes */
307         dma_addr_t first_dma;
308         struct scatterlist sg[0];
309 };
310
311 static __le64 **iod_list(struct nvme_iod *iod)
312 {
313         return ((void *)iod) + iod->offset;
314 }
315
316 /*
317  * Will slightly overestimate the number of pages needed.  This is OK
318  * as it only leads to a small amount of wasted memory for the lifetime of
319  * the I/O.
320  */
321 static int nvme_npages(unsigned size)
322 {
323         unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
324         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
325 }
326
327 static struct nvme_iod *
328 nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
329 {
330         struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
331                                 sizeof(__le64 *) * nvme_npages(nbytes) +
332                                 sizeof(struct scatterlist) * nseg, gfp);
333
334         if (iod) {
335                 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
336                 iod->npages = -1;
337                 iod->length = nbytes;
338         }
339
340         return iod;
341 }
342
343 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
344 {
345         const int last_prp = PAGE_SIZE / 8 - 1;
346         int i;
347         __le64 **list = iod_list(iod);
348         dma_addr_t prp_dma = iod->first_dma;
349
350         if (iod->npages == 0)
351                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
352         for (i = 0; i < iod->npages; i++) {
353                 __le64 *prp_list = list[i];
354                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
355                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
356                 prp_dma = next_prp_dma;
357         }
358         kfree(iod);
359 }
360
361 static void requeue_bio(struct nvme_dev *dev, struct bio *bio)
362 {
363         struct nvme_queue *nvmeq = get_nvmeq(dev);
364         if (bio_list_empty(&nvmeq->sq_cong))
365                 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
366         bio_list_add(&nvmeq->sq_cong, bio);
367         put_nvmeq(nvmeq);
368         wake_up_process(nvme_thread);
369 }
370
371 static void bio_completion(struct nvme_dev *dev, void *ctx,
372                                                 struct nvme_completion *cqe)
373 {
374         struct nvme_iod *iod = ctx;
375         struct bio *bio = iod->private;
376         u16 status = le16_to_cpup(&cqe->status) >> 1;
377
378         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
379                         bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
380         nvme_free_iod(dev, iod);
381         if (status) {
382                 bio_endio(bio, -EIO);
383         } else if (bio->bi_vcnt > bio->bi_idx) {
384                 requeue_bio(dev, bio);
385         } else {
386                 bio_endio(bio, 0);
387         }
388 }
389
390 /* length is in bytes.  gfp flags indicates whether we may sleep. */
391 static int nvme_setup_prps(struct nvme_dev *dev,
392                         struct nvme_common_command *cmd, struct nvme_iod *iod,
393                         int total_len, gfp_t gfp)
394 {
395         struct dma_pool *pool;
396         int length = total_len;
397         struct scatterlist *sg = iod->sg;
398         int dma_len = sg_dma_len(sg);
399         u64 dma_addr = sg_dma_address(sg);
400         int offset = offset_in_page(dma_addr);
401         __le64 *prp_list;
402         __le64 **list = iod_list(iod);
403         dma_addr_t prp_dma;
404         int nprps, i;
405
406         cmd->prp1 = cpu_to_le64(dma_addr);
407         length -= (PAGE_SIZE - offset);
408         if (length <= 0)
409                 return total_len;
410
411         dma_len -= (PAGE_SIZE - offset);
412         if (dma_len) {
413                 dma_addr += (PAGE_SIZE - offset);
414         } else {
415                 sg = sg_next(sg);
416                 dma_addr = sg_dma_address(sg);
417                 dma_len = sg_dma_len(sg);
418         }
419
420         if (length <= PAGE_SIZE) {
421                 cmd->prp2 = cpu_to_le64(dma_addr);
422                 return total_len;
423         }
424
425         nprps = DIV_ROUND_UP(length, PAGE_SIZE);
426         if (nprps <= (256 / 8)) {
427                 pool = dev->prp_small_pool;
428                 iod->npages = 0;
429         } else {
430                 pool = dev->prp_page_pool;
431                 iod->npages = 1;
432         }
433
434         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
435         if (!prp_list) {
436                 cmd->prp2 = cpu_to_le64(dma_addr);
437                 iod->npages = -1;
438                 return (total_len - length) + PAGE_SIZE;
439         }
440         list[0] = prp_list;
441         iod->first_dma = prp_dma;
442         cmd->prp2 = cpu_to_le64(prp_dma);
443         i = 0;
444         for (;;) {
445                 if (i == PAGE_SIZE / 8) {
446                         __le64 *old_prp_list = prp_list;
447                         prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
448                         if (!prp_list)
449                                 return total_len - length;
450                         list[iod->npages++] = prp_list;
451                         prp_list[0] = old_prp_list[i - 1];
452                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
453                         i = 1;
454                 }
455                 prp_list[i++] = cpu_to_le64(dma_addr);
456                 dma_len -= PAGE_SIZE;
457                 dma_addr += PAGE_SIZE;
458                 length -= PAGE_SIZE;
459                 if (length <= 0)
460                         break;
461                 if (dma_len > 0)
462                         continue;
463                 BUG_ON(dma_len < 0);
464                 sg = sg_next(sg);
465                 dma_addr = sg_dma_address(sg);
466                 dma_len = sg_dma_len(sg);
467         }
468
469         return total_len;
470 }
471
472 /* NVMe scatterlists require no holes in the virtual address */
473 #define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2)   ((vec2)->bv_offset || \
474                         (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
475
476 static int nvme_map_bio(struct device *dev, struct nvme_iod *iod,
477                 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
478 {
479         struct bio_vec *bvec, *bvprv = NULL;
480         struct scatterlist *sg = NULL;
481         int i, old_idx, length = 0, nsegs = 0;
482
483         sg_init_table(iod->sg, psegs);
484         old_idx = bio->bi_idx;
485         bio_for_each_segment(bvec, bio, i) {
486                 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
487                         sg->length += bvec->bv_len;
488                 } else {
489                         if (bvprv && BIOVEC_NOT_VIRT_MERGEABLE(bvprv, bvec))
490                                 break;
491                         sg = sg ? sg + 1 : iod->sg;
492                         sg_set_page(sg, bvec->bv_page, bvec->bv_len,
493                                                         bvec->bv_offset);
494                         nsegs++;
495                 }
496                 length += bvec->bv_len;
497                 bvprv = bvec;
498         }
499         bio->bi_idx = i;
500         iod->nents = nsegs;
501         sg_mark_end(sg);
502         if (dma_map_sg(dev, iod->sg, iod->nents, dma_dir) == 0) {
503                 bio->bi_idx = old_idx;
504                 return -ENOMEM;
505         }
506         return length;
507 }
508
509 static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
510                                                                 int cmdid)
511 {
512         struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
513
514         memset(cmnd, 0, sizeof(*cmnd));
515         cmnd->common.opcode = nvme_cmd_flush;
516         cmnd->common.command_id = cmdid;
517         cmnd->common.nsid = cpu_to_le32(ns->ns_id);
518
519         if (++nvmeq->sq_tail == nvmeq->q_depth)
520                 nvmeq->sq_tail = 0;
521         writel(nvmeq->sq_tail, nvmeq->q_db);
522
523         return 0;
524 }
525
526 static int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
527 {
528         int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
529                                         special_completion, NVME_IO_TIMEOUT);
530         if (unlikely(cmdid < 0))
531                 return cmdid;
532
533         return nvme_submit_flush(nvmeq, ns, cmdid);
534 }
535
536 /*
537  * Called with local interrupts disabled and the q_lock held.  May not sleep.
538  */
539 static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
540                                                                 struct bio *bio)
541 {
542         struct nvme_command *cmnd;
543         struct nvme_iod *iod;
544         enum dma_data_direction dma_dir;
545         int cmdid, length, result = -ENOMEM;
546         u16 control;
547         u32 dsmgmt;
548         int psegs = bio_phys_segments(ns->queue, bio);
549
550         if ((bio->bi_rw & REQ_FLUSH) && psegs) {
551                 result = nvme_submit_flush_data(nvmeq, ns);
552                 if (result)
553                         return result;
554         }
555
556         iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
557         if (!iod)
558                 goto nomem;
559         iod->private = bio;
560
561         result = -EBUSY;
562         cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
563         if (unlikely(cmdid < 0))
564                 goto free_iod;
565
566         if ((bio->bi_rw & REQ_FLUSH) && !psegs)
567                 return nvme_submit_flush(nvmeq, ns, cmdid);
568
569         control = 0;
570         if (bio->bi_rw & REQ_FUA)
571                 control |= NVME_RW_FUA;
572         if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
573                 control |= NVME_RW_LR;
574
575         dsmgmt = 0;
576         if (bio->bi_rw & REQ_RAHEAD)
577                 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
578
579         cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
580
581         memset(cmnd, 0, sizeof(*cmnd));
582         if (bio_data_dir(bio)) {
583                 cmnd->rw.opcode = nvme_cmd_write;
584                 dma_dir = DMA_TO_DEVICE;
585         } else {
586                 cmnd->rw.opcode = nvme_cmd_read;
587                 dma_dir = DMA_FROM_DEVICE;
588         }
589
590         result = nvme_map_bio(nvmeq->q_dmadev, iod, bio, dma_dir, psegs);
591         if (result < 0)
592                 goto free_iod;
593         length = result;
594
595         cmnd->rw.command_id = cmdid;
596         cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
597         length = nvme_setup_prps(nvmeq->dev, &cmnd->common, iod, length,
598                                                                 GFP_ATOMIC);
599         cmnd->rw.slba = cpu_to_le64(bio->bi_sector >> (ns->lba_shift - 9));
600         cmnd->rw.length = cpu_to_le16((length >> ns->lba_shift) - 1);
601         cmnd->rw.control = cpu_to_le16(control);
602         cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
603
604         bio->bi_sector += length >> 9;
605
606         if (++nvmeq->sq_tail == nvmeq->q_depth)
607                 nvmeq->sq_tail = 0;
608         writel(nvmeq->sq_tail, nvmeq->q_db);
609
610         return 0;
611
612  free_iod:
613         nvme_free_iod(nvmeq->dev, iod);
614  nomem:
615         return result;
616 }
617
618 static void nvme_make_request(struct request_queue *q, struct bio *bio)
619 {
620         struct nvme_ns *ns = q->queuedata;
621         struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
622         int result = -EBUSY;
623
624         spin_lock_irq(&nvmeq->q_lock);
625         if (bio_list_empty(&nvmeq->sq_cong))
626                 result = nvme_submit_bio_queue(nvmeq, ns, bio);
627         if (unlikely(result)) {
628                 if (bio_list_empty(&nvmeq->sq_cong))
629                         add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
630                 bio_list_add(&nvmeq->sq_cong, bio);
631         }
632
633         spin_unlock_irq(&nvmeq->q_lock);
634         put_nvmeq(nvmeq);
635 }
636
637 static irqreturn_t nvme_process_cq(struct nvme_queue *nvmeq)
638 {
639         u16 head, phase;
640
641         head = nvmeq->cq_head;
642         phase = nvmeq->cq_phase;
643
644         for (;;) {
645                 void *ctx;
646                 nvme_completion_fn fn;
647                 struct nvme_completion cqe = nvmeq->cqes[head];
648                 if ((le16_to_cpu(cqe.status) & 1) != phase)
649                         break;
650                 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
651                 if (++head == nvmeq->q_depth) {
652                         head = 0;
653                         phase = !phase;
654                 }
655
656                 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
657                 fn(nvmeq->dev, ctx, &cqe);
658         }
659
660         /* If the controller ignores the cq head doorbell and continuously
661          * writes to the queue, it is theoretically possible to wrap around
662          * the queue twice and mistakenly return IRQ_NONE.  Linux only
663          * requires that 0.1% of your interrupts are handled, so this isn't
664          * a big problem.
665          */
666         if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
667                 return IRQ_NONE;
668
669         writel(head, nvmeq->q_db + (1 << nvmeq->dev->db_stride));
670         nvmeq->cq_head = head;
671         nvmeq->cq_phase = phase;
672
673         return IRQ_HANDLED;
674 }
675
676 static irqreturn_t nvme_irq(int irq, void *data)
677 {
678         irqreturn_t result;
679         struct nvme_queue *nvmeq = data;
680         spin_lock(&nvmeq->q_lock);
681         result = nvme_process_cq(nvmeq);
682         spin_unlock(&nvmeq->q_lock);
683         return result;
684 }
685
686 static irqreturn_t nvme_irq_check(int irq, void *data)
687 {
688         struct nvme_queue *nvmeq = data;
689         struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
690         if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
691                 return IRQ_NONE;
692         return IRQ_WAKE_THREAD;
693 }
694
695 static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
696 {
697         spin_lock_irq(&nvmeq->q_lock);
698         cancel_cmdid(nvmeq, cmdid, NULL);
699         spin_unlock_irq(&nvmeq->q_lock);
700 }
701
702 struct sync_cmd_info {
703         struct task_struct *task;
704         u32 result;
705         int status;
706 };
707
708 static void sync_completion(struct nvme_dev *dev, void *ctx,
709                                                 struct nvme_completion *cqe)
710 {
711         struct sync_cmd_info *cmdinfo = ctx;
712         cmdinfo->result = le32_to_cpup(&cqe->result);
713         cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
714         wake_up_process(cmdinfo->task);
715 }
716
717 /*
718  * Returns 0 on success.  If the result is negative, it's a Linux error code;
719  * if the result is positive, it's an NVM Express status code
720  */
721 static int nvme_submit_sync_cmd(struct nvme_queue *nvmeq,
722                         struct nvme_command *cmd, u32 *result, unsigned timeout)
723 {
724         int cmdid;
725         struct sync_cmd_info cmdinfo;
726
727         cmdinfo.task = current;
728         cmdinfo.status = -EINTR;
729
730         cmdid = alloc_cmdid_killable(nvmeq, &cmdinfo, sync_completion,
731                                                                 timeout);
732         if (cmdid < 0)
733                 return cmdid;
734         cmd->common.command_id = cmdid;
735
736         set_current_state(TASK_KILLABLE);
737         nvme_submit_cmd(nvmeq, cmd);
738         schedule();
739
740         if (cmdinfo.status == -EINTR) {
741                 nvme_abort_command(nvmeq, cmdid);
742                 return -EINTR;
743         }
744
745         if (result)
746                 *result = cmdinfo.result;
747
748         return cmdinfo.status;
749 }
750
751 static int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
752                                                                 u32 *result)
753 {
754         return nvme_submit_sync_cmd(dev->queues[0], cmd, result, ADMIN_TIMEOUT);
755 }
756
757 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
758 {
759         int status;
760         struct nvme_command c;
761
762         memset(&c, 0, sizeof(c));
763         c.delete_queue.opcode = opcode;
764         c.delete_queue.qid = cpu_to_le16(id);
765
766         status = nvme_submit_admin_cmd(dev, &c, NULL);
767         if (status)
768                 return -EIO;
769         return 0;
770 }
771
772 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
773                                                 struct nvme_queue *nvmeq)
774 {
775         int status;
776         struct nvme_command c;
777         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
778
779         memset(&c, 0, sizeof(c));
780         c.create_cq.opcode = nvme_admin_create_cq;
781         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
782         c.create_cq.cqid = cpu_to_le16(qid);
783         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
784         c.create_cq.cq_flags = cpu_to_le16(flags);
785         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
786
787         status = nvme_submit_admin_cmd(dev, &c, NULL);
788         if (status)
789                 return -EIO;
790         return 0;
791 }
792
793 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
794                                                 struct nvme_queue *nvmeq)
795 {
796         int status;
797         struct nvme_command c;
798         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
799
800         memset(&c, 0, sizeof(c));
801         c.create_sq.opcode = nvme_admin_create_sq;
802         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
803         c.create_sq.sqid = cpu_to_le16(qid);
804         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
805         c.create_sq.sq_flags = cpu_to_le16(flags);
806         c.create_sq.cqid = cpu_to_le16(qid);
807
808         status = nvme_submit_admin_cmd(dev, &c, NULL);
809         if (status)
810                 return -EIO;
811         return 0;
812 }
813
814 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
815 {
816         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
817 }
818
819 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
820 {
821         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
822 }
823
824 static int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
825                                                         dma_addr_t dma_addr)
826 {
827         struct nvme_command c;
828
829         memset(&c, 0, sizeof(c));
830         c.identify.opcode = nvme_admin_identify;
831         c.identify.nsid = cpu_to_le32(nsid);
832         c.identify.prp1 = cpu_to_le64(dma_addr);
833         c.identify.cns = cpu_to_le32(cns);
834
835         return nvme_submit_admin_cmd(dev, &c, NULL);
836 }
837
838 static int nvme_get_features(struct nvme_dev *dev, unsigned fid,
839                                 unsigned dword11, dma_addr_t dma_addr)
840 {
841         struct nvme_command c;
842
843         memset(&c, 0, sizeof(c));
844         c.features.opcode = nvme_admin_get_features;
845         c.features.prp1 = cpu_to_le64(dma_addr);
846         c.features.fid = cpu_to_le32(fid);
847         c.features.dword11 = cpu_to_le32(dword11);
848
849         return nvme_submit_admin_cmd(dev, &c, NULL);
850 }
851
852 static int nvme_set_features(struct nvme_dev *dev, unsigned fid,
853                         unsigned dword11, dma_addr_t dma_addr, u32 *result)
854 {
855         struct nvme_command c;
856
857         memset(&c, 0, sizeof(c));
858         c.features.opcode = nvme_admin_set_features;
859         c.features.prp1 = cpu_to_le64(dma_addr);
860         c.features.fid = cpu_to_le32(fid);
861         c.features.dword11 = cpu_to_le32(dword11);
862
863         return nvme_submit_admin_cmd(dev, &c, result);
864 }
865
866 static void nvme_free_queue(struct nvme_dev *dev, int qid)
867 {
868         struct nvme_queue *nvmeq = dev->queues[qid];
869         int vector = dev->entry[nvmeq->cq_vector].vector;
870
871         irq_set_affinity_hint(vector, NULL);
872         free_irq(vector, nvmeq);
873
874         /* Don't tell the adapter to delete the admin queue */
875         if (qid) {
876                 adapter_delete_sq(dev, qid);
877                 adapter_delete_cq(dev, qid);
878         }
879
880         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
881                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
882         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
883                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
884         kfree(nvmeq);
885 }
886
887 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
888                                                         int depth, int vector)
889 {
890         struct device *dmadev = &dev->pci_dev->dev;
891         unsigned extra = (depth / 8) + (depth * sizeof(struct nvme_cmd_info));
892         struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
893         if (!nvmeq)
894                 return NULL;
895
896         nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
897                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
898         if (!nvmeq->cqes)
899                 goto free_nvmeq;
900         memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
901
902         nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
903                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
904         if (!nvmeq->sq_cmds)
905                 goto free_cqdma;
906
907         nvmeq->q_dmadev = dmadev;
908         nvmeq->dev = dev;
909         spin_lock_init(&nvmeq->q_lock);
910         nvmeq->cq_head = 0;
911         nvmeq->cq_phase = 1;
912         init_waitqueue_head(&nvmeq->sq_full);
913         init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
914         bio_list_init(&nvmeq->sq_cong);
915         nvmeq->q_db = &dev->dbs[qid << (dev->db_stride + 1)];
916         nvmeq->q_depth = depth;
917         nvmeq->cq_vector = vector;
918
919         return nvmeq;
920
921  free_cqdma:
922         dma_free_coherent(dmadev, CQ_SIZE(nvmeq->q_depth), (void *)nvmeq->cqes,
923                                                         nvmeq->cq_dma_addr);
924  free_nvmeq:
925         kfree(nvmeq);
926         return NULL;
927 }
928
929 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
930                                                         const char *name)
931 {
932         if (use_threaded_interrupts)
933                 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
934                                         nvme_irq_check, nvme_irq,
935                                         IRQF_DISABLED | IRQF_SHARED,
936                                         name, nvmeq);
937         return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
938                                 IRQF_DISABLED | IRQF_SHARED, name, nvmeq);
939 }
940
941 static __devinit struct nvme_queue *nvme_create_queue(struct nvme_dev *dev,
942                                         int qid, int cq_size, int vector)
943 {
944         int result;
945         struct nvme_queue *nvmeq = nvme_alloc_queue(dev, qid, cq_size, vector);
946
947         if (!nvmeq)
948                 return ERR_PTR(-ENOMEM);
949
950         result = adapter_alloc_cq(dev, qid, nvmeq);
951         if (result < 0)
952                 goto free_nvmeq;
953
954         result = adapter_alloc_sq(dev, qid, nvmeq);
955         if (result < 0)
956                 goto release_cq;
957
958         result = queue_request_irq(dev, nvmeq, "nvme");
959         if (result < 0)
960                 goto release_sq;
961
962         return nvmeq;
963
964  release_sq:
965         adapter_delete_sq(dev, qid);
966  release_cq:
967         adapter_delete_cq(dev, qid);
968  free_nvmeq:
969         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
970                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
971         dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
972                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
973         kfree(nvmeq);
974         return ERR_PTR(result);
975 }
976
977 static int __devinit nvme_configure_admin_queue(struct nvme_dev *dev)
978 {
979         int result;
980         u32 aqa;
981         u64 cap;
982         unsigned long timeout;
983         struct nvme_queue *nvmeq;
984
985         dev->dbs = ((void __iomem *)dev->bar) + 4096;
986
987         nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
988         if (!nvmeq)
989                 return -ENOMEM;
990
991         aqa = nvmeq->q_depth - 1;
992         aqa |= aqa << 16;
993
994         dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
995         dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
996         dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
997         dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
998
999         writel(0, &dev->bar->cc);
1000         writel(aqa, &dev->bar->aqa);
1001         writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1002         writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1003         writel(dev->ctrl_config, &dev->bar->cc);
1004
1005         cap = readq(&dev->bar->cap);
1006         timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1007         dev->db_stride = NVME_CAP_STRIDE(cap);
1008
1009         while (!(readl(&dev->bar->csts) & NVME_CSTS_RDY)) {
1010                 msleep(100);
1011                 if (fatal_signal_pending(current))
1012                         return -EINTR;
1013                 if (time_after(jiffies, timeout)) {
1014                         dev_err(&dev->pci_dev->dev,
1015                                 "Device not ready; aborting initialisation\n");
1016                         return -ENODEV;
1017                 }
1018         }
1019
1020         result = queue_request_irq(dev, nvmeq, "nvme admin");
1021         dev->queues[0] = nvmeq;
1022         return result;
1023 }
1024
1025 static struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
1026                                 unsigned long addr, unsigned length)
1027 {
1028         int i, err, count, nents, offset;
1029         struct scatterlist *sg;
1030         struct page **pages;
1031         struct nvme_iod *iod;
1032
1033         if (addr & 3)
1034                 return ERR_PTR(-EINVAL);
1035         if (!length)
1036                 return ERR_PTR(-EINVAL);
1037
1038         offset = offset_in_page(addr);
1039         count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1040         pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
1041
1042         err = get_user_pages_fast(addr, count, 1, pages);
1043         if (err < count) {
1044                 count = err;
1045                 err = -EFAULT;
1046                 goto put_pages;
1047         }
1048
1049         iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1050         sg = iod->sg;
1051         sg_init_table(sg, count);
1052         for (i = 0; i < count; i++) {
1053                 sg_set_page(&sg[i], pages[i],
1054                                 min_t(int, length, PAGE_SIZE - offset), offset);
1055                 length -= (PAGE_SIZE - offset);
1056                 offset = 0;
1057         }
1058         sg_mark_end(&sg[i - 1]);
1059         iod->nents = count;
1060
1061         err = -ENOMEM;
1062         nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1063                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1064         if (!nents)
1065                 goto free_iod;
1066
1067         kfree(pages);
1068         return iod;
1069
1070  free_iod:
1071         kfree(iod);
1072  put_pages:
1073         for (i = 0; i < count; i++)
1074                 put_page(pages[i]);
1075         kfree(pages);
1076         return ERR_PTR(err);
1077 }
1078
1079 static void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1080                         struct nvme_iod *iod)
1081 {
1082         int i;
1083
1084         dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1085                                 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
1086
1087         for (i = 0; i < iod->nents; i++)
1088                 put_page(sg_page(&iod->sg[i]));
1089 }
1090
1091 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1092 {
1093         struct nvme_dev *dev = ns->dev;
1094         struct nvme_queue *nvmeq;
1095         struct nvme_user_io io;
1096         struct nvme_command c;
1097         unsigned length;
1098         int status;
1099         struct nvme_iod *iod;
1100
1101         if (copy_from_user(&io, uio, sizeof(io)))
1102                 return -EFAULT;
1103         length = (io.nblocks + 1) << ns->lba_shift;
1104
1105         switch (io.opcode) {
1106         case nvme_cmd_write:
1107         case nvme_cmd_read:
1108         case nvme_cmd_compare:
1109                 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
1110                 break;
1111         default:
1112                 return -EINVAL;
1113         }
1114
1115         if (IS_ERR(iod))
1116                 return PTR_ERR(iod);
1117
1118         memset(&c, 0, sizeof(c));
1119         c.rw.opcode = io.opcode;
1120         c.rw.flags = io.flags;
1121         c.rw.nsid = cpu_to_le32(ns->ns_id);
1122         c.rw.slba = cpu_to_le64(io.slba);
1123         c.rw.length = cpu_to_le16(io.nblocks);
1124         c.rw.control = cpu_to_le16(io.control);
1125         c.rw.dsmgmt = cpu_to_le16(io.dsmgmt);
1126         c.rw.reftag = io.reftag;
1127         c.rw.apptag = io.apptag;
1128         c.rw.appmask = io.appmask;
1129         /* XXX: metadata */
1130         length = nvme_setup_prps(dev, &c.common, iod, length, GFP_KERNEL);
1131
1132         nvmeq = get_nvmeq(dev);
1133         /*
1134          * Since nvme_submit_sync_cmd sleeps, we can't keep preemption
1135          * disabled.  We may be preempted at any point, and be rescheduled
1136          * to a different CPU.  That will cause cacheline bouncing, but no
1137          * additional races since q_lock already protects against other CPUs.
1138          */
1139         put_nvmeq(nvmeq);
1140         if (length != (io.nblocks + 1) << ns->lba_shift)
1141                 status = -ENOMEM;
1142         else
1143                 status = nvme_submit_sync_cmd(nvmeq, &c, NULL, NVME_IO_TIMEOUT);
1144
1145         nvme_unmap_user_pages(dev, io.opcode & 1, iod);
1146         nvme_free_iod(dev, iod);
1147         return status;
1148 }
1149
1150 static int nvme_user_admin_cmd(struct nvme_ns *ns,
1151                                         struct nvme_admin_cmd __user *ucmd)
1152 {
1153         struct nvme_dev *dev = ns->dev;
1154         struct nvme_admin_cmd cmd;
1155         struct nvme_command c;
1156         int status, length;
1157         struct nvme_iod *iod;
1158
1159         if (!capable(CAP_SYS_ADMIN))
1160                 return -EACCES;
1161         if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1162                 return -EFAULT;
1163
1164         memset(&c, 0, sizeof(c));
1165         c.common.opcode = cmd.opcode;
1166         c.common.flags = cmd.flags;
1167         c.common.nsid = cpu_to_le32(cmd.nsid);
1168         c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1169         c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1170         c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1171         c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1172         c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1173         c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1174         c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1175         c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1176
1177         length = cmd.data_len;
1178         if (cmd.data_len) {
1179                 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1180                                                                 length);
1181                 if (IS_ERR(iod))
1182                         return PTR_ERR(iod);
1183                 length = nvme_setup_prps(dev, &c.common, iod, length,
1184                                                                 GFP_KERNEL);
1185         }
1186
1187         if (length != cmd.data_len)
1188                 status = -ENOMEM;
1189         else
1190                 status = nvme_submit_admin_cmd(dev, &c, NULL);
1191
1192         if (cmd.data_len) {
1193                 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
1194                 nvme_free_iod(dev, iod);
1195         }
1196         return status;
1197 }
1198
1199 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1200                                                         unsigned long arg)
1201 {
1202         struct nvme_ns *ns = bdev->bd_disk->private_data;
1203
1204         switch (cmd) {
1205         case NVME_IOCTL_ID:
1206                 return ns->ns_id;
1207         case NVME_IOCTL_ADMIN_CMD:
1208                 return nvme_user_admin_cmd(ns, (void __user *)arg);
1209         case NVME_IOCTL_SUBMIT_IO:
1210                 return nvme_submit_io(ns, (void __user *)arg);
1211         default:
1212                 return -ENOTTY;
1213         }
1214 }
1215
1216 static const struct block_device_operations nvme_fops = {
1217         .owner          = THIS_MODULE,
1218         .ioctl          = nvme_ioctl,
1219         .compat_ioctl   = nvme_ioctl,
1220 };
1221
1222 static void nvme_timeout_ios(struct nvme_queue *nvmeq)
1223 {
1224         int depth = nvmeq->q_depth - 1;
1225         struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1226         unsigned long now = jiffies;
1227         int cmdid;
1228
1229         for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1230                 void *ctx;
1231                 nvme_completion_fn fn;
1232                 static struct nvme_completion cqe = { .status = cpu_to_le16(NVME_SC_ABORT_REQ) << 1, };
1233
1234                 if (!time_after(now, info[cmdid].timeout))
1235                         continue;
1236                 dev_warn(nvmeq->q_dmadev, "Timing out I/O %d\n", cmdid);
1237                 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
1238                 fn(nvmeq->dev, ctx, &cqe);
1239         }
1240 }
1241
1242 static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1243 {
1244         while (bio_list_peek(&nvmeq->sq_cong)) {
1245                 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1246                 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
1247                 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
1248                         bio_list_add_head(&nvmeq->sq_cong, bio);
1249                         break;
1250                 }
1251                 if (bio_list_empty(&nvmeq->sq_cong))
1252                         remove_wait_queue(&nvmeq->sq_full,
1253                                                         &nvmeq->sq_cong_wait);
1254         }
1255 }
1256
1257 static int nvme_kthread(void *data)
1258 {
1259         struct nvme_dev *dev;
1260
1261         while (!kthread_should_stop()) {
1262                 __set_current_state(TASK_RUNNING);
1263                 spin_lock(&dev_list_lock);
1264                 list_for_each_entry(dev, &dev_list, node) {
1265                         int i;
1266                         for (i = 0; i < dev->queue_count; i++) {
1267                                 struct nvme_queue *nvmeq = dev->queues[i];
1268                                 if (!nvmeq)
1269                                         continue;
1270                                 spin_lock_irq(&nvmeq->q_lock);
1271                                 if (nvme_process_cq(nvmeq))
1272                                         printk("process_cq did something\n");
1273                                 nvme_timeout_ios(nvmeq);
1274                                 nvme_resubmit_bios(nvmeq);
1275                                 spin_unlock_irq(&nvmeq->q_lock);
1276                         }
1277                 }
1278                 spin_unlock(&dev_list_lock);
1279                 set_current_state(TASK_INTERRUPTIBLE);
1280                 schedule_timeout(HZ);
1281         }
1282         return 0;
1283 }
1284
1285 static DEFINE_IDA(nvme_index_ida);
1286
1287 static int nvme_get_ns_idx(void)
1288 {
1289         int index, error;
1290
1291         do {
1292                 if (!ida_pre_get(&nvme_index_ida, GFP_KERNEL))
1293                         return -1;
1294
1295                 spin_lock(&dev_list_lock);
1296                 error = ida_get_new(&nvme_index_ida, &index);
1297                 spin_unlock(&dev_list_lock);
1298         } while (error == -EAGAIN);
1299
1300         if (error)
1301                 index = -1;
1302         return index;
1303 }
1304
1305 static void nvme_put_ns_idx(int index)
1306 {
1307         spin_lock(&dev_list_lock);
1308         ida_remove(&nvme_index_ida, index);
1309         spin_unlock(&dev_list_lock);
1310 }
1311
1312 static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, int nsid,
1313                         struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1314 {
1315         struct nvme_ns *ns;
1316         struct gendisk *disk;
1317         int lbaf;
1318
1319         if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1320                 return NULL;
1321
1322         ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1323         if (!ns)
1324                 return NULL;
1325         ns->queue = blk_alloc_queue(GFP_KERNEL);
1326         if (!ns->queue)
1327                 goto out_free_ns;
1328         ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1329         queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1330         queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
1331 /*      queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); */
1332         blk_queue_make_request(ns->queue, nvme_make_request);
1333         ns->dev = dev;
1334         ns->queue->queuedata = ns;
1335
1336         disk = alloc_disk(NVME_MINORS);
1337         if (!disk)
1338                 goto out_free_queue;
1339         ns->ns_id = nsid;
1340         ns->disk = disk;
1341         lbaf = id->flbas & 0xf;
1342         ns->lba_shift = id->lbaf[lbaf].ds;
1343
1344         disk->major = nvme_major;
1345         disk->minors = NVME_MINORS;
1346         disk->first_minor = NVME_MINORS * nvme_get_ns_idx();
1347         disk->fops = &nvme_fops;
1348         disk->private_data = ns;
1349         disk->queue = ns->queue;
1350         disk->driverfs_dev = &dev->pci_dev->dev;
1351         sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
1352         set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1353
1354         return ns;
1355
1356  out_free_queue:
1357         blk_cleanup_queue(ns->queue);
1358  out_free_ns:
1359         kfree(ns);
1360         return NULL;
1361 }
1362
1363 static void nvme_ns_free(struct nvme_ns *ns)
1364 {
1365         int index = ns->disk->first_minor / NVME_MINORS;
1366         put_disk(ns->disk);
1367         nvme_put_ns_idx(index);
1368         blk_cleanup_queue(ns->queue);
1369         kfree(ns);
1370 }
1371
1372 static int set_queue_count(struct nvme_dev *dev, int count)
1373 {
1374         int status;
1375         u32 result;
1376         u32 q_count = (count - 1) | ((count - 1) << 16);
1377
1378         status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
1379                                                                 &result);
1380         if (status)
1381                 return -EIO;
1382         return min(result & 0xffff, result >> 16) + 1;
1383 }
1384
1385 static int __devinit nvme_setup_io_queues(struct nvme_dev *dev)
1386 {
1387         int result, cpu, i, nr_io_queues, db_bar_size;
1388
1389         nr_io_queues = num_online_cpus();
1390         result = set_queue_count(dev, nr_io_queues);
1391         if (result < 0)
1392                 return result;
1393         if (result < nr_io_queues)
1394                 nr_io_queues = result;
1395
1396         /* Deregister the admin queue's interrupt */
1397         free_irq(dev->entry[0].vector, dev->queues[0]);
1398
1399         db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
1400         if (db_bar_size > 8192) {
1401                 iounmap(dev->bar);
1402                 dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
1403                                                                 db_bar_size);
1404                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
1405                 dev->queues[0]->q_db = dev->dbs;
1406         }
1407
1408         for (i = 0; i < nr_io_queues; i++)
1409                 dev->entry[i].entry = i;
1410         for (;;) {
1411                 result = pci_enable_msix(dev->pci_dev, dev->entry,
1412                                                                 nr_io_queues);
1413                 if (result == 0) {
1414                         break;
1415                 } else if (result > 0) {
1416                         nr_io_queues = result;
1417                         continue;
1418                 } else {
1419                         nr_io_queues = 1;
1420                         break;
1421                 }
1422         }
1423
1424         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
1425         /* XXX: handle failure here */
1426
1427         cpu = cpumask_first(cpu_online_mask);
1428         for (i = 0; i < nr_io_queues; i++) {
1429                 irq_set_affinity_hint(dev->entry[i].vector, get_cpu_mask(cpu));
1430                 cpu = cpumask_next(cpu, cpu_online_mask);
1431         }
1432
1433         for (i = 0; i < nr_io_queues; i++) {
1434                 dev->queues[i + 1] = nvme_create_queue(dev, i + 1,
1435                                                         NVME_Q_DEPTH, i);
1436                 if (IS_ERR(dev->queues[i + 1]))
1437                         return PTR_ERR(dev->queues[i + 1]);
1438                 dev->queue_count++;
1439         }
1440
1441         for (; i < num_possible_cpus(); i++) {
1442                 int target = i % rounddown_pow_of_two(dev->queue_count - 1);
1443                 dev->queues[i + 1] = dev->queues[target + 1];
1444         }
1445
1446         return 0;
1447 }
1448
1449 static void nvme_free_queues(struct nvme_dev *dev)
1450 {
1451         int i;
1452
1453         for (i = dev->queue_count - 1; i >= 0; i--)
1454                 nvme_free_queue(dev, i);
1455 }
1456
1457 static int __devinit nvme_dev_add(struct nvme_dev *dev)
1458 {
1459         int res, nn, i;
1460         struct nvme_ns *ns, *next;
1461         struct nvme_id_ctrl *ctrl;
1462         struct nvme_id_ns *id_ns;
1463         void *mem;
1464         dma_addr_t dma_addr;
1465
1466         res = nvme_setup_io_queues(dev);
1467         if (res)
1468                 return res;
1469
1470         mem = dma_alloc_coherent(&dev->pci_dev->dev, 8192, &dma_addr,
1471                                                                 GFP_KERNEL);
1472
1473         res = nvme_identify(dev, 0, 1, dma_addr);
1474         if (res) {
1475                 res = -EIO;
1476                 goto out_free;
1477         }
1478
1479         ctrl = mem;
1480         nn = le32_to_cpup(&ctrl->nn);
1481         memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
1482         memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
1483         memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
1484
1485         id_ns = mem;
1486         for (i = 1; i <= nn; i++) {
1487                 res = nvme_identify(dev, i, 0, dma_addr);
1488                 if (res)
1489                         continue;
1490
1491                 if (id_ns->ncap == 0)
1492                         continue;
1493
1494                 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
1495                                                         dma_addr + 4096);
1496                 if (res)
1497                         continue;
1498
1499                 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
1500                 if (ns)
1501                         list_add_tail(&ns->list, &dev->namespaces);
1502         }
1503         list_for_each_entry(ns, &dev->namespaces, list)
1504                 add_disk(ns->disk);
1505
1506         goto out;
1507
1508  out_free:
1509         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1510                 list_del(&ns->list);
1511                 nvme_ns_free(ns);
1512         }
1513
1514  out:
1515         dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
1516         return res;
1517 }
1518
1519 static int nvme_dev_remove(struct nvme_dev *dev)
1520 {
1521         struct nvme_ns *ns, *next;
1522
1523         spin_lock(&dev_list_lock);
1524         list_del(&dev->node);
1525         spin_unlock(&dev_list_lock);
1526
1527         /* TODO: wait all I/O finished or cancel them */
1528
1529         list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
1530                 list_del(&ns->list);
1531                 del_gendisk(ns->disk);
1532                 nvme_ns_free(ns);
1533         }
1534
1535         nvme_free_queues(dev);
1536
1537         return 0;
1538 }
1539
1540 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1541 {
1542         struct device *dmadev = &dev->pci_dev->dev;
1543         dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
1544                                                 PAGE_SIZE, PAGE_SIZE, 0);
1545         if (!dev->prp_page_pool)
1546                 return -ENOMEM;
1547
1548         /* Optimisation for I/Os between 4k and 128k */
1549         dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
1550                                                 256, 256, 0);
1551         if (!dev->prp_small_pool) {
1552                 dma_pool_destroy(dev->prp_page_pool);
1553                 return -ENOMEM;
1554         }
1555         return 0;
1556 }
1557
1558 static void nvme_release_prp_pools(struct nvme_dev *dev)
1559 {
1560         dma_pool_destroy(dev->prp_page_pool);
1561         dma_pool_destroy(dev->prp_small_pool);
1562 }
1563
1564 /* XXX: Use an ida or something to let remove / add work correctly */
1565 static void nvme_set_instance(struct nvme_dev *dev)
1566 {
1567         static int instance;
1568         dev->instance = instance++;
1569 }
1570
1571 static void nvme_release_instance(struct nvme_dev *dev)
1572 {
1573 }
1574
1575 static int __devinit nvme_probe(struct pci_dev *pdev,
1576                                                 const struct pci_device_id *id)
1577 {
1578         int bars, result = -ENOMEM;
1579         struct nvme_dev *dev;
1580
1581         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1582         if (!dev)
1583                 return -ENOMEM;
1584         dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
1585                                                                 GFP_KERNEL);
1586         if (!dev->entry)
1587                 goto free;
1588         dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
1589                                                                 GFP_KERNEL);
1590         if (!dev->queues)
1591                 goto free;
1592
1593         if (pci_enable_device_mem(pdev))
1594                 goto free;
1595         pci_set_master(pdev);
1596         bars = pci_select_bars(pdev, IORESOURCE_MEM);
1597         if (pci_request_selected_regions(pdev, bars, "nvme"))
1598                 goto disable;
1599
1600         INIT_LIST_HEAD(&dev->namespaces);
1601         dev->pci_dev = pdev;
1602         pci_set_drvdata(pdev, dev);
1603         dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1604         dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1605         nvme_set_instance(dev);
1606         dev->entry[0].vector = pdev->irq;
1607
1608         result = nvme_setup_prp_pools(dev);
1609         if (result)
1610                 goto disable_msix;
1611
1612         dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1613         if (!dev->bar) {
1614                 result = -ENOMEM;
1615                 goto disable_msix;
1616         }
1617
1618         result = nvme_configure_admin_queue(dev);
1619         if (result)
1620                 goto unmap;
1621         dev->queue_count++;
1622
1623         spin_lock(&dev_list_lock);
1624         list_add(&dev->node, &dev_list);
1625         spin_unlock(&dev_list_lock);
1626
1627         result = nvme_dev_add(dev);
1628         if (result)
1629                 goto delete;
1630
1631         return 0;
1632
1633  delete:
1634         spin_lock(&dev_list_lock);
1635         list_del(&dev->node);
1636         spin_unlock(&dev_list_lock);
1637
1638         nvme_free_queues(dev);
1639  unmap:
1640         iounmap(dev->bar);
1641  disable_msix:
1642         pci_disable_msix(pdev);
1643         nvme_release_instance(dev);
1644         nvme_release_prp_pools(dev);
1645  disable:
1646         pci_disable_device(pdev);
1647         pci_release_regions(pdev);
1648  free:
1649         kfree(dev->queues);
1650         kfree(dev->entry);
1651         kfree(dev);
1652         return result;
1653 }
1654
1655 static void __devexit nvme_remove(struct pci_dev *pdev)
1656 {
1657         struct nvme_dev *dev = pci_get_drvdata(pdev);
1658         nvme_dev_remove(dev);
1659         pci_disable_msix(pdev);
1660         iounmap(dev->bar);
1661         nvme_release_instance(dev);
1662         nvme_release_prp_pools(dev);
1663         pci_disable_device(pdev);
1664         pci_release_regions(pdev);
1665         kfree(dev->queues);
1666         kfree(dev->entry);
1667         kfree(dev);
1668 }
1669
1670 /* These functions are yet to be implemented */
1671 #define nvme_error_detected NULL
1672 #define nvme_dump_registers NULL
1673 #define nvme_link_reset NULL
1674 #define nvme_slot_reset NULL
1675 #define nvme_error_resume NULL
1676 #define nvme_suspend NULL
1677 #define nvme_resume NULL
1678
1679 static struct pci_error_handlers nvme_err_handler = {
1680         .error_detected = nvme_error_detected,
1681         .mmio_enabled   = nvme_dump_registers,
1682         .link_reset     = nvme_link_reset,
1683         .slot_reset     = nvme_slot_reset,
1684         .resume         = nvme_error_resume,
1685 };
1686
1687 /* Move to pci_ids.h later */
1688 #define PCI_CLASS_STORAGE_EXPRESS       0x010802
1689
1690 static DEFINE_PCI_DEVICE_TABLE(nvme_id_table) = {
1691         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
1692         { 0, }
1693 };
1694 MODULE_DEVICE_TABLE(pci, nvme_id_table);
1695
1696 static struct pci_driver nvme_driver = {
1697         .name           = "nvme",
1698         .id_table       = nvme_id_table,
1699         .probe          = nvme_probe,
1700         .remove         = __devexit_p(nvme_remove),
1701         .suspend        = nvme_suspend,
1702         .resume         = nvme_resume,
1703         .err_handler    = &nvme_err_handler,
1704 };
1705
1706 static int __init nvme_init(void)
1707 {
1708         int result = -EBUSY;
1709
1710         nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
1711         if (IS_ERR(nvme_thread))
1712                 return PTR_ERR(nvme_thread);
1713
1714         nvme_major = register_blkdev(nvme_major, "nvme");
1715         if (nvme_major <= 0)
1716                 goto kill_kthread;
1717
1718         result = pci_register_driver(&nvme_driver);
1719         if (result)
1720                 goto unregister_blkdev;
1721         return 0;
1722
1723  unregister_blkdev:
1724         unregister_blkdev(nvme_major, "nvme");
1725  kill_kthread:
1726         kthread_stop(nvme_thread);
1727         return result;
1728 }
1729
1730 static void __exit nvme_exit(void)
1731 {
1732         pci_unregister_driver(&nvme_driver);
1733         unregister_blkdev(nvme_major, "nvme");
1734         kthread_stop(nvme_thread);
1735 }
1736
1737 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
1738 MODULE_LICENSE("GPL");
1739 MODULE_VERSION("0.8");
1740 module_init(nvme_init);
1741 module_exit(nvme_exit);