microblaze: Move exception_table_entry upward
[linux-2.6.git] / drivers / atm / idt77252.h
1 /******************************************************************* 
2  *
3  * Copyright (c) 2000 ATecoM GmbH 
4  *
5  * The author may be reached at ecd@atecom.com.
6  *
7  * This program is free software; you can redistribute  it and/or modify it
8  * under  the terms of  the GNU General  Public License as published by the
9  * Free Software Foundation;  either version 2 of the  License, or (at your
10  * option) any later version.
11  *
12  * THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR   IMPLIED
13  * WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
15  * NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT,  INDIRECT,
16  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
17  * NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
18  * USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
19  * ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
20  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
21  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22  *
23  * You should have received a copy of the  GNU General Public License along
24  * with this program; if not, write  to the Free Software Foundation, Inc.,
25  * 675 Mass Ave, Cambridge, MA 02139, USA.
26  *
27  *******************************************************************/
28
29 #ifndef _IDT77252_H
30 #define _IDT77252_H 1
31
32
33 #include <linux/ptrace.h>
34 #include <linux/skbuff.h>
35 #include <linux/workqueue.h>
36 #include <linux/mutex.h>
37
38 /*****************************************************************************/
39 /*                                                                           */
40 /* Makros                                                                    */
41 /*                                                                           */
42 /*****************************************************************************/
43 #define VPCI2VC(card, vpi, vci) \
44         (((vpi) << card->vcibits) | ((vci) & card->vcimask))
45
46 /*****************************************************************************/
47 /*                                                                           */
48 /*   DEBUGGING definitions                                                   */
49 /*                                                                           */
50 /*****************************************************************************/
51
52 #define DBG_RAW_CELL    0x00000400
53 #define DBG_TINY        0x00000200
54 #define DBG_GENERAL     0x00000100
55 #define DBG_XGENERAL    0x00000080
56 #define DBG_INIT        0x00000040
57 #define DBG_DEINIT      0x00000020
58 #define DBG_INTERRUPT   0x00000010
59 #define DBG_OPEN_CONN   0x00000008
60 #define DBG_CLOSE_CONN  0x00000004
61 #define DBG_RX_DATA     0x00000002
62 #define DBG_TX_DATA     0x00000001
63
64 #ifdef CONFIG_ATM_IDT77252_DEBUG
65
66 #define CPRINTK(args...)   do { if (debug & DBG_CLOSE_CONN) printk(args); } while(0)
67 #define OPRINTK(args...)   do { if (debug & DBG_OPEN_CONN)  printk(args); } while(0)
68 #define IPRINTK(args...)   do { if (debug & DBG_INIT)       printk(args); } while(0)
69 #define INTPRINTK(args...) do { if (debug & DBG_INTERRUPT)  printk(args); } while(0)
70 #define DIPRINTK(args...)  do { if (debug & DBG_DEINIT)     printk(args); } while(0)
71 #define TXPRINTK(args...)  do { if (debug & DBG_TX_DATA)    printk(args); } while(0)
72 #define RXPRINTK(args...)  do { if (debug & DBG_RX_DATA)    printk(args); } while(0)
73 #define XPRINTK(args...)   do { if (debug & DBG_XGENERAL)   printk(args); } while(0)
74 #define DPRINTK(args...)   do { if (debug & DBG_GENERAL)    printk(args); } while(0)
75 #define NPRINTK(args...)   do { if (debug & DBG_TINY)       printk(args); } while(0)
76 #define RPRINTK(args...)   do { if (debug & DBG_RAW_CELL)   printk(args); } while(0)
77
78 #else
79
80 #define CPRINTK(args...)        do { } while(0)
81 #define OPRINTK(args...)        do { } while(0)
82 #define IPRINTK(args...)        do { } while(0)
83 #define INTPRINTK(args...)      do { } while(0)
84 #define DIPRINTK(args...)       do { } while(0)
85 #define TXPRINTK(args...)       do { } while(0)
86 #define RXPRINTK(args...)       do { } while(0)
87 #define XPRINTK(args...)        do { } while(0)
88 #define DPRINTK(args...)        do { } while(0)
89 #define NPRINTK(args...)        do { } while(0)
90 #define RPRINTK(args...)        do { } while(0)
91
92 #endif
93
94 #define SCHED_UBR0              0
95 #define SCHED_UBR               1
96 #define SCHED_VBR               2
97 #define SCHED_ABR               3
98 #define SCHED_CBR               4
99
100 #define SCQFULL_TIMEOUT         HZ
101
102 /*****************************************************************************/
103 /*                                                                           */
104 /*   Free Buffer Queue Layout                                                */
105 /*                                                                           */
106 /*****************************************************************************/
107 #define SAR_FB_SIZE_0           (2048 - 256)
108 #define SAR_FB_SIZE_1           (4096 - 256)
109 #define SAR_FB_SIZE_2           (8192 - 256)
110 #define SAR_FB_SIZE_3           (16384 - 256)
111
112 #define SAR_FBQ0_LOW            4
113 #define SAR_FBQ0_HIGH           8
114 #define SAR_FBQ1_LOW            2
115 #define SAR_FBQ1_HIGH           4
116 #define SAR_FBQ2_LOW            1
117 #define SAR_FBQ2_HIGH           2
118 #define SAR_FBQ3_LOW            1
119 #define SAR_FBQ3_HIGH           2
120
121 #if 0
122 #define SAR_TST_RESERVED        44      /* Num TST reserved for UBR/ABR/VBR */
123 #else
124 #define SAR_TST_RESERVED        0       /* Num TST reserved for UBR/ABR/VBR */
125 #endif
126
127 #define TCT_CBR                 0x00000000
128 #define TCT_UBR                 0x00000000
129 #define TCT_VBR                 0x40000000
130 #define TCT_ABR                 0x80000000
131 #define TCT_TYPE                0xc0000000
132
133 #define TCT_RR                  0x20000000
134 #define TCT_LMCR                0x08000000
135 #define TCT_SCD_MASK            0x0007ffff
136
137 #define TCT_TSIF                0x00004000
138 #define TCT_HALT                0x80000000
139 #define TCT_IDLE                0x40000000
140 #define TCT_FLAG_UBR            0x80000000
141
142 /*****************************************************************************/
143 /*                                                                           */
144 /*   Structure describing an IDT77252                                        */
145 /*                                                                           */
146 /*****************************************************************************/
147
148 struct scqe
149 {
150         u32             word_1;
151         u32             word_2;
152         u32             word_3;
153         u32             word_4;
154 };
155
156 #define SCQ_ENTRIES     64
157 #define SCQ_SIZE        (SCQ_ENTRIES * sizeof(struct scqe))
158 #define SCQ_MASK        (SCQ_SIZE - 1)
159
160 struct scq_info
161 {
162         struct scqe             *base;
163         struct scqe             *next;
164         struct scqe             *last;
165         dma_addr_t              paddr;
166         spinlock_t              lock;
167         atomic_t                used;
168         unsigned long           trans_start;
169         unsigned long           scd;
170         spinlock_t              skblock;
171         struct sk_buff_head     transmit;
172         struct sk_buff_head     pending;
173 };
174
175 struct rx_pool {
176         struct sk_buff_head     queue;
177         unsigned int            len;
178 };
179
180 struct aal1 {
181         unsigned int            total;
182         unsigned int            count;
183         struct sk_buff          *data;
184         unsigned char           sequence;
185 };
186
187 struct rate_estimator {
188         struct timer_list       timer;
189         unsigned int            interval;
190         unsigned int            ewma_log;
191         u64                     cells;
192         u64                     last_cells;
193         long                    avcps;
194         u32                     cps;
195         u32                     maxcps;
196 };
197
198 struct vc_map {
199         unsigned int            index;
200         unsigned long           flags;
201 #define VCF_TX          0
202 #define VCF_RX          1
203 #define VCF_IDLE        2
204 #define VCF_RSV         3
205         unsigned int            class;
206         u8                      init_er;
207         u8                      lacr;
208         u8                      max_er;
209         unsigned int            ntste;
210         spinlock_t              lock;
211         struct atm_vcc          *tx_vcc;
212         struct atm_vcc          *rx_vcc;
213         struct idt77252_dev     *card;
214         struct scq_info         *scq;           /* To keep track of the SCQ */
215         struct rate_estimator   *estimator;
216         int                     scd_index;
217         union {
218                 struct rx_pool  rx_pool;
219                 struct aal1     aal1;
220         } rcv;
221 };
222
223 /*****************************************************************************/
224 /*                                                                           */
225 /*   RCTE - Receive Connection Table Entry                                   */
226 /*                                                                           */
227 /*****************************************************************************/
228
229 struct rct_entry
230 {
231         u32             word_1;
232         u32             buffer_handle;
233         u32             dma_address;
234         u32             aal5_crc32;
235 };
236
237 /*****************************************************************************/
238 /*                                                                           */
239 /*   RSQ - Receive Status Queue                                              */
240 /*                                                                           */
241 /*****************************************************************************/
242
243 #define SAR_RSQE_VALID      0x80000000
244 #define SAR_RSQE_IDLE       0x40000000
245 #define SAR_RSQE_BUF_MASK   0x00030000
246 #define SAR_RSQE_BUF_ASGN   0x00008000
247 #define SAR_RSQE_NZGFC      0x00004000
248 #define SAR_RSQE_EPDU       0x00002000
249 #define SAR_RSQE_BUF_CONT   0x00001000
250 #define SAR_RSQE_EFCIE      0x00000800
251 #define SAR_RSQE_CLP        0x00000400
252 #define SAR_RSQE_CRC        0x00000200
253 #define SAR_RSQE_CELLCNT    0x000001FF
254
255
256 #define RSQSIZE            8192
257 #define RSQ_NUM_ENTRIES    (RSQSIZE / 16)
258 #define RSQ_ALIGNMENT      8192
259
260 struct rsq_entry {
261         u32                     word_1;
262         u32                     word_2;
263         u32                     word_3;
264         u32                     word_4;
265 };
266
267 struct rsq_info {
268         struct rsq_entry        *base;
269         struct rsq_entry        *next;
270         struct rsq_entry        *last;
271         dma_addr_t              paddr;
272 };
273
274
275 /*****************************************************************************/
276 /*                                                                           */
277 /*   TSQ - Transmit Status Queue                                             */
278 /*                                                                           */
279 /*****************************************************************************/
280
281 #define SAR_TSQE_INVALID         0x80000000
282 #define SAR_TSQE_TIMESTAMP       0x00FFFFFF
283 #define SAR_TSQE_TYPE            0x60000000
284 #define SAR_TSQE_TYPE_TIMER      0x00000000
285 #define SAR_TSQE_TYPE_TSR        0x20000000
286 #define SAR_TSQE_TYPE_IDLE       0x40000000
287 #define SAR_TSQE_TYPE_TBD_COMP   0x60000000
288
289 #define SAR_TSQE_TAG(stat)      (((stat) >> 24) & 0x1f)
290
291 #define TSQSIZE            8192
292 #define TSQ_NUM_ENTRIES    1024
293 #define TSQ_ALIGNMENT      8192
294
295 struct tsq_entry
296 {
297         u32                     word_1;
298         u32                     word_2;
299 };
300
301 struct tsq_info
302 {
303         struct tsq_entry        *base;
304         struct tsq_entry        *next;
305         struct tsq_entry        *last;
306         dma_addr_t              paddr;
307 };
308
309 struct tst_info
310 {
311         struct vc_map           *vc;
312         u32                     tste;
313 };
314
315 #define TSTE_MASK               0x601fffff
316
317 #define TSTE_OPC_MASK           0x60000000
318 #define TSTE_OPC_NULL           0x00000000
319 #define TSTE_OPC_CBR            0x20000000
320 #define TSTE_OPC_VAR            0x40000000
321 #define TSTE_OPC_JMP            0x60000000
322
323 #define TSTE_PUSH_IDLE          0x01000000
324 #define TSTE_PUSH_ACTIVE        0x02000000
325
326 #define TST_SWITCH_DONE         0
327 #define TST_SWITCH_PENDING      1
328 #define TST_SWITCH_WAIT         2
329
330 #define FBQ_SHIFT               9
331 #define FBQ_SIZE                (1 << FBQ_SHIFT)
332 #define FBQ_MASK                (FBQ_SIZE - 1)
333
334 struct sb_pool
335 {
336         unsigned int            index;
337         struct sk_buff          *skb[FBQ_SIZE];
338 };
339
340 #define POOL_HANDLE(queue, index)       (((queue + 1) << 16) | (index))
341 #define POOL_QUEUE(handle)              (((handle) >> 16) - 1)
342 #define POOL_INDEX(handle)              ((handle) & 0xffff)
343
344 struct idt77252_dev
345 {
346         struct tsq_info         tsq;            /* Transmit Status Queue */
347         struct rsq_info         rsq;            /* Receive Status Queue */
348
349         struct pci_dev          *pcidev;        /* PCI handle (desriptor) */
350         struct atm_dev          *atmdev;        /* ATM device desriptor */
351
352         void __iomem            *membase;       /* SAR's memory base address */
353         unsigned long           srambase;       /* SAR's sram  base address */
354         void __iomem            *fbq[4];        /* FBQ fill addresses */
355
356         struct mutex            mutex;
357         spinlock_t              cmd_lock;       /* for r/w utility/sram */
358
359         unsigned long           softstat;
360         unsigned long           flags;          /* see blow */
361
362         struct work_struct      tqueue;
363
364         unsigned long           tct_base;       /* TCT base address in SRAM */
365         unsigned long           rct_base;       /* RCT base address in SRAM */
366         unsigned long           rt_base;        /* Rate Table base in SRAM */
367         unsigned long           scd_base;       /* SCD base address in SRAM */
368         unsigned long           tst[2];         /* TST base address in SRAM */
369         unsigned long           abrst_base;     /* ABRST base address in SRAM */
370         unsigned long           fifo_base;      /* RX FIFO base in SRAM */
371
372         unsigned long           irqstat[16];
373
374         unsigned int            sramsize;       /* SAR's sram size */
375
376         unsigned int            tct_size;       /* total TCT entries */
377         unsigned int            rct_size;       /* total RCT entries */
378         unsigned int            scd_size;       /* length of SCD */
379         unsigned int            tst_size;       /* total TST entries */
380         unsigned int            tst_free;       /* free TSTEs in TST */
381         unsigned int            abrst_size;     /* size of ABRST in words */
382         unsigned int            fifo_size;      /* size of RX FIFO in words */
383
384         unsigned int            vpibits;        /* Bits used for VPI index */
385         unsigned int            vcibits;        /* Bits used for VCI index */
386         unsigned int            vcimask;        /* Mask for VCI index */
387
388         unsigned int            utopia_pcr;     /* Utopia Itf's Cell Rate */
389         unsigned int            link_pcr;       /* PHY's Peek Cell Rate */
390
391         struct vc_map           **vcs;          /* Open Connections */
392         struct vc_map           **scd2vc;       /* SCD to Connection map */
393
394         struct tst_info         *soft_tst;      /* TST to Connection map */
395         unsigned int            tst_index;      /* Current TST in use */
396         struct timer_list       tst_timer;
397         spinlock_t              tst_lock;
398         unsigned long           tst_state;
399
400         struct sb_pool          sbpool[4];      /* Pool of RX skbuffs */
401         struct sk_buff          *raw_cell_head; /* Pointer to raw cell queue */
402         u32                     *raw_cell_hnd;  /* Pointer to RCQ handle */
403         dma_addr_t              raw_cell_paddr;
404
405         int                     index;          /* SAR's ID */
406         int                     revision;       /* chip revision */
407
408         char                    name[16];       /* Device name */
409
410         struct idt77252_dev     *next;
411 };
412
413
414 /* definition for flag field above */
415 #define IDT77252_BIT_INIT               1
416 #define IDT77252_BIT_INTERRUPT          2
417
418
419 #define ATM_CELL_PAYLOAD         48
420
421 #define FREEBUF_ALIGNMENT        16
422
423 /*****************************************************************************/
424 /*                                                                           */
425 /* Makros                                                                    */
426 /*                                                                           */
427 /*****************************************************************************/
428 #define ALIGN_ADDRESS(addr, alignment) \
429         ((((u32)(addr)) + (((u32)(alignment))-1)) & ~(((u32)(alignment)) - 1))
430
431
432 /*****************************************************************************/
433 /*                                                                           */
434 /*   ABR SAR Network operation Register                                      */
435 /*                                                                           */
436 /*****************************************************************************/
437
438 #define SAR_REG_DR0     (card->membase + 0x00)
439 #define SAR_REG_DR1     (card->membase + 0x04)
440 #define SAR_REG_DR2     (card->membase + 0x08)
441 #define SAR_REG_DR3     (card->membase + 0x0C)
442 #define SAR_REG_CMD     (card->membase + 0x10)
443 #define SAR_REG_CFG     (card->membase + 0x14)
444 #define SAR_REG_STAT    (card->membase + 0x18)
445 #define SAR_REG_RSQB    (card->membase + 0x1C)
446 #define SAR_REG_RSQT    (card->membase + 0x20)
447 #define SAR_REG_RSQH    (card->membase + 0x24)
448 #define SAR_REG_CDC     (card->membase + 0x28)
449 #define SAR_REG_VPEC    (card->membase + 0x2C)
450 #define SAR_REG_ICC     (card->membase + 0x30)
451 #define SAR_REG_RAWCT   (card->membase + 0x34)
452 #define SAR_REG_TMR     (card->membase + 0x38)
453 #define SAR_REG_TSTB    (card->membase + 0x3C)
454 #define SAR_REG_TSQB    (card->membase + 0x40)
455 #define SAR_REG_TSQT    (card->membase + 0x44)
456 #define SAR_REG_TSQH    (card->membase + 0x48)
457 #define SAR_REG_GP      (card->membase + 0x4C)
458 #define SAR_REG_VPM     (card->membase + 0x50)
459 #define SAR_REG_RXFD    (card->membase + 0x54)
460 #define SAR_REG_RXFT    (card->membase + 0x58)
461 #define SAR_REG_RXFH    (card->membase + 0x5C)
462 #define SAR_REG_RAWHND  (card->membase + 0x60)
463 #define SAR_REG_RXSTAT  (card->membase + 0x64)
464 #define SAR_REG_ABRSTD  (card->membase + 0x68)
465 #define SAR_REG_ABRRQ   (card->membase + 0x6C)
466 #define SAR_REG_VBRRQ   (card->membase + 0x70)
467 #define SAR_REG_RTBL    (card->membase + 0x74)
468 #define SAR_REG_MDFCT   (card->membase + 0x78)
469 #define SAR_REG_TXSTAT  (card->membase + 0x7C)
470 #define SAR_REG_TCMDQ   (card->membase + 0x80)
471 #define SAR_REG_IRCP    (card->membase + 0x84)
472 #define SAR_REG_FBQP0   (card->membase + 0x88)
473 #define SAR_REG_FBQP1   (card->membase + 0x8C)
474 #define SAR_REG_FBQP2   (card->membase + 0x90)
475 #define SAR_REG_FBQP3   (card->membase + 0x94)
476 #define SAR_REG_FBQS0   (card->membase + 0x98)
477 #define SAR_REG_FBQS1   (card->membase + 0x9C)
478 #define SAR_REG_FBQS2   (card->membase + 0xA0)
479 #define SAR_REG_FBQS3   (card->membase + 0xA4)
480 #define SAR_REG_FBQWP0  (card->membase + 0xA8)
481 #define SAR_REG_FBQWP1  (card->membase + 0xAC)
482 #define SAR_REG_FBQWP2  (card->membase + 0xB0)
483 #define SAR_REG_FBQWP3  (card->membase + 0xB4)
484 #define SAR_REG_NOW     (card->membase + 0xB8)
485
486
487 /*****************************************************************************/
488 /*                                                                           */
489 /*   Commands                                                                */
490 /*                                                                           */
491 /*****************************************************************************/
492
493 #define SAR_CMD_NO_OPERATION         0x00000000
494 #define SAR_CMD_OPENCLOSE_CONNECTION 0x20000000
495 #define SAR_CMD_WRITE_SRAM           0x40000000
496 #define SAR_CMD_READ_SRAM            0x50000000
497 #define SAR_CMD_READ_UTILITY         0x80000000
498 #define SAR_CMD_WRITE_UTILITY        0x90000000
499
500 #define SAR_CMD_OPEN_CONNECTION     (SAR_CMD_OPENCLOSE_CONNECTION | 0x00080000)
501 #define SAR_CMD_CLOSE_CONNECTION     SAR_CMD_OPENCLOSE_CONNECTION
502
503
504 /*****************************************************************************/
505 /*                                                                           */
506 /*   Configuration Register bits                                             */
507 /*                                                                           */
508 /*****************************************************************************/
509
510 #define SAR_CFG_SWRST          0x80000000  /* Software reset                 */
511 #define SAR_CFG_LOOP           0x40000000  /* Internal Loopback              */
512 #define SAR_CFG_RXPTH          0x20000000  /* Receive Path Enable            */
513 #define SAR_CFG_IDLE_CLP       0x10000000  /* SAR set CLP Bits of Null Cells */
514 #define SAR_CFG_TX_FIFO_SIZE_1 0x04000000  /* TX FIFO Size = 1 cell          */
515 #define SAR_CFG_TX_FIFO_SIZE_2 0x08000000  /* TX FIFO Size = 2 cells         */
516 #define SAR_CFG_TX_FIFO_SIZE_4 0x0C000000  /* TX FIFO Size = 4 cells         */
517 #define SAR_CFG_TX_FIFO_SIZE_9 0x00000000  /* TX FIFO Size = 9 cells (full)  */
518 #define SAR_CFG_NO_IDLE        0x02000000  /* SAR sends no Null Cells        */
519 #define SAR_CFG_RSVD1          0x01000000  /* Reserved                       */
520 #define SAR_CFG_RXSTQ_SIZE_2k  0x00000000  /* RX Stat Queue Size = 2048 byte */
521 #define SAR_CFG_RXSTQ_SIZE_4k  0x00400000  /* RX Stat Queue Size = 4096 byte */
522 #define SAR_CFG_RXSTQ_SIZE_8k  0x00800000  /* RX Stat Queue Size = 8192 byte */
523 #define SAR_CFG_RXSTQ_SIZE_R   0x00C00000  /* RX Stat Queue Size = reserved  */
524 #define SAR_CFG_ICAPT          0x00200000  /* accept Invalid Cells           */
525 #define SAR_CFG_IGGFC          0x00100000  /* Ignore GFC                     */
526 #define SAR_CFG_VPVCS_0        0x00000000  /* VPI/VCI Select bit range       */
527 #define SAR_CFG_VPVCS_1        0x00040000  /* VPI/VCI Select bit range       */
528 #define SAR_CFG_VPVCS_2        0x00080000  /* VPI/VCI Select bit range       */
529 #define SAR_CFG_VPVCS_8        0x000C0000  /* VPI/VCI Select bit range       */
530 #define SAR_CFG_CNTBL_1k       0x00000000  /* Connection Table Size          */
531 #define SAR_CFG_CNTBL_4k       0x00010000  /* Connection Table Size          */
532 #define SAR_CFG_CNTBL_16k      0x00020000  /* Connection Table Size          */
533 #define SAR_CFG_CNTBL_512      0x00030000  /* Connection Table Size          */
534 #define SAR_CFG_VPECA          0x00008000  /* VPI/VCI Error Cell Accept      */
535 #define SAR_CFG_RXINT_NOINT    0x00000000  /* No Interrupt on PDU received   */
536 #define SAR_CFG_RXINT_NODELAY  0x00001000  /* Interrupt without delay to host*/
537 #define SAR_CFG_RXINT_256US    0x00002000  /* Interrupt with delay 256 usec  */
538 #define SAR_CFG_RXINT_505US    0x00003000  /* Interrupt with delay 505 usec  */
539 #define SAR_CFG_RXINT_742US    0x00004000  /* Interrupt with delay 742 usec  */
540 #define SAR_CFG_RAWIE          0x00000800  /* Raw Cell Queue Interrupt Enable*/
541 #define SAR_CFG_RQFIE          0x00000400  /* RSQ Almost Full Int Enable     */
542 #define SAR_CFG_RSVD2          0x00000200  /* Reserved                       */
543 #define SAR_CFG_CACHE          0x00000100  /* DMA on Cache Line Boundary     */
544 #define SAR_CFG_TMOIE          0x00000080  /* Timer Roll Over Int Enable     */
545 #define SAR_CFG_FBIE           0x00000040  /* Free Buffer Queue Int Enable   */
546 #define SAR_CFG_TXEN           0x00000020  /* Transmit Operation Enable      */
547 #define SAR_CFG_TXINT          0x00000010  /* Transmit status Int Enable     */
548 #define SAR_CFG_TXUIE          0x00000008  /* Transmit underrun Int Enable   */
549 #define SAR_CFG_UMODE          0x00000004  /* Utopia Mode Select             */
550 #define SAR_CFG_TXSFI          0x00000002  /* Transmit status Full Int Enable*/
551 #define SAR_CFG_PHYIE          0x00000001  /* PHY Interrupt Enable           */
552
553 #define SAR_CFG_TX_FIFO_SIZE_MASK 0x0C000000  /* TX FIFO Size Mask           */
554 #define SAR_CFG_RXSTQSIZE_MASK 0x00C00000
555 #define SAR_CFG_CNTBL_MASK     0x00030000
556 #define SAR_CFG_RXINT_MASK     0x00007000
557
558
559 /*****************************************************************************/
560 /*                                                                           */
561 /*   Status Register bits                                                    */
562 /*                                                                           */
563 /*****************************************************************************/
564
565 #define SAR_STAT_FRAC_3     0xF0000000 /* Fraction of Free Buffer Queue 3 */
566 #define SAR_STAT_FRAC_2     0x0F000000 /* Fraction of Free Buffer Queue 2 */
567 #define SAR_STAT_FRAC_1     0x00F00000 /* Fraction of Free Buffer Queue 1 */
568 #define SAR_STAT_FRAC_0     0x000F0000 /* Fraction of Free Buffer Queue 0 */
569 #define SAR_STAT_TSIF       0x00008000 /* Transmit Status Indicator       */
570 #define SAR_STAT_TXICP      0x00004000 /* Transmit Status Indicator       */
571 #define SAR_STAT_RSVD1      0x00002000 /* Reserved                        */
572 #define SAR_STAT_TSQF       0x00001000 /* Transmit Status Queue full      */
573 #define SAR_STAT_TMROF      0x00000800 /* Timer overflow                  */
574 #define SAR_STAT_PHYI       0x00000400 /* PHY device Interrupt flag       */
575 #define SAR_STAT_CMDBZ      0x00000200 /* ABR SAR Comand Busy Flag        */
576 #define SAR_STAT_FBQ3A      0x00000100 /* Free Buffer Queue 3 Attention   */
577 #define SAR_STAT_FBQ2A      0x00000080 /* Free Buffer Queue 2 Attention   */
578 #define SAR_STAT_RSQF       0x00000040 /* Receive Status Queue full       */
579 #define SAR_STAT_EPDU       0x00000020 /* End Of PDU Flag                 */
580 #define SAR_STAT_RAWCF      0x00000010 /* Raw Cell Flag                   */ 
581 #define SAR_STAT_FBQ1A      0x00000008 /* Free Buffer Queue 1 Attention   */
582 #define SAR_STAT_FBQ0A      0x00000004 /* Free Buffer Queue 0 Attention   */
583 #define SAR_STAT_RSQAF      0x00000002 /* Receive Status Queue almost full*/  
584 #define SAR_STAT_RSVD2      0x00000001 /* Reserved                        */
585
586
587 /*****************************************************************************/
588 /*                                                                           */
589 /*   General Purpose Register bits                                           */
590 /*                                                                           */
591 /*****************************************************************************/
592
593 #define SAR_GP_TXNCC_MASK   0xff000000  /* Transmit Negative Credit Count   */
594 #define SAR_GP_EEDI         0x00010000  /* EEPROM Data In                   */
595 #define SAR_GP_BIGE         0x00008000  /* Big Endian Operation             */
596 #define SAR_GP_RM_NORMAL    0x00000000  /* Normal handling of RM cells      */
597 #define SAR_GP_RM_TO_RCQ    0x00002000  /* put RM cells into Raw Cell Queue */
598 #define SAR_GP_RM_RSVD      0x00004000  /* Reserved                         */
599 #define SAR_GP_RM_INHIBIT   0x00006000  /* Inhibit update of Connection tab */
600 #define SAR_GP_PHY_RESET    0x00000008  /* PHY Reset                        */
601 #define SAR_GP_EESCLK       0x00000004  /* EEPROM SCLK                      */
602 #define SAR_GP_EECS         0x00000002  /* EEPROM Chip Select               */
603 #define SAR_GP_EEDO         0x00000001  /* EEPROM Data Out                  */
604
605
606 /*****************************************************************************/
607 /*                                                                           */
608 /*   SAR local SRAM layout for 128k work SRAM                                */
609 /*                                                                           */
610 /*****************************************************************************/
611
612 #define SAR_SRAM_SCD_SIZE        12
613 #define SAR_SRAM_TCT_SIZE         8
614 #define SAR_SRAM_RCT_SIZE         4
615
616 #define SAR_SRAM_TCT_128_BASE    0x00000
617 #define SAR_SRAM_TCT_128_TOP     0x01fff
618 #define SAR_SRAM_RCT_128_BASE    0x02000
619 #define SAR_SRAM_RCT_128_TOP     0x02fff
620 #define SAR_SRAM_FB0_128_BASE    0x03000
621 #define SAR_SRAM_FB0_128_TOP     0x033ff
622 #define SAR_SRAM_FB1_128_BASE    0x03400
623 #define SAR_SRAM_FB1_128_TOP     0x037ff
624 #define SAR_SRAM_FB2_128_BASE    0x03800
625 #define SAR_SRAM_FB2_128_TOP     0x03bff
626 #define SAR_SRAM_FB3_128_BASE    0x03c00
627 #define SAR_SRAM_FB3_128_TOP     0x03fff
628 #define SAR_SRAM_SCD_128_BASE    0x04000
629 #define SAR_SRAM_SCD_128_TOP     0x07fff
630 #define SAR_SRAM_TST1_128_BASE   0x08000
631 #define SAR_SRAM_TST1_128_TOP    0x0bfff
632 #define SAR_SRAM_TST2_128_BASE   0x0c000
633 #define SAR_SRAM_TST2_128_TOP    0x0ffff
634 #define SAR_SRAM_ABRSTD_128_BASE 0x10000
635 #define SAR_SRAM_ABRSTD_128_TOP  0x13fff
636 #define SAR_SRAM_RT_128_BASE     0x14000
637 #define SAR_SRAM_RT_128_TOP      0x15fff
638
639 #define SAR_SRAM_FIFO_128_BASE   0x18000
640 #define SAR_SRAM_FIFO_128_TOP    0x1ffff
641
642
643 /*****************************************************************************/
644 /*                                                                           */
645 /*   SAR local SRAM layout for 32k work SRAM                                 */
646 /*                                                                           */
647 /*****************************************************************************/
648
649 #define SAR_SRAM_TCT_32_BASE     0x00000
650 #define SAR_SRAM_TCT_32_TOP      0x00fff
651 #define SAR_SRAM_RCT_32_BASE     0x01000
652 #define SAR_SRAM_RCT_32_TOP      0x017ff
653 #define SAR_SRAM_FB0_32_BASE     0x01800
654 #define SAR_SRAM_FB0_32_TOP      0x01bff
655 #define SAR_SRAM_FB1_32_BASE     0x01c00
656 #define SAR_SRAM_FB1_32_TOP      0x01fff
657 #define SAR_SRAM_FB2_32_BASE     0x02000
658 #define SAR_SRAM_FB2_32_TOP      0x023ff
659 #define SAR_SRAM_FB3_32_BASE     0x02400
660 #define SAR_SRAM_FB3_32_TOP      0x027ff
661 #define SAR_SRAM_SCD_32_BASE     0x02800
662 #define SAR_SRAM_SCD_32_TOP      0x03fff
663 #define SAR_SRAM_TST1_32_BASE    0x04000
664 #define SAR_SRAM_TST1_32_TOP     0x04fff
665 #define SAR_SRAM_TST2_32_BASE    0x05000
666 #define SAR_SRAM_TST2_32_TOP     0x05fff
667 #define SAR_SRAM_ABRSTD_32_BASE  0x06000
668 #define SAR_SRAM_ABRSTD_32_TOP   0x067ff
669 #define SAR_SRAM_RT_32_BASE      0x06800
670 #define SAR_SRAM_RT_32_TOP       0x06fff
671 #define SAR_SRAM_FIFO_32_BASE    0x07000
672 #define SAR_SRAM_FIFO_32_TOP     0x07fff
673
674
675 /*****************************************************************************/
676 /*                                                                           */
677 /*   TSR - Transmit Status Request                                           */
678 /*                                                                           */
679 /*****************************************************************************/
680
681 #define SAR_TSR_TYPE_TSR  0x80000000
682 #define SAR_TSR_TYPE_TBD  0x00000000
683 #define SAR_TSR_TSIF      0x20000000
684 #define SAR_TSR_TAG_MASK  0x01F00000
685
686
687 /*****************************************************************************/
688 /*                                                                           */
689 /*   TBD - Transmit Buffer Descriptor                                        */
690 /*                                                                           */
691 /*****************************************************************************/
692
693 #define SAR_TBD_EPDU      0x40000000
694 #define SAR_TBD_TSIF      0x20000000
695 #define SAR_TBD_OAM       0x10000000
696 #define SAR_TBD_AAL0      0x00000000
697 #define SAR_TBD_AAL34     0x04000000
698 #define SAR_TBD_AAL5      0x08000000
699 #define SAR_TBD_GTSI      0x02000000
700 #define SAR_TBD_TAG_MASK  0x01F00000
701
702 #define SAR_TBD_VPI_MASK  0x0FF00000
703 #define SAR_TBD_VCI_MASK  0x000FFFF0
704 #define SAR_TBD_VC_MASK   (SAR_TBD_VPI_MASK | SAR_TBD_VCI_MASK)
705
706 #define SAR_TBD_VPI_SHIFT 20
707 #define SAR_TBD_VCI_SHIFT 4
708
709
710 /*****************************************************************************/
711 /*                                                                           */
712 /*   RXFD - Receive FIFO Descriptor                                          */
713 /*                                                                           */
714 /*****************************************************************************/
715
716 #define SAR_RXFD_SIZE_MASK     0x0F000000
717 #define SAR_RXFD_SIZE_512      0x00000000  /* 512 words                      */
718 #define SAR_RXFD_SIZE_1K       0x01000000  /* 1k words                       */
719 #define SAR_RXFD_SIZE_2K       0x02000000  /* 2k words                       */
720 #define SAR_RXFD_SIZE_4K       0x03000000  /* 4k words                       */
721 #define SAR_RXFD_SIZE_8K       0x04000000  /* 8k words                       */
722 #define SAR_RXFD_SIZE_16K      0x05000000  /* 16k words                      */
723 #define SAR_RXFD_SIZE_32K      0x06000000  /* 32k words                      */
724 #define SAR_RXFD_SIZE_64K      0x07000000  /* 64k words                      */
725 #define SAR_RXFD_SIZE_128K     0x08000000  /* 128k words                     */
726 #define SAR_RXFD_SIZE_256K     0x09000000  /* 256k words                     */
727 #define SAR_RXFD_ADDR_MASK     0x001ffc00
728
729
730 /*****************************************************************************/
731 /*                                                                           */
732 /*   ABRSTD - ABR + VBR Schedule Tables                                      */
733 /*                                                                           */
734 /*****************************************************************************/
735
736 #define SAR_ABRSTD_SIZE_MASK   0x07000000
737 #define SAR_ABRSTD_SIZE_512    0x00000000  /* 512 words                      */
738 #define SAR_ABRSTD_SIZE_1K     0x01000000  /* 1k words                       */
739 #define SAR_ABRSTD_SIZE_2K     0x02000000  /* 2k words                       */
740 #define SAR_ABRSTD_SIZE_4K     0x03000000  /* 4k words                       */
741 #define SAR_ABRSTD_SIZE_8K     0x04000000  /* 8k words                       */
742 #define SAR_ABRSTD_SIZE_16K    0x05000000  /* 16k words                      */
743 #define SAR_ABRSTD_ADDR_MASK   0x001ffc00
744
745
746 /*****************************************************************************/
747 /*                                                                           */
748 /*   RCTE - Receive Connection Table Entry                                   */
749 /*                                                                           */
750 /*****************************************************************************/
751
752 #define SAR_RCTE_IL_MASK       0xE0000000  /* inactivity limit               */
753 #define SAR_RCTE_IC_MASK       0x1C000000  /* inactivity count               */
754 #define SAR_RCTE_RSVD          0x02000000  /* reserved                       */
755 #define SAR_RCTE_LCD           0x01000000  /* last cell data                 */
756 #define SAR_RCTE_CI_VC         0x00800000  /* EFCI in previous cell of VC    */
757 #define SAR_RCTE_FBP_01        0x00000000  /* 1. cell->FBQ0, others->FBQ1    */
758 #define SAR_RCTE_FBP_1         0x00200000  /* use FBQ 1 for all cells        */
759 #define SAR_RCTE_FBP_2         0x00400000  /* use FBQ 2 for all cells        */
760 #define SAR_RCTE_FBP_3         0x00600000  /* use FBQ 3 for all cells        */
761 #define SAR_RCTE_NZ_GFC        0x00100000  /* non zero GFC in all cell of VC */
762 #define SAR_RCTE_CONNECTOPEN   0x00080000  /* VC is open                     */
763 #define SAR_RCTE_AAL_MASK      0x00070000  /* mask for AAL type field s.b.   */
764 #define SAR_RCTE_RAWCELLINTEN  0x00008000  /* raw cell interrupt enable      */
765 #define SAR_RCTE_RXCONCELLADDR 0x00004000  /* RX constant cell address       */
766 #define SAR_RCTE_BUFFSTAT_MASK 0x00003000  /* buffer status                  */
767 #define SAR_RCTE_EFCI          0x00000800  /* EFCI Congestion flag           */
768 #define SAR_RCTE_CLP           0x00000400  /* Cell Loss Priority flag        */
769 #define SAR_RCTE_CRC           0x00000200  /* Recieved CRC Error             */
770 #define SAR_RCTE_CELLCNT_MASK  0x000001FF  /* cell Count                     */
771
772 #define SAR_RCTE_AAL0          0x00000000  /* AAL types for ALL field        */
773 #define SAR_RCTE_AAL34         0x00010000
774 #define SAR_RCTE_AAL5          0x00020000
775 #define SAR_RCTE_RCQ           0x00030000
776 #define SAR_RCTE_OAM           0x00040000
777
778 #define TCMDQ_START             0x01000000
779 #define TCMDQ_LACR              0x02000000
780 #define TCMDQ_START_LACR        0x03000000
781 #define TCMDQ_INIT_ER           0x04000000
782 #define TCMDQ_HALT              0x05000000
783
784
785 struct idt77252_skb_prv {
786         struct scqe     tbd;    /* Transmit Buffer Descriptor */
787         dma_addr_t      paddr;  /* DMA handle */
788         u32             pool;   /* sb_pool handle */
789 };
790
791 #define IDT77252_PRV_TBD(skb)   \
792         (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->tbd)
793 #define IDT77252_PRV_PADDR(skb) \
794         (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->paddr)
795 #define IDT77252_PRV_POOL(skb)  \
796         (((struct idt77252_skb_prv *)(ATM_SKB(skb)+1))->pool)
797
798 /*****************************************************************************/
799 /*                                                                           */
800 /*   PCI related items                                                       */
801 /*                                                                           */
802 /*****************************************************************************/
803
804 #ifndef PCI_VENDOR_ID_IDT
805 #define PCI_VENDOR_ID_IDT 0x111D
806 #endif /* PCI_VENDOR_ID_IDT */
807
808 #ifndef PCI_DEVICE_ID_IDT_IDT77252
809 #define PCI_DEVICE_ID_IDT_IDT77252 0x0003
810 #endif /* PCI_DEVICE_ID_IDT_IDT772052 */
811
812
813 #endif /* !(_IDT77252_H) */