libata: add another IRQ calls (libata drivers)
[linux-2.6.git] / drivers / ata / sata_vsc.c
1 /*
2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
3  *
4  *  Maintained by:  Jeremy Higdon @ SGI
5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
6  *                  on emails.
7  *
8  *  Copyright 2004 SGI
9  *
10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
11  *
12  *
13  *  This program is free software; you can redistribute it and/or modify
14  *  it under the terms of the GNU General Public License as published by
15  *  the Free Software Foundation; either version 2, or (at your option)
16  *  any later version.
17  *
18  *  This program is distributed in the hope that it will be useful,
19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
21  *  GNU General Public License for more details.
22  *
23  *  You should have received a copy of the GNU General Public License
24  *  along with this program; see the file COPYING.  If not, write to
25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26  *
27  *
28  *  libata documentation is available via 'make {ps|pdf}docs',
29  *  as Documentation/DocBook/libata.*
30  *
31  *  Vitesse hardware documentation presumably available under NDA.
32  *  Intel 31244 (same hardware interface) documentation presumably
33  *  available from http://developer.intel.com/
34  *
35  */
36
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/init.h>
41 #include <linux/blkdev.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
45 #include <linux/device.h>
46 #include <scsi/scsi_host.h>
47 #include <linux/libata.h>
48
49 #define DRV_NAME        "sata_vsc"
50 #define DRV_VERSION     "2.0"
51
52 enum {
53         VSC_MMIO_BAR                    = 0,
54
55         /* Interrupt register offsets (from chip base address) */
56         VSC_SATA_INT_STAT_OFFSET        = 0x00,
57         VSC_SATA_INT_MASK_OFFSET        = 0x04,
58
59         /* Taskfile registers offsets */
60         VSC_SATA_TF_CMD_OFFSET          = 0x00,
61         VSC_SATA_TF_DATA_OFFSET         = 0x00,
62         VSC_SATA_TF_ERROR_OFFSET        = 0x04,
63         VSC_SATA_TF_FEATURE_OFFSET      = 0x06,
64         VSC_SATA_TF_NSECT_OFFSET        = 0x08,
65         VSC_SATA_TF_LBAL_OFFSET         = 0x0c,
66         VSC_SATA_TF_LBAM_OFFSET         = 0x10,
67         VSC_SATA_TF_LBAH_OFFSET         = 0x14,
68         VSC_SATA_TF_DEVICE_OFFSET       = 0x18,
69         VSC_SATA_TF_STATUS_OFFSET       = 0x1c,
70         VSC_SATA_TF_COMMAND_OFFSET      = 0x1d,
71         VSC_SATA_TF_ALTSTATUS_OFFSET    = 0x28,
72         VSC_SATA_TF_CTL_OFFSET          = 0x29,
73
74         /* DMA base */
75         VSC_SATA_UP_DESCRIPTOR_OFFSET   = 0x64,
76         VSC_SATA_UP_DATA_BUFFER_OFFSET  = 0x6C,
77         VSC_SATA_DMA_CMD_OFFSET         = 0x70,
78
79         /* SCRs base */
80         VSC_SATA_SCR_STATUS_OFFSET      = 0x100,
81         VSC_SATA_SCR_ERROR_OFFSET       = 0x104,
82         VSC_SATA_SCR_CONTROL_OFFSET     = 0x108,
83
84         /* Port stride */
85         VSC_SATA_PORT_OFFSET            = 0x200,
86
87         /* Error interrupt status bit offsets */
88         VSC_SATA_INT_ERROR_CRC          = 0x40,
89         VSC_SATA_INT_ERROR_T            = 0x20,
90         VSC_SATA_INT_ERROR_P            = 0x10,
91         VSC_SATA_INT_ERROR_R            = 0x8,
92         VSC_SATA_INT_ERROR_E            = 0x4,
93         VSC_SATA_INT_ERROR_M            = 0x2,
94         VSC_SATA_INT_PHY_CHANGE         = 0x1,
95         VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
96                               VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
97                               VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
98                               VSC_SATA_INT_PHY_CHANGE),
99 };
100
101 #define is_vsc_sata_int_err(port_idx, int_status) \
102          (int_status & (VSC_SATA_INT_ERROR << (8 * port_idx)))
103
104
105 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
106 {
107         if (sc_reg > SCR_CONTROL)
108                 return 0xffffffffU;
109         return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
110 }
111
112
113 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
114                                u32 val)
115 {
116         if (sc_reg > SCR_CONTROL)
117                 return;
118         writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
119 }
120
121
122 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
123 {
124         void __iomem *mask_addr;
125         u8 mask;
126
127         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
128                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
129         mask = readb(mask_addr);
130         if (ctl & ATA_NIEN)
131                 mask |= 0x80;
132         else
133                 mask &= 0x7F;
134         writeb(mask, mask_addr);
135 }
136
137
138 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
139 {
140         struct ata_ioports *ioaddr = &ap->ioaddr;
141         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
142
143         /*
144          * The only thing the ctl register is used for is SRST.
145          * That is not enabled or disabled via tf_load.
146          * However, if ATA_NIEN is changed, then we need to change the interrupt register.
147          */
148         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
149                 ap->last_ctl = tf->ctl;
150                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
151         }
152         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
153                 writew(tf->feature | (((u16)tf->hob_feature) << 8),
154                        ioaddr->feature_addr);
155                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
156                        ioaddr->nsect_addr);
157                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
158                        ioaddr->lbal_addr);
159                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
160                        ioaddr->lbam_addr);
161                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
162                        ioaddr->lbah_addr);
163         } else if (is_addr) {
164                 writew(tf->feature, ioaddr->feature_addr);
165                 writew(tf->nsect, ioaddr->nsect_addr);
166                 writew(tf->lbal, ioaddr->lbal_addr);
167                 writew(tf->lbam, ioaddr->lbam_addr);
168                 writew(tf->lbah, ioaddr->lbah_addr);
169         }
170
171         if (tf->flags & ATA_TFLAG_DEVICE)
172                 writeb(tf->device, ioaddr->device_addr);
173
174         ata_wait_idle(ap);
175 }
176
177
178 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
179 {
180         struct ata_ioports *ioaddr = &ap->ioaddr;
181         u16 nsect, lbal, lbam, lbah, feature;
182
183         tf->command = ata_check_status(ap);
184         tf->device = readw(ioaddr->device_addr);
185         feature = readw(ioaddr->error_addr);
186         nsect = readw(ioaddr->nsect_addr);
187         lbal = readw(ioaddr->lbal_addr);
188         lbam = readw(ioaddr->lbam_addr);
189         lbah = readw(ioaddr->lbah_addr);
190
191         tf->feature = feature;
192         tf->nsect = nsect;
193         tf->lbal = lbal;
194         tf->lbam = lbam;
195         tf->lbah = lbah;
196
197         if (tf->flags & ATA_TFLAG_LBA48) {
198                 tf->hob_feature = feature >> 8;
199                 tf->hob_nsect = nsect >> 8;
200                 tf->hob_lbal = lbal >> 8;
201                 tf->hob_lbam = lbam >> 8;
202                 tf->hob_lbah = lbah >> 8;
203         }
204 }
205
206
207 /*
208  * vsc_sata_interrupt
209  *
210  * Read the interrupt register and process for the devices that have them pending.
211  */
212 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance)
213 {
214         struct ata_host *host = dev_instance;
215         unsigned int i;
216         unsigned int handled = 0;
217         u32 int_status;
218
219         spin_lock(&host->lock);
220
221         int_status = readl(host->iomap[VSC_MMIO_BAR] +
222                            VSC_SATA_INT_STAT_OFFSET);
223
224         for (i = 0; i < host->n_ports; i++) {
225                 if (int_status & ((u32) 0xFF << (8 * i))) {
226                         struct ata_port *ap;
227
228                         ap = host->ports[i];
229
230                         if (is_vsc_sata_int_err(i, int_status)) {
231                                 u32 err_status;
232                                 printk(KERN_DEBUG "%s: ignoring interrupt(s)\n", __FUNCTION__);
233                                 err_status = ap ? vsc_sata_scr_read(ap, SCR_ERROR) : 0;
234                                 vsc_sata_scr_write(ap, SCR_ERROR, err_status);
235                                 handled++;
236                         }
237
238                         if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
239                                 struct ata_queued_cmd *qc;
240
241                                 qc = ata_qc_from_tag(ap, ap->active_tag);
242                                 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
243                                         handled += ata_host_intr(ap, qc);
244                                 else if (is_vsc_sata_int_err(i, int_status)) {
245                                         /*
246                                          * On some chips (i.e. Intel 31244), an error
247                                          * interrupt will sneak in at initialization
248                                          * time (phy state changes).  Clearing the SCR
249                                          * error register is not required, but it prevents
250                                          * the phy state change interrupts from recurring
251                                          * later.
252                                          */
253                                         u32 err_status;
254                                         err_status = vsc_sata_scr_read(ap, SCR_ERROR);
255                                         printk(KERN_DEBUG "%s: clearing interrupt, "
256                                                "status %x; sata err status %x\n",
257                                                __FUNCTION__,
258                                                int_status, err_status);
259                                         vsc_sata_scr_write(ap, SCR_ERROR, err_status);
260                                         /* Clear interrupt status */
261                                         ata_chk_status(ap);
262                                         handled++;
263                                 }
264                         }
265                 }
266         }
267
268         spin_unlock(&host->lock);
269
270         return IRQ_RETVAL(handled);
271 }
272
273
274 static struct scsi_host_template vsc_sata_sht = {
275         .module                 = THIS_MODULE,
276         .name                   = DRV_NAME,
277         .ioctl                  = ata_scsi_ioctl,
278         .queuecommand           = ata_scsi_queuecmd,
279         .can_queue              = ATA_DEF_QUEUE,
280         .this_id                = ATA_SHT_THIS_ID,
281         .sg_tablesize           = LIBATA_MAX_PRD,
282         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
283         .emulated               = ATA_SHT_EMULATED,
284         .use_clustering         = ATA_SHT_USE_CLUSTERING,
285         .proc_name              = DRV_NAME,
286         .dma_boundary           = ATA_DMA_BOUNDARY,
287         .slave_configure        = ata_scsi_slave_config,
288         .slave_destroy          = ata_scsi_slave_destroy,
289         .bios_param             = ata_std_bios_param,
290 };
291
292
293 static const struct ata_port_operations vsc_sata_ops = {
294         .port_disable           = ata_port_disable,
295         .tf_load                = vsc_sata_tf_load,
296         .tf_read                = vsc_sata_tf_read,
297         .exec_command           = ata_exec_command,
298         .check_status           = ata_check_status,
299         .dev_select             = ata_std_dev_select,
300         .bmdma_setup            = ata_bmdma_setup,
301         .bmdma_start            = ata_bmdma_start,
302         .bmdma_stop             = ata_bmdma_stop,
303         .bmdma_status           = ata_bmdma_status,
304         .qc_prep                = ata_qc_prep,
305         .qc_issue               = ata_qc_issue_prot,
306         .data_xfer              = ata_data_xfer,
307         .freeze                 = ata_bmdma_freeze,
308         .thaw                   = ata_bmdma_thaw,
309         .error_handler          = ata_bmdma_error_handler,
310         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
311         .irq_handler            = vsc_sata_interrupt,
312         .irq_clear              = ata_bmdma_irq_clear,
313         .irq_on                 = ata_irq_on,
314         .irq_ack                = ata_irq_ack,
315         .scr_read               = vsc_sata_scr_read,
316         .scr_write              = vsc_sata_scr_write,
317         .port_start             = ata_port_start,
318 };
319
320 static void __devinit vsc_sata_setup_port(struct ata_ioports *port,
321                                           void __iomem *base)
322 {
323         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
324         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
325         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
326         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
327         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
328         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
329         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
330         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
331         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
332         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
333         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
334         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
335         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
336         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
337         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
338         writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
339         writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
340 }
341
342
343 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
344 {
345         static int printed_version;
346         struct ata_probe_ent *probe_ent;
347         void __iomem *mmio_base;
348         int rc;
349
350         if (!printed_version++)
351                 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
352
353         rc = pcim_enable_device(pdev);
354         if (rc)
355                 return rc;
356
357         /*
358          * Check if we have needed resource mapped.
359          */
360         if (pci_resource_len(pdev, 0) == 0)
361                 return -ENODEV;
362
363         rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
364         if (rc == -EBUSY)
365                 pcim_pin_device(pdev);
366         if (rc)
367                 return rc;
368
369         /*
370          * Use 32 bit DMA mask, because 64 bit address support is poor.
371          */
372         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
373         if (rc)
374                 return rc;
375         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
376         if (rc)
377                 return rc;
378
379         probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
380         if (probe_ent == NULL)
381                 return -ENOMEM;
382         probe_ent->dev = pci_dev_to_dev(pdev);
383         INIT_LIST_HEAD(&probe_ent->node);
384
385         /*
386          * Due to a bug in the chip, the default cache line size can't be used
387          */
388         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
389
390         if (pci_enable_msi(pdev) == 0)
391                 pci_intx(pdev, 0);
392         else
393                 probe_ent->irq_flags = IRQF_SHARED;
394
395         probe_ent->sht = &vsc_sata_sht;
396         probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
397                                 ATA_FLAG_MMIO;
398         probe_ent->port_ops = &vsc_sata_ops;
399         probe_ent->n_ports = 4;
400         probe_ent->irq = pdev->irq;
401         probe_ent->iomap = pcim_iomap_table(pdev);
402
403         /* We don't care much about the PIO/UDMA masks, but the core won't like us
404          * if we don't fill these
405          */
406         probe_ent->pio_mask = 0x1f;
407         probe_ent->mwdma_mask = 0x07;
408         probe_ent->udma_mask = 0x7f;
409
410         mmio_base = probe_ent->iomap[VSC_MMIO_BAR];
411
412         /* We have 4 ports per PCI function */
413         vsc_sata_setup_port(&probe_ent->port[0], mmio_base + 1 * VSC_SATA_PORT_OFFSET);
414         vsc_sata_setup_port(&probe_ent->port[1], mmio_base + 2 * VSC_SATA_PORT_OFFSET);
415         vsc_sata_setup_port(&probe_ent->port[2], mmio_base + 3 * VSC_SATA_PORT_OFFSET);
416         vsc_sata_setup_port(&probe_ent->port[3], mmio_base + 4 * VSC_SATA_PORT_OFFSET);
417
418         pci_set_master(pdev);
419
420         /*
421          * Config offset 0x98 is "Extended Control and Status Register 0"
422          * Default value is (1 << 28).  All bits except bit 28 are reserved in
423          * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
424          * If bit 28 is clear, each port has its own LED.
425          */
426         pci_write_config_dword(pdev, 0x98, 0);
427
428         if (!ata_device_add(probe_ent))
429                 return -ENODEV;
430
431         devm_kfree(&pdev->dev, probe_ent);
432         return 0;
433 }
434
435 static const struct pci_device_id vsc_sata_pci_tbl[] = {
436         { PCI_VENDOR_ID_VITESSE, 0x7174,
437           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
438         { PCI_VENDOR_ID_INTEL, 0x3200,
439           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
440
441         { }     /* terminate list */
442 };
443
444 static struct pci_driver vsc_sata_pci_driver = {
445         .name                   = DRV_NAME,
446         .id_table               = vsc_sata_pci_tbl,
447         .probe                  = vsc_sata_init_one,
448         .remove                 = ata_pci_remove_one,
449 };
450
451 static int __init vsc_sata_init(void)
452 {
453         return pci_register_driver(&vsc_sata_pci_driver);
454 }
455
456 static void __exit vsc_sata_exit(void)
457 {
458         pci_unregister_driver(&vsc_sata_pci_driver);
459 }
460
461 MODULE_AUTHOR("Jeremy Higdon");
462 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
463 MODULE_LICENSE("GPL");
464 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
465 MODULE_VERSION(DRV_VERSION);
466
467 module_init(vsc_sata_init);
468 module_exit(vsc_sata_exit);