config: tegra3: enable /dev mount with ACL
[linux-2.6.git] / drivers / ata / ahci-tegra.c
1 /*
2  * ahci-tegra.c - AHCI SATA support for TEGRA AHCI device
3  *
4  * Copyright (c) 2011-2012, NVIDIA Corporation.  All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
17  *
18  *
19  * libata documentation is available via 'make {ps|pdf}docs',
20  * as Documentation/DocBook/libata.*
21  *
22  * AHCI hardware documentation:
23  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
24  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
25  *
26  */
27
28 #include <linux/platform_device.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/blkdev.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/device.h>
38 #include <linux/dmi.h>
39 #include <scsi/scsi_host.h>
40 #include <scsi/scsi_cmnd.h>
41 #include <linux/libata.h>
42 #include <linux/regulator/machine.h>
43 #include <linux/pm_runtime.h>
44 #include "ahci.h"
45
46 #include <linux/clk.h>
47 #include <mach/clk.h>
48 #include <mach/iomap.h>
49 #include <mach/io.h>
50 #include <mach/powergate.h>
51
52 #define DRV_NAME        "tegra-sata"
53 #define DRV_VERSION     "1.0"
54
55 #define ENABLE_AHCI_DBG_PRINT                   0
56 #if ENABLE_AHCI_DBG_PRINT
57 #define AHCI_DBG_PRINT(fmt, arg...)  printk(KERN_ERR fmt, ## arg)
58 #else
59 #define AHCI_DBG_PRINT(fmt, arg...) do {} while (0)
60 #endif
61
62 /* number of AHCI ports */
63 #define TEGRA_AHCI_NUM_PORTS                    1
64
65 /* idle timeout for PM in msec */
66 #define TEGRA_AHCI_MIN_IDLE_TIME                1000
67 #define TEGRA_AHCI_DEFAULT_IDLE_TIME            2000
68
69 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
70 static u32 tegra_ahci_idle_time = TEGRA_AHCI_DEFAULT_IDLE_TIME;
71 #endif
72
73 /* Bit 0 (EN_FPCI) to allow FPCI accesses to SATA */
74 #define SATA_CONFIGURATION_0_OFFSET             0x180
75 #define EN_FPCI                                 (1 << 0)
76
77 #define SATA_INTR_MASK_0_OFFSET                 0x188
78 #define IP_INT_MASK                             (1 << 16)
79
80 /* Need to write 0x00400200 to 0x70020094 */
81 #define SATA_FPCI_BAR5_0_OFFSET                 0x094
82 #define PRI_ICTLR_CPU_IER_SET_0_OFFSET          0x024
83 #define CPU_IER_SATA_CTL                        (1 << 23)
84
85 #define AHCI_BAR5_CONFIG_LOCATION               0x24
86 #define TEGRA_SATA_BAR5_INIT_PROGRAM            0xFFFFFFFF
87 #define TEGRA_SATA_BAR5_FINAL_PROGRAM           0x40020000
88
89 #define FUSE_SATA_CALIB_OFFSET                  0x224
90 #define FUSE_SATA_CALIB_MASK                    0x3
91
92 #define T_SATA0_CFG_PHY_REG                     0x120
93 #define PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK     (1 << 11)
94
95 #define T_SATA0_CFG_POWER_GATE                  0x4ac
96 #define POWER_GATE_SSTS_RESTORED_MASK           (1 << 23)
97 #define POWER_GATE_SSTS_RESTORED_YES            (1 << 23)
98 #define POWER_GATE_SSTS_RESTORED_NO             (0 << 23)
99
100 #define T_SATA0_DBG0_OFFSET                     0x550
101
102 #define T_SATA0_INDEX_OFFSET                    0x680
103 #define SATA0_NONE_SELECTED                     0
104 #define SATA0_CH1_SELECTED                      (1 << 0)
105
106 #define T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET       0x690
107 #define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT   0
108 #define SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK    (0xff << 0)
109 #define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT  8
110 #define SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK   (0xff << 8)
111
112 #define T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET       0x694
113 #define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT   0
114 #define SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK    (0xff << 0)
115 #define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT  12
116 #define SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK   (0xff << 12)
117 #define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_SHIFT    24
118 #define SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_MASK     (0xf << 24)
119
120 /* AHCI config space defines */
121 #define TEGRA_PRIVATE_AHCI_CC_BKDR              0x4a4
122 #define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE     0x54c
123 #define TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN  (1 << 12)
124 #define TEGRA_PRIVATE_AHCI_CC_BKDR_PGM          0x01060100
125
126 /* AHCI HBA_CAP */
127 #define TEGRA_PRIVATE_AHCI_CAP_BKDR             0xa0
128 #define T_SATA0_AHCI_HBA_CAP_BKDR               0x300
129
130 #define TEGRA_SATA_IO_SPACE_OFFSET              4
131 #define TEGRA_SATA_ENABLE_IO_SPACE              (1 << 0)
132 #define TEGRA_SATA_ENABLE_MEM_SPACE             (1 << 1)
133 #define TEGRA_SATA_ENABLE_BUS_MASTER            (1 << 2)
134 #define TEGRA_SATA_ENABLE_SERR                  (1 << 8)
135
136 #define TEGRA_SATA_CORE_CLOCK_FREQ_HZ           (108*1000*1000)
137 #define TEGRA_SATA_OOB_CLOCK_FREQ_HZ            (216*1000*1000)
138
139 #define APB_PMC_SATA_PWRGT_0_REG                0x1ac
140 #define CLK_RST_SATA_PLL_CFG0_REG               0x490
141 #define CLK_RST_SATA_PLL_CFG1_REG               0x494
142 #define SATA_AUX_PAD_PLL_CNTL_1_REG             0x1100
143 #define SATA_AUX_MISC_CNTL_1_REG                0x1108
144
145 /* for APB_PMC_SATA_PWRGT_0_REG */
146 #define PG_INFO_MASK                            (1 << 6)
147 #define PG_INFO_ON                              (1 << 6)
148 #define PG_INFO_OFF                             (0 << 6)
149 #define PLLE_IDDQ_SWCTL_MASK                    (1 << 4)
150 #define PLLE_IDDQ_SWCTL_ON                      (1 << 4)
151 #define PLLE_IDDQ_SWCTL_OFF                     (0 << 4)
152 #define PADPHY_IDDQ_OVERRIDE_VALUE_MASK         (1 << 3)
153 #define PADPHY_IDDQ_OVERRIDE_VALUE_ON           (1 << 3)
154 #define PADPHY_IDDQ_OVERRIDE_VALUE_OFF          (0 << 3)
155 #define PADPHY_IDDQ_SWCTL_MASK                  (1 << 2)
156 #define PADPHY_IDDQ_SWCTL_ON                    (1 << 2)
157 #define PADPHY_IDDQ_SWCTL_OFF                   (0 << 2)
158 #define PADPLL_IDDQ_OVERRIDE_VALUE_MASK         (1 << 1)
159 #define PADPLL_IDDQ_OVERRIDE_VALUE_ON           (1 << 1)
160 #define PADPLL_IDDQ_OVERRIDE_VALUE_OFF          (0 << 1)
161 #define PADPLL_IDDQ_SWCTL_MASK                  (1 << 0)
162 #define PADPLL_IDDQ_SWCTL_ON                    (1 << 0)
163 #define PADPLL_IDDQ_SWCTL_OFF                   (0 << 0)
164
165 /* for CLK_RST_SATA_PLL_CFG0_REG */
166 #define PADPLL_RESET_OVERRIDE_VALUE_MASK        (1 << 1)
167 #define PADPLL_RESET_OVERRIDE_VALUE_ON          (1 << 1)
168 #define PADPLL_RESET_OVERRIDE_VALUE_OFF         (0 << 1)
169 #define PADPLL_RESET_SWCTL_MASK                 (1 << 0)
170 #define PADPLL_RESET_SWCTL_ON                   (1 << 0)
171 #define PADPLL_RESET_SWCTL_OFF                  (0 << 0)
172
173 /* for CLK_RST_SATA_PLL_CFG1_REG */
174 #define IDDQ2LANE_SLUMBER_DLY_MASK              (0xffL << 16)
175 #define IDDQ2LANE_SLUMBER_DLY_SHIFT             16
176 #define IDDQ2LANE_SLUMBER_DLY_3MS               (3 << 16)
177 #define IDDQ2LANE_IDDQ_DLY_SHIFT                0
178 #define IDDQ2LANE_IDDQ_DLY_MASK                 (0xffL << 0)
179
180 /* for SATA_AUX_PAD_PLL_CNTL_1_REG */
181 #define REFCLK_SEL_MASK                         (3 << 11)
182 #define REFCLK_SEL_INT_CML                      (0 << 11)
183 #define LOCKDET_FIELD                           (1 << 6)
184
185 /* for SATA_AUX_MISC_CNTL_1_REG */
186 #define NVA2SATA_OOB_ON_POR_MASK                (1 << 7)
187 #define NVA2SATA_OOB_ON_POR_YES                 (1 << 7)
188 #define NVA2SATA_OOB_ON_POR_NO                  (0 << 7)
189 #define L0_RX_IDLE_T_SAX_SHIFT                  5
190 #define L0_RX_IDLE_T_SAX_MASK                   (3 << 5)
191 #define L0_RX_IDLE_T_NPG_SHIFT                  3
192 #define L0_RX_IDLE_T_NPG_MASK                   (3 << 3)
193 #define L0_RX_IDLE_T_MUX_MASK                   (1 << 2)
194 #define L0_RX_IDLE_T_MUX_FROM_APB_MISC          (1 << 2)
195 #define L0_RX_IDLE_T_MUX_FROM_SATA              (0 << 2)
196
197 #define SSTAT_IPM_STATE_MASK                    0xF00
198 #define SSTAT_IPM_SLUMBER_STATE                 0x600
199
200 enum {
201         AHCI_PCI_BAR = 5,
202 };
203
204 enum port_idle_status {
205         PORT_IS_NOT_IDLE,
206         PORT_IS_IDLE,
207         PORT_IS_IDLE_NOT_SLUMBER,
208         PORT_IS_SLUMBER,
209 };
210
211 enum sata_state {
212         SATA_ON,
213         SATA_OFF,
214         SATA_GOING_ON,
215         SATA_GOING_OFF,
216         SATA_ABORT_OFF,
217 };
218
219 char *sata_power_rails[] = {
220         "avdd_sata",
221         "vdd_sata",
222         "hvdd_sata",
223         "avdd_sata_pll"
224 };
225
226 #define NUM_SATA_POWER_RAILS    ARRAY_SIZE(sata_power_rails)
227
228 struct tegra_qc_list {
229         struct list_head list;
230         struct ata_queued_cmd *qc;
231 };
232
233 /*
234  *  tegra_ahci_host_priv is the extension of ahci_host_priv
235  *  with extra fields: idle_timer, pg_save, pg_state, etc.
236  */
237 struct tegra_ahci_host_priv {
238         struct ahci_host_priv   ahci_host_priv;
239         struct regulator        *power_rails[NUM_SATA_POWER_RAILS];
240         void __iomem            *bars_table[6];
241         struct ata_host         *host;
242         struct timer_list       idle_timer;
243         struct device           *dev;
244         void                    *pg_save;
245         enum sata_state         pg_state;
246         struct list_head        qc_list;
247 };
248
249 static int tegra_ahci_init_one(struct platform_device *pdev);
250 static int tegra_ahci_remove_one(struct platform_device *pdev);
251
252 #ifdef CONFIG_PM
253 static bool tegra_ahci_power_un_gate(struct ata_host *host);
254 static bool tegra_ahci_power_gate(struct ata_host *host);
255 static void tegra_ahci_abort_power_gate(struct ata_host *host);
256 static int tegra_ahci_controller_suspend(struct platform_device *pdev);
257 static int tegra_ahci_controller_resume(struct platform_device *pdev);
258 static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg);
259 static int tegra_ahci_resume(struct platform_device *pdev);
260 static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap);
261 static bool tegra_ahci_are_all_ports_idle(struct ata_host *host);
262 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
263 static enum port_idle_status tegra_ahci_is_port_slumber(struct ata_port *ap);
264 static bool tegra_ahci_are_all_ports_slumber(struct ata_host *host);
265 static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc);
266 static int tegra_ahci_hardreset(struct ata_link *link, unsigned int *class,
267                                 unsigned long deadline);
268 static int tegra_ahci_runtime_suspend(struct device *dev);
269 static int tegra_ahci_runtime_resume(struct device *dev);
270 static void tegra_ahci_idle_timer(unsigned long arg);
271 static int tegra_ahci_queue_one_qc(struct tegra_ahci_host_priv *tegra_hpriv,
272                                    struct ata_queued_cmd *qc);
273 static void tegra_ahci_dequeue_qcs(struct tegra_ahci_host_priv *tegra_hpriv);
274 #endif
275 #else
276 #define tegra_ahci_controller_suspend   NULL
277 #define tegra_ahci_controller_resume    NULL
278 #define tegra_ahci_suspend              NULL
279 #define tegra_ahci_resume               NULL
280 #endif
281
282 static struct scsi_host_template ahci_sht = {
283         AHCI_SHT("tegra-sata"),
284 };
285
286 static struct ata_port_operations tegra_ahci_ops = {
287         .inherits       = &ahci_ops,
288 #ifdef CONFIG_PM
289 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
290         .qc_issue       = tegra_ahci_qc_issue,
291         .hardreset      = tegra_ahci_hardreset,
292 #endif
293 #endif
294 };
295
296 static const struct ata_port_info ahci_port_info = {
297         .flags          = AHCI_FLAG_COMMON,
298         .pio_mask       = 0x1f, /* pio0-4 */
299         .udma_mask      = ATA_UDMA6,
300         .port_ops       = &tegra_ahci_ops,
301 };
302
303 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
304 static const struct dev_pm_ops tegra_ahci_dev_rt_ops = {
305         .runtime_suspend = tegra_ahci_runtime_suspend,
306         .runtime_resume = tegra_ahci_runtime_resume,
307 };
308 #endif
309
310 static struct platform_driver tegra_platform_ahci_driver = {
311         .probe          = tegra_ahci_init_one,
312         .remove         = __devexit_p(tegra_ahci_remove_one),
313 #ifdef CONFIG_PM
314         .suspend        = tegra_ahci_suspend,
315         .resume         = tegra_ahci_resume,
316         .driver = {
317                 .name = DRV_NAME,
318 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
319                 .pm     = &tegra_ahci_dev_rt_ops,
320 #endif
321         }
322 #else
323         .driver = {
324                 .name = DRV_NAME,
325         }
326 #endif
327 };
328
329 struct tegra_ahci_host_priv *g_tegra_hpriv;
330
331 static inline u32 pmc_readl(u32 offset)
332 {
333         u32 val;
334         val = readl(IO_ADDRESS(TEGRA_PMC_BASE + offset));
335         AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_PMC_BASE+offset, val);
336         return val;
337 }
338
339 static inline void pmc_writel(u32 val, u32 offset)
340 {
341         AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PMC_BASE+offset, val);
342         writel(val, IO_ADDRESS(TEGRA_PMC_BASE + offset));
343 }
344
345 static inline u32 clk_readl(u32 offset)
346 {
347         u32 val;
348
349         val = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
350         AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val);
351         return val;
352 }
353
354 static inline void clk_writel(u32 val, u32 offset)
355 {
356         AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_CLK_RESET_BASE+offset, val);
357         writel(val, IO_ADDRESS(TEGRA_CLK_RESET_BASE + offset));
358 }
359
360 static inline u32 misc_readl(u32 offset)
361 {
362         u32 val;
363
364         val = readl(IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
365         AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val);
366         return val;
367 }
368
369 static inline void misc_writel(u32 val, u32 offset)
370 {
371         AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_APB_MISC_BASE+offset, val);
372         writel(val, IO_ADDRESS(TEGRA_APB_MISC_BASE + offset));
373 }
374
375 static inline u32 sata_readl(u32 offset)
376 {
377         u32 val;
378
379         val = readl(IO_ADDRESS(TEGRA_SATA_BASE + offset));
380         AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_BASE+offset, val);
381         return val;
382 }
383
384 static inline void sata_writel(u32 val, u32 offset)
385 {
386         AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_BASE+offset, val);
387         writel(val, IO_ADDRESS(TEGRA_SATA_BASE + offset));
388 }
389
390 static inline u32 scfg_readl(u32 offset)
391 {
392         u32 val;
393
394         val = readl(IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
395         AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset,
396                                              val);
397         return val;
398 }
399
400 static inline void scfg_writel(u32 val, u32 offset)
401 {
402         AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_SATA_CONFIG_BASE+offset,
403                                              val);
404         writel(val, IO_ADDRESS(TEGRA_SATA_CONFIG_BASE + offset));
405 }
406
407 static inline u32 pictlr_readl(u32 offset)
408 {
409         u32 val;
410
411         val = readl(IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
412         AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset,
413                                              val);
414         return val;
415 }
416
417 static inline void pictlr_writel(u32 val, u32 offset)
418 {
419         AHCI_DBG_PRINT("[0x%x] <= 0x%08x\n", TEGRA_PRIMARY_ICTLR_BASE+offset,
420                                              val);
421         writel(val, IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE + offset));
422 }
423
424 static inline u32 fuse_readl(u32 offset)
425 {
426         u32 val;
427
428         val = readl(IO_ADDRESS(TEGRA_FUSE_BASE + offset));
429         AHCI_DBG_PRINT("[0x%x] => 0x%08x\n", TEGRA_FUSE_BASE+offset, val);
430
431         return val;
432 }
433
434 /* Sata Pad Cntrl Values */
435 struct sata_pad_cntrl {
436         u8 gen1_tx_amp;
437         u8 gen1_tx_peak;
438         u8 gen2_tx_amp;
439         u8 gen2_tx_peak;
440 };
441
442 static const struct sata_pad_cntrl sata_calib_pad_val[] = {
443         {       /* SATA_CALIB[1:0]  = 00 */
444                 0x0c,
445                 0x04,
446                 0x0e,
447                 0x0a
448         },
449         {       /* SATA_CALIB[1:0]  = 01 */
450                 0x0e,
451                 0x04,
452                 0x14,
453                 0x0a
454         },
455         {       /* SATA_CALIB[1:0]  = 10 */
456                 0x0e,
457                 0x07,
458                 0x1a,
459                 0x0e
460         },
461         {       /* SATA_CALIB[1:0]  = 11 */
462                 0x14,
463                 0x0e,
464                 0x1a,
465                 0x0e
466         }
467 };
468
469 static void tegra_ahci_set_pad_cntrl_regs(void)
470 {
471         int     calib_val;
472         int     val;
473         int     i;
474
475         calib_val = fuse_readl(FUSE_SATA_CALIB_OFFSET) & FUSE_SATA_CALIB_MASK;
476
477         for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
478                 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
479
480                 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
481                 val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK;
482                 val |= (sata_calib_pad_val[calib_val].gen1_tx_amp <<
483                         SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT);
484                 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
485
486                 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
487                 val &= ~SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK;
488                 val |= (sata_calib_pad_val[calib_val].gen1_tx_peak <<
489                         SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
490                 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN1_OFFSET);
491
492                 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
493                 val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK;
494                 val |= (sata_calib_pad_val[calib_val].gen2_tx_amp <<
495                         SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT);
496                 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
497
498                 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
499                 val &= ~SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK;
500                 val |= (sata_calib_pad_val[calib_val].gen2_tx_peak <<
501                         SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT);
502                 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
503
504                 /* set 2 to SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ field */
505                 val = scfg_readl(T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
506                 val &= ~SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_MASK;
507                 val |= (2 << SATA0_CHX_PHY_CTRL1_GEN2_RX_EQ_SHIFT);
508                 scfg_writel(val, T_SATA0_CHX_PHY_CTRL1_GEN2_OFFSET);
509         }
510         scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
511 }
512
513 int tegra_ahci_get_rails(struct regulator *regulators[])
514 {
515         struct regulator *reg;
516         int i;
517         int ret = 0;
518
519         for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
520                 reg = regulator_get(NULL, sata_power_rails[i]);
521                 if (IS_ERR_OR_NULL(reg)) {
522                         pr_err("%s: can't get regulator %s\n",
523                                 __func__, sata_power_rails[i]);
524                         WARN_ON(1);
525                         ret = PTR_ERR(reg);
526                         goto exit;
527                 }
528                 regulators[i] = reg;
529         }
530 exit:
531         return ret;
532 }
533
534 void tegra_ahci_put_rails(struct regulator *regulators[])
535 {
536         int i;
537
538         for (i = 0; i < NUM_SATA_POWER_RAILS; ++i)
539                 regulator_put(regulators[i]);
540 }
541
542 int tegra_ahci_power_on_rails(struct regulator *regulators[])
543 {
544         struct regulator *reg;
545         int i;
546         int ret = 0;
547
548         for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
549                 reg = regulators[i];
550                 ret = regulator_enable(reg);
551                 if (ret) {
552                         pr_err("%s: can't enable regulator[%d]\n",
553                                 __func__, i);
554                         WARN_ON(1);
555                         goto exit;
556                 }
557         }
558
559 exit:
560         return ret;
561 }
562
563 int tegra_ahci_power_off_rails(struct regulator *regulators[])
564 {
565         struct regulator *reg;
566         int i;
567         int ret = 0;
568
569         for (i = 0; i < NUM_SATA_POWER_RAILS; ++i) {
570                 reg = regulators[i];
571                 if (!IS_ERR_OR_NULL(reg)) {
572                         ret = regulator_disable(reg);
573                         if (ret) {
574                                 pr_err("%s: can't disable regulator[%d]\n",
575                                         __func__, i);
576                                 WARN_ON(1);
577                                 goto exit;
578                         }
579                 }
580         }
581
582 exit:
583         return ret;
584 }
585 static int tegra_ahci_controller_init(struct tegra_ahci_host_priv *tegra_hpriv)
586 {
587         int err;
588         struct clk *clk_sata = NULL;
589         struct clk *clk_sata_oob = NULL;
590         struct clk *clk_sata_cold = NULL;
591         struct clk *clk_pllp = NULL;
592         u32 val;
593         u32 timeout;
594
595         err = tegra_ahci_get_rails(tegra_hpriv->power_rails);
596         if (err) {
597                 pr_err("%s: fails to get rails (%d)\n", __func__, err);
598                 goto exit;
599         }
600
601         err = tegra_ahci_power_on_rails(tegra_hpriv->power_rails);
602         if (err) {
603                 pr_err("%s: fails to power on rails (%d)\n", __func__, err);
604                 goto exit;
605         }
606
607         /* pll_p is the parent of tegra_sata and tegra_sata_oob */
608         clk_pllp = clk_get_sys(NULL, "pll_p");
609         if (IS_ERR_OR_NULL(clk_pllp)) {
610                 pr_err("%s: unable to get PLL_P clock\n", __func__);
611                 err = -ENODEV;
612                 goto exit;
613         }
614
615         clk_sata = clk_get_sys("tegra_sata", NULL);
616         if (IS_ERR_OR_NULL(clk_sata)) {
617                 pr_err("%s: unable to get SATA clock\n", __func__);
618                 err = -ENODEV;
619                 goto exit;
620         }
621
622         clk_sata_oob = clk_get_sys("tegra_sata_oob", NULL);
623         if (IS_ERR_OR_NULL(clk_sata_oob)) {
624                 pr_err("%s: unable to get SATA OOB clock\n", __func__);
625                 err = -ENODEV;
626                 goto exit;
627         }
628
629         clk_sata_cold = clk_get_sys("tegra_sata_cold", NULL);
630         if (IS_ERR_OR_NULL(clk_sata_cold)) {
631                 pr_err("%s: unable to get SATA COLD clock\n", __func__);
632                 err = -ENODEV;
633                 goto exit;
634         }
635
636         tegra_periph_reset_assert(clk_sata);
637         tegra_periph_reset_assert(clk_sata_oob);
638         tegra_periph_reset_assert(clk_sata_cold);
639         udelay(10);
640
641         /* need to establish both clocks divisors before setting clk sources */
642         clk_set_rate(clk_sata, clk_get_rate(clk_sata)/10);
643         clk_set_rate(clk_sata_oob, clk_get_rate(clk_sata_oob)/10);
644
645         /* set SATA clk and SATA_OOB clk source */
646         clk_set_parent(clk_sata, clk_pllp);
647         clk_set_parent(clk_sata_oob, clk_pllp);
648
649         /* Configure SATA clocks */
650         /* Core clock runs at 108MHz */
651         if (clk_set_rate(clk_sata, TEGRA_SATA_CORE_CLOCK_FREQ_HZ)) {
652                 err = -ENODEV;
653                 goto exit;
654         }
655         /* OOB clock runs at 216MHz */
656         if (clk_set_rate(clk_sata_oob, TEGRA_SATA_OOB_CLOCK_FREQ_HZ)) {
657                 err = -ENODEV;
658                 goto exit;
659         }
660
661         /**** Init the SATA PAD PLL ****/
662         /* SATA_PADPLL_IDDQ_SWCTL=1 and SATA_PADPLL_IDDQ_OVERRIDE_VALUE=1 */
663         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
664         val &= ~(PADPLL_IDDQ_SWCTL_MASK | PADPLL_IDDQ_OVERRIDE_VALUE_MASK);
665         val |= (PADPLL_IDDQ_SWCTL_ON | PADPLL_IDDQ_OVERRIDE_VALUE_ON);
666         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
667
668         /* SATA_PADPLL_RESET_OVERRIDE_VALUE=1 and SATA_PADPLL_RESET_SWCTL=1 */
669         val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
670         val &= ~(PADPLL_RESET_OVERRIDE_VALUE_MASK | PADPLL_RESET_SWCTL_MASK);
671         val |= (PADPLL_RESET_OVERRIDE_VALUE_ON | PADPLL_RESET_SWCTL_ON);
672         clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
673
674         /* SATA_PADPHY_IDDQ_OVERRIDE_VALUE and SATA_PADPHY_IDDQ_SWCTL = 1 */
675         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
676         val &= ~(PADPHY_IDDQ_OVERRIDE_VALUE_MASK | PADPHY_IDDQ_SWCTL_MASK);
677         val |= (PADPHY_IDDQ_OVERRIDE_VALUE_ON | PADPHY_IDDQ_SWCTL_ON);
678         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
679
680         /* Get SATA pad PLL out of IDDQ mode */
681         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
682         val &= ~PADPLL_IDDQ_OVERRIDE_VALUE_MASK;
683         val |= PADPLL_IDDQ_OVERRIDE_VALUE_OFF;
684         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
685         udelay(3);
686
687         /* select internal CML ref clk
688          * select PLLE as input to IO phy */
689         val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
690         val &= ~REFCLK_SEL_MASK;
691         val |= REFCLK_SEL_INT_CML;
692         misc_writel(val, SATA_AUX_PAD_PLL_CNTL_1_REG);
693
694         /* wait for SATA_PADPLL_IDDQ2LANE_SLUMBER_DLY = 3 microseconds. */
695         val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
696         val &= ~IDDQ2LANE_SLUMBER_DLY_MASK;
697         val |= IDDQ2LANE_SLUMBER_DLY_3MS;
698         clk_writel(val, CLK_RST_SATA_PLL_CFG1_REG);
699         udelay(3);
700
701         /* de-assert IDDQ mode signal going to PHY */
702         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
703         val &= ~PADPHY_IDDQ_OVERRIDE_VALUE_MASK;
704         val |= PADPHY_IDDQ_OVERRIDE_VALUE_OFF;
705         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
706
707         err = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);
708         if (err) {
709                 pr_err("%s: ** failed to turn-on SATA (0x%x) **\n",
710                                 __func__, err);
711                 goto exit;
712         }
713
714         /*
715          * place SATA Pad PLL out of reset by writing
716          * SATA_PADPLL_RST_OVERRIDE_VALUE = 0
717          */
718         val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
719         val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
720         val |= PADPLL_RESET_OVERRIDE_VALUE_OFF;
721         clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
722
723         /*
724          * Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with a timeout
725          * of 15 us.
726          */
727         timeout = 15;
728         while (timeout--) {
729                 udelay(1);
730                 val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
731                 if (val & LOCKDET_FIELD)
732                         break;
733         }
734         if (timeout == 0)
735                 pr_err("%s: AUX_PAD_PLL_CNTL_1 (0x%x) is not locked in 15us.\n",
736                         __func__, val);
737
738         /* clear SW control of SATA PADPLL, SATA PHY and PLLE */
739         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
740         val &= ~(PADPLL_IDDQ_SWCTL_MASK | PADPHY_IDDQ_SWCTL_MASK |
741                  PLLE_IDDQ_SWCTL_MASK);
742         val |= (PADPLL_IDDQ_SWCTL_OFF | PADPHY_IDDQ_SWCTL_OFF |
743                 PLLE_IDDQ_SWCTL_OFF);
744         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
745
746         val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
747         val &= ~PADPLL_RESET_SWCTL_MASK;
748         val |= PADPLL_RESET_SWCTL_OFF;
749         clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
750
751         /* clear NVA2SATA_OOB_ON_POR in SATA_AUX_MISC_CNTL_1_REG */
752         val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
753         val &= ~NVA2SATA_OOB_ON_POR_MASK;
754         misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
755
756         val = sata_readl(SATA_CONFIGURATION_0_OFFSET);
757         val |= EN_FPCI;
758         sata_writel(val, SATA_CONFIGURATION_0_OFFSET);
759
760         /* program sata pad control based on the fuse */
761         tegra_ahci_set_pad_cntrl_regs();
762
763         /*
764          * clear bit T_SATA0_CFG_PHY_0_USE_7BIT_ALIGN_DET_FOR_SPD of
765          * T_SATA0_CFG_PHY_0
766          */
767         val = scfg_readl(T_SATA0_CFG_PHY_REG);
768         val &= ~PHY_USE_7BIT_ALIGN_DET_FOR_SPD_MASK;
769         scfg_writel(val, T_SATA0_CFG_PHY_REG);
770
771         /*
772          * WAR: Before enabling SATA PLL shutdown, lockdet needs to be ignored.
773          *      To ignore lockdet, T_SATA0_DBG0_OFFSET register bit 10 needs to
774          *      be 1, and bit 8 needs to be 0.
775          */
776         val = scfg_readl(T_SATA0_DBG0_OFFSET);
777         val |= (1 << 10);
778         val &= ~(1 << 8);
779         scfg_writel(val, T_SATA0_DBG0_OFFSET);
780
781         /* program class code and programming interface for AHCI */
782         val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
783         val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
784         scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
785         scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
786         val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
787         scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
788
789         /* Program config space registers: */
790
791         /* Enable BUS_MASTER+MEM+IO space, and SERR */
792         val = scfg_readl(TEGRA_SATA_IO_SPACE_OFFSET);
793         val |= TEGRA_SATA_ENABLE_IO_SPACE | TEGRA_SATA_ENABLE_MEM_SPACE |
794                TEGRA_SATA_ENABLE_BUS_MASTER | TEGRA_SATA_ENABLE_SERR;
795         scfg_writel(val, TEGRA_SATA_IO_SPACE_OFFSET);
796
797         /* program bar5 space, by first writing 1's to bar5 register */
798         scfg_writel(TEGRA_SATA_BAR5_INIT_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
799         /* flush */
800         val = scfg_readl(AHCI_BAR5_CONFIG_LOCATION);
801
802         /* then, write the BAR5_FINAL_PROGRAM address */
803         scfg_writel(TEGRA_SATA_BAR5_FINAL_PROGRAM, AHCI_BAR5_CONFIG_LOCATION);
804         /* flush */
805         scfg_readl(AHCI_BAR5_CONFIG_LOCATION);
806
807         sata_writel((TEGRA_SATA_BAR5_FINAL_PROGRAM >> 8),
808                     SATA_FPCI_BAR5_0_OFFSET);
809
810         val = scfg_readl(T_SATA0_AHCI_HBA_CAP_BKDR);
811         val |= (HOST_CAP_ALPM | HOST_CAP_SSC | HOST_CAP_PART);
812         scfg_writel(val, T_SATA0_AHCI_HBA_CAP_BKDR);
813
814         /* enable Interrupt channel */
815         val = pictlr_readl(PRI_ICTLR_CPU_IER_SET_0_OFFSET);
816         val |= CPU_IER_SATA_CTL;
817         pictlr_writel(val, PRI_ICTLR_CPU_IER_SET_0_OFFSET);
818
819         /* set IP_INT_MASK */
820         val = sata_readl(SATA_INTR_MASK_0_OFFSET);
821         val |= IP_INT_MASK;
822         sata_writel(val, SATA_INTR_MASK_0_OFFSET);
823
824 exit:
825         if (!IS_ERR_OR_NULL(clk_pllp))
826                 clk_put(clk_pllp);
827         if (!IS_ERR_OR_NULL(clk_sata))
828                 clk_put(clk_sata);
829         if (!IS_ERR_OR_NULL(clk_sata_oob))
830                 clk_put(clk_sata_oob);
831         if (!IS_ERR_OR_NULL(clk_sata_cold))
832                 clk_put(clk_sata_cold);
833
834         if (err) {
835                 /* turn off all SATA power rails; ignore returned status */
836                 tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
837                 /* return regulators to system */
838                 tegra_ahci_put_rails(tegra_hpriv->power_rails);
839         }
840
841         return err;
842 }
843
844 static void tegra_ahci_save_initial_config(struct platform_device *pdev,
845                                            struct ahci_host_priv *hpriv)
846 {
847         ahci_save_initial_config(&pdev->dev, hpriv, 0, 0);
848 }
849
850 static void tegra_ahci_controller_remove(struct platform_device *pdev)
851 {
852         struct ata_host *host = dev_get_drvdata(&pdev->dev);
853         struct tegra_ahci_host_priv *tegra_hpriv;
854         int status;
855
856         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
857
858 #ifdef CONFIG_PM
859         /* call tegra_ahci_controller_suspend() to power-down the SATA */
860         status = tegra_ahci_controller_suspend(pdev);
861         if (status)
862                 dev_err(host->dev, "remove: error suspend SATA (0x%x)\n",
863                                    status);
864 #else
865         /* power off the sata */
866         status = tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
867         if (status)
868                 dev_err(host->dev, "remove: error turn-off SATA (0x%x)\n",
869                                    status);
870         tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
871 #endif
872
873         /* return system resources */
874         tegra_ahci_put_rails(tegra_hpriv->power_rails);
875 }
876
877 #ifdef CONFIG_PM
878 static int tegra_ahci_controller_suspend(struct platform_device *pdev)
879 {
880         struct ata_host *host = dev_get_drvdata(&pdev->dev);
881         struct tegra_ahci_host_priv *tegra_hpriv;
882         unsigned long flags;
883
884         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
885
886         /* stop the idle timer */
887         if (timer_pending(&tegra_hpriv->idle_timer))
888                 del_timer_sync(&tegra_hpriv->idle_timer);
889
890         spin_lock_irqsave(&host->lock, flags);
891         if (tegra_hpriv->pg_state == SATA_OFF)
892                 dev_dbg(host->dev, "suspend: SATA already power gated\n");
893         else {
894                 bool pg_ok;
895
896                 dev_dbg(host->dev, "suspend: power gating SATA...\n");
897                 pg_ok = tegra_ahci_power_gate(host);
898                 if (pg_ok) {
899                         tegra_hpriv->pg_state = SATA_OFF;
900                         dev_dbg(host->dev, "suspend: SATA is power gated\n");
901                 } else {
902                         dev_err(host->dev, "suspend: abort power gating\n");
903                         tegra_ahci_abort_power_gate(host);
904                         spin_unlock_irqrestore(&host->lock, flags);
905                         return -EBUSY;
906                 }
907         }
908         spin_unlock_irqrestore(&host->lock, flags);
909
910         return tegra_ahci_power_off_rails(tegra_hpriv->power_rails);
911 }
912
913 static int tegra_ahci_controller_resume(struct platform_device *pdev)
914 {
915         struct ata_host *host = dev_get_drvdata(&pdev->dev);
916         struct tegra_ahci_host_priv *tegra_hpriv;
917         unsigned long flags;
918         int err;
919
920         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
921
922         err = tegra_ahci_power_on_rails(tegra_hpriv->power_rails);
923         if (err) {
924                 pr_err("%s: fails to power on rails (%d)\n", __func__, err);
925                 return err;
926         }
927
928         spin_lock_irqsave(&host->lock, flags);
929         if (tegra_hpriv->pg_state == SATA_ON) {
930                 dev_dbg(host->dev, "resume: SATA already powered on\n");
931         } else {
932                 dev_dbg(host->dev, "resume: powering on SATA...\n");
933                 tegra_ahci_power_un_gate(host);
934                 tegra_hpriv->pg_state = SATA_ON;
935         }
936         spin_unlock_irqrestore(&host->lock, flags);
937
938         return 0;
939 }
940
941 static int tegra_ahci_suspend(struct platform_device *pdev, pm_message_t mesg)
942 {
943         struct ata_host *host = dev_get_drvdata(&pdev->dev);
944         void __iomem *mmio = host->iomap[AHCI_PCI_BAR];
945         u32 ctl;
946         int rc;
947
948         dev_dbg(host->dev, "** entering %s: **\n", __func__);
949         if (mesg.event & PM_EVENT_SLEEP) {
950                 /*
951                  * AHCI spec rev1.1 section 8.3.3:
952                  * Software must disable interrupts prior to requesting a
953                  * transition of the HBA to D3 state.
954                  */
955                 ctl = readl(mmio + HOST_CTL);
956                 ctl &= ~HOST_IRQ_EN;
957                 writel(ctl, mmio + HOST_CTL);
958                 readl(mmio + HOST_CTL); /* flush */
959         }
960
961         rc = ata_host_suspend(host, mesg);
962         if (rc)
963                 return rc;
964
965         return tegra_ahci_controller_suspend(pdev);
966 }
967
968 static int tegra_ahci_resume(struct platform_device *pdev)
969 {
970         struct ata_host *host = dev_get_drvdata(&pdev->dev);
971         int rc;
972
973         dev_dbg(host->dev, "** entering %s: **\n", __func__);
974         rc = tegra_ahci_controller_resume(pdev);
975         if (rc)
976                 return rc;
977
978         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
979                 rc = ahci_reset_controller(host);
980                 if (rc)
981                         return rc;
982
983                 ahci_init_controller(host);
984         }
985
986         ata_host_resume(host);
987         return 0;
988 }
989
990 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
991 static int tegra_ahci_runtime_suspend(struct device *dev)
992 {
993         struct ata_host *host;
994         struct tegra_ahci_host_priv *tegra_hpriv;
995         bool pg_ok;
996         unsigned long flags;
997         int err = 0;
998
999         host = dev_get_drvdata(dev);
1000         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1001
1002         spin_lock_irqsave(&host->lock, flags);
1003
1004         switch (tegra_hpriv->pg_state) {
1005         case SATA_OFF:
1006                 dev_dbg(dev, "** rt-suspend: already power gated **\n");
1007                 break;
1008
1009         case SATA_ABORT_OFF:
1010                 dev_dbg(dev, "** rt-suspend: abort suspend **\n");
1011                 pm_runtime_get_noresume(dev);
1012                 tegra_hpriv->pg_state = SATA_ON;
1013                 tegra_ahci_dequeue_qcs(tegra_hpriv);
1014                 err = -EBUSY;
1015                 break;
1016
1017         case SATA_ON:
1018         case SATA_GOING_OFF:
1019                 if (tegra_ahci_are_all_ports_idle(host)) {
1020                         /* if all ports are in idle, do power-gate */
1021                         dev_dbg(dev, "** rt-suspend: power-down sata (%u) **\n",
1022                                         tegra_hpriv->pg_state);
1023                         pg_ok = tegra_ahci_power_gate(host);
1024                         dev_dbg(dev, "** rt-suspend: done **\n");
1025                         if (pg_ok) {
1026                                 tegra_hpriv->pg_state = SATA_OFF;
1027                         } else {
1028                                 dev_err(dev, "** rt-suspend: abort pg **\n");
1029                                 tegra_ahci_abort_power_gate(host);
1030                                 tegra_hpriv->pg_state = SATA_ON;
1031                                 err = -EBUSY;
1032                         }
1033                 } else {
1034                         dev_dbg(dev, "** rt-suspend: port not idle (%u) **\n",
1035                                         tegra_hpriv->pg_state);
1036                         err = -EBUSY;
1037                 }
1038                 break;
1039
1040         case SATA_GOING_ON:
1041         default:
1042                 dev_err(dev, "** rt-suspend: bad state (%u) **\n",
1043                         tegra_hpriv->pg_state);
1044                 WARN_ON(1);
1045                 err = -EBUSY;
1046                 break;
1047
1048         }
1049
1050         spin_unlock_irqrestore(&host->lock, flags);
1051
1052         return err;
1053 }
1054
1055 static int tegra_ahci_runtime_resume(struct device *dev)
1056 {
1057         struct ata_host *host;
1058         struct tegra_ahci_host_priv *tegra_hpriv;
1059         unsigned long flags;
1060         int err = 0;
1061
1062         host = dev_get_drvdata(dev);
1063         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1064
1065         spin_lock_irqsave(&host->lock, flags);
1066
1067         if (tegra_hpriv->pg_state == SATA_ON) {
1068                 dev_dbg(dev, "** rt-resume: already power ungated **\n");
1069                 goto exit;
1070         }
1071
1072         if ((tegra_hpriv->pg_state == SATA_OFF) ||
1073             (tegra_hpriv->pg_state == SATA_GOING_ON)) {
1074                 dev_dbg(dev, "** rt-resume: power-up sata (%u) **\n",
1075                                 tegra_hpriv->pg_state);
1076                 tegra_ahci_power_un_gate(host);
1077                 dev_dbg(dev, "** rt-resume: done **\n");
1078                 tegra_hpriv->pg_state = SATA_ON;
1079
1080                 /* now qc_issue all qcs in the qc_list */
1081                 tegra_ahci_dequeue_qcs(tegra_hpriv);
1082         } else {
1083                 dev_err(dev, "** rt-resume: bad state (%u) **\n",
1084                                 tegra_hpriv->pg_state);
1085                 WARN_ON(1);
1086                 err = -EBUSY;
1087         }
1088
1089 exit:
1090         spin_unlock_irqrestore(&host->lock, flags);
1091         return err;
1092 }
1093 #endif
1094
1095 static u16 pg_save_bar5_registers[] = {
1096         0x018,  /* T_AHCI_HBA_CCC_PORTS */
1097         0x004,  /* T_AHCI_HBA_GHC */
1098         0x014,  /* T_AHCI_HBA_CCC_CTL - OP (optional) */
1099         0x01C,  /* T_AHCI_HBA_EM_LOC */
1100         0x020   /* T_AHCI_HBA_EM_CTL - OP */
1101 };
1102
1103 static u16 pg_save_bar5_port_registers[] = {
1104         0x100,  /* T_AHCI_PORT_PXCLB */
1105         0x104,  /* T_AHCI_PORT_PXCLBU */
1106         0x108,  /* T_AHCI_PORT_PXFB */
1107         0x10C,  /* T_AHCI_PORT_PXFBU */
1108         0x114,  /* T_AHCI_PORT_PXIE */
1109         0x118,  /* T_AHCI_PORT_PXCMD */
1110         0x12C   /* T_AHCI_PORT_PXSCTL */
1111 };
1112
1113 /*
1114  * pg_save_bar5_bkdr_registers:
1115  *    These registers in BAR5 are read only.
1116  * To restore back those register values, write the saved value
1117  *    to the registers specified in pg_restore_bar5_bkdr_registers[].
1118  *    These pg_restore_bar5_bkdr_registers[] are in SATA_CONFIG space.
1119  */
1120 static u16 pg_save_bar5_bkdr_registers[] = {
1121         /* Save and restore via bkdr writes */
1122         0x000,  /* T_AHCI_HBA_CAP */
1123         0x00C,  /* T_AHCI_HBA_PI */
1124         0x024   /* T_AHCI_HBA_CAP2 */
1125 };
1126
1127 static u16 pg_restore_bar5_bkdr_registers[] = {
1128         /* Save and restore via bkdr writes */
1129         0x300,  /* BKDR of T_AHCI_HBA_CAP */
1130         0x33c,  /* BKDR of T_AHCI_HBA_PI */
1131         0x330   /* BKDR of T_AHCI_HBA_CAP2 */
1132 };
1133
1134 /* These registers are saved for each port */
1135 static u16 pg_save_bar5_bkdr_port_registers[] = {
1136         0x120,  /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXTFD  */
1137         0x124,  /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXSIG */
1138         0x128   /* NV_PROJ__SATA0_CHX_AHCI_PORT_PXSSTS */
1139 };
1140
1141 static u16 pg_restore_bar5_bkdr_port_registers[] = {
1142         /* Save and restore via bkdr writes */
1143         0x790,  /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXTFD  */
1144         0x794,  /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXSIG */
1145         0x798   /* BKDR of NV_PROJ__SATA0_CHX_AHCI_PORT_PXSSTS */
1146 };
1147
1148 static u16 pg_save_config_registers[] = {
1149         0x004,  /* T_SATA0_CFG_1 */
1150         0x00C,  /* T_SATA0_CFG_3 */
1151         0x024,  /* T_SATA0_CFG_9 */
1152         0x028,  /* T_SATA0_CFG_10 */
1153         0x030,  /* T_SATA0_CFG_12 */
1154         0x034,  /* T_SATA0_CFG_13 */
1155         0x038,  /* T_SATA0_CFG_14 */
1156         0x03C,  /* T_SATA0_CFG_15 */
1157         0x040,  /* T_SATA0_CFG_16 */
1158         0x044,  /* T_SATA0_CFG_17 */
1159         0x048,  /* T_SATA0_CFG_18 */
1160         0x0B0,  /* T_SATA0_MSI_CTRL */
1161         0x0B4,  /* T_SATA0_MSI_ADDR1 */
1162         0x0B8,  /* T_SATA0_MSI_ADDR2 */
1163         0x0BC,  /* T_SATA0_MSI_DATA */
1164         0x0C0,  /* T_SATA0_MSI_QUEUE */
1165         0x0EC,  /* T_SATA0_MSI_MAP */
1166         0x124,  /* T_SATA0_CFG_PHY_POWER */
1167         0x128,  /* T_SATA0_CFG_PHY_POWER_1 */
1168         0x12C,  /* T_SATA0_CFG_PHY_1 */
1169         0x174,  /* T_SATA0_CFG_LINK_0 */
1170         0x178,  /* T_SATA0_CFG_LINK_1 */
1171         0x1D0,  /* MCP_SATA0_CFG_TRANS_0 */
1172         0x238,  /* T_SATA0_ALPM_CTRL */
1173         0x30C,  /* T_SATA0_AHCI_HBA_CYA_0 */
1174         0x320,  /* T_SATA0_AHCI_HBA_SPARE_1 */
1175         0x324,  /* T_SATA0_AHCI_HBA_SPARE_2 */
1176         0x328,  /* T_SATA0_AHCI_HBA_DYN_CLK_CLAMP */
1177         0x32C,  /* T_SATA0_AHCI_CFG_ERR_CTRL */
1178         0x338,  /* T_SATA0_AHCI_HBA_CYA_1 */
1179         0x340,  /* T_SATA0_AHCI_HBA_PRE_STAGING_CONTROL */
1180         0x430,  /* T_SATA0_CFG_FPCI_0 */
1181         0x494,  /* T_SATA0_CFG_ESATA_CTRL */
1182         0x4A0,  /* T_SATA0_CYA1 */
1183         0x4B0,  /* T_SATA0_CFG_GLUE */
1184         0x534,  /* T_SATA0_PHY_CTRL */
1185         0x540,  /* T_SATA0_CTRL */
1186         0x550,  /* T_SATA0_DBG0 */
1187         0x554   /* T_SATA0_LOW_POWER_COUNT */
1188 };
1189
1190 static u16 pg_save_config_port_registers[] = {
1191         /* Save and restore per port */
1192         /* need to have port selected */
1193         0x530,  /* T_SATA0_CHXCFG1 */
1194         0x684,  /* T_SATA0_CHX_MISC */
1195         0x700,  /* T_SATA0_CHXCFG3 */
1196         0x704,  /* T_SATA0_CHXCFG4_CHX */
1197         0x690,  /* T_SATA0_CHX_PHY_CTRL1_GEN1 */
1198         0x694,  /* T_SATA0_CHX_PHY_CTRL1_GEN2 */
1199         0x698,  /* T_SATA0_CHX_PHY_CTRL1_GEN3 */
1200         0x69C,  /* T_SATA0_CHX_PHY_CTRL_2 */
1201         0x6B0,  /* T_SATA0_CHX_PHY_CTRL_3 */
1202         0x6B4,  /* T_SATA0_CHX_PHY_CTRL_4 */
1203         0x6B8,  /* T_SATA0_CHX_PHY_CTRL_5 */
1204         0x6BC,  /* T_SATA0_CHX_PHY_CTRL_6 */
1205         0x714,  /* T_SATA0_PRBS_CHX - OP */
1206         0x750,  /* T_SATA0_CHX_LINK0 */
1207         0x7F0   /* T_SATA0_CHX_GLUE */
1208 };
1209
1210 static u16 pg_save_ipfs_registers[] = {
1211         0x094,  /* SATA_FPCI_BAR5_0 */
1212         0x0C0,  /* SATA_MSI_BAR_SZ_0 */
1213         0x0C4,  /* SATA_MSI_AXI_BAR_ST_0 */
1214         0x0C8,  /* SATA_MSI_FPCI_BAR_ST_0 */
1215         0x140,  /* SATA_MSI_EN_VEC0_0 */
1216         0x144,  /* SATA_MSI_EN_VEC1_0 */
1217         0x148,  /* SATA_MSI_EN_VEC2_0 */
1218         0x14C,  /* SATA_MSI_EN_VEC3_0 */
1219         0x150,  /* SATA_MSI_EN_VEC4_0 */
1220         0x154,  /* SATA_MSI_EN_VEC5_0 */
1221         0x158,  /* SATA_MSI_EN_VEC6_0 */
1222         0x15C,  /* SATA_MSI_EN_VEC7_0 */
1223         0x180,  /* SATA_CONFIGURATION_0 */
1224         0x184,  /* SATA_FPCI_ERROR_MASKS_0 */
1225         0x188,  /* SATA_INTR_MASK_0 */
1226         0x1A0,  /* SATA_CFG_REVID_0 */
1227         0x198,  /* SATA_IPFS_INTR_ENABLE_0 */
1228         0x1BC,  /* SATA_CLKGATE_HYSTERSIS_0 */
1229         0x1DC   /* SATA_SATA_MCCIF_FIFOCTRL_0 */
1230 };
1231
1232 static void tegra_ahci_save_regs(u32 **save_addr,
1233                                  u32 reg_base,
1234                                  u16 reg_array[],
1235                                  u32 regs)
1236 {
1237         u32 i;
1238         u32 *dest = (u32 *)*save_addr;
1239         u32 base = (u32)IO_ADDRESS(reg_base);
1240
1241         for (i = 0; i < regs; ++i, ++dest) {
1242                 *dest = readl(base + (u32)reg_array[i]);
1243                 AHCI_DBG_PRINT("save: [0x%x]=0x%08x\n",
1244                                (reg_base+(u32)reg_array[i]), *dest);
1245         }
1246         *save_addr = dest;
1247 }
1248
1249 static void tegra_ahci_restore_regs(void **save_addr,
1250                                     u32 reg_base,
1251                                     u16 reg_array[],
1252                                     u32 regs)
1253 {
1254         u32 i;
1255         u32 *src = (u32 *)*save_addr;
1256         u32 base = (u32)IO_ADDRESS(reg_base);
1257
1258         for (i = 0; i < regs; ++i, ++src) {
1259                 writel(*src, base + (u32)reg_array[i]);
1260                 AHCI_DBG_PRINT("restore: [0x%x]=0x%08x\n",
1261                                 (reg_base+(u32)reg_array[i]), *src);
1262         }
1263         *save_addr = src;
1264 }
1265
1266 static void tegra_ahci_pg_save_registers(struct ata_host *host)
1267 {
1268         struct tegra_ahci_host_priv *tegra_hpriv;
1269         u32 *pg_save;
1270         u32 regs;
1271         int i;
1272
1273         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1274         pg_save = tegra_hpriv->pg_save;
1275
1276         /*
1277          * Driver should save/restore the registers in the order of
1278          * IPFS, CFG, Ext CFG, BAR5.
1279          */
1280
1281         /* save IPFS registers */
1282         regs = ARRAY_SIZE(pg_save_ipfs_registers);
1283         tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BASE,
1284                              pg_save_ipfs_registers, regs);
1285         /* after the call, pg_save should point to the next address to save */
1286
1287         /* save CONFIG registers */
1288         regs = ARRAY_SIZE(pg_save_config_registers);
1289         tegra_ahci_save_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1290                              pg_save_config_registers, regs);
1291
1292         /* save CONFIG per port registers */
1293         for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1294                 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1295                 regs = ARRAY_SIZE(pg_save_config_port_registers);
1296                 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1297                                      pg_save_config_port_registers, regs);
1298         }
1299         scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1300
1301         /* save BAR5 registers */
1302         regs = ARRAY_SIZE(pg_save_bar5_registers);
1303         tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1304                              pg_save_bar5_registers, regs);
1305
1306         /* save BAR5 port_registers */
1307         regs = ARRAY_SIZE(pg_save_bar5_port_registers);
1308         for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i)
1309                 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE + (0x80*i),
1310                                      pg_save_bar5_port_registers, regs);
1311
1312         /* save bkdr registers */
1313         regs = ARRAY_SIZE(pg_save_bar5_bkdr_registers);
1314         tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1315                              pg_save_bar5_bkdr_registers, regs);
1316
1317         /* and save bkdr per_port registers */
1318         for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1319                 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1320                 regs = ARRAY_SIZE(pg_save_bar5_bkdr_port_registers);
1321                 tegra_ahci_save_regs(&pg_save, TEGRA_SATA_BAR5_BASE + (0x80*i),
1322                                      pg_save_bar5_bkdr_port_registers,
1323                                      regs);
1324         }
1325         scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1326 }
1327
1328 static void tegra_ahci_pg_restore_registers(struct ata_host *host)
1329 {
1330         struct tegra_ahci_host_priv *tegra_hpriv;
1331         void *pg_save;
1332         u32 regs, val;
1333         int i;
1334
1335         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1336         pg_save = tegra_hpriv->pg_save;
1337
1338         /*
1339          * Driver should restore the registers in the order of
1340          * IPFS, CFG, Ext CFG, BAR5.
1341          */
1342
1343         /* restore IPFS registers */
1344         regs = ARRAY_SIZE(pg_save_ipfs_registers);
1345         tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BASE,
1346                                 pg_save_ipfs_registers, regs);
1347         /* after the call, pg_save should point to the next addr to restore */
1348
1349         /* restore CONFIG registers */
1350         regs = ARRAY_SIZE(pg_save_config_registers);
1351         tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1352                                 pg_save_config_registers, regs);
1353
1354         /* restore CONFIG per port registers */
1355         for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1356                 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1357                 regs = ARRAY_SIZE(pg_save_config_port_registers);
1358                 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1359                                         pg_save_config_port_registers,
1360                                         regs);
1361         }
1362         scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1363
1364         /* restore BAR5 registers */
1365         regs = ARRAY_SIZE(pg_save_bar5_registers);
1366         tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BAR5_BASE,
1367                                 pg_save_bar5_registers, regs);
1368
1369         /* restore BAR5 port_registers */
1370         regs = ARRAY_SIZE(pg_save_bar5_port_registers);
1371         for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i)
1372                 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_BAR5_BASE+(0x80*i),
1373                                         pg_save_bar5_port_registers, regs);
1374
1375         /* restore bkdr registers */
1376         regs = ARRAY_SIZE(pg_restore_bar5_bkdr_registers);
1377         tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1378                              pg_restore_bar5_bkdr_registers, regs);
1379
1380         /* and restore BAR5 bkdr per_port registers */
1381         for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
1382                 scfg_writel((1 << i), T_SATA0_INDEX_OFFSET);
1383                 regs = ARRAY_SIZE(pg_restore_bar5_bkdr_port_registers);
1384                 tegra_ahci_restore_regs(&pg_save, TEGRA_SATA_CONFIG_BASE,
1385                                         pg_restore_bar5_bkdr_port_registers,
1386                                         regs);
1387         }
1388         scfg_writel(SATA0_NONE_SELECTED, T_SATA0_INDEX_OFFSET);
1389
1390         /* program class code and programming interface for AHCI */
1391         val = scfg_readl(TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1392         val |= TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
1393         scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1394         scfg_writel(TEGRA_PRIVATE_AHCI_CC_BKDR_PGM, TEGRA_PRIVATE_AHCI_CC_BKDR);
1395         val &= ~TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE_EN;
1396         scfg_writel(val, TEGRA_PRIVATE_AHCI_CC_BKDR_OVERRIDE);
1397 }
1398
1399 static u32 tegra_ahci_port_error(struct ata_port *ap)
1400 {
1401         void __iomem *port_mmio = ahci_port_base(ap);
1402         u32 err_status;
1403
1404         err_status = readl(port_mmio + PORT_IRQ_STAT);
1405         /* excludes PhyRdy and Connect Change status */
1406         err_status &= (PORT_IRQ_ERROR & (~(PORT_IRQ_PHYRDY|PORT_IRQ_CONNECT)));
1407         return err_status;
1408 }
1409
1410 static bool tegra_ahci_check_errors(struct ata_host *host)
1411 {       int i;
1412         struct ata_port *ap;
1413         u32 err;
1414
1415         for (i = 0; i < host->n_ports; i++) {
1416                 ap = host->ports[i];
1417                 err = tegra_ahci_port_error(ap);
1418                 if (err) {
1419                         dev_err(host->dev,
1420                                 "pg-chk-err = 0x%08x on port %d\n", err, i);
1421                         return true;
1422                 }
1423         }
1424         return false;
1425 }
1426
1427 static void tegra_ahci_abort_power_gate(struct ata_host *host)
1428 {
1429         u32 val;
1430
1431         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1432         val &= ~PG_INFO_MASK;
1433         val |= PG_INFO_OFF;
1434         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1435 }
1436
1437 static bool tegra_ahci_power_gate(struct ata_host *host)
1438 {
1439         u32 val;
1440         u32 dat;
1441         struct tegra_ahci_host_priv *tegra_hpriv;
1442         int status;
1443
1444         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1445
1446         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1447         val &= ~PG_INFO_MASK;
1448         val |= PG_INFO_ON;
1449         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1450
1451         tegra_ahci_pg_save_registers(host);
1452
1453         /*
1454          * Read SATA_AUX_MISC_CNTL_1_0 register L0_RX_IDLE_T_SAX field and
1455          * write that value into same register L0_RX_IDLE_T_NPG field.
1456          * And write 1 to L0_RX_IDLE_T_MUX field.
1457          */
1458         val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
1459         dat = val;
1460         dat &= L0_RX_IDLE_T_SAX_MASK;
1461         dat >>= L0_RX_IDLE_T_SAX_SHIFT;
1462         dat <<= L0_RX_IDLE_T_NPG_SHIFT;
1463         val &= ~L0_RX_IDLE_T_NPG_MASK;
1464         val |= dat;
1465         val &= ~L0_RX_IDLE_T_MUX_MASK;
1466         val |= L0_RX_IDLE_T_MUX_FROM_APB_MISC;
1467         misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
1468
1469         /* abort PG if there are errors occurred */
1470         if (tegra_ahci_check_errors(host)) {
1471                 dev_err(host->dev, "** pg: errors; abort power gating **\n");
1472                 return false;
1473         }
1474         /* make sure all ports have no outstanding commands and are idle. */
1475         if (!tegra_ahci_are_all_ports_idle(host)) {
1476                 dev_err(host->dev, "** pg: cmds; abort power gating **\n");
1477                 return false;
1478         }
1479
1480         /*
1481          * Hw wake up is not needed:
1482          * Driver/RM shall place the SATA PHY and SATA PADPLL in IDDQ.
1483          * SATA_PADPLL_RESET_SWCTL =1
1484          * SATA_PADPLL_RESET_OVERRIDE_VALUE=1
1485          * SATA_PADPHY_IDDQ_SWCTL=1
1486          * SATA_PADPHY_IDDQ_OVERRIDE_VALUE=1
1487          */
1488         val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1489         val &= ~(PADPLL_RESET_SWCTL_MASK | PADPLL_RESET_OVERRIDE_VALUE_MASK);
1490         val |= (PADPLL_RESET_SWCTL_ON | PADPLL_RESET_OVERRIDE_VALUE_ON);
1491         clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1492         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1493         val &= ~(PADPHY_IDDQ_OVERRIDE_VALUE_MASK | PADPHY_IDDQ_SWCTL_MASK);
1494         val |= (PADPHY_IDDQ_SWCTL_ON | PADPHY_IDDQ_OVERRIDE_VALUE_ON);
1495         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1496
1497         /* Wait for time specified in SATA_LANE_IDDQ2_PADPLL_IDDQ */
1498         val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
1499         dat = (val & IDDQ2LANE_IDDQ_DLY_MASK) >> IDDQ2LANE_IDDQ_DLY_SHIFT;
1500         udelay(dat);
1501
1502         /* SATA_PADPLL_IDDQ_SWCTL=1 & SATA_PADPLL_IDDQ_OVERRIDE_VALUE=1 */
1503         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1504         val &= ~(PADPLL_IDDQ_OVERRIDE_VALUE_MASK | PADPLL_IDDQ_SWCTL_MASK);
1505         val |= (PADPLL_IDDQ_SWCTL_ON | PADPLL_IDDQ_OVERRIDE_VALUE_ON);
1506         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1507
1508         /* power off the sata */
1509         status = tegra_powergate_partition_with_clk_off(TEGRA_POWERGATE_SATA);
1510         if (status)
1511                 dev_err(host->dev, "** failed to turn-off SATA (0x%x) **\n",
1512                                    status);
1513
1514         return true;
1515 }
1516
1517 static bool tegra_ahci_power_un_gate(struct ata_host *host)
1518 {
1519         u32 val;
1520         u32 dat;
1521         u32 timeout;
1522         struct tegra_ahci_host_priv *tegra_hpriv;
1523         int status;
1524
1525         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1526
1527         /* get sata phy and pll out of iddq: */
1528         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1529         val &= ~PADPLL_IDDQ_OVERRIDE_VALUE_MASK;
1530         val |= PADPLL_IDDQ_OVERRIDE_VALUE_OFF;
1531         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1532         /* wait for delay of IDDQ2LAND_SLUMBER_DLY */
1533         val = clk_readl(CLK_RST_SATA_PLL_CFG1_REG);
1534         dat = (val & IDDQ2LANE_SLUMBER_DLY_MASK) >> IDDQ2LANE_SLUMBER_DLY_SHIFT;
1535         udelay(dat);
1536         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1537         val &= ~PADPHY_IDDQ_OVERRIDE_VALUE_MASK;
1538         val |= PADPHY_IDDQ_OVERRIDE_VALUE_OFF;
1539         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1540
1541         status = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_SATA);
1542         if (status)
1543                 dev_err(host->dev, "** failed to turn-on SATA (0x%x) **\n",
1544                                    status);
1545
1546         /* deasset PADPLL and wait until it locks. */
1547         val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1548         val &= ~PADPLL_RESET_OVERRIDE_VALUE_MASK;
1549         val |= PADPLL_RESET_OVERRIDE_VALUE_OFF;
1550         clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1551
1552         /*
1553          * Wait for SATA_AUX_PAD_PLL_CNTL_1_0_LOCKDET to turn 1 with a timeout
1554          * of 15 us.
1555          */
1556         timeout = 15;
1557         while (timeout--) {
1558                 udelay(1);
1559                 val = misc_readl(SATA_AUX_PAD_PLL_CNTL_1_REG);
1560                 if (val & LOCKDET_FIELD)
1561                         break;
1562         }
1563         if (timeout == 0)
1564                 pr_err("%s: SATA_PAD_PLL is not locked in 15us.\n", __func__);
1565
1566         /* restore registers */
1567         tegra_ahci_pg_restore_registers(host);
1568
1569         /*
1570          * During the restoration of the registers, the driver would now need to
1571          * restore the register T_SATA0_CFG_POWER_GATE_SSTS_RESTORED after the
1572          * ssts_det, ssts_spd are restored. This register is used to tell the
1573          * controller whether a drive existed earlier or not and move the PHY
1574          * state machines into either HR_slumber or not.
1575          */
1576         val = scfg_readl(T_SATA0_CFG_POWER_GATE);
1577         val &= ~POWER_GATE_SSTS_RESTORED_MASK;
1578         val |= POWER_GATE_SSTS_RESTORED_YES;
1579         scfg_writel(val, T_SATA0_CFG_POWER_GATE);
1580
1581         /*
1582          * Driver needs to switch the rx_idle_t driven source back to from
1583          * Sata controller after SAX is power-ungated.
1584          */
1585         val = misc_readl(SATA_AUX_MISC_CNTL_1_REG);
1586         val &= ~L0_RX_IDLE_T_MUX_MASK;
1587         val |= L0_RX_IDLE_T_MUX_FROM_SATA;
1588         misc_writel(val, SATA_AUX_MISC_CNTL_1_REG);
1589
1590         /*
1591          * Driver can start to use main SATA interrupt instead of the
1592          * rx_stat_t interrupt.
1593          */
1594         val = pictlr_readl(PRI_ICTLR_CPU_IER_SET_0_OFFSET);
1595         val |= CPU_IER_SATA_CTL;
1596         pictlr_writel(val, PRI_ICTLR_CPU_IER_SET_0_OFFSET);
1597
1598         /* Set the bits in the CAR to allow HW based low power sequencing. */
1599         val = clk_readl(CLK_RST_SATA_PLL_CFG0_REG);
1600         val &= ~PADPLL_RESET_SWCTL_MASK;
1601         val |= PADPLL_RESET_SWCTL_OFF;
1602         clk_writel(val, CLK_RST_SATA_PLL_CFG0_REG);
1603
1604         /*
1605          * power un-gating process is complete by clearing
1606          * APBDEV_PMC_SATA_PWRGT_0.Pmc2sata_pg_info = 0
1607          */
1608         val = pmc_readl(APB_PMC_SATA_PWRGT_0_REG);
1609         val &= ~PG_INFO_MASK;
1610         val |= PG_INFO_OFF;
1611         pmc_writel(val, APB_PMC_SATA_PWRGT_0_REG);
1612
1613         return true;
1614 }
1615
1616 static enum port_idle_status tegra_ahci_is_port_idle(struct ata_port *ap)
1617 {
1618         void __iomem *port_mmio = ahci_port_base(ap);
1619
1620         if (readl(port_mmio + PORT_CMD_ISSUE) ||
1621             readl(port_mmio + PORT_SCR_ACT))
1622                 return PORT_IS_NOT_IDLE;
1623         return PORT_IS_IDLE;
1624 }
1625
1626 /* check if all supported ports are idle (no outstanding commands) */
1627 static bool tegra_ahci_are_all_ports_idle(struct ata_host *host)
1628 {       int i;
1629         struct ata_port *ap;
1630
1631         for (i = 0; i < host->n_ports; i++) {
1632                 ap = host->ports[i];
1633                 if (ap && (tegra_ahci_is_port_idle(ap) == PORT_IS_NOT_IDLE))
1634                         return false;
1635         }
1636         return true;
1637 }
1638
1639 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
1640 static enum port_idle_status tegra_ahci_is_port_slumber(struct ata_port *ap)
1641 {
1642         void __iomem *port_mmio = ahci_port_base(ap);
1643         u32 sstat;
1644
1645         if (tegra_ahci_is_port_idle(ap) == PORT_IS_NOT_IDLE)
1646                 return PORT_IS_NOT_IDLE;
1647
1648         /* return 1 if PORT_SCR_STAT is in IPM_SLUMBER_STATE */
1649         sstat = readl(port_mmio + PORT_SCR_STAT);
1650         if ((sstat & SSTAT_IPM_STATE_MASK) == SSTAT_IPM_SLUMBER_STATE)
1651                 return PORT_IS_SLUMBER;
1652         return PORT_IS_IDLE_NOT_SLUMBER;
1653 }
1654
1655 /* check if all supported ports are in slumber */
1656 static bool tegra_ahci_are_all_ports_slumber(struct ata_host *host)
1657 {       int i;
1658         struct ata_port *ap;
1659
1660         for (i = 0; i < host->n_ports; i++) {
1661                 ap = host->ports[i];
1662                 if (ap && (tegra_ahci_is_port_slumber(ap) != PORT_IS_SLUMBER))
1663                         return false;
1664         }
1665         return true;
1666 }
1667
1668 static void tegra_ahci_to_add_idle_timer(struct ata_host *host)
1669 {
1670         struct tegra_ahci_host_priv *tegra_hpriv;
1671
1672         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1673
1674         /* note: the routine is called from interrupt context */
1675         spin_lock(&host->lock);
1676         /* start idle-timer if all ports have no outstanding commands */
1677         if (tegra_ahci_are_all_ports_idle(host)) {
1678                 /* adjust tegra_ahci_idle_time to minimum if it is too small */
1679                 tegra_ahci_idle_time = max((u32)TEGRA_AHCI_MIN_IDLE_TIME,
1680                                            tegra_ahci_idle_time);
1681                 tegra_hpriv->idle_timer.expires =
1682                         ata_deadline(jiffies, tegra_ahci_idle_time);
1683                 mod_timer(&tegra_hpriv->idle_timer,
1684                           tegra_hpriv->idle_timer.expires);
1685         }
1686         spin_unlock(&host->lock);
1687 }
1688
1689 static void tegra_ahci_idle_timer(unsigned long arg)
1690 {
1691         struct ata_host *host = (void *)arg;
1692         struct tegra_ahci_host_priv *tegra_hpriv;
1693         unsigned long flags;
1694
1695         tegra_hpriv = (struct tegra_ahci_host_priv *)host->private_data;
1696
1697         spin_lock_irqsave(&host->lock, flags);
1698         if (tegra_hpriv->pg_state == SATA_ON)
1699                 tegra_hpriv->pg_state = SATA_GOING_OFF;
1700         else {
1701                 dev_err(host->dev, "idle_timer: bad state (%u)\n",
1702                                 tegra_hpriv->pg_state);
1703                 WARN_ON(1);
1704                 spin_unlock_irqrestore(&host->lock, flags);
1705                 return;
1706         }
1707         spin_unlock_irqrestore(&host->lock, flags);
1708
1709         pm_runtime_put(tegra_hpriv->dev);
1710 }
1711
1712 static int tegra_ahci_queue_one_qc(struct tegra_ahci_host_priv *tegra_hpriv,
1713                                    struct ata_queued_cmd *qc)
1714 {
1715         struct tegra_qc_list *qc_list;
1716
1717         qc_list = kmalloc(sizeof(struct tegra_qc_list), GFP_ATOMIC);
1718         if (!qc_list) {
1719                 dev_err(tegra_hpriv->dev, "failed to alloc qc_list\n");
1720                 return AC_ERR_SYSTEM;
1721         }
1722         qc_list->qc = qc;
1723         list_add_tail(&(qc_list->list), &(tegra_hpriv->qc_list));
1724         dev_dbg(tegra_hpriv->dev, "queuing qc=%x\n", (unsigned int)qc);
1725         return 0;
1726 }
1727
1728 static void tegra_ahci_dequeue_qcs(struct tegra_ahci_host_priv *tegra_hpriv)
1729 {
1730         struct list_head *list, *next;
1731         struct tegra_qc_list *qc_list;
1732         struct ata_queued_cmd *qc;
1733
1734         /* now qc_issue all qcs in the qc_list */
1735         list_for_each_safe(list, next, &tegra_hpriv->qc_list) {
1736                 qc_list = list_entry(list, struct tegra_qc_list, list);
1737                 qc = qc_list->qc;
1738                 dev_dbg(tegra_hpriv->dev, "dequeue qc=%x\n", (unsigned int)qc);
1739                 ahci_ops.qc_issue(qc);
1740                 list_del(list);
1741                 kfree(qc_list);
1742         }
1743 }
1744
1745 static unsigned int tegra_ahci_qc_issue(struct ata_queued_cmd *qc)
1746 {
1747         struct ata_port *ap = qc->ap;
1748         struct ata_host *host = ap->host;
1749         struct tegra_ahci_host_priv *tegra_hpriv = host->private_data;
1750         int rc;
1751
1752         /* stop the idle timer */
1753         if (timer_pending(&tegra_hpriv->idle_timer))
1754                 del_timer_sync(&tegra_hpriv->idle_timer);
1755
1756         /* note: host->lock is locked */
1757         switch (tegra_hpriv->pg_state) {
1758         case SATA_ON:
1759                 /* normal case, issue the qc */
1760                 return ahci_ops.qc_issue(qc);
1761         case SATA_GOING_OFF:
1762         case SATA_ABORT_OFF:
1763                 /* SATA is going OFF, let's abort the suspend */
1764                 dev_dbg(host->dev, "** qc_issue: going OFF **\n");
1765                 tegra_hpriv->pg_state = SATA_ABORT_OFF;
1766                 return tegra_ahci_queue_one_qc(tegra_hpriv, qc);
1767         case SATA_OFF:
1768                 dev_dbg(host->dev, "** qc_issue: request power-up sata **\n");
1769                 rc = pm_runtime_get(tegra_hpriv->dev);
1770                 /* rc == 0 means the request has been queued successfully */
1771                 if (rc) {
1772                         dev_err(host->dev, "** qc_issue: rt_get()=%d **\n",
1773                                                 rc);
1774                         WARN_ON(1);
1775                         return AC_ERR_SYSTEM;
1776                 }
1777                 tegra_hpriv->pg_state = SATA_GOING_ON;
1778                 /* continue with the following code to queue the qc */
1779         case SATA_GOING_ON:
1780                 return tegra_ahci_queue_one_qc(tegra_hpriv, qc);
1781         default:
1782                 dev_err(host->dev, "** qc_issue: bad state (%u) **\n",
1783                                         tegra_hpriv->pg_state);
1784                 WARN_ON(1);
1785                 return AC_ERR_SYSTEM;
1786         }
1787 }
1788
1789 static int tegra_ahci_hardreset(struct ata_link *link, unsigned int *class,
1790                                 unsigned long deadline)
1791 {
1792         struct ata_port *ap = link->ap;
1793         struct ata_host *host = ap->host;
1794         struct tegra_ahci_host_priv *tegra_hpriv = host->private_data;
1795         int rc;
1796
1797         if (tegra_hpriv->pg_state == SATA_OFF) {
1798                 dev_dbg(host->dev, "** hreset: request power-up sata **\n");
1799                 rc = pm_runtime_get_sync(tegra_hpriv->dev);
1800                 /* rc == 0 means the request has been run successfully */
1801                 if (rc) {
1802                         dev_err(host->dev, "** hreset: rt_get()=%d **\n", rc);
1803                         WARN_ON(1);
1804                         return AC_ERR_SYSTEM;
1805                 }
1806                 tegra_hpriv->pg_state = SATA_ON;
1807         }
1808
1809         return ahci_ops.hardreset(link, class, deadline);
1810 }
1811
1812 static irqreturn_t tegra_ahci_interrupt(int irq, void *dev_instance)
1813 {
1814         irqreturn_t irq_retval;
1815
1816         irq_retval = ahci_interrupt(irq, dev_instance);
1817         if (irq_retval == IRQ_NONE)
1818                 return IRQ_NONE;
1819
1820 #ifdef CONFIG_PM
1821         tegra_ahci_to_add_idle_timer((struct ata_host *)dev_instance);
1822 #endif
1823
1824         return irq_retval;
1825 }
1826 #endif
1827 #endif
1828
1829 static int __devexit tegra_ahci_remove_one(struct platform_device *pdev)
1830 {
1831         struct ata_host *host = dev_get_drvdata(&pdev->dev);
1832         struct ahci_host_priv *hpriv;
1833
1834         BUG_ON(host == NULL);
1835         BUG_ON(host->iomap[AHCI_PCI_BAR] == NULL);
1836         hpriv = host->private_data;
1837
1838         tegra_ahci_controller_remove(pdev);
1839
1840         devm_iounmap(&pdev->dev, host->iomap[AHCI_PCI_BAR]);
1841         devres_free(host);
1842
1843 #ifdef CONFIG_PM
1844         /* Free PG save/restore area */
1845         devm_kfree(&pdev->dev, ((struct tegra_ahci_host_priv *)hpriv)->pg_save);
1846
1847 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
1848         pm_runtime_disable(&pdev->dev);
1849 #endif
1850 #endif
1851
1852         devm_kfree(&pdev->dev, hpriv);
1853
1854         return 0;
1855 }
1856
1857 static int __devinit tegra_ahci_init_one(struct platform_device *pdev)
1858 {
1859         struct ata_port_info pi = ahci_port_info;
1860         const struct ata_port_info *ppi[] = { &pi, NULL };
1861         struct device *dev = &pdev->dev;
1862         struct ahci_host_priv *hpriv = NULL;
1863         struct tegra_ahci_host_priv *tegra_hpriv;
1864         struct ata_host *host = NULL;
1865         int n_ports, i, rc;
1866         struct resource *res, *irq_res;
1867         void __iomem *mmio;
1868         u32 save_size;
1869         irq_handler_t irq_handler = ahci_interrupt;
1870
1871         VPRINTK("ENTER\n");
1872
1873         WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1874
1875         ata_print_version_once(&pdev->dev, DRV_VERSION);
1876
1877         /* Simple resource validation */
1878         if (pdev->num_resources != 3) {
1879                 dev_err(dev, "invalid number of resources\n");
1880                 dev_err(dev, "not enough SATA resources\n");
1881                 return -EINVAL;
1882         }
1883
1884         /* acquire bar resources */
1885         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1886         if (res == NULL)
1887                 return -EINVAL;
1888
1889         /* acquire IRQ resource */
1890         irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1891         if (irq_res == NULL)
1892                 return -EINVAL;
1893         if (irq_res->start <= 0)
1894                 return -EINVAL;
1895
1896         /* allocate sizeof tegra_ahci_host_priv, which contains extra fields */
1897         hpriv = devm_kzalloc(dev, sizeof(struct tegra_ahci_host_priv),
1898                              GFP_KERNEL);
1899         if (!hpriv) {
1900                 rc = -ENOMEM;
1901                 goto fail;
1902         }
1903         hpriv->flags |= (unsigned long)pi.private_data;
1904         tegra_hpriv = (struct tegra_ahci_host_priv *)hpriv;
1905         g_tegra_hpriv = tegra_hpriv;
1906
1907         /* Call tegra init routine */
1908         rc = tegra_ahci_controller_init(tegra_hpriv);
1909         if (rc != 0) {
1910                 dev_err(dev, "TEGRA SATA init failed\n");
1911                 goto fail;
1912         }
1913
1914         /*
1915          * We reserve a table of 6 BARs in tegra_hpriv to store BARs.
1916          * Save the mapped AHCI_PCI_BAR address to the table.
1917          */
1918         mmio = devm_ioremap(dev, res->start, (res->end-res->start+1));
1919         tegra_hpriv->bars_table[AHCI_PCI_BAR] = mmio;
1920         hpriv->mmio = mmio;
1921
1922         /* save initial config */
1923         tegra_ahci_save_initial_config(pdev, hpriv);
1924         dev_dbg(dev, "past save init config\n");
1925
1926         /* prepare host */
1927         if (hpriv->cap & HOST_CAP_NCQ) {
1928                 pi.flags |= ATA_FLAG_NCQ;
1929                 pi.flags |= ATA_FLAG_FPDMA_AA;
1930         }
1931
1932         /*
1933          * CAP.NP sometimes indicate the index of the last enabled
1934          * port, at other times, that of the last possible port, so
1935          * determining the maximum port number requires looking at
1936          * both CAP.NP and port_map.
1937          */
1938         n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1939         host = ata_host_alloc_pinfo(dev, ppi, n_ports);
1940         if (!host) {
1941                 rc = -ENOMEM;
1942                 goto fail;
1943         }
1944         host->private_data = hpriv;
1945         tegra_hpriv->host = host;
1946         tegra_hpriv->dev = dev;
1947         host->iomap = tegra_hpriv->bars_table;
1948
1949         if (!(hpriv->cap & HOST_CAP_SSS))
1950                 host->flags |= ATA_HOST_PARALLEL_SCAN;
1951         else
1952                 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1953
1954         for (i = 0; i < host->n_ports; i++) {
1955                 struct ata_port *ap = host->ports[i];
1956
1957                 /* set initial link pm policy */
1958                 ap->target_lpm_policy = ATA_LPM_UNKNOWN;
1959
1960                 /* disabled/not-implemented port */
1961                 if (!(hpriv->port_map & (1 << i)))
1962                         ap->ops = &ata_dummy_port_ops;
1963                 else
1964                         ap->target_lpm_policy = ATA_LPM_MIN_POWER;
1965         }
1966
1967         rc = ahci_reset_controller(host);
1968         if (rc) {
1969                 dev_err(dev, "Reset controller failed! (rc=%d)\n", rc);
1970                 goto fail;
1971         }
1972
1973         ahci_init_controller(host);
1974         ahci_print_info(host, "TEGRA-SATA");
1975         dev_dbg(dev, "controller init okay\n");
1976
1977 #ifdef CONFIG_PM
1978         /* Setup PG save/restore area: */
1979
1980         /* calculate the size */
1981         save_size = ARRAY_SIZE(pg_save_ipfs_registers) +
1982                             ARRAY_SIZE(pg_save_config_registers) +
1983                             ARRAY_SIZE(pg_save_bar5_registers) +
1984                             ARRAY_SIZE(pg_save_bar5_bkdr_registers);
1985
1986         /* and add save port_registers for all the ports */
1987         save_size += TEGRA_AHCI_NUM_PORTS *
1988                      (ARRAY_SIZE(pg_save_config_port_registers) +
1989                       ARRAY_SIZE(pg_save_bar5_port_registers) +
1990                       ARRAY_SIZE(pg_save_bar5_bkdr_port_registers));
1991
1992         /*
1993          * save_size is number of registers times number of bytes per
1994          * register to get total save size.
1995          */
1996         save_size *= sizeof(u32);
1997         tegra_hpriv->pg_save = devm_kzalloc(dev, save_size, GFP_KERNEL);
1998         if (!tegra_hpriv->pg_save) {
1999                 rc = -ENOMEM;
2000                 goto fail;
2001         }
2002
2003 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2004         pm_runtime_set_active(dev);
2005         pm_suspend_ignore_children(dev, true);
2006         pm_runtime_enable(dev);
2007
2008         tegra_hpriv->pg_state = SATA_ON;
2009
2010         /* setup sata idle timer */
2011         init_timer_deferrable(&tegra_hpriv->idle_timer);
2012         tegra_hpriv->idle_timer.function = tegra_ahci_idle_timer;
2013         tegra_hpriv->idle_timer.data = (unsigned long)host;
2014
2015         INIT_LIST_HEAD(&tegra_hpriv->qc_list);
2016
2017         /* use our own irq handler */
2018         irq_handler = tegra_ahci_interrupt;
2019 #endif
2020
2021 #endif
2022
2023         rc = ata_host_activate(host, irq_res->start, irq_handler, 0, &ahci_sht);
2024         if (rc == 0)
2025                 return 0;
2026
2027         /* Free PG save/restore area */
2028         devm_kfree(dev, tegra_hpriv->pg_save);
2029
2030 #ifdef CONFIG_TEGRA_SATA_IDLE_POWERGATE
2031         pm_runtime_put(dev);
2032         pm_runtime_enable(dev);
2033 #endif
2034
2035 fail:
2036         if (host) {
2037                 if (host->iomap[AHCI_PCI_BAR])
2038                         devm_iounmap(dev, host->iomap[AHCI_PCI_BAR]);
2039                 devres_free(host);
2040         }
2041         if (hpriv)
2042                 devm_kfree(dev, hpriv);
2043
2044         return rc;
2045 }
2046
2047 static int __init ahci_init(void)
2048 {
2049         return platform_driver_register(&tegra_platform_ahci_driver);
2050 }
2051
2052 static void __exit ahci_exit(void)
2053 {
2054         platform_driver_unregister(&tegra_platform_ahci_driver);
2055 }
2056
2057
2058 #ifdef  CONFIG_DEBUG_FS
2059
2060 #include <linux/debugfs.h>
2061 #include <linux/seq_file.h>
2062
2063 static void dbg_ahci_dump_regs(struct seq_file *s, u32 *ptr, u32 base, u32 regs)
2064 {
2065 #define REGS_PER_LINE   4
2066
2067         u32 i, j;
2068         u32 lines = regs / REGS_PER_LINE;
2069
2070         for (i = 0; i < lines; i++) {
2071                 seq_printf(s, "0x%08x: ", base+(i*16));
2072                 for (j = 0; j < REGS_PER_LINE; ++j) {
2073                         seq_printf(s, "0x%08x ", readl(ptr));
2074                         ++ptr;
2075                 }
2076                 seq_printf(s, "\n");
2077         }
2078 #undef REGS_PER_LINE
2079 }
2080
2081 static int dbg_ahci_dump_show(struct seq_file *s, void *unused)
2082 {
2083         u32 base;
2084         u32 *ptr;
2085         u32 i;
2086
2087         base = TEGRA_SATA_CONFIG_BASE;
2088         ptr = (u32 *)IO_TO_VIRT(base);
2089         seq_printf(s, "SATA CONFIG Registers:\n");
2090         seq_printf(s, "----------------------\n");
2091         dbg_ahci_dump_regs(s, ptr, base, 0x200);
2092
2093         base = TEGRA_SATA_BAR5_BASE;
2094         ptr = (u32 *)IO_TO_VIRT(base);
2095         seq_printf(s, "\nAHCI HBA Registers:\n");
2096         seq_printf(s, "-------------------\n");
2097         dbg_ahci_dump_regs(s, ptr, base, 64);
2098
2099         for (i = 0; i < TEGRA_AHCI_NUM_PORTS; ++i) {
2100                 base = TEGRA_SATA_BAR5_BASE + 0x100 + (0x80*i);
2101                 ptr = (u32 *)IO_TO_VIRT(base);
2102                 seq_printf(s, "\nPort %u Registers:\n", i);
2103                 seq_printf(s, "---------------\n");
2104                 dbg_ahci_dump_regs(s, ptr, base, 16);
2105         }
2106
2107 #ifdef  CONFIG_TEGRA_SATA_IDLE_POWERGATE
2108         /* adjust tegra_ahci_idle_time to minimum if it is too small */
2109         tegra_ahci_idle_time = max((u32)TEGRA_AHCI_MIN_IDLE_TIME,
2110                                    tegra_ahci_idle_time);
2111         seq_printf(s, "\nIdle Timeout = %u milli-seconds.\n",
2112                       tegra_ahci_idle_time);
2113 #endif
2114
2115         if (tegra_powergate_is_powered(TEGRA_POWERGATE_SATA))
2116                 seq_printf(s, "\n=== SATA controller is powered on ===\n\n");
2117         else
2118                 seq_printf(s, "\n=== SATA controller is powered off ===\n\n");
2119
2120         return 0;
2121 }
2122
2123 static int dbg_ahci_dump_open(struct inode *inode, struct file *file)
2124 {
2125         return single_open(file, dbg_ahci_dump_show, &inode->i_private);
2126 }
2127
2128 static const struct file_operations debug_fops = {
2129         .open           = dbg_ahci_dump_open,
2130         .read           = seq_read,
2131         .llseek         = seq_lseek,
2132         .release        = single_release,
2133 };
2134
2135 static int __init tegra_ahci_dump_debuginit(void)
2136 {
2137         (void) debugfs_create_file("tegra_ahci", S_IRUGO,
2138                                    NULL, NULL, &debug_fops);
2139 #ifdef  CONFIG_TEGRA_SATA_IDLE_POWERGATE
2140         (void) debugfs_create_u32("tegra_ahci_idle_ms", S_IRWXUGO,
2141                                    NULL, &tegra_ahci_idle_time);
2142 #endif
2143         return 0;
2144 }
2145 late_initcall(tegra_ahci_dump_debuginit);
2146 #endif
2147
2148 MODULE_AUTHOR("NVIDIA");
2149 MODULE_DESCRIPTION("Tegra AHCI SATA low-level driver");
2150 MODULE_LICENSE("GPL v2");
2151 MODULE_VERSION(DRV_VERSION);
2152
2153 module_init(ahci_init);
2154 module_exit(ahci_exit);