31c270fee3379d54acb93fbba6f1d192191208ed
[linux-2.6.git] / arch / x86_64 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/smp_lock.h>
29 #include <linux/pci.h>
30 #include <linux/mc146818rtc.h>
31 #include <linux/acpi.h>
32 #include <linux/sysdev.h>
33 #ifdef CONFIG_ACPI
34 #include <acpi/acpi_bus.h>
35 #endif
36
37 #include <asm/io.h>
38 #include <asm/smp.h>
39 #include <asm/desc.h>
40 #include <asm/proto.h>
41 #include <asm/mach_apic.h>
42 #include <asm/acpi.h>
43 #include <asm/dma.h>
44 #include <asm/nmi.h>
45 #include <asm/msidef.h>
46 #include <asm/hypertransport.h>
47
48 static int assign_irq_vector(int irq, cpumask_t mask);
49
50 #define __apicdebuginit  __init
51
52 int sis_apic_bug; /* not actually supported, dummy for compile */
53
54 static int no_timer_check;
55
56 static int disable_timer_pin_1 __initdata;
57
58 int timer_over_8254 __initdata = 0;
59
60 /* Where if anywhere is the i8259 connect in external int mode */
61 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
62
63 static DEFINE_SPINLOCK(ioapic_lock);
64 static DEFINE_SPINLOCK(vector_lock);
65
66 /*
67  * # of IRQ routing registers
68  */
69 int nr_ioapic_registers[MAX_IO_APICS];
70
71 /*
72  * Rough estimation of how many shared IRQs there are, can
73  * be changed anytime.
74  */
75 #define MAX_PLUS_SHARED_IRQS NR_IRQ_VECTORS
76 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
77
78 /*
79  * This is performance-critical, we want to do it O(1)
80  *
81  * the indexing order of this array favors 1:1 mappings
82  * between pins and IRQs.
83  */
84
85 static struct irq_pin_list {
86         short apic, pin, next;
87 } irq_2_pin[PIN_MAP_SIZE];
88
89 #define __DO_ACTION(R, ACTION, FINAL)                                   \
90                                                                         \
91 {                                                                       \
92         int pin;                                                        \
93         struct irq_pin_list *entry = irq_2_pin + irq;                   \
94                                                                         \
95         BUG_ON(irq >= NR_IRQS);                                         \
96         for (;;) {                                                      \
97                 unsigned int reg;                                       \
98                 pin = entry->pin;                                       \
99                 if (pin == -1)                                          \
100                         break;                                          \
101                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
102                 reg ACTION;                                             \
103                 io_apic_modify(entry->apic, reg);                       \
104                 if (!entry->next)                                       \
105                         break;                                          \
106                 entry = irq_2_pin + entry->next;                        \
107         }                                                               \
108         FINAL;                                                          \
109 }
110
111 union entry_union {
112         struct { u32 w1, w2; };
113         struct IO_APIC_route_entry entry;
114 };
115
116 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
117 {
118         union entry_union eu;
119         unsigned long flags;
120         spin_lock_irqsave(&ioapic_lock, flags);
121         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
122         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
123         spin_unlock_irqrestore(&ioapic_lock, flags);
124         return eu.entry;
125 }
126
127 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
128 {
129         unsigned long flags;
130         union entry_union eu;
131         eu.entry = e;
132         spin_lock_irqsave(&ioapic_lock, flags);
133         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
134         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
135         spin_unlock_irqrestore(&ioapic_lock, flags);
136 }
137
138 #ifdef CONFIG_SMP
139 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
140 {
141         int apic, pin;
142         struct irq_pin_list *entry = irq_2_pin + irq;
143
144         BUG_ON(irq >= NR_IRQS);
145         for (;;) {
146                 unsigned int reg;
147                 apic = entry->apic;
148                 pin = entry->pin;
149                 if (pin == -1)
150                         break;
151                 io_apic_write(apic, 0x11 + pin*2, dest);
152                 reg = io_apic_read(apic, 0x10 + pin*2);
153                 reg &= ~0x000000ff;
154                 reg |= vector;
155                 io_apic_modify(apic, reg);
156                 if (!entry->next)
157                         break;
158                 entry = irq_2_pin + entry->next;
159         }
160 }
161
162 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
163 {
164         unsigned long flags;
165         unsigned int dest;
166         cpumask_t tmp;
167         int vector;
168
169         cpus_and(tmp, mask, cpu_online_map);
170         if (cpus_empty(tmp))
171                 tmp = TARGET_CPUS;
172
173         cpus_and(mask, tmp, CPU_MASK_ALL);
174
175         vector = assign_irq_vector(irq, mask);
176         if (vector < 0)
177                 return;
178
179         cpus_clear(tmp);
180         cpu_set(vector >> 8, tmp);
181         dest = cpu_mask_to_apicid(tmp);
182
183         /*
184          * Only the high 8 bits are valid.
185          */
186         dest = SET_APIC_LOGICAL_ID(dest);
187
188         spin_lock_irqsave(&ioapic_lock, flags);
189         __target_IO_APIC_irq(irq, dest, vector & 0xff);
190         set_native_irq_info(irq, mask);
191         spin_unlock_irqrestore(&ioapic_lock, flags);
192 }
193 #endif
194
195 /*
196  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
197  * shared ISA-space IRQs, so we have to support them. We are super
198  * fast in the common case, and fast for shared ISA-space IRQs.
199  */
200 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
201 {
202         static int first_free_entry = NR_IRQS;
203         struct irq_pin_list *entry = irq_2_pin + irq;
204
205         BUG_ON(irq >= NR_IRQS);
206         while (entry->next)
207                 entry = irq_2_pin + entry->next;
208
209         if (entry->pin != -1) {
210                 entry->next = first_free_entry;
211                 entry = irq_2_pin + entry->next;
212                 if (++first_free_entry >= PIN_MAP_SIZE)
213                         panic("io_apic.c: ran out of irq_2_pin entries!");
214         }
215         entry->apic = apic;
216         entry->pin = pin;
217 }
218
219
220 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
221                                                                         \
222         static void name##_IO_APIC_irq (unsigned int irq)               \
223         __DO_ACTION(R, ACTION, FINAL)
224
225 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
226                                                 /* mask = 1 */
227 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
228                                                 /* mask = 0 */
229
230 static void mask_IO_APIC_irq (unsigned int irq)
231 {
232         unsigned long flags;
233
234         spin_lock_irqsave(&ioapic_lock, flags);
235         __mask_IO_APIC_irq(irq);
236         spin_unlock_irqrestore(&ioapic_lock, flags);
237 }
238
239 static void unmask_IO_APIC_irq (unsigned int irq)
240 {
241         unsigned long flags;
242
243         spin_lock_irqsave(&ioapic_lock, flags);
244         __unmask_IO_APIC_irq(irq);
245         spin_unlock_irqrestore(&ioapic_lock, flags);
246 }
247
248 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
249 {
250         struct IO_APIC_route_entry entry;
251
252         /* Check delivery_mode to be sure we're not clearing an SMI pin */
253         entry = ioapic_read_entry(apic, pin);
254         if (entry.delivery_mode == dest_SMI)
255                 return;
256         /*
257          * Disable it in the IO-APIC irq-routing table:
258          */
259         memset(&entry, 0, sizeof(entry));
260         entry.mask = 1;
261         ioapic_write_entry(apic, pin, entry);
262 }
263
264 static void clear_IO_APIC (void)
265 {
266         int apic, pin;
267
268         for (apic = 0; apic < nr_ioapics; apic++)
269                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
270                         clear_IO_APIC_pin(apic, pin);
271 }
272
273 int skip_ioapic_setup;
274 int ioapic_force;
275
276 /* dummy parsing: see setup.c */
277
278 static int __init disable_ioapic_setup(char *str)
279 {
280         skip_ioapic_setup = 1;
281         return 0;
282 }
283 early_param("noapic", disable_ioapic_setup);
284
285 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
286 static int __init disable_timer_pin_setup(char *arg)
287 {
288         disable_timer_pin_1 = 1;
289         return 1;
290 }
291 __setup("disable_timer_pin_1", disable_timer_pin_setup);
292
293 static int __init setup_disable_8254_timer(char *s)
294 {
295         timer_over_8254 = -1;
296         return 1;
297 }
298 static int __init setup_enable_8254_timer(char *s)
299 {
300         timer_over_8254 = 2;
301         return 1;
302 }
303
304 __setup("disable_8254_timer", setup_disable_8254_timer);
305 __setup("enable_8254_timer", setup_enable_8254_timer);
306
307
308 /*
309  * Find the IRQ entry number of a certain pin.
310  */
311 static int find_irq_entry(int apic, int pin, int type)
312 {
313         int i;
314
315         for (i = 0; i < mp_irq_entries; i++)
316                 if (mp_irqs[i].mpc_irqtype == type &&
317                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
318                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
319                     mp_irqs[i].mpc_dstirq == pin)
320                         return i;
321
322         return -1;
323 }
324
325 /*
326  * Find the pin to which IRQ[irq] (ISA) is connected
327  */
328 static int __init find_isa_irq_pin(int irq, int type)
329 {
330         int i;
331
332         for (i = 0; i < mp_irq_entries; i++) {
333                 int lbus = mp_irqs[i].mpc_srcbus;
334
335                 if (test_bit(lbus, mp_bus_not_pci) &&
336                     (mp_irqs[i].mpc_irqtype == type) &&
337                     (mp_irqs[i].mpc_srcbusirq == irq))
338
339                         return mp_irqs[i].mpc_dstirq;
340         }
341         return -1;
342 }
343
344 static int __init find_isa_irq_apic(int irq, int type)
345 {
346         int i;
347
348         for (i = 0; i < mp_irq_entries; i++) {
349                 int lbus = mp_irqs[i].mpc_srcbus;
350
351                 if (test_bit(lbus, mp_bus_not_pci) &&
352                     (mp_irqs[i].mpc_irqtype == type) &&
353                     (mp_irqs[i].mpc_srcbusirq == irq))
354                         break;
355         }
356         if (i < mp_irq_entries) {
357                 int apic;
358                 for(apic = 0; apic < nr_ioapics; apic++) {
359                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
360                                 return apic;
361                 }
362         }
363
364         return -1;
365 }
366
367 /*
368  * Find a specific PCI IRQ entry.
369  * Not an __init, possibly needed by modules
370  */
371 static int pin_2_irq(int idx, int apic, int pin);
372
373 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
374 {
375         int apic, i, best_guess = -1;
376
377         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
378                 bus, slot, pin);
379         if (mp_bus_id_to_pci_bus[bus] == -1) {
380                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
381                 return -1;
382         }
383         for (i = 0; i < mp_irq_entries; i++) {
384                 int lbus = mp_irqs[i].mpc_srcbus;
385
386                 for (apic = 0; apic < nr_ioapics; apic++)
387                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
388                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
389                                 break;
390
391                 if (!test_bit(lbus, mp_bus_not_pci) &&
392                     !mp_irqs[i].mpc_irqtype &&
393                     (bus == lbus) &&
394                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
395                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
396
397                         if (!(apic || IO_APIC_IRQ(irq)))
398                                 continue;
399
400                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
401                                 return irq;
402                         /*
403                          * Use the first all-but-pin matching entry as a
404                          * best-guess fuzzy result for broken mptables.
405                          */
406                         if (best_guess < 0)
407                                 best_guess = irq;
408                 }
409         }
410         BUG_ON(best_guess >= NR_IRQS);
411         return best_guess;
412 }
413
414 /* ISA interrupts are always polarity zero edge triggered,
415  * when listed as conforming in the MP table. */
416
417 #define default_ISA_trigger(idx)        (0)
418 #define default_ISA_polarity(idx)       (0)
419
420 /* PCI interrupts are always polarity one level triggered,
421  * when listed as conforming in the MP table. */
422
423 #define default_PCI_trigger(idx)        (1)
424 #define default_PCI_polarity(idx)       (1)
425
426 static int __init MPBIOS_polarity(int idx)
427 {
428         int bus = mp_irqs[idx].mpc_srcbus;
429         int polarity;
430
431         /*
432          * Determine IRQ line polarity (high active or low active):
433          */
434         switch (mp_irqs[idx].mpc_irqflag & 3)
435         {
436                 case 0: /* conforms, ie. bus-type dependent polarity */
437                         if (test_bit(bus, mp_bus_not_pci))
438                                 polarity = default_ISA_polarity(idx);
439                         else
440                                 polarity = default_PCI_polarity(idx);
441                         break;
442                 case 1: /* high active */
443                 {
444                         polarity = 0;
445                         break;
446                 }
447                 case 2: /* reserved */
448                 {
449                         printk(KERN_WARNING "broken BIOS!!\n");
450                         polarity = 1;
451                         break;
452                 }
453                 case 3: /* low active */
454                 {
455                         polarity = 1;
456                         break;
457                 }
458                 default: /* invalid */
459                 {
460                         printk(KERN_WARNING "broken BIOS!!\n");
461                         polarity = 1;
462                         break;
463                 }
464         }
465         return polarity;
466 }
467
468 static int MPBIOS_trigger(int idx)
469 {
470         int bus = mp_irqs[idx].mpc_srcbus;
471         int trigger;
472
473         /*
474          * Determine IRQ trigger mode (edge or level sensitive):
475          */
476         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
477         {
478                 case 0: /* conforms, ie. bus-type dependent */
479                         if (test_bit(bus, mp_bus_not_pci))
480                                 trigger = default_ISA_trigger(idx);
481                         else
482                                 trigger = default_PCI_trigger(idx);
483                         break;
484                 case 1: /* edge */
485                 {
486                         trigger = 0;
487                         break;
488                 }
489                 case 2: /* reserved */
490                 {
491                         printk(KERN_WARNING "broken BIOS!!\n");
492                         trigger = 1;
493                         break;
494                 }
495                 case 3: /* level */
496                 {
497                         trigger = 1;
498                         break;
499                 }
500                 default: /* invalid */
501                 {
502                         printk(KERN_WARNING "broken BIOS!!\n");
503                         trigger = 0;
504                         break;
505                 }
506         }
507         return trigger;
508 }
509
510 static inline int irq_polarity(int idx)
511 {
512         return MPBIOS_polarity(idx);
513 }
514
515 static inline int irq_trigger(int idx)
516 {
517         return MPBIOS_trigger(idx);
518 }
519
520 static int pin_2_irq(int idx, int apic, int pin)
521 {
522         int irq, i;
523         int bus = mp_irqs[idx].mpc_srcbus;
524
525         /*
526          * Debugging check, we are in big trouble if this message pops up!
527          */
528         if (mp_irqs[idx].mpc_dstirq != pin)
529                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
530
531         if (test_bit(bus, mp_bus_not_pci)) {
532                 irq = mp_irqs[idx].mpc_srcbusirq;
533         } else {
534                 /*
535                  * PCI IRQs are mapped in order
536                  */
537                 i = irq = 0;
538                 while (i < apic)
539                         irq += nr_ioapic_registers[i++];
540                 irq += pin;
541         }
542         BUG_ON(irq >= NR_IRQS);
543         return irq;
544 }
545
546 static inline int IO_APIC_irq_trigger(int irq)
547 {
548         int apic, idx, pin;
549
550         for (apic = 0; apic < nr_ioapics; apic++) {
551                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
552                         idx = find_irq_entry(apic,pin,mp_INT);
553                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
554                                 return irq_trigger(idx);
555                 }
556         }
557         /*
558          * nonexistent IRQs are edge default
559          */
560         return 0;
561 }
562
563 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
564 unsigned int irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_EXTERNAL_VECTOR, 0 };
565
566 static int __assign_irq_vector(int irq, cpumask_t mask)
567 {
568         /*
569          * NOTE! The local APIC isn't very good at handling
570          * multiple interrupts at the same interrupt level.
571          * As the interrupt level is determined by taking the
572          * vector number and shifting that right by 4, we
573          * want to spread these out a bit so that they don't
574          * all fall in the same interrupt level.
575          *
576          * Also, we've got to be careful not to trash gate
577          * 0x80, because int 0x80 is hm, kind of importantish. ;)
578          */
579         static struct {
580                 int vector;
581                 int offset;
582         } pos[NR_CPUS] = { [ 0 ... NR_CPUS - 1] = {FIRST_DEVICE_VECTOR, 0} };
583         int old_vector = -1;
584         int cpu;
585
586         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
587
588         if (IO_APIC_VECTOR(irq) > 0)
589                 old_vector = IO_APIC_VECTOR(irq);
590         if ((old_vector > 0) && cpu_isset(old_vector >> 8, mask)) {
591                 return old_vector;
592         }
593
594         for_each_cpu_mask(cpu, mask) {
595                 int vector, offset;
596                 vector = pos[cpu].vector;
597                 offset = pos[cpu].offset;
598 next:
599                 vector += 8;
600                 if (vector >= FIRST_SYSTEM_VECTOR) {
601                         /* If we run out of vectors on large boxen, must share them. */
602                         offset = (offset + 1) % 8;
603                         vector = FIRST_DEVICE_VECTOR + offset;
604                 }
605                 if (unlikely(pos[cpu].vector == vector))
606                         continue;
607                 if (vector == IA32_SYSCALL_VECTOR)
608                         goto next;
609                 if (per_cpu(vector_irq, cpu)[vector] != -1)
610                         goto next;
611                 /* Found one! */
612                 pos[cpu].vector = vector;
613                 pos[cpu].offset = offset;
614                 if (old_vector >= 0) {
615                         int old_cpu = old_vector >> 8;
616                         old_vector &= 0xff;
617                         per_cpu(vector_irq, old_cpu)[old_vector] = -1;
618                 }
619                 per_cpu(vector_irq, cpu)[vector] = irq;
620                 vector |= cpu << 8;
621                 IO_APIC_VECTOR(irq) = vector;
622                 return vector;
623         }
624         return -ENOSPC;
625 }
626
627 static int assign_irq_vector(int irq, cpumask_t mask)
628 {
629         int vector;
630         unsigned long flags;
631
632         spin_lock_irqsave(&vector_lock, flags);
633         vector = __assign_irq_vector(irq, mask);
634         spin_unlock_irqrestore(&vector_lock, flags);
635         return vector;
636 }
637
638 extern void (*interrupt[NR_IRQS])(void);
639
640 static struct irq_chip ioapic_chip;
641
642 #define IOAPIC_AUTO     -1
643 #define IOAPIC_EDGE     0
644 #define IOAPIC_LEVEL    1
645
646 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
647 {
648         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
649                         trigger == IOAPIC_LEVEL)
650                 set_irq_chip_and_handler(irq, &ioapic_chip,
651                                          handle_fasteoi_irq);
652         else
653                 set_irq_chip_and_handler(irq, &ioapic_chip,
654                                          handle_edge_irq);
655 }
656
657 static void __init setup_IO_APIC_irqs(void)
658 {
659         struct IO_APIC_route_entry entry;
660         int apic, pin, idx, irq, first_notcon = 1, vector;
661         unsigned long flags;
662
663         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
664
665         for (apic = 0; apic < nr_ioapics; apic++) {
666         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
667
668                 /*
669                  * add it to the IO-APIC irq-routing table:
670                  */
671                 memset(&entry,0,sizeof(entry));
672
673                 entry.delivery_mode = INT_DELIVERY_MODE;
674                 entry.dest_mode = INT_DEST_MODE;
675                 entry.mask = 0;                         /* enable IRQ */
676                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
677
678                 idx = find_irq_entry(apic,pin,mp_INT);
679                 if (idx == -1) {
680                         if (first_notcon) {
681                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
682                                 first_notcon = 0;
683                         } else
684                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
685                         continue;
686                 }
687
688                 entry.trigger = irq_trigger(idx);
689                 entry.polarity = irq_polarity(idx);
690
691                 if (irq_trigger(idx)) {
692                         entry.trigger = 1;
693                         entry.mask = 1;
694                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
695                 }
696
697                 irq = pin_2_irq(idx, apic, pin);
698                 add_pin_to_irq(irq, apic, pin);
699
700                 if (!apic && !IO_APIC_IRQ(irq))
701                         continue;
702
703                 if (IO_APIC_IRQ(irq)) {
704                         cpumask_t mask;
705                         vector = assign_irq_vector(irq, TARGET_CPUS);
706                         if (vector < 0)
707                                 continue;
708
709                         cpus_clear(mask);
710                         cpu_set(vector >> 8, mask);
711                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
712                         entry.vector = vector & 0xff;
713
714                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
715                         if (!apic && (irq < 16))
716                                 disable_8259A_irq(irq);
717                 }
718                 ioapic_write_entry(apic, pin, entry);
719
720                 spin_lock_irqsave(&ioapic_lock, flags);
721                 set_native_irq_info(irq, TARGET_CPUS);
722                 spin_unlock_irqrestore(&ioapic_lock, flags);
723         }
724         }
725
726         if (!first_notcon)
727                 apic_printk(APIC_VERBOSE," not connected.\n");
728 }
729
730 /*
731  * Set up the 8259A-master output pin as broadcast to all
732  * CPUs.
733  */
734 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
735 {
736         struct IO_APIC_route_entry entry;
737         unsigned long flags;
738
739         memset(&entry,0,sizeof(entry));
740
741         disable_8259A_irq(0);
742
743         /* mask LVT0 */
744         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
745
746         /*
747          * We use logical delivery to get the timer IRQ
748          * to the first CPU.
749          */
750         entry.dest_mode = INT_DEST_MODE;
751         entry.mask = 0;                                 /* unmask IRQ now */
752         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
753         entry.delivery_mode = INT_DELIVERY_MODE;
754         entry.polarity = 0;
755         entry.trigger = 0;
756         entry.vector = vector;
757
758         /*
759          * The timer IRQ doesn't have to know that behind the
760          * scene we have a 8259A-master in AEOI mode ...
761          */
762         set_irq_chip_and_handler(0, &ioapic_chip, handle_edge_irq);
763
764         /*
765          * Add it to the IO-APIC irq-routing table:
766          */
767         spin_lock_irqsave(&ioapic_lock, flags);
768         io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
769         io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
770         spin_unlock_irqrestore(&ioapic_lock, flags);
771
772         enable_8259A_irq(0);
773 }
774
775 void __init UNEXPECTED_IO_APIC(void)
776 {
777 }
778
779 void __apicdebuginit print_IO_APIC(void)
780 {
781         int apic, i;
782         union IO_APIC_reg_00 reg_00;
783         union IO_APIC_reg_01 reg_01;
784         union IO_APIC_reg_02 reg_02;
785         unsigned long flags;
786
787         if (apic_verbosity == APIC_QUIET)
788                 return;
789
790         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
791         for (i = 0; i < nr_ioapics; i++)
792                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
793                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
794
795         /*
796          * We are a bit conservative about what we expect.  We have to
797          * know about every hardware change ASAP.
798          */
799         printk(KERN_INFO "testing the IO APIC.......................\n");
800
801         for (apic = 0; apic < nr_ioapics; apic++) {
802
803         spin_lock_irqsave(&ioapic_lock, flags);
804         reg_00.raw = io_apic_read(apic, 0);
805         reg_01.raw = io_apic_read(apic, 1);
806         if (reg_01.bits.version >= 0x10)
807                 reg_02.raw = io_apic_read(apic, 2);
808         spin_unlock_irqrestore(&ioapic_lock, flags);
809
810         printk("\n");
811         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
812         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
813         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
814         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
815                 UNEXPECTED_IO_APIC();
816
817         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
818         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
819         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
820                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
821                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
822                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
823                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
824                 (reg_01.bits.entries != 0x2E) &&
825                 (reg_01.bits.entries != 0x3F) &&
826                 (reg_01.bits.entries != 0x03) 
827         )
828                 UNEXPECTED_IO_APIC();
829
830         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
831         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
832         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
833                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
834                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
835                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
836                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
837                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
838         )
839                 UNEXPECTED_IO_APIC();
840         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
841                 UNEXPECTED_IO_APIC();
842
843         if (reg_01.bits.version >= 0x10) {
844                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
845                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
846                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
847                         UNEXPECTED_IO_APIC();
848         }
849
850         printk(KERN_DEBUG ".... IRQ redirection table:\n");
851
852         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
853                           " Stat Dest Deli Vect:   \n");
854
855         for (i = 0; i <= reg_01.bits.entries; i++) {
856                 struct IO_APIC_route_entry entry;
857
858                 entry = ioapic_read_entry(apic, i);
859
860                 printk(KERN_DEBUG " %02x %03X %02X  ",
861                         i,
862                         entry.dest.logical.logical_dest,
863                         entry.dest.physical.physical_dest
864                 );
865
866                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
867                         entry.mask,
868                         entry.trigger,
869                         entry.irr,
870                         entry.polarity,
871                         entry.delivery_status,
872                         entry.dest_mode,
873                         entry.delivery_mode,
874                         entry.vector
875                 );
876         }
877         }
878         printk(KERN_DEBUG "IRQ to pin mappings:\n");
879         for (i = 0; i < NR_IRQS; i++) {
880                 struct irq_pin_list *entry = irq_2_pin + i;
881                 if (entry->pin < 0)
882                         continue;
883                 printk(KERN_DEBUG "IRQ%d ", i);
884                 for (;;) {
885                         printk("-> %d:%d", entry->apic, entry->pin);
886                         if (!entry->next)
887                                 break;
888                         entry = irq_2_pin + entry->next;
889                 }
890                 printk("\n");
891         }
892
893         printk(KERN_INFO ".................................... done.\n");
894
895         return;
896 }
897
898 #if 0
899
900 static __apicdebuginit void print_APIC_bitfield (int base)
901 {
902         unsigned int v;
903         int i, j;
904
905         if (apic_verbosity == APIC_QUIET)
906                 return;
907
908         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
909         for (i = 0; i < 8; i++) {
910                 v = apic_read(base + i*0x10);
911                 for (j = 0; j < 32; j++) {
912                         if (v & (1<<j))
913                                 printk("1");
914                         else
915                                 printk("0");
916                 }
917                 printk("\n");
918         }
919 }
920
921 void __apicdebuginit print_local_APIC(void * dummy)
922 {
923         unsigned int v, ver, maxlvt;
924
925         if (apic_verbosity == APIC_QUIET)
926                 return;
927
928         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
929                 smp_processor_id(), hard_smp_processor_id());
930         v = apic_read(APIC_ID);
931         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
932         v = apic_read(APIC_LVR);
933         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
934         ver = GET_APIC_VERSION(v);
935         maxlvt = get_maxlvt();
936
937         v = apic_read(APIC_TASKPRI);
938         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
939
940         v = apic_read(APIC_ARBPRI);
941         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
942                 v & APIC_ARBPRI_MASK);
943         v = apic_read(APIC_PROCPRI);
944         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
945
946         v = apic_read(APIC_EOI);
947         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
948         v = apic_read(APIC_RRR);
949         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
950         v = apic_read(APIC_LDR);
951         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
952         v = apic_read(APIC_DFR);
953         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
954         v = apic_read(APIC_SPIV);
955         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
956
957         printk(KERN_DEBUG "... APIC ISR field:\n");
958         print_APIC_bitfield(APIC_ISR);
959         printk(KERN_DEBUG "... APIC TMR field:\n");
960         print_APIC_bitfield(APIC_TMR);
961         printk(KERN_DEBUG "... APIC IRR field:\n");
962         print_APIC_bitfield(APIC_IRR);
963
964         v = apic_read(APIC_ESR);
965         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
966
967         v = apic_read(APIC_ICR);
968         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
969         v = apic_read(APIC_ICR2);
970         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
971
972         v = apic_read(APIC_LVTT);
973         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
974
975         if (maxlvt > 3) {                       /* PC is LVT#4. */
976                 v = apic_read(APIC_LVTPC);
977                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
978         }
979         v = apic_read(APIC_LVT0);
980         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
981         v = apic_read(APIC_LVT1);
982         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
983
984         if (maxlvt > 2) {                       /* ERR is LVT#3. */
985                 v = apic_read(APIC_LVTERR);
986                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
987         }
988
989         v = apic_read(APIC_TMICT);
990         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
991         v = apic_read(APIC_TMCCT);
992         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
993         v = apic_read(APIC_TDCR);
994         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
995         printk("\n");
996 }
997
998 void print_all_local_APICs (void)
999 {
1000         on_each_cpu(print_local_APIC, NULL, 1, 1);
1001 }
1002
1003 void __apicdebuginit print_PIC(void)
1004 {
1005         unsigned int v;
1006         unsigned long flags;
1007
1008         if (apic_verbosity == APIC_QUIET)
1009                 return;
1010
1011         printk(KERN_DEBUG "\nprinting PIC contents\n");
1012
1013         spin_lock_irqsave(&i8259A_lock, flags);
1014
1015         v = inb(0xa1) << 8 | inb(0x21);
1016         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1017
1018         v = inb(0xa0) << 8 | inb(0x20);
1019         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1020
1021         outb(0x0b,0xa0);
1022         outb(0x0b,0x20);
1023         v = inb(0xa0) << 8 | inb(0x20);
1024         outb(0x0a,0xa0);
1025         outb(0x0a,0x20);
1026
1027         spin_unlock_irqrestore(&i8259A_lock, flags);
1028
1029         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1030
1031         v = inb(0x4d1) << 8 | inb(0x4d0);
1032         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1033 }
1034
1035 #endif  /*  0  */
1036
1037 static void __init enable_IO_APIC(void)
1038 {
1039         union IO_APIC_reg_01 reg_01;
1040         int i8259_apic, i8259_pin;
1041         int i, apic;
1042         unsigned long flags;
1043
1044         for (i = 0; i < PIN_MAP_SIZE; i++) {
1045                 irq_2_pin[i].pin = -1;
1046                 irq_2_pin[i].next = 0;
1047         }
1048
1049         /*
1050          * The number of IO-APIC IRQ registers (== #pins):
1051          */
1052         for (apic = 0; apic < nr_ioapics; apic++) {
1053                 spin_lock_irqsave(&ioapic_lock, flags);
1054                 reg_01.raw = io_apic_read(apic, 1);
1055                 spin_unlock_irqrestore(&ioapic_lock, flags);
1056                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1057         }
1058         for(apic = 0; apic < nr_ioapics; apic++) {
1059                 int pin;
1060                 /* See if any of the pins is in ExtINT mode */
1061                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1062                         struct IO_APIC_route_entry entry;
1063                         entry = ioapic_read_entry(apic, pin);
1064
1065                         /* If the interrupt line is enabled and in ExtInt mode
1066                          * I have found the pin where the i8259 is connected.
1067                          */
1068                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1069                                 ioapic_i8259.apic = apic;
1070                                 ioapic_i8259.pin  = pin;
1071                                 goto found_i8259;
1072                         }
1073                 }
1074         }
1075  found_i8259:
1076         /* Look to see what if the MP table has reported the ExtINT */
1077         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1078         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1079         /* Trust the MP table if nothing is setup in the hardware */
1080         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1081                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1082                 ioapic_i8259.pin  = i8259_pin;
1083                 ioapic_i8259.apic = i8259_apic;
1084         }
1085         /* Complain if the MP table and the hardware disagree */
1086         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1087                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1088         {
1089                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1090         }
1091
1092         /*
1093          * Do not trust the IO-APIC being empty at bootup
1094          */
1095         clear_IO_APIC();
1096 }
1097
1098 /*
1099  * Not an __init, needed by the reboot code
1100  */
1101 void disable_IO_APIC(void)
1102 {
1103         /*
1104          * Clear the IO-APIC before rebooting:
1105          */
1106         clear_IO_APIC();
1107
1108         /*
1109          * If the i8259 is routed through an IOAPIC
1110          * Put that IOAPIC in virtual wire mode
1111          * so legacy interrupts can be delivered.
1112          */
1113         if (ioapic_i8259.pin != -1) {
1114                 struct IO_APIC_route_entry entry;
1115
1116                 memset(&entry, 0, sizeof(entry));
1117                 entry.mask            = 0; /* Enabled */
1118                 entry.trigger         = 0; /* Edge */
1119                 entry.irr             = 0;
1120                 entry.polarity        = 0; /* High */
1121                 entry.delivery_status = 0;
1122                 entry.dest_mode       = 0; /* Physical */
1123                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1124                 entry.vector          = 0;
1125                 entry.dest.physical.physical_dest =
1126                                         GET_APIC_ID(apic_read(APIC_ID));
1127
1128                 /*
1129                  * Add it to the IO-APIC irq-routing table:
1130                  */
1131                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1132         }
1133
1134         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1135 }
1136
1137 /*
1138  * There is a nasty bug in some older SMP boards, their mptable lies
1139  * about the timer IRQ. We do the following to work around the situation:
1140  *
1141  *      - timer IRQ defaults to IO-APIC IRQ
1142  *      - if this function detects that timer IRQs are defunct, then we fall
1143  *        back to ISA timer IRQs
1144  */
1145 static int __init timer_irq_works(void)
1146 {
1147         unsigned long t1 = jiffies;
1148
1149         local_irq_enable();
1150         /* Let ten ticks pass... */
1151         mdelay((10 * 1000) / HZ);
1152
1153         /*
1154          * Expect a few ticks at least, to be sure some possible
1155          * glue logic does not lock up after one or two first
1156          * ticks in a non-ExtINT mode.  Also the local APIC
1157          * might have cached one ExtINT interrupt.  Finally, at
1158          * least one tick may be lost due to delays.
1159          */
1160
1161         /* jiffies wrap? */
1162         if (jiffies - t1 > 4)
1163                 return 1;
1164         return 0;
1165 }
1166
1167 /*
1168  * In the SMP+IOAPIC case it might happen that there are an unspecified
1169  * number of pending IRQ events unhandled. These cases are very rare,
1170  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1171  * better to do it this way as thus we do not have to be aware of
1172  * 'pending' interrupts in the IRQ path, except at this point.
1173  */
1174 /*
1175  * Edge triggered needs to resend any interrupt
1176  * that was delayed but this is now handled in the device
1177  * independent code.
1178  */
1179
1180 /*
1181  * Starting up a edge-triggered IO-APIC interrupt is
1182  * nasty - we need to make sure that we get the edge.
1183  * If it is already asserted for some reason, we need
1184  * return 1 to indicate that is was pending.
1185  *
1186  * This is not complete - we should be able to fake
1187  * an edge even if it isn't on the 8259A...
1188  */
1189
1190 static unsigned int startup_ioapic_irq(unsigned int irq)
1191 {
1192         int was_pending = 0;
1193         unsigned long flags;
1194
1195         spin_lock_irqsave(&ioapic_lock, flags);
1196         if (irq < 16) {
1197                 disable_8259A_irq(irq);
1198                 if (i8259A_irq_pending(irq))
1199                         was_pending = 1;
1200         }
1201         __unmask_IO_APIC_irq(irq);
1202         spin_unlock_irqrestore(&ioapic_lock, flags);
1203
1204         return was_pending;
1205 }
1206
1207 static int ioapic_retrigger_irq(unsigned int irq)
1208 {
1209         cpumask_t mask;
1210         unsigned vector;
1211
1212         vector = irq_vector[irq];
1213         cpus_clear(mask);
1214         cpu_set(vector >> 8, mask);
1215
1216         send_IPI_mask(mask, vector & 0xff);
1217
1218         return 1;
1219 }
1220
1221 /*
1222  * Level and edge triggered IO-APIC interrupts need different handling,
1223  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1224  * handled with the level-triggered descriptor, but that one has slightly
1225  * more overhead. Level-triggered interrupts cannot be handled with the
1226  * edge-triggered handler, without risking IRQ storms and other ugly
1227  * races.
1228  */
1229
1230 static void ack_apic_edge(unsigned int irq)
1231 {
1232         move_native_irq(irq);
1233         ack_APIC_irq();
1234 }
1235
1236 static void ack_apic_level(unsigned int irq)
1237 {
1238         int do_unmask_irq = 0;
1239
1240 #if defined(CONFIG_GENERIC_PENDING_IRQ) || defined(CONFIG_IRQBALANCE)
1241         /* If we are moving the irq we need to mask it */
1242         if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1243                 do_unmask_irq = 1;
1244                 mask_IO_APIC_irq(irq);
1245         }
1246 #endif
1247
1248         /*
1249          * We must acknowledge the irq before we move it or the acknowledge will
1250          * not propogate properly.
1251          */
1252         ack_APIC_irq();
1253
1254         /* Now we can move and renable the irq */
1255         move_masked_irq(irq);
1256         if (unlikely(do_unmask_irq))
1257                 unmask_IO_APIC_irq(irq);
1258 }
1259
1260 static struct irq_chip ioapic_chip __read_mostly = {
1261         .name           = "IO-APIC",
1262         .startup        = startup_ioapic_irq,
1263         .mask           = mask_IO_APIC_irq,
1264         .unmask         = unmask_IO_APIC_irq,
1265         .ack            = ack_apic_edge,
1266         .eoi            = ack_apic_level,
1267 #ifdef CONFIG_SMP
1268         .set_affinity   = set_ioapic_affinity_irq,
1269 #endif
1270         .retrigger      = ioapic_retrigger_irq,
1271 };
1272
1273 static inline void init_IO_APIC_traps(void)
1274 {
1275         int irq;
1276
1277         /*
1278          * NOTE! The local APIC isn't very good at handling
1279          * multiple interrupts at the same interrupt level.
1280          * As the interrupt level is determined by taking the
1281          * vector number and shifting that right by 4, we
1282          * want to spread these out a bit so that they don't
1283          * all fall in the same interrupt level.
1284          *
1285          * Also, we've got to be careful not to trash gate
1286          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1287          */
1288         for (irq = 0; irq < NR_IRQS ; irq++) {
1289                 int tmp = irq;
1290                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1291                         /*
1292                          * Hmm.. We don't have an entry for this,
1293                          * so default to an old-fashioned 8259
1294                          * interrupt if we can..
1295                          */
1296                         if (irq < 16)
1297                                 make_8259A_irq(irq);
1298                         else
1299                                 /* Strange. Oh, well.. */
1300                                 irq_desc[irq].chip = &no_irq_chip;
1301                 }
1302         }
1303 }
1304
1305 static void enable_lapic_irq (unsigned int irq)
1306 {
1307         unsigned long v;
1308
1309         v = apic_read(APIC_LVT0);
1310         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1311 }
1312
1313 static void disable_lapic_irq (unsigned int irq)
1314 {
1315         unsigned long v;
1316
1317         v = apic_read(APIC_LVT0);
1318         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1319 }
1320
1321 static void ack_lapic_irq (unsigned int irq)
1322 {
1323         ack_APIC_irq();
1324 }
1325
1326 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1327
1328 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1329         .typename = "local-APIC-edge",
1330         .startup = NULL, /* startup_irq() not used for IRQ0 */
1331         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1332         .enable = enable_lapic_irq,
1333         .disable = disable_lapic_irq,
1334         .ack = ack_lapic_irq,
1335         .end = end_lapic_irq,
1336 };
1337
1338 static void setup_nmi (void)
1339 {
1340         /*
1341          * Dirty trick to enable the NMI watchdog ...
1342          * We put the 8259A master into AEOI mode and
1343          * unmask on all local APICs LVT0 as NMI.
1344          *
1345          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1346          * is from Maciej W. Rozycki - so we do not have to EOI from
1347          * the NMI handler or the timer interrupt.
1348          */ 
1349         printk(KERN_INFO "activating NMI Watchdog ...");
1350
1351         enable_NMI_through_LVT0(NULL);
1352
1353         printk(" done.\n");
1354 }
1355
1356 /*
1357  * This looks a bit hackish but it's about the only one way of sending
1358  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1359  * not support the ExtINT mode, unfortunately.  We need to send these
1360  * cycles as some i82489DX-based boards have glue logic that keeps the
1361  * 8259A interrupt line asserted until INTA.  --macro
1362  */
1363 static inline void unlock_ExtINT_logic(void)
1364 {
1365         int apic, pin, i;
1366         struct IO_APIC_route_entry entry0, entry1;
1367         unsigned char save_control, save_freq_select;
1368         unsigned long flags;
1369
1370         pin  = find_isa_irq_pin(8, mp_INT);
1371         apic = find_isa_irq_apic(8, mp_INT);
1372         if (pin == -1)
1373                 return;
1374
1375         spin_lock_irqsave(&ioapic_lock, flags);
1376         *(((int *)&entry0) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
1377         *(((int *)&entry0) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
1378         spin_unlock_irqrestore(&ioapic_lock, flags);
1379         clear_IO_APIC_pin(apic, pin);
1380
1381         memset(&entry1, 0, sizeof(entry1));
1382
1383         entry1.dest_mode = 0;                   /* physical delivery */
1384         entry1.mask = 0;                        /* unmask IRQ now */
1385         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1386         entry1.delivery_mode = dest_ExtINT;
1387         entry1.polarity = entry0.polarity;
1388         entry1.trigger = 0;
1389         entry1.vector = 0;
1390
1391         spin_lock_irqsave(&ioapic_lock, flags);
1392         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1393         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1394         spin_unlock_irqrestore(&ioapic_lock, flags);
1395
1396         save_control = CMOS_READ(RTC_CONTROL);
1397         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1398         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1399                    RTC_FREQ_SELECT);
1400         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1401
1402         i = 100;
1403         while (i-- > 0) {
1404                 mdelay(10);
1405                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1406                         i -= 10;
1407         }
1408
1409         CMOS_WRITE(save_control, RTC_CONTROL);
1410         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1411         clear_IO_APIC_pin(apic, pin);
1412
1413         spin_lock_irqsave(&ioapic_lock, flags);
1414         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1415         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1416         spin_unlock_irqrestore(&ioapic_lock, flags);
1417 }
1418
1419 /*
1420  * This code may look a bit paranoid, but it's supposed to cooperate with
1421  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1422  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1423  * fanatically on his truly buggy board.
1424  *
1425  * FIXME: really need to revamp this for modern platforms only.
1426  */
1427 static inline void check_timer(void)
1428 {
1429         int apic1, pin1, apic2, pin2;
1430         int vector;
1431
1432         /*
1433          * get/set the timer IRQ vector:
1434          */
1435         disable_8259A_irq(0);
1436         vector = assign_irq_vector(0, TARGET_CPUS);
1437
1438         /*
1439          * Subtle, code in do_timer_interrupt() expects an AEOI
1440          * mode for the 8259A whenever interrupts are routed
1441          * through I/O APICs.  Also IRQ0 has to be enabled in
1442          * the 8259A which implies the virtual wire has to be
1443          * disabled in the local APIC.
1444          */
1445         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1446         init_8259A(1);
1447         if (timer_over_8254 > 0)
1448                 enable_8259A_irq(0);
1449
1450         pin1  = find_isa_irq_pin(0, mp_INT);
1451         apic1 = find_isa_irq_apic(0, mp_INT);
1452         pin2  = ioapic_i8259.pin;
1453         apic2 = ioapic_i8259.apic;
1454
1455         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1456                 vector, apic1, pin1, apic2, pin2);
1457
1458         if (pin1 != -1) {
1459                 /*
1460                  * Ok, does IRQ0 through the IOAPIC work?
1461                  */
1462                 unmask_IO_APIC_irq(0);
1463                 if (!no_timer_check && timer_irq_works()) {
1464                         nmi_watchdog_default();
1465                         if (nmi_watchdog == NMI_IO_APIC) {
1466                                 disable_8259A_irq(0);
1467                                 setup_nmi();
1468                                 enable_8259A_irq(0);
1469                         }
1470                         if (disable_timer_pin_1 > 0)
1471                                 clear_IO_APIC_pin(0, pin1);
1472                         return;
1473                 }
1474                 clear_IO_APIC_pin(apic1, pin1);
1475                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not "
1476                                 "connected to IO-APIC\n");
1477         }
1478
1479         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) "
1480                                 "through the 8259A ... ");
1481         if (pin2 != -1) {
1482                 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1483                         apic2, pin2);
1484                 /*
1485                  * legacy devices should be connected to IO APIC #0
1486                  */
1487                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
1488                 if (timer_irq_works()) {
1489                         apic_printk(APIC_VERBOSE," works.\n");
1490                         nmi_watchdog_default();
1491                         if (nmi_watchdog == NMI_IO_APIC) {
1492                                 setup_nmi();
1493                         }
1494                         return;
1495                 }
1496                 /*
1497                  * Cleanup, just in case ...
1498                  */
1499                 clear_IO_APIC_pin(apic2, pin2);
1500         }
1501         apic_printk(APIC_VERBOSE," failed.\n");
1502
1503         if (nmi_watchdog == NMI_IO_APIC) {
1504                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1505                 nmi_watchdog = 0;
1506         }
1507
1508         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1509
1510         disable_8259A_irq(0);
1511         irq_desc[0].chip = &lapic_irq_type;
1512         apic_write(APIC_LVT0, APIC_DM_FIXED | vector);  /* Fixed mode */
1513         enable_8259A_irq(0);
1514
1515         if (timer_irq_works()) {
1516                 apic_printk(APIC_VERBOSE," works.\n");
1517                 return;
1518         }
1519         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1520         apic_printk(APIC_VERBOSE," failed.\n");
1521
1522         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1523
1524         init_8259A(0);
1525         make_8259A_irq(0);
1526         apic_write(APIC_LVT0, APIC_DM_EXTINT);
1527
1528         unlock_ExtINT_logic();
1529
1530         if (timer_irq_works()) {
1531                 apic_printk(APIC_VERBOSE," works.\n");
1532                 return;
1533         }
1534         apic_printk(APIC_VERBOSE," failed :(.\n");
1535         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1536 }
1537
1538 static int __init notimercheck(char *s)
1539 {
1540         no_timer_check = 1;
1541         return 1;
1542 }
1543 __setup("no_timer_check", notimercheck);
1544
1545 /*
1546  *
1547  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1548  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1549  *   Linux doesn't really care, as it's not actually used
1550  *   for any interrupt handling anyway.
1551  */
1552 #define PIC_IRQS        (1<<2)
1553
1554 void __init setup_IO_APIC(void)
1555 {
1556         enable_IO_APIC();
1557
1558         if (acpi_ioapic)
1559                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1560         else
1561                 io_apic_irqs = ~PIC_IRQS;
1562
1563         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1564
1565         sync_Arb_IDs();
1566         setup_IO_APIC_irqs();
1567         init_IO_APIC_traps();
1568         check_timer();
1569         if (!acpi_ioapic)
1570                 print_IO_APIC();
1571 }
1572
1573 struct sysfs_ioapic_data {
1574         struct sys_device dev;
1575         struct IO_APIC_route_entry entry[0];
1576 };
1577 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1578
1579 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1580 {
1581         struct IO_APIC_route_entry *entry;
1582         struct sysfs_ioapic_data *data;
1583         int i;
1584
1585         data = container_of(dev, struct sysfs_ioapic_data, dev);
1586         entry = data->entry;
1587         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1588                 *entry = ioapic_read_entry(dev->id, i);
1589
1590         return 0;
1591 }
1592
1593 static int ioapic_resume(struct sys_device *dev)
1594 {
1595         struct IO_APIC_route_entry *entry;
1596         struct sysfs_ioapic_data *data;
1597         unsigned long flags;
1598         union IO_APIC_reg_00 reg_00;
1599         int i;
1600
1601         data = container_of(dev, struct sysfs_ioapic_data, dev);
1602         entry = data->entry;
1603
1604         spin_lock_irqsave(&ioapic_lock, flags);
1605         reg_00.raw = io_apic_read(dev->id, 0);
1606         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1607                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1608                 io_apic_write(dev->id, 0, reg_00.raw);
1609         }
1610         spin_unlock_irqrestore(&ioapic_lock, flags);
1611         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1612                 ioapic_write_entry(dev->id, i, entry[i]);
1613
1614         return 0;
1615 }
1616
1617 static struct sysdev_class ioapic_sysdev_class = {
1618         set_kset_name("ioapic"),
1619         .suspend = ioapic_suspend,
1620         .resume = ioapic_resume,
1621 };
1622
1623 static int __init ioapic_init_sysfs(void)
1624 {
1625         struct sys_device * dev;
1626         int i, size, error = 0;
1627
1628         error = sysdev_class_register(&ioapic_sysdev_class);
1629         if (error)
1630                 return error;
1631
1632         for (i = 0; i < nr_ioapics; i++ ) {
1633                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1634                         * sizeof(struct IO_APIC_route_entry);
1635                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1636                 if (!mp_ioapic_data[i]) {
1637                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1638                         continue;
1639                 }
1640                 memset(mp_ioapic_data[i], 0, size);
1641                 dev = &mp_ioapic_data[i]->dev;
1642                 dev->id = i;
1643                 dev->cls = &ioapic_sysdev_class;
1644                 error = sysdev_register(dev);
1645                 if (error) {
1646                         kfree(mp_ioapic_data[i]);
1647                         mp_ioapic_data[i] = NULL;
1648                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1649                         continue;
1650                 }
1651         }
1652
1653         return 0;
1654 }
1655
1656 device_initcall(ioapic_init_sysfs);
1657
1658 /*
1659  * Dynamic irq allocate and deallocation
1660  */
1661 int create_irq(void)
1662 {
1663         /* Allocate an unused irq */
1664         int irq;
1665         int new;
1666         int vector = 0;
1667         unsigned long flags;
1668
1669         irq = -ENOSPC;
1670         spin_lock_irqsave(&vector_lock, flags);
1671         for (new = (NR_IRQS - 1); new >= 0; new--) {
1672                 if (platform_legacy_irq(new))
1673                         continue;
1674                 if (irq_vector[new] != 0)
1675                         continue;
1676                 vector = __assign_irq_vector(new, TARGET_CPUS);
1677                 if (likely(vector > 0))
1678                         irq = new;
1679                 break;
1680         }
1681         spin_unlock_irqrestore(&vector_lock, flags);
1682
1683         if (irq >= 0) {
1684                 dynamic_irq_init(irq);
1685         }
1686         return irq;
1687 }
1688
1689 void destroy_irq(unsigned int irq)
1690 {
1691         unsigned long flags;
1692
1693         dynamic_irq_cleanup(irq);
1694
1695         spin_lock_irqsave(&vector_lock, flags);
1696         irq_vector[irq] = 0;
1697         spin_unlock_irqrestore(&vector_lock, flags);
1698 }
1699
1700 /*
1701  * MSI mesage composition
1702  */
1703 #ifdef CONFIG_PCI_MSI
1704 static int msi_msg_setup(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1705 {
1706         /* For now always this code always uses physical delivery
1707          * mode.
1708          */
1709         int vector;
1710         unsigned dest;
1711
1712         vector = assign_irq_vector(irq, TARGET_CPUS);
1713         if (vector >= 0) {
1714                 cpumask_t tmp;
1715
1716                 cpus_clear(tmp);
1717                 cpu_set(vector >> 8, tmp);
1718                 dest = cpu_mask_to_apicid(tmp);
1719
1720                 msg->address_hi = MSI_ADDR_BASE_HI;
1721                 msg->address_lo =
1722                         MSI_ADDR_BASE_LO |
1723                         ((INT_DEST_MODE == 0) ?
1724                                 MSI_ADDR_DEST_MODE_PHYSICAL:
1725                                 MSI_ADDR_DEST_MODE_LOGICAL) |
1726                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1727                                 MSI_ADDR_REDIRECTION_CPU:
1728                                 MSI_ADDR_REDIRECTION_LOWPRI) |
1729                         MSI_ADDR_DEST_ID(dest);
1730
1731                 msg->data =
1732                         MSI_DATA_TRIGGER_EDGE |
1733                         MSI_DATA_LEVEL_ASSERT |
1734                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1735                                 MSI_DATA_DELIVERY_FIXED:
1736                                 MSI_DATA_DELIVERY_LOWPRI) |
1737                         MSI_DATA_VECTOR(vector);
1738         }
1739         return vector;
1740 }
1741
1742 static void msi_msg_teardown(unsigned int irq)
1743 {
1744         return;
1745 }
1746
1747 static void msi_msg_set_affinity(unsigned int irq, cpumask_t mask, struct msi_msg *msg)
1748 {
1749         int vector;
1750         unsigned dest;
1751
1752         vector = assign_irq_vector(irq, mask);
1753         if (vector > 0) {
1754                 cpumask_t tmp;
1755
1756                 cpus_clear(tmp);
1757                 cpu_set(vector >> 8, tmp);
1758                 dest = cpu_mask_to_apicid(tmp);
1759
1760                 msg->data &= ~MSI_DATA_VECTOR_MASK;
1761                 msg->data |= MSI_DATA_VECTOR(vector);
1762                 msg->address_lo &= ~MSI_ADDR_DEST_ID_MASK;
1763                 msg->address_lo |= MSI_ADDR_DEST_ID(dest);
1764         }
1765 }
1766
1767 struct msi_ops arch_msi_ops = {
1768         .needs_64bit_address = 0,
1769         .setup = msi_msg_setup,
1770         .teardown = msi_msg_teardown,
1771         .target = msi_msg_set_affinity,
1772 };
1773
1774 #endif
1775
1776 /*
1777  * Hypertransport interrupt support
1778  */
1779 #ifdef CONFIG_HT_IRQ
1780
1781 #ifdef CONFIG_SMP
1782
1783 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1784 {
1785         u32 low, high;
1786         low  = read_ht_irq_low(irq);
1787         high = read_ht_irq_high(irq);
1788
1789         low  &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1790         high &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1791
1792         low  |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1793         high |= HT_IRQ_HIGH_DEST_ID(dest);
1794
1795         write_ht_irq_low(irq, low);
1796         write_ht_irq_high(irq, high);
1797 }
1798
1799 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1800 {
1801         unsigned int dest;
1802         cpumask_t tmp;
1803         int vector;
1804
1805         cpus_and(tmp, mask, cpu_online_map);
1806         if (cpus_empty(tmp))
1807                 tmp = TARGET_CPUS;
1808
1809         cpus_and(mask, tmp, CPU_MASK_ALL);
1810
1811         vector = assign_irq_vector(irq, mask);
1812         if (vector < 0)
1813                 return;
1814
1815         cpus_clear(tmp);
1816         cpu_set(vector >> 8, tmp);
1817         dest = cpu_mask_to_apicid(tmp);
1818
1819         target_ht_irq(irq, dest, vector & 0xff);
1820         set_native_irq_info(irq, mask);
1821 }
1822 #endif
1823
1824 static struct hw_interrupt_type ht_irq_chip = {
1825         .name           = "PCI-HT",
1826         .mask           = mask_ht_irq,
1827         .unmask         = unmask_ht_irq,
1828         .ack            = ack_apic_edge,
1829 #ifdef CONFIG_SMP
1830         .set_affinity   = set_ht_irq_affinity,
1831 #endif
1832         .retrigger      = ioapic_retrigger_irq,
1833 };
1834
1835 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
1836 {
1837         int vector;
1838
1839         vector = assign_irq_vector(irq, TARGET_CPUS);
1840         if (vector >= 0) {
1841                 u32 low, high;
1842                 unsigned dest;
1843                 cpumask_t tmp;
1844
1845                 cpus_clear(tmp);
1846                 cpu_set(vector >> 8, tmp);
1847                 dest = cpu_mask_to_apicid(tmp);
1848
1849                 high =  HT_IRQ_HIGH_DEST_ID(dest);
1850
1851                 low =   HT_IRQ_LOW_BASE |
1852                         HT_IRQ_LOW_DEST_ID(dest) |
1853                         HT_IRQ_LOW_VECTOR(vector) |
1854                         ((INT_DEST_MODE == 0) ?
1855                                 HT_IRQ_LOW_DM_PHYSICAL :
1856                                 HT_IRQ_LOW_DM_LOGICAL) |
1857                         HT_IRQ_LOW_RQEOI_EDGE |
1858                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1859                                 HT_IRQ_LOW_MT_FIXED :
1860                                 HT_IRQ_LOW_MT_ARBITRATED);
1861
1862                 write_ht_irq_low(irq, low);
1863                 write_ht_irq_high(irq, high);
1864
1865                 set_irq_chip_and_handler(irq, &ht_irq_chip, handle_edge_irq);
1866         }
1867         return vector;
1868 }
1869 #endif /* CONFIG_HT_IRQ */
1870
1871 /* --------------------------------------------------------------------------
1872                           ACPI-based IOAPIC Configuration
1873    -------------------------------------------------------------------------- */
1874
1875 #ifdef CONFIG_ACPI
1876
1877 #define IO_APIC_MAX_ID          0xFE
1878
1879 int __init io_apic_get_redir_entries (int ioapic)
1880 {
1881         union IO_APIC_reg_01    reg_01;
1882         unsigned long flags;
1883
1884         spin_lock_irqsave(&ioapic_lock, flags);
1885         reg_01.raw = io_apic_read(ioapic, 1);
1886         spin_unlock_irqrestore(&ioapic_lock, flags);
1887
1888         return reg_01.bits.entries;
1889 }
1890
1891
1892 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
1893 {
1894         struct IO_APIC_route_entry entry;
1895         unsigned long flags;
1896         int vector;
1897         cpumask_t mask;
1898
1899         if (!IO_APIC_IRQ(irq)) {
1900                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1901                         ioapic);
1902                 return -EINVAL;
1903         }
1904
1905         /*
1906          * IRQs < 16 are already in the irq_2_pin[] map
1907          */
1908         if (irq >= 16)
1909                 add_pin_to_irq(irq, ioapic, pin);
1910
1911
1912         vector = assign_irq_vector(irq, TARGET_CPUS);
1913         if (vector < 0)
1914                 return vector;
1915
1916         cpus_clear(mask);
1917         cpu_set(vector >> 8, mask);
1918
1919         /*
1920          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1921          * Note that we mask (disable) IRQs now -- these get enabled when the
1922          * corresponding device driver registers for this IRQ.
1923          */
1924
1925         memset(&entry,0,sizeof(entry));
1926
1927         entry.delivery_mode = INT_DELIVERY_MODE;
1928         entry.dest_mode = INT_DEST_MODE;
1929         entry.dest.logical.logical_dest = cpu_mask_to_apicid(mask);
1930         entry.trigger = triggering;
1931         entry.polarity = polarity;
1932         entry.mask = 1;                                  /* Disabled (masked) */
1933         entry.vector = vector & 0xff;
1934
1935         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1936                 "IRQ %d Mode:%i Active:%i)\n", ioapic, 
1937                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1938                triggering, polarity);
1939
1940         ioapic_register_intr(irq, entry.vector, triggering);
1941
1942         if (!ioapic && (irq < 16))
1943                 disable_8259A_irq(irq);
1944
1945         ioapic_write_entry(ioapic, pin, entry);
1946
1947         spin_lock_irqsave(&ioapic_lock, flags);
1948         set_native_irq_info(irq, TARGET_CPUS);
1949         spin_unlock_irqrestore(&ioapic_lock, flags);
1950
1951         return 0;
1952 }
1953
1954 #endif /* CONFIG_ACPI */
1955
1956
1957 /*
1958  * This function currently is only a helper for the i386 smp boot process where
1959  * we need to reprogram the ioredtbls to cater for the cpus which have come online
1960  * so mask in all cases should simply be TARGET_CPUS
1961  */
1962 #ifdef CONFIG_SMP
1963 void __init setup_ioapic_dest(void)
1964 {
1965         int pin, ioapic, irq, irq_entry;
1966
1967         if (skip_ioapic_setup == 1)
1968                 return;
1969
1970         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1971                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1972                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1973                         if (irq_entry == -1)
1974                                 continue;
1975                         irq = pin_2_irq(irq_entry, ioapic, pin);
1976                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
1977                 }
1978
1979         }
1980 }
1981 #endif