a9d194734a8e5b2e9fe3c2350d138f84f708f7d4
[linux-2.6.git] / arch / x86 / oprofile / op_model_amd.c
1 /*
2  * @file op_model_amd.c
3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
4  *
5  * @remark Copyright 2002-2009 OProfile authors
6  * @remark Read the file COPYING
7  *
8  * @author John Levon
9  * @author Philippe Elie
10  * @author Graydon Hoare
11  * @author Robert Richter <robert.richter@amd.com>
12  * @author Barry Kasindorf <barry.kasindorf@amd.com>
13  * @author Jason Yeh <jason.yeh@amd.com>
14  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
15  */
16
17 #include <linux/oprofile.h>
18 #include <linux/device.h>
19 #include <linux/pci.h>
20 #include <linux/percpu.h>
21
22 #include <asm/ptrace.h>
23 #include <asm/msr.h>
24 #include <asm/nmi.h>
25 #include <asm/apic.h>
26 #include <asm/processor.h>
27 #include <asm/cpufeature.h>
28
29 #include "op_x86_model.h"
30 #include "op_counter.h"
31
32 #define NUM_COUNTERS 4
33 #define NUM_CONTROLS 4
34 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
35 #define NUM_VIRT_COUNTERS 32
36 #define NUM_VIRT_CONTROLS 32
37 #else
38 #define NUM_VIRT_COUNTERS NUM_COUNTERS
39 #define NUM_VIRT_CONTROLS NUM_CONTROLS
40 #endif
41
42 #define OP_EVENT_MASK                   0x0FFF
43 #define OP_CTR_OVERFLOW                 (1ULL<<31)
44
45 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
46
47 static unsigned long reset_value[NUM_VIRT_COUNTERS];
48
49 /* IbsFetchCtl bits/masks */
50 #define IBS_FETCH_RAND_EN               (1ULL<<57)
51 #define IBS_FETCH_VAL                   (1ULL<<49)
52 #define IBS_FETCH_ENABLE                (1ULL<<48)
53 #define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
54
55 /* IbsOpCtl bits */
56 #define IBS_OP_CNT_CTL                  (1ULL<<19)
57 #define IBS_OP_VAL                      (1ULL<<18)
58 #define IBS_OP_ENABLE                   (1ULL<<17)
59
60 #define IBS_FETCH_SIZE                  6
61 #define IBS_OP_SIZE                     12
62
63 static u32 ibs_caps;
64
65 struct op_ibs_config {
66         unsigned long op_enabled;
67         unsigned long fetch_enabled;
68         unsigned long max_cnt_fetch;
69         unsigned long max_cnt_op;
70         unsigned long rand_en;
71         unsigned long dispatched_ops;
72 };
73
74 static struct op_ibs_config ibs_config;
75 static u64 ibs_op_ctl;
76
77 /*
78  * IBS cpuid feature detection
79  */
80
81 #define IBS_CPUID_FEATURES      0x8000001b
82
83 /*
84  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
85  * bit 0 is used to indicate the existence of IBS.
86  */
87 #define IBS_CAPS_AVAIL                  (1LL<<0)
88 #define IBS_CAPS_RDWROPCNT              (1LL<<3)
89 #define IBS_CAPS_OPCNT                  (1LL<<4)
90
91 /*
92  * IBS randomization macros
93  */
94 #define IBS_RANDOM_BITS                 12
95 #define IBS_RANDOM_MASK                 ((1ULL << IBS_RANDOM_BITS) - 1)
96 #define IBS_RANDOM_MAXCNT_OFFSET        (1ULL << (IBS_RANDOM_BITS - 5))
97
98 static u32 get_ibs_caps(void)
99 {
100         u32 ibs_caps;
101         unsigned int max_level;
102
103         if (!boot_cpu_has(X86_FEATURE_IBS))
104                 return 0;
105
106         /* check IBS cpuid feature flags */
107         max_level = cpuid_eax(0x80000000);
108         if (max_level < IBS_CPUID_FEATURES)
109                 return IBS_CAPS_AVAIL;
110
111         ibs_caps = cpuid_eax(IBS_CPUID_FEATURES);
112         if (!(ibs_caps & IBS_CAPS_AVAIL))
113                 /* cpuid flags not valid */
114                 return IBS_CAPS_AVAIL;
115
116         return ibs_caps;
117 }
118
119 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
120
121 static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
122 {
123         int i;
124
125         for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
126                 int hw_counter = op_x86_virt_to_phys(i);
127                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
128                         msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
129                 else
130                         msrs->multiplex[i].addr = 0;
131         }
132 }
133
134 static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
135                                struct op_msrs const * const msrs)
136 {
137         u64 val;
138         int i;
139
140         /* enable active counters */
141         for (i = 0; i < NUM_COUNTERS; ++i) {
142                 int virt = op_x86_phys_to_virt(i);
143                 if (!counter_config[virt].enabled)
144                         continue;
145                 rdmsrl(msrs->controls[i].addr, val);
146                 val &= model->reserved;
147                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
148                 wrmsrl(msrs->controls[i].addr, val);
149         }
150 }
151
152 #else
153
154 static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
155
156 #endif
157
158 /* functions for op_amd_spec */
159
160 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
161 {
162         int i;
163
164         for (i = 0; i < NUM_COUNTERS; i++) {
165                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
166                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
167                 else
168                         msrs->counters[i].addr = 0;
169         }
170
171         for (i = 0; i < NUM_CONTROLS; i++) {
172                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
173                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
174                 else
175                         msrs->controls[i].addr = 0;
176         }
177
178         op_mux_fill_in_addresses(msrs);
179 }
180
181 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
182                               struct op_msrs const * const msrs)
183 {
184         u64 val;
185         int i;
186
187         /* setup reset_value */
188         for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
189                 if (counter_config[i].enabled)
190                         reset_value[i] = counter_config[i].count;
191                 else
192                         reset_value[i] = 0;
193         }
194
195         /* clear all counters */
196         for (i = 0; i < NUM_CONTROLS; ++i) {
197                 if (unlikely(!msrs->controls[i].addr))
198                         continue;
199                 rdmsrl(msrs->controls[i].addr, val);
200                 val &= model->reserved;
201                 wrmsrl(msrs->controls[i].addr, val);
202         }
203
204         /* avoid a false detection of ctr overflows in NMI handler */
205         for (i = 0; i < NUM_COUNTERS; ++i) {
206                 if (unlikely(!msrs->counters[i].addr))
207                         continue;
208                 wrmsrl(msrs->counters[i].addr, -1LL);
209         }
210
211         /* enable active counters */
212         for (i = 0; i < NUM_COUNTERS; ++i) {
213                 int virt = op_x86_phys_to_virt(i);
214                 if (!counter_config[virt].enabled)
215                         continue;
216                 if (!msrs->counters[i].addr)
217                         continue;
218
219                 /* setup counter registers */
220                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
221
222                 /* setup control registers */
223                 rdmsrl(msrs->controls[i].addr, val);
224                 val &= model->reserved;
225                 val |= op_x86_get_ctrl(model, &counter_config[virt]);
226                 wrmsrl(msrs->controls[i].addr, val);
227         }
228 }
229
230 /*
231  * 16-bit Linear Feedback Shift Register (LFSR)
232  *
233  *                       16   14   13    11
234  * Feedback polynomial = X  + X  + X  +  X  + 1
235  */
236 static unsigned int lfsr_random(void)
237 {
238         static unsigned int lfsr_value = 0xF00D;
239         unsigned int bit;
240
241         /* Compute next bit to shift in */
242         bit = ((lfsr_value >> 0) ^
243                (lfsr_value >> 2) ^
244                (lfsr_value >> 3) ^
245                (lfsr_value >> 5)) & 0x0001;
246
247         /* Advance to next register value */
248         lfsr_value = (lfsr_value >> 1) | (bit << 15);
249
250         return lfsr_value;
251 }
252
253 /*
254  * IBS software randomization
255  *
256  * The IBS periodic op counter is randomized in software. The lower 12
257  * bits of the 20 bit counter are randomized. IbsOpCurCnt is
258  * initialized with a 12 bit random value.
259  */
260 static inline u64 op_amd_randomize_ibs_op(u64 val)
261 {
262         unsigned int random = lfsr_random();
263
264         if (!(ibs_caps & IBS_CAPS_RDWROPCNT))
265                 /*
266                  * Work around if the hw can not write to IbsOpCurCnt
267                  *
268                  * Randomize the lower 8 bits of the 16 bit
269                  * IbsOpMaxCnt [15:0] value in the range of -128 to
270                  * +127 by adding/subtracting an offset to the
271                  * maximum count (IbsOpMaxCnt).
272                  *
273                  * To avoid over or underflows and protect upper bits
274                  * starting at bit 16, the initial value for
275                  * IbsOpMaxCnt must fit in the range from 0x0081 to
276                  * 0xff80.
277                  */
278                 val += (s8)(random >> 4);
279         else
280                 val |= (u64)(random & IBS_RANDOM_MASK) << 32;
281
282         return val;
283 }
284
285 static inline void
286 op_amd_handle_ibs(struct pt_regs * const regs,
287                   struct op_msrs const * const msrs)
288 {
289         u64 val, ctl;
290         struct op_entry entry;
291
292         if (!ibs_caps)
293                 return;
294
295         if (ibs_config.fetch_enabled) {
296                 rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
297                 if (ctl & IBS_FETCH_VAL) {
298                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
299                         oprofile_write_reserve(&entry, regs, val,
300                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
301                         oprofile_add_data64(&entry, val);
302                         oprofile_add_data64(&entry, ctl);
303                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
304                         oprofile_add_data64(&entry, val);
305                         oprofile_write_commit(&entry);
306
307                         /* reenable the IRQ */
308                         ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
309                         ctl |= IBS_FETCH_ENABLE;
310                         wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
311                 }
312         }
313
314         if (ibs_config.op_enabled) {
315                 rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
316                 if (ctl & IBS_OP_VAL) {
317                         rdmsrl(MSR_AMD64_IBSOPRIP, val);
318                         oprofile_write_reserve(&entry, regs, val,
319                                                IBS_OP_CODE, IBS_OP_SIZE);
320                         oprofile_add_data64(&entry, val);
321                         rdmsrl(MSR_AMD64_IBSOPDATA, val);
322                         oprofile_add_data64(&entry, val);
323                         rdmsrl(MSR_AMD64_IBSOPDATA2, val);
324                         oprofile_add_data64(&entry, val);
325                         rdmsrl(MSR_AMD64_IBSOPDATA3, val);
326                         oprofile_add_data64(&entry, val);
327                         rdmsrl(MSR_AMD64_IBSDCLINAD, val);
328                         oprofile_add_data64(&entry, val);
329                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
330                         oprofile_add_data64(&entry, val);
331                         oprofile_write_commit(&entry);
332
333                         /* reenable the IRQ */
334                         ctl = op_amd_randomize_ibs_op(ibs_op_ctl);
335                         wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
336                 }
337         }
338 }
339
340 static inline void op_amd_start_ibs(void)
341 {
342         u64 val;
343
344         if (!ibs_caps)
345                 return;
346
347         if (ibs_config.fetch_enabled) {
348                 val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
349                 val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
350                 val |= IBS_FETCH_ENABLE;
351                 wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
352         }
353
354         if (ibs_config.op_enabled) {
355                 ibs_op_ctl = ibs_config.max_cnt_op >> 4;
356                 if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) {
357                         /*
358                          * IbsOpCurCnt not supported.  See
359                          * op_amd_randomize_ibs_op() for details.
360                          */
361                         ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL);
362                 } else {
363                         /*
364                          * The start value is randomized with a
365                          * positive offset, we need to compensate it
366                          * with the half of the randomized range. Also
367                          * avoid underflows.
368                          */
369                         ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET,
370                                          0xFFFFULL);
371                 }
372                 if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops)
373                         ibs_op_ctl |= IBS_OP_CNT_CTL;
374                 ibs_op_ctl |= IBS_OP_ENABLE;
375                 val = op_amd_randomize_ibs_op(ibs_op_ctl);
376                 wrmsrl(MSR_AMD64_IBSOPCTL, val);
377         }
378 }
379
380 static void op_amd_stop_ibs(void)
381 {
382         if (!ibs_caps)
383                 return;
384
385         if (ibs_config.fetch_enabled)
386                 /* clear max count and enable */
387                 wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
388
389         if (ibs_config.op_enabled)
390                 /* clear max count and enable */
391                 wrmsrl(MSR_AMD64_IBSOPCTL, 0);
392 }
393
394 static int op_amd_check_ctrs(struct pt_regs * const regs,
395                              struct op_msrs const * const msrs)
396 {
397         u64 val;
398         int i;
399
400         for (i = 0; i < NUM_COUNTERS; ++i) {
401                 int virt = op_x86_phys_to_virt(i);
402                 if (!reset_value[virt])
403                         continue;
404                 rdmsrl(msrs->counters[i].addr, val);
405                 /* bit is clear if overflowed: */
406                 if (val & OP_CTR_OVERFLOW)
407                         continue;
408                 oprofile_add_sample(regs, virt);
409                 wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
410         }
411
412         op_amd_handle_ibs(regs, msrs);
413
414         /* See op_model_ppro.c */
415         return 1;
416 }
417
418 static void op_amd_start(struct op_msrs const * const msrs)
419 {
420         u64 val;
421         int i;
422
423         for (i = 0; i < NUM_COUNTERS; ++i) {
424                 if (!reset_value[op_x86_phys_to_virt(i)])
425                         continue;
426                 rdmsrl(msrs->controls[i].addr, val);
427                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
428                 wrmsrl(msrs->controls[i].addr, val);
429         }
430
431         op_amd_start_ibs();
432 }
433
434 static void op_amd_stop(struct op_msrs const * const msrs)
435 {
436         u64 val;
437         int i;
438
439         /*
440          * Subtle: stop on all counters to avoid race with setting our
441          * pm callback
442          */
443         for (i = 0; i < NUM_COUNTERS; ++i) {
444                 if (!reset_value[op_x86_phys_to_virt(i)])
445                         continue;
446                 rdmsrl(msrs->controls[i].addr, val);
447                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
448                 wrmsrl(msrs->controls[i].addr, val);
449         }
450
451         op_amd_stop_ibs();
452 }
453
454 static void op_amd_shutdown(struct op_msrs const * const msrs)
455 {
456         int i;
457
458         for (i = 0; i < NUM_COUNTERS; ++i) {
459                 if (msrs->counters[i].addr)
460                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
461         }
462         for (i = 0; i < NUM_CONTROLS; ++i) {
463                 if (msrs->controls[i].addr)
464                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
465         }
466 }
467
468 static u8 ibs_eilvt_off;
469
470 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
471 {
472         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
473 }
474
475 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
476 {
477         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
478 }
479
480 static int init_ibs_nmi(void)
481 {
482 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
483 #define IBSCTL                          0x1cc
484         struct pci_dev *cpu_cfg;
485         int nodes;
486         u32 value = 0;
487
488         /* per CPU setup */
489         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
490
491         nodes = 0;
492         cpu_cfg = NULL;
493         do {
494                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
495                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
496                                          cpu_cfg);
497                 if (!cpu_cfg)
498                         break;
499                 ++nodes;
500                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
501                                        | IBSCTL_LVTOFFSETVAL);
502                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
503                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
504                         pci_dev_put(cpu_cfg);
505                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
506                                 "IBSCTL = 0x%08x", value);
507                         return 1;
508                 }
509         } while (1);
510
511         if (!nodes) {
512                 printk(KERN_DEBUG "No CPU node configured for IBS");
513                 return 1;
514         }
515
516         return 0;
517 }
518
519 /* uninitialize the APIC for the IBS interrupts if needed */
520 static void clear_ibs_nmi(void)
521 {
522         if (ibs_caps)
523                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
524 }
525
526 /* initialize the APIC for the IBS interrupts if available */
527 static void ibs_init(void)
528 {
529         ibs_caps = get_ibs_caps();
530
531         if (!ibs_caps)
532                 return;
533
534         if (init_ibs_nmi()) {
535                 ibs_caps = 0;
536                 return;
537         }
538
539         printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n",
540                (unsigned)ibs_caps);
541 }
542
543 static void ibs_exit(void)
544 {
545         if (!ibs_caps)
546                 return;
547
548         clear_ibs_nmi();
549 }
550
551 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
552
553 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
554 {
555         struct dentry *dir;
556         int ret = 0;
557
558         /* architecture specific files */
559         if (create_arch_files)
560                 ret = create_arch_files(sb, root);
561
562         if (ret)
563                 return ret;
564
565         if (!ibs_caps)
566                 return ret;
567
568         /* model specific files */
569
570         /* setup some reasonable defaults */
571         ibs_config.max_cnt_fetch = 250000;
572         ibs_config.fetch_enabled = 0;
573         ibs_config.max_cnt_op = 250000;
574         ibs_config.op_enabled = 0;
575         ibs_config.dispatched_ops = 0;
576
577         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
578         oprofilefs_create_ulong(sb, dir, "enable",
579                                 &ibs_config.fetch_enabled);
580         oprofilefs_create_ulong(sb, dir, "max_count",
581                                 &ibs_config.max_cnt_fetch);
582         oprofilefs_create_ulong(sb, dir, "rand_enable",
583                                 &ibs_config.rand_en);
584
585         dir = oprofilefs_mkdir(sb, root, "ibs_op");
586         oprofilefs_create_ulong(sb, dir, "enable",
587                                 &ibs_config.op_enabled);
588         oprofilefs_create_ulong(sb, dir, "max_count",
589                                 &ibs_config.max_cnt_op);
590         if (ibs_caps & IBS_CAPS_OPCNT)
591                 oprofilefs_create_ulong(sb, dir, "dispatched_ops",
592                                         &ibs_config.dispatched_ops);
593
594         return 0;
595 }
596
597 static int op_amd_init(struct oprofile_operations *ops)
598 {
599         ibs_init();
600         create_arch_files = ops->create_files;
601         ops->create_files = setup_ibs_files;
602         return 0;
603 }
604
605 static void op_amd_exit(void)
606 {
607         ibs_exit();
608 }
609
610 struct op_x86_model_spec op_amd_spec = {
611         .num_counters           = NUM_COUNTERS,
612         .num_controls           = NUM_CONTROLS,
613         .num_virt_counters      = NUM_VIRT_COUNTERS,
614         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
615         .event_mask             = OP_EVENT_MASK,
616         .init                   = op_amd_init,
617         .exit                   = op_amd_exit,
618         .fill_in_addresses      = &op_amd_fill_in_addresses,
619         .setup_ctrs             = &op_amd_setup_ctrs,
620         .check_ctrs             = &op_amd_check_ctrs,
621         .start                  = &op_amd_start,
622         .stop                   = &op_amd_stop,
623         .shutdown               = &op_amd_shutdown,
624 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
625         .switch_ctrl            = &op_mux_switch_ctrl,
626 #endif
627 };