x86/oprofile: use 64 bit wrmsr functions
[linux-2.6.git] / arch / x86 / oprofile / op_model_amd.c
1 /*
2  * @file op_model_amd.c
3  * athlon / K7 / K8 / Family 10h model-specific MSR operations
4  *
5  * @remark Copyright 2002-2009 OProfile authors
6  * @remark Read the file COPYING
7  *
8  * @author John Levon
9  * @author Philippe Elie
10  * @author Graydon Hoare
11  * @author Robert Richter <robert.richter@amd.com>
12  * @author Barry Kasindorf
13  */
14
15 #include <linux/oprofile.h>
16 #include <linux/device.h>
17 #include <linux/pci.h>
18
19 #include <asm/ptrace.h>
20 #include <asm/msr.h>
21 #include <asm/nmi.h>
22
23 #include "op_x86_model.h"
24 #include "op_counter.h"
25
26 #define NUM_COUNTERS 4
27 #define NUM_CONTROLS 4
28 #define OP_EVENT_MASK                   0x0FFF
29 #define OP_CTR_OVERFLOW                 (1ULL<<31)
30
31 #define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
32
33 static unsigned long reset_value[NUM_COUNTERS];
34
35 #ifdef CONFIG_OPROFILE_IBS
36
37 /* IbsFetchCtl bits/masks */
38 #define IBS_FETCH_HIGH_VALID_BIT        (1UL << 17)     /* bit 49 */
39 #define IBS_FETCH_HIGH_ENABLE           (1UL << 16)     /* bit 48 */
40 #define IBS_FETCH_LOW_MAX_CNT_MASK      0x0000FFFFUL    /* MaxCnt mask */
41
42 /*IbsOpCtl bits */
43 #define IBS_OP_LOW_VALID_BIT            (1ULL<<18)      /* bit 18 */
44 #define IBS_OP_LOW_ENABLE               (1ULL<<17)      /* bit 17 */
45
46 #define IBS_FETCH_SIZE  6
47 #define IBS_OP_SIZE     12
48
49 static int has_ibs;     /* AMD Family10h and later */
50
51 struct op_ibs_config {
52         unsigned long op_enabled;
53         unsigned long fetch_enabled;
54         unsigned long max_cnt_fetch;
55         unsigned long max_cnt_op;
56         unsigned long rand_en;
57         unsigned long dispatched_ops;
58 };
59
60 static struct op_ibs_config ibs_config;
61
62 #endif
63
64 /* functions for op_amd_spec */
65
66 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
67 {
68         int i;
69
70         for (i = 0; i < NUM_COUNTERS; i++) {
71                 if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
72                         msrs->counters[i].addr = MSR_K7_PERFCTR0 + i;
73                 else
74                         msrs->counters[i].addr = 0;
75         }
76
77         for (i = 0; i < NUM_CONTROLS; i++) {
78                 if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i))
79                         msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i;
80                 else
81                         msrs->controls[i].addr = 0;
82         }
83 }
84
85 static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
86                               struct op_msrs const * const msrs)
87 {
88         u64 val;
89         int i;
90
91         /* clear all counters */
92         for (i = 0 ; i < NUM_CONTROLS; ++i) {
93                 if (unlikely(!msrs->controls[i].addr))
94                         continue;
95                 rdmsrl(msrs->controls[i].addr, val);
96                 val &= model->reserved;
97                 wrmsrl(msrs->controls[i].addr, val);
98         }
99
100         /* avoid a false detection of ctr overflows in NMI handler */
101         for (i = 0; i < NUM_COUNTERS; ++i) {
102                 if (unlikely(!msrs->counters[i].addr))
103                         continue;
104                 wrmsrl(msrs->counters[i].addr, -1LL);
105         }
106
107         /* enable active counters */
108         for (i = 0; i < NUM_COUNTERS; ++i) {
109                 if (counter_config[i].enabled && msrs->counters[i].addr) {
110                         reset_value[i] = counter_config[i].count;
111                         wrmsrl(msrs->counters[i].addr,
112                                -(s64)counter_config[i].count);
113                         rdmsrl(msrs->controls[i].addr, val);
114                         val &= model->reserved;
115                         val |= op_x86_get_ctrl(model, &counter_config[i]);
116                         wrmsrl(msrs->controls[i].addr, val);
117                 } else {
118                         reset_value[i] = 0;
119                 }
120         }
121 }
122
123 #ifdef CONFIG_OPROFILE_IBS
124
125 static inline int
126 op_amd_handle_ibs(struct pt_regs * const regs,
127                   struct op_msrs const * const msrs)
128 {
129         u32 low, high;
130         u64 msr;
131         struct op_entry entry;
132
133         if (!has_ibs)
134                 return 1;
135
136         if (ibs_config.fetch_enabled) {
137                 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
138                 if (high & IBS_FETCH_HIGH_VALID_BIT) {
139                         rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
140                         oprofile_write_reserve(&entry, regs, msr,
141                                                IBS_FETCH_CODE, IBS_FETCH_SIZE);
142                         oprofile_add_data(&entry, (u32)msr);
143                         oprofile_add_data(&entry, (u32)(msr >> 32));
144                         oprofile_add_data(&entry, low);
145                         oprofile_add_data(&entry, high);
146                         rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
147                         oprofile_add_data(&entry, (u32)msr);
148                         oprofile_add_data(&entry, (u32)(msr >> 32));
149                         oprofile_write_commit(&entry);
150
151                         /* reenable the IRQ */
152                         high &= ~IBS_FETCH_HIGH_VALID_BIT;
153                         high |= IBS_FETCH_HIGH_ENABLE;
154                         low &= IBS_FETCH_LOW_MAX_CNT_MASK;
155                         wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
156                 }
157         }
158
159         if (ibs_config.op_enabled) {
160                 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
161                 if (low & IBS_OP_LOW_VALID_BIT) {
162                         rdmsrl(MSR_AMD64_IBSOPRIP, msr);
163                         oprofile_write_reserve(&entry, regs, msr,
164                                                IBS_OP_CODE, IBS_OP_SIZE);
165                         oprofile_add_data(&entry, (u32)msr);
166                         oprofile_add_data(&entry, (u32)(msr >> 32));
167                         rdmsrl(MSR_AMD64_IBSOPDATA, msr);
168                         oprofile_add_data(&entry, (u32)msr);
169                         oprofile_add_data(&entry, (u32)(msr >> 32));
170                         rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
171                         oprofile_add_data(&entry, (u32)msr);
172                         oprofile_add_data(&entry, (u32)(msr >> 32));
173                         rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
174                         oprofile_add_data(&entry, (u32)msr);
175                         oprofile_add_data(&entry, (u32)(msr >> 32));
176                         rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
177                         oprofile_add_data(&entry, (u32)msr);
178                         oprofile_add_data(&entry, (u32)(msr >> 32));
179                         rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
180                         oprofile_add_data(&entry, (u32)msr);
181                         oprofile_add_data(&entry, (u32)(msr >> 32));
182                         oprofile_write_commit(&entry);
183
184                         /* reenable the IRQ */
185                         high = 0;
186                         low &= ~IBS_OP_LOW_VALID_BIT;
187                         low |= IBS_OP_LOW_ENABLE;
188                         wrmsr(MSR_AMD64_IBSOPCTL, low, high);
189                 }
190         }
191
192         return 1;
193 }
194
195 static inline void op_amd_start_ibs(void)
196 {
197         unsigned int low, high;
198         if (has_ibs && ibs_config.fetch_enabled) {
199                 low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
200                 high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
201                         + IBS_FETCH_HIGH_ENABLE;
202                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
203         }
204
205         if (has_ibs && ibs_config.op_enabled) {
206                 low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
207                         + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
208                         + IBS_OP_LOW_ENABLE;
209                 high = 0;
210                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
211         }
212 }
213
214 static void op_amd_stop_ibs(void)
215 {
216         unsigned int low, high;
217         if (has_ibs && ibs_config.fetch_enabled) {
218                 /* clear max count and enable */
219                 low = 0;
220                 high = 0;
221                 wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
222         }
223
224         if (has_ibs && ibs_config.op_enabled) {
225                 /* clear max count and enable */
226                 low = 0;
227                 high = 0;
228                 wrmsr(MSR_AMD64_IBSOPCTL, low, high);
229         }
230 }
231
232 #else
233
234 static inline int op_amd_handle_ibs(struct pt_regs * const regs,
235                                     struct op_msrs const * const msrs) { }
236 static inline void op_amd_start_ibs(void) { }
237 static inline void op_amd_stop_ibs(void) { }
238
239 #endif
240
241 static int op_amd_check_ctrs(struct pt_regs * const regs,
242                              struct op_msrs const * const msrs)
243 {
244         u64 val;
245         int i;
246
247         for (i = 0 ; i < NUM_COUNTERS; ++i) {
248                 if (!reset_value[i])
249                         continue;
250                 rdmsrl(msrs->counters[i].addr, val);
251                 /* bit is clear if overflowed: */
252                 if (val & OP_CTR_OVERFLOW)
253                         continue;
254                 oprofile_add_sample(regs, i);
255                 wrmsrl(msrs->counters[i].addr, -(s64)reset_value[i]);
256         }
257
258         op_amd_handle_ibs(regs, msrs);
259
260         /* See op_model_ppro.c */
261         return 1;
262 }
263
264 static void op_amd_start(struct op_msrs const * const msrs)
265 {
266         u64 val;
267         int i;
268         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
269                 if (reset_value[i]) {
270                         rdmsrl(msrs->controls[i].addr, val);
271                         val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
272                         wrmsrl(msrs->controls[i].addr, val);
273                 }
274         }
275
276         op_amd_start_ibs();
277 }
278
279 static void op_amd_stop(struct op_msrs const * const msrs)
280 {
281         u64 val;
282         int i;
283
284         /*
285          * Subtle: stop on all counters to avoid race with setting our
286          * pm callback
287          */
288         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
289                 if (!reset_value[i])
290                         continue;
291                 rdmsrl(msrs->controls[i].addr, val);
292                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
293                 wrmsrl(msrs->controls[i].addr, val);
294         }
295
296         op_amd_stop_ibs();
297 }
298
299 static void op_amd_shutdown(struct op_msrs const * const msrs)
300 {
301         int i;
302
303         for (i = 0 ; i < NUM_COUNTERS ; ++i) {
304                 if (msrs->counters[i].addr)
305                         release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
306         }
307         for (i = 0 ; i < NUM_CONTROLS ; ++i) {
308                 if (msrs->controls[i].addr)
309                         release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
310         }
311 }
312
313 #ifdef CONFIG_OPROFILE_IBS
314
315 static u8 ibs_eilvt_off;
316
317 static inline void apic_init_ibs_nmi_per_cpu(void *arg)
318 {
319         ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0);
320 }
321
322 static inline void apic_clear_ibs_nmi_per_cpu(void *arg)
323 {
324         setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1);
325 }
326
327 static int init_ibs_nmi(void)
328 {
329 #define IBSCTL_LVTOFFSETVAL             (1 << 8)
330 #define IBSCTL                          0x1cc
331         struct pci_dev *cpu_cfg;
332         int nodes;
333         u32 value = 0;
334
335         /* per CPU setup */
336         on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1);
337
338         nodes = 0;
339         cpu_cfg = NULL;
340         do {
341                 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
342                                          PCI_DEVICE_ID_AMD_10H_NB_MISC,
343                                          cpu_cfg);
344                 if (!cpu_cfg)
345                         break;
346                 ++nodes;
347                 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
348                                        | IBSCTL_LVTOFFSETVAL);
349                 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
350                 if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) {
351                         pci_dev_put(cpu_cfg);
352                         printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
353                                 "IBSCTL = 0x%08x", value);
354                         return 1;
355                 }
356         } while (1);
357
358         if (!nodes) {
359                 printk(KERN_DEBUG "No CPU node configured for IBS");
360                 return 1;
361         }
362
363 #ifdef CONFIG_NUMA
364         /* Sanity check */
365         /* Works only for 64bit with proper numa implementation. */
366         if (nodes != num_possible_nodes()) {
367                 printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, "
368                         "found: %d, expected %d",
369                         nodes, num_possible_nodes());
370                 return 1;
371         }
372 #endif
373         return 0;
374 }
375
376 /* uninitialize the APIC for the IBS interrupts if needed */
377 static void clear_ibs_nmi(void)
378 {
379         if (has_ibs)
380                 on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1);
381 }
382
383 /* initialize the APIC for the IBS interrupts if available */
384 static void ibs_init(void)
385 {
386         has_ibs = boot_cpu_has(X86_FEATURE_IBS);
387
388         if (!has_ibs)
389                 return;
390
391         if (init_ibs_nmi()) {
392                 has_ibs = 0;
393                 return;
394         }
395
396         printk(KERN_INFO "oprofile: AMD IBS detected\n");
397 }
398
399 static void ibs_exit(void)
400 {
401         if (!has_ibs)
402                 return;
403
404         clear_ibs_nmi();
405 }
406
407 static int (*create_arch_files)(struct super_block *sb, struct dentry *root);
408
409 static int setup_ibs_files(struct super_block *sb, struct dentry *root)
410 {
411         struct dentry *dir;
412         int ret = 0;
413
414         /* architecture specific files */
415         if (create_arch_files)
416                 ret = create_arch_files(sb, root);
417
418         if (ret)
419                 return ret;
420
421         if (!has_ibs)
422                 return ret;
423
424         /* model specific files */
425
426         /* setup some reasonable defaults */
427         ibs_config.max_cnt_fetch = 250000;
428         ibs_config.fetch_enabled = 0;
429         ibs_config.max_cnt_op = 250000;
430         ibs_config.op_enabled = 0;
431         ibs_config.dispatched_ops = 1;
432
433         dir = oprofilefs_mkdir(sb, root, "ibs_fetch");
434         oprofilefs_create_ulong(sb, dir, "enable",
435                                 &ibs_config.fetch_enabled);
436         oprofilefs_create_ulong(sb, dir, "max_count",
437                                 &ibs_config.max_cnt_fetch);
438         oprofilefs_create_ulong(sb, dir, "rand_enable",
439                                 &ibs_config.rand_en);
440
441         dir = oprofilefs_mkdir(sb, root, "ibs_op");
442         oprofilefs_create_ulong(sb, dir, "enable",
443                                 &ibs_config.op_enabled);
444         oprofilefs_create_ulong(sb, dir, "max_count",
445                                 &ibs_config.max_cnt_op);
446         oprofilefs_create_ulong(sb, dir, "dispatched_ops",
447                                 &ibs_config.dispatched_ops);
448
449         return 0;
450 }
451
452 static int op_amd_init(struct oprofile_operations *ops)
453 {
454         ibs_init();
455         create_arch_files = ops->create_files;
456         ops->create_files = setup_ibs_files;
457         return 0;
458 }
459
460 static void op_amd_exit(void)
461 {
462         ibs_exit();
463 }
464
465 #else
466
467 /* no IBS support */
468
469 static int op_amd_init(struct oprofile_operations *ops)
470 {
471         return 0;
472 }
473
474 static void op_amd_exit(void) {}
475
476 #endif /* CONFIG_OPROFILE_IBS */
477
478 struct op_x86_model_spec const op_amd_spec = {
479         .num_counters           = NUM_COUNTERS,
480         .num_controls           = NUM_CONTROLS,
481         .reserved               = MSR_AMD_EVENTSEL_RESERVED,
482         .event_mask             = OP_EVENT_MASK,
483         .init                   = op_amd_init,
484         .exit                   = op_amd_exit,
485         .fill_in_addresses      = &op_amd_fill_in_addresses,
486         .setup_ctrs             = &op_amd_setup_ctrs,
487         .check_ctrs             = &op_amd_check_ctrs,
488         .start                  = &op_amd_start,
489         .stop                   = &op_amd_stop,
490         .shutdown               = &op_amd_shutdown,
491 };