4108d02c5292a6c67d9c654f364662248a402988
[linux-2.6.git] / arch / x86 / oprofile / nmi_int.c
1 /**
2  * @file nmi_int.c
3  *
4  * @remark Copyright 2002-2008 OProfile authors
5  * @remark Read the file COPYING
6  *
7  * @author John Levon <levon@movementarian.org>
8  * @author Robert Richter <robert.richter@amd.com>
9  */
10
11 #include <linux/init.h>
12 #include <linux/notifier.h>
13 #include <linux/smp.h>
14 #include <linux/oprofile.h>
15 #include <linux/sysdev.h>
16 #include <linux/slab.h>
17 #include <linux/moduleparam.h>
18 #include <linux/kdebug.h>
19 #include <asm/nmi.h>
20 #include <asm/msr.h>
21 #include <asm/apic.h>
22
23 #include "op_counter.h"
24 #include "op_x86_model.h"
25
26 DEFINE_PER_CPU(int, switch_index);
27
28 static struct op_x86_model_spec const *model;
29 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
30 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
31
32 static int nmi_start(void);
33 static void nmi_stop(void);
34 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs);
35 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs);
36 static void nmi_cpu_stop(void *dummy);
37 static void nmi_cpu_start(void *dummy);
38
39 /* 0 == registered but off, 1 == registered and on */
40 static int nmi_enabled = 0;
41
42 #ifdef CONFIG_PM
43
44 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
45 {
46         if (nmi_enabled == 1)
47                 nmi_stop();
48         return 0;
49 }
50
51 static int nmi_resume(struct sys_device *dev)
52 {
53         if (nmi_enabled == 1)
54                 nmi_start();
55         return 0;
56 }
57
58 static struct sysdev_class oprofile_sysclass = {
59         .name           = "oprofile",
60         .resume         = nmi_resume,
61         .suspend        = nmi_suspend,
62 };
63
64 static struct sys_device device_oprofile = {
65         .id     = 0,
66         .cls    = &oprofile_sysclass,
67 };
68
69 static int __init init_sysfs(void)
70 {
71         int error;
72
73         error = sysdev_class_register(&oprofile_sysclass);
74         if (!error)
75                 error = sysdev_register(&device_oprofile);
76         return error;
77 }
78
79 static void exit_sysfs(void)
80 {
81         sysdev_unregister(&device_oprofile);
82         sysdev_class_unregister(&oprofile_sysclass);
83 }
84
85 #else
86 #define init_sysfs() do { } while (0)
87 #define exit_sysfs() do { } while (0)
88 #endif /* CONFIG_PM */
89
90 static void nmi_cpu_switch(void *dummy)
91 {
92         int cpu = smp_processor_id();
93         int si = per_cpu(switch_index, cpu);
94         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
95
96         nmi_cpu_stop(NULL);
97         nmi_cpu_save_mpx_registers(msrs);
98
99         /* move to next set */
100         si += model->num_hardware_counters;
101         if ((si > model->num_counters) || (counter_config[si].count == 0))
102                 per_cpu(switch_index, smp_processor_id()) = 0;
103         else
104                 per_cpu(switch_index, smp_processor_id()) = si;
105
106         nmi_cpu_restore_mpx_registers(msrs);
107         model->setup_ctrs(msrs);
108         nmi_cpu_start(NULL);
109 }
110
111 /*
112  * Quick check to see if multiplexing is necessary.
113  * The check should be sufficient since counters are used
114  * in ordre.
115  */
116 static int nmi_multiplex_on(void)
117 {
118         return counter_config[model->num_hardware_counters].count ? 0 : -EINVAL;
119 }
120
121 static int nmi_switch_event(void)
122 {
123         if (nmi_multiplex_on() < 0)
124                 return -EINVAL;
125
126         on_each_cpu(nmi_cpu_switch, NULL, 1);
127
128         return 0;
129 }
130
131 static int profile_exceptions_notify(struct notifier_block *self,
132                                      unsigned long val, void *data)
133 {
134         struct die_args *args = (struct die_args *)data;
135         int ret = NOTIFY_DONE;
136         int cpu = smp_processor_id();
137
138         switch (val) {
139         case DIE_NMI:
140                 if (model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu)))
141                         ret = NOTIFY_STOP;
142                 break;
143         default:
144                 break;
145         }
146         return ret;
147 }
148
149 static void nmi_cpu_save_registers(struct op_msrs *msrs)
150 {
151         unsigned int const nr_ctrs = model->num_counters;
152         unsigned int const nr_ctrls = model->num_controls;
153         struct op_msr *counters = msrs->counters;
154         struct op_msr *controls = msrs->controls;
155         unsigned int i;
156
157         for (i = 0; i < nr_ctrs; ++i) {
158                 if (counters[i].addr) {
159                         rdmsr(counters[i].addr,
160                                 counters[i].saved.low,
161                                 counters[i].saved.high);
162                 }
163         }
164
165         for (i = 0; i < nr_ctrls; ++i) {
166                 if (controls[i].addr) {
167                         rdmsr(controls[i].addr,
168                                 controls[i].saved.low,
169                                 controls[i].saved.high);
170                 }
171         }
172 }
173
174 static void nmi_save_registers(void *dummy)
175 {
176         int cpu = smp_processor_id();
177         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
178         nmi_cpu_save_registers(msrs);
179 }
180
181 static void free_msrs(void)
182 {
183         int i;
184         for_each_possible_cpu(i) {
185                 kfree(per_cpu(cpu_msrs, i).counters);
186                 per_cpu(cpu_msrs, i).counters = NULL;
187                 kfree(per_cpu(cpu_msrs, i).controls);
188                 per_cpu(cpu_msrs, i).controls = NULL;
189         }
190 }
191
192 static int allocate_msrs(void)
193 {
194         int i, success = 1;
195         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
196         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
197
198         for_each_possible_cpu(i) {
199                 per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
200                                                                 GFP_KERNEL);
201                 if (!per_cpu(cpu_msrs, i).counters) {
202                         success = 0;
203                         break;
204                 }
205                 per_cpu(cpu_msrs, i).controls =
206                                 kmalloc(controls_size, GFP_KERNEL);
207                 if (!per_cpu(cpu_msrs, i).controls) {
208                         success = 0;
209                         break;
210                 }
211         }
212
213         if (!success)
214                 free_msrs();
215
216         return success;
217 }
218
219 static void nmi_cpu_setup(void *dummy)
220 {
221         int cpu = smp_processor_id();
222         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
223         spin_lock(&oprofilefs_lock);
224         model->setup_ctrs(msrs);
225         spin_unlock(&oprofilefs_lock);
226         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
227         apic_write(APIC_LVTPC, APIC_DM_NMI);
228 }
229
230 static struct notifier_block profile_exceptions_nb = {
231         .notifier_call = profile_exceptions_notify,
232         .next = NULL,
233         .priority = 0
234 };
235
236 static int nmi_setup(void)
237 {
238         int err = 0;
239         int cpu;
240
241         if (!allocate_msrs())
242                 return -ENOMEM;
243
244         err = register_die_notifier(&profile_exceptions_nb);
245         if (err) {
246                 free_msrs();
247                 return err;
248         }
249
250         /*
251          * We need to serialize save and setup for HT because the subset
252          * of msrs are distinct for save and setup operations
253          */
254
255         /* Assume saved/restored counters are the same on all CPUs */
256         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
257         for_each_possible_cpu(cpu) {
258                 if (cpu != 0) {
259                         memcpy(per_cpu(cpu_msrs, cpu).counters,
260                                 per_cpu(cpu_msrs, 0).counters,
261                                 sizeof(struct op_msr) * model->num_counters);
262
263                         memcpy(per_cpu(cpu_msrs, cpu).controls,
264                                 per_cpu(cpu_msrs, 0).controls,
265                                 sizeof(struct op_msr) * model->num_controls);
266                 }
267         }
268         on_each_cpu(nmi_save_registers, NULL, 1);
269         on_each_cpu(nmi_cpu_setup, NULL, 1);
270         nmi_enabled = 1;
271         return 0;
272 }
273
274 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
275 {
276         unsigned int si = __get_cpu_var(switch_index);
277         unsigned int const nr_ctrs = model->num_hardware_counters;
278         struct op_msr *counters = &msrs->counters[si];
279         unsigned int i;
280
281         for (i = 0; i < nr_ctrs; ++i) {
282                 int offset = i + si;
283                 if (counters[offset].addr) {
284                         rdmsr(counters[offset].addr,
285                                 counters[offset].multiplex.low,
286                                 counters[offset].multiplex.high);
287                 }
288         }
289 }
290
291 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
292 {
293         unsigned int si = __get_cpu_var(switch_index);
294         unsigned int const nr_ctrs = model->num_hardware_counters;
295         struct op_msr *counters = &msrs->counters[si];
296         unsigned int i;
297
298         for (i = 0; i < nr_ctrs; ++i) {
299                 int offset = i + si;
300                 if (counters[offset].addr) {
301                         wrmsr(counters[offset].addr,
302                                 counters[offset].multiplex.low,
303                                 counters[offset].multiplex.high);
304                 }
305         }
306 }
307
308 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
309 {
310         unsigned int const nr_ctrs = model->num_counters;
311         unsigned int const nr_ctrls = model->num_controls;
312         struct op_msr *counters = msrs->counters;
313         struct op_msr *controls = msrs->controls;
314         unsigned int i;
315
316         for (i = 0; i < nr_ctrls; ++i) {
317                 if (controls[i].addr) {
318                         wrmsr(controls[i].addr,
319                                 controls[i].saved.low,
320                                 controls[i].saved.high);
321                 }
322         }
323
324         for (i = 0; i < nr_ctrs; ++i) {
325                 if (counters[i].addr) {
326                         wrmsr(counters[i].addr,
327                                 counters[i].saved.low,
328                                 counters[i].saved.high);
329                 }
330         }
331 }
332
333 static void nmi_cpu_shutdown(void *dummy)
334 {
335         unsigned int v;
336         int cpu = smp_processor_id();
337         struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
338
339         /* restoring APIC_LVTPC can trigger an apic error because the delivery
340          * mode and vector nr combination can be illegal. That's by design: on
341          * power on apic lvt contain a zero vector nr which are legal only for
342          * NMI delivery mode. So inhibit apic err before restoring lvtpc
343          */
344         v = apic_read(APIC_LVTERR);
345         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
346         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
347         apic_write(APIC_LVTERR, v);
348         nmi_cpu_restore_registers(msrs);
349         __get_cpu_var(switch_index) = 0;
350 }
351
352 static void nmi_shutdown(void)
353 {
354         struct op_msrs *msrs = &get_cpu_var(cpu_msrs);
355         nmi_enabled = 0;
356         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
357         unregister_die_notifier(&profile_exceptions_nb);
358         model->shutdown(msrs);
359         free_msrs();
360         put_cpu_var(cpu_msrs);
361 }
362
363 static void nmi_cpu_start(void *dummy)
364 {
365         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
366         model->start(msrs);
367 }
368
369 static int nmi_start(void)
370 {
371         on_each_cpu(nmi_cpu_start, NULL, 1);
372         return 0;
373 }
374
375 static void nmi_cpu_stop(void *dummy)
376 {
377         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
378         model->stop(msrs);
379 }
380
381 static void nmi_stop(void)
382 {
383         on_each_cpu(nmi_cpu_stop, NULL, 1);
384 }
385
386 struct op_counter_config counter_config[OP_MAX_COUNTER];
387
388 static int nmi_create_files(struct super_block *sb, struct dentry *root)
389 {
390         unsigned int i;
391
392         for (i = 0; i < model->num_counters; ++i) {
393                 struct dentry *dir;
394                 char buf[4];
395
396                 /* quick little hack to _not_ expose a counter if it is not
397                  * available for use.  This should protect userspace app.
398                  * NOTE:  assumes 1:1 mapping here (that counters are organized
399                  *        sequentially in their struct assignment).
400                  */
401                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
402                         continue;
403
404                 snprintf(buf,  sizeof(buf), "%d", i);
405                 dir = oprofilefs_mkdir(sb, root, buf);
406                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
407                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
408                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
409                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
410                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
411                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
412                 counter_config[i].save_count_low = 0;
413         }
414
415         return 0;
416 }
417
418 static int p4force;
419 module_param(p4force, int, 0);
420
421 static int __init p4_init(char **cpu_type)
422 {
423         __u8 cpu_model = boot_cpu_data.x86_model;
424
425         if (!p4force && (cpu_model > 6 || cpu_model == 5))
426                 return 0;
427
428 #ifndef CONFIG_SMP
429         *cpu_type = "i386/p4";
430         model = &op_p4_spec;
431         return 1;
432 #else
433         switch (smp_num_siblings) {
434         case 1:
435                 *cpu_type = "i386/p4";
436                 model = &op_p4_spec;
437                 return 1;
438
439         case 2:
440                 *cpu_type = "i386/p4-ht";
441                 model = &op_p4_ht2_spec;
442                 return 1;
443         }
444 #endif
445
446         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
447         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
448         return 0;
449 }
450
451 static int __init ppro_init(char **cpu_type)
452 {
453         __u8 cpu_model = boot_cpu_data.x86_model;
454
455         switch (cpu_model) {
456         case 0 ... 2:
457                 *cpu_type = "i386/ppro";
458                 break;
459         case 3 ... 5:
460                 *cpu_type = "i386/pii";
461                 break;
462         case 6 ... 8:
463                 *cpu_type = "i386/piii";
464                 break;
465         case 9:
466                 *cpu_type = "i386/p6_mobile";
467                 break;
468         case 10 ... 13:
469                 *cpu_type = "i386/p6";
470                 break;
471         case 14:
472                 *cpu_type = "i386/core";
473                 break;
474         case 15: case 23:
475                 *cpu_type = "i386/core_2";
476                 break;
477         case 26:
478                 *cpu_type = "i386/core_2";
479                 break;
480         default:
481                 /* Unknown */
482                 return 0;
483         }
484
485         model = &op_ppro_spec;
486         return 1;
487 }
488
489 /* in order to get sysfs right */
490 static int using_nmi;
491
492 int __init op_nmi_init(struct oprofile_operations *ops)
493 {
494         __u8 vendor = boot_cpu_data.x86_vendor;
495         __u8 family = boot_cpu_data.x86;
496         char *cpu_type;
497         int ret = 0;
498
499         if (!cpu_has_apic)
500                 return -ENODEV;
501
502         switch (vendor) {
503         case X86_VENDOR_AMD:
504                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
505
506                 switch (family) {
507                 default:
508                         return -ENODEV;
509                 case 6:
510                         model = &op_amd_spec;
511                         cpu_type = "i386/athlon";
512                         break;
513                 case 0xf:
514                         model = &op_amd_spec;
515                         /* Actually it could be i386/hammer too, but give
516                          user space an consistent name. */
517                         cpu_type = "x86-64/hammer";
518                         break;
519                 case 0x10:
520                         model = &op_amd_spec;
521                         cpu_type = "x86-64/family10";
522                         break;
523                 case 0x11:
524                         model = &op_amd_spec;
525                         cpu_type = "x86-64/family11h";
526                         break;
527                 }
528                 break;
529
530         case X86_VENDOR_INTEL:
531                 switch (family) {
532                         /* Pentium IV */
533                 case 0xf:
534                         if (!p4_init(&cpu_type))
535                                 return -ENODEV;
536                         break;
537
538                         /* A P6-class processor */
539                 case 6:
540                         if (!ppro_init(&cpu_type))
541                                 return -ENODEV;
542                         break;
543
544                 default:
545                         return -ENODEV;
546                 }
547                 break;
548
549         default:
550                 return -ENODEV;
551         }
552
553         /* default values, can be overwritten by model */
554         __raw_get_cpu_var(switch_index) = 0;
555         ops->create_files = nmi_create_files;
556         ops->setup = nmi_setup;
557         ops->shutdown = nmi_shutdown;
558         ops->start = nmi_start;
559         ops->stop = nmi_stop;
560         ops->cpu_type = cpu_type;
561         ops->switch_events = nmi_switch_event;
562
563         if (model->init)
564                 ret = model->init(ops);
565         if (ret)
566                 return ret;
567
568         init_sysfs();
569         using_nmi = 1;
570         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
571         return 0;
572 }
573
574 void op_nmi_exit(void)
575 {
576         if (using_nmi)
577                 exit_sysfs();
578         if (model->exit)
579                 model->exit();
580 }