f5b49c7fc89d00e21dae8ee446194b24c66fda72
[linux-2.6.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9  *
10  * Authors:
11  *   Avi Kivity   <avi@qumranet.com>
12  *   Yaniv Kamay  <yaniv@qumranet.com>
13  *
14  * This work is licensed under the terms of the GNU GPL, version 2.  See
15  * the COPYING file in the top-level directory.
16  *
17  */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
48
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
51
52 static int __read_mostly bypass_guest_pf = 1;
53 module_param(bypass_guest_pf, bool, S_IRUGO);
54
55 static int __read_mostly enable_vpid = 1;
56 module_param_named(vpid, enable_vpid, bool, 0444);
57
58 static int __read_mostly flexpriority_enabled = 1;
59 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
60
61 static int __read_mostly enable_ept = 1;
62 module_param_named(ept, enable_ept, bool, S_IRUGO);
63
64 static int __read_mostly enable_unrestricted_guest = 1;
65 module_param_named(unrestricted_guest,
66                         enable_unrestricted_guest, bool, S_IRUGO);
67
68 static int __read_mostly emulate_invalid_guest_state = 0;
69 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
70
71 static int __read_mostly vmm_exclusive = 1;
72 module_param(vmm_exclusive, bool, S_IRUGO);
73
74 static int __read_mostly yield_on_hlt = 1;
75 module_param(yield_on_hlt, bool, S_IRUGO);
76
77 /*
78  * If nested=1, nested virtualization is supported, i.e., guests may use
79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80  * use VMX instructions.
81  */
82 static int __read_mostly nested = 0;
83 module_param(nested, bool, S_IRUGO);
84
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK                                              \
88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
90         (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON                                            \
92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
95          | X86_CR4_OSXMMEXCPT)
96
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
102 /*
103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104  * ple_gap:    upper bound on the amount of time between two successive
105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
106  *             According to test, this time is usually smaller than 128 cycles.
107  * ple_window: upper bound on the amount of time a guest is allowed to execute
108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
109  *             less than 2^12 cycles
110  * Time is measured based on a counter that runs at the same rate as the TSC,
111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
112  */
113 #define KVM_VMX_DEFAULT_PLE_GAP    128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116 module_param(ple_gap, int, S_IRUGO);
117
118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119 module_param(ple_window, int, S_IRUGO);
120
121 #define NR_AUTOLOAD_MSRS 1
122 #define VMCS02_POOL_SIZE 1
123
124 struct vmcs {
125         u32 revision_id;
126         u32 abort;
127         char data[0];
128 };
129
130 /*
131  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133  * loaded on this CPU (so we can clear them if the CPU goes down).
134  */
135 struct loaded_vmcs {
136         struct vmcs *vmcs;
137         int cpu;
138         int launched;
139         struct list_head loaded_vmcss_on_cpu_link;
140 };
141
142 struct shared_msr_entry {
143         unsigned index;
144         u64 data;
145         u64 mask;
146 };
147
148 /*
149  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154  * More than one of these structures may exist, if L1 runs multiple L2 guests.
155  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156  * underlying hardware which will be used to run L2.
157  * This structure is packed to ensure that its layout is identical across
158  * machines (necessary for live migration).
159  * If there are changes in this struct, VMCS12_REVISION must be changed.
160  */
161 typedef u64 natural_width;
162 struct __packed vmcs12 {
163         /* According to the Intel spec, a VMCS region must start with the
164          * following two fields. Then follow implementation-specific data.
165          */
166         u32 revision_id;
167         u32 abort;
168
169         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170         u32 padding[7]; /* room for future expansion */
171
172         u64 io_bitmap_a;
173         u64 io_bitmap_b;
174         u64 msr_bitmap;
175         u64 vm_exit_msr_store_addr;
176         u64 vm_exit_msr_load_addr;
177         u64 vm_entry_msr_load_addr;
178         u64 tsc_offset;
179         u64 virtual_apic_page_addr;
180         u64 apic_access_addr;
181         u64 ept_pointer;
182         u64 guest_physical_address;
183         u64 vmcs_link_pointer;
184         u64 guest_ia32_debugctl;
185         u64 guest_ia32_pat;
186         u64 guest_ia32_efer;
187         u64 guest_ia32_perf_global_ctrl;
188         u64 guest_pdptr0;
189         u64 guest_pdptr1;
190         u64 guest_pdptr2;
191         u64 guest_pdptr3;
192         u64 host_ia32_pat;
193         u64 host_ia32_efer;
194         u64 host_ia32_perf_global_ctrl;
195         u64 padding64[8]; /* room for future expansion */
196         /*
197          * To allow migration of L1 (complete with its L2 guests) between
198          * machines of different natural widths (32 or 64 bit), we cannot have
199          * unsigned long fields with no explict size. We use u64 (aliased
200          * natural_width) instead. Luckily, x86 is little-endian.
201          */
202         natural_width cr0_guest_host_mask;
203         natural_width cr4_guest_host_mask;
204         natural_width cr0_read_shadow;
205         natural_width cr4_read_shadow;
206         natural_width cr3_target_value0;
207         natural_width cr3_target_value1;
208         natural_width cr3_target_value2;
209         natural_width cr3_target_value3;
210         natural_width exit_qualification;
211         natural_width guest_linear_address;
212         natural_width guest_cr0;
213         natural_width guest_cr3;
214         natural_width guest_cr4;
215         natural_width guest_es_base;
216         natural_width guest_cs_base;
217         natural_width guest_ss_base;
218         natural_width guest_ds_base;
219         natural_width guest_fs_base;
220         natural_width guest_gs_base;
221         natural_width guest_ldtr_base;
222         natural_width guest_tr_base;
223         natural_width guest_gdtr_base;
224         natural_width guest_idtr_base;
225         natural_width guest_dr7;
226         natural_width guest_rsp;
227         natural_width guest_rip;
228         natural_width guest_rflags;
229         natural_width guest_pending_dbg_exceptions;
230         natural_width guest_sysenter_esp;
231         natural_width guest_sysenter_eip;
232         natural_width host_cr0;
233         natural_width host_cr3;
234         natural_width host_cr4;
235         natural_width host_fs_base;
236         natural_width host_gs_base;
237         natural_width host_tr_base;
238         natural_width host_gdtr_base;
239         natural_width host_idtr_base;
240         natural_width host_ia32_sysenter_esp;
241         natural_width host_ia32_sysenter_eip;
242         natural_width host_rsp;
243         natural_width host_rip;
244         natural_width paddingl[8]; /* room for future expansion */
245         u32 pin_based_vm_exec_control;
246         u32 cpu_based_vm_exec_control;
247         u32 exception_bitmap;
248         u32 page_fault_error_code_mask;
249         u32 page_fault_error_code_match;
250         u32 cr3_target_count;
251         u32 vm_exit_controls;
252         u32 vm_exit_msr_store_count;
253         u32 vm_exit_msr_load_count;
254         u32 vm_entry_controls;
255         u32 vm_entry_msr_load_count;
256         u32 vm_entry_intr_info_field;
257         u32 vm_entry_exception_error_code;
258         u32 vm_entry_instruction_len;
259         u32 tpr_threshold;
260         u32 secondary_vm_exec_control;
261         u32 vm_instruction_error;
262         u32 vm_exit_reason;
263         u32 vm_exit_intr_info;
264         u32 vm_exit_intr_error_code;
265         u32 idt_vectoring_info_field;
266         u32 idt_vectoring_error_code;
267         u32 vm_exit_instruction_len;
268         u32 vmx_instruction_info;
269         u32 guest_es_limit;
270         u32 guest_cs_limit;
271         u32 guest_ss_limit;
272         u32 guest_ds_limit;
273         u32 guest_fs_limit;
274         u32 guest_gs_limit;
275         u32 guest_ldtr_limit;
276         u32 guest_tr_limit;
277         u32 guest_gdtr_limit;
278         u32 guest_idtr_limit;
279         u32 guest_es_ar_bytes;
280         u32 guest_cs_ar_bytes;
281         u32 guest_ss_ar_bytes;
282         u32 guest_ds_ar_bytes;
283         u32 guest_fs_ar_bytes;
284         u32 guest_gs_ar_bytes;
285         u32 guest_ldtr_ar_bytes;
286         u32 guest_tr_ar_bytes;
287         u32 guest_interruptibility_info;
288         u32 guest_activity_state;
289         u32 guest_sysenter_cs;
290         u32 host_ia32_sysenter_cs;
291         u32 padding32[8]; /* room for future expansion */
292         u16 virtual_processor_id;
293         u16 guest_es_selector;
294         u16 guest_cs_selector;
295         u16 guest_ss_selector;
296         u16 guest_ds_selector;
297         u16 guest_fs_selector;
298         u16 guest_gs_selector;
299         u16 guest_ldtr_selector;
300         u16 guest_tr_selector;
301         u16 host_es_selector;
302         u16 host_cs_selector;
303         u16 host_ss_selector;
304         u16 host_ds_selector;
305         u16 host_fs_selector;
306         u16 host_gs_selector;
307         u16 host_tr_selector;
308 };
309
310 /*
311  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314  */
315 #define VMCS12_REVISION 0x11e57ed0
316
317 /*
318  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320  * current implementation, 4K are reserved to avoid future complications.
321  */
322 #define VMCS12_SIZE 0x1000
323
324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
325 struct vmcs02_list {
326         struct list_head list;
327         gpa_t vmptr;
328         struct loaded_vmcs vmcs02;
329 };
330
331 /*
332  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
334  */
335 struct nested_vmx {
336         /* Has the level1 guest done vmxon? */
337         bool vmxon;
338
339         /* The guest-physical address of the current VMCS L1 keeps for L2 */
340         gpa_t current_vmptr;
341         /* The host-usable pointer to the above */
342         struct page *current_vmcs12_page;
343         struct vmcs12 *current_vmcs12;
344
345         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346         struct list_head vmcs02_pool;
347         int vmcs02_num;
348         u64 vmcs01_tsc_offset;
349         /* L2 must run next, and mustn't decide to exit to L1. */
350         bool nested_run_pending;
351         /*
352          * Guest pages referred to in vmcs02 with host-physical pointers, so
353          * we must keep them pinned while L2 runs.
354          */
355         struct page *apic_access_page;
356 };
357
358 struct vcpu_vmx {
359         struct kvm_vcpu       vcpu;
360         unsigned long         host_rsp;
361         u8                    fail;
362         u8                    cpl;
363         bool                  nmi_known_unmasked;
364         u32                   exit_intr_info;
365         u32                   idt_vectoring_info;
366         ulong                 rflags;
367         struct shared_msr_entry *guest_msrs;
368         int                   nmsrs;
369         int                   save_nmsrs;
370 #ifdef CONFIG_X86_64
371         u64                   msr_host_kernel_gs_base;
372         u64                   msr_guest_kernel_gs_base;
373 #endif
374         /*
375          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376          * non-nested (L1) guest, it always points to vmcs01. For a nested
377          * guest (L2), it points to a different VMCS.
378          */
379         struct loaded_vmcs    vmcs01;
380         struct loaded_vmcs   *loaded_vmcs;
381         bool                  __launched; /* temporary, used in vmx_vcpu_run */
382         struct msr_autoload {
383                 unsigned nr;
384                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
385                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
386         } msr_autoload;
387         struct {
388                 int           loaded;
389                 u16           fs_sel, gs_sel, ldt_sel;
390                 int           gs_ldt_reload_needed;
391                 int           fs_reload_needed;
392         } host_state;
393         struct {
394                 int vm86_active;
395                 ulong save_rflags;
396                 struct kvm_save_segment {
397                         u16 selector;
398                         unsigned long base;
399                         u32 limit;
400                         u32 ar;
401                 } tr, es, ds, fs, gs;
402         } rmode;
403         struct {
404                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
405                 struct kvm_save_segment seg[8];
406         } segment_cache;
407         int vpid;
408         bool emulation_required;
409
410         /* Support for vnmi-less CPUs */
411         int soft_vnmi_blocked;
412         ktime_t entry_time;
413         s64 vnmi_blocked_time;
414         u32 exit_reason;
415
416         bool rdtscp_enabled;
417
418         /* Support for a guest hypervisor (nested VMX) */
419         struct nested_vmx nested;
420 };
421
422 enum segment_cache_field {
423         SEG_FIELD_SEL = 0,
424         SEG_FIELD_BASE = 1,
425         SEG_FIELD_LIMIT = 2,
426         SEG_FIELD_AR = 3,
427
428         SEG_FIELD_NR = 4
429 };
430
431 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
432 {
433         return container_of(vcpu, struct vcpu_vmx, vcpu);
434 }
435
436 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
438 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
439                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
440
441 static unsigned short vmcs_field_to_offset_table[] = {
442         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
443         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
444         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
445         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
446         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
447         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
448         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
449         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
450         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
451         FIELD(HOST_ES_SELECTOR, host_es_selector),
452         FIELD(HOST_CS_SELECTOR, host_cs_selector),
453         FIELD(HOST_SS_SELECTOR, host_ss_selector),
454         FIELD(HOST_DS_SELECTOR, host_ds_selector),
455         FIELD(HOST_FS_SELECTOR, host_fs_selector),
456         FIELD(HOST_GS_SELECTOR, host_gs_selector),
457         FIELD(HOST_TR_SELECTOR, host_tr_selector),
458         FIELD64(IO_BITMAP_A, io_bitmap_a),
459         FIELD64(IO_BITMAP_B, io_bitmap_b),
460         FIELD64(MSR_BITMAP, msr_bitmap),
461         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
462         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
463         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
464         FIELD64(TSC_OFFSET, tsc_offset),
465         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
466         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
467         FIELD64(EPT_POINTER, ept_pointer),
468         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
469         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
470         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
471         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
472         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
473         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
474         FIELD64(GUEST_PDPTR0, guest_pdptr0),
475         FIELD64(GUEST_PDPTR1, guest_pdptr1),
476         FIELD64(GUEST_PDPTR2, guest_pdptr2),
477         FIELD64(GUEST_PDPTR3, guest_pdptr3),
478         FIELD64(HOST_IA32_PAT, host_ia32_pat),
479         FIELD64(HOST_IA32_EFER, host_ia32_efer),
480         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
481         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
482         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
483         FIELD(EXCEPTION_BITMAP, exception_bitmap),
484         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
485         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
486         FIELD(CR3_TARGET_COUNT, cr3_target_count),
487         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
488         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
489         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
490         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
491         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
492         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
493         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
494         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
495         FIELD(TPR_THRESHOLD, tpr_threshold),
496         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
497         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
498         FIELD(VM_EXIT_REASON, vm_exit_reason),
499         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
500         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
501         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
502         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
503         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
504         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
505         FIELD(GUEST_ES_LIMIT, guest_es_limit),
506         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
507         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
508         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
509         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
510         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
511         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
512         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
513         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
514         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
515         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
516         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
517         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
518         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
519         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
520         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
521         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
522         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
523         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
524         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
525         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
526         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
527         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
528         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
529         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
530         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
531         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
532         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
533         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
534         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
535         FIELD(EXIT_QUALIFICATION, exit_qualification),
536         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
537         FIELD(GUEST_CR0, guest_cr0),
538         FIELD(GUEST_CR3, guest_cr3),
539         FIELD(GUEST_CR4, guest_cr4),
540         FIELD(GUEST_ES_BASE, guest_es_base),
541         FIELD(GUEST_CS_BASE, guest_cs_base),
542         FIELD(GUEST_SS_BASE, guest_ss_base),
543         FIELD(GUEST_DS_BASE, guest_ds_base),
544         FIELD(GUEST_FS_BASE, guest_fs_base),
545         FIELD(GUEST_GS_BASE, guest_gs_base),
546         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
547         FIELD(GUEST_TR_BASE, guest_tr_base),
548         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
549         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
550         FIELD(GUEST_DR7, guest_dr7),
551         FIELD(GUEST_RSP, guest_rsp),
552         FIELD(GUEST_RIP, guest_rip),
553         FIELD(GUEST_RFLAGS, guest_rflags),
554         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
555         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
556         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
557         FIELD(HOST_CR0, host_cr0),
558         FIELD(HOST_CR3, host_cr3),
559         FIELD(HOST_CR4, host_cr4),
560         FIELD(HOST_FS_BASE, host_fs_base),
561         FIELD(HOST_GS_BASE, host_gs_base),
562         FIELD(HOST_TR_BASE, host_tr_base),
563         FIELD(HOST_GDTR_BASE, host_gdtr_base),
564         FIELD(HOST_IDTR_BASE, host_idtr_base),
565         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
566         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
567         FIELD(HOST_RSP, host_rsp),
568         FIELD(HOST_RIP, host_rip),
569 };
570 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
571
572 static inline short vmcs_field_to_offset(unsigned long field)
573 {
574         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
575                 return -1;
576         return vmcs_field_to_offset_table[field];
577 }
578
579 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
580 {
581         return to_vmx(vcpu)->nested.current_vmcs12;
582 }
583
584 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
585 {
586         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
587         if (is_error_page(page)) {
588                 kvm_release_page_clean(page);
589                 return NULL;
590         }
591         return page;
592 }
593
594 static void nested_release_page(struct page *page)
595 {
596         kvm_release_page_dirty(page);
597 }
598
599 static void nested_release_page_clean(struct page *page)
600 {
601         kvm_release_page_clean(page);
602 }
603
604 static u64 construct_eptp(unsigned long root_hpa);
605 static void kvm_cpu_vmxon(u64 addr);
606 static void kvm_cpu_vmxoff(void);
607 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
608 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
609
610 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
611 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
612 /*
613  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
615  */
616 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
617 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
618
619 static unsigned long *vmx_io_bitmap_a;
620 static unsigned long *vmx_io_bitmap_b;
621 static unsigned long *vmx_msr_bitmap_legacy;
622 static unsigned long *vmx_msr_bitmap_longmode;
623
624 static bool cpu_has_load_ia32_efer;
625
626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
627 static DEFINE_SPINLOCK(vmx_vpid_lock);
628
629 static struct vmcs_config {
630         int size;
631         int order;
632         u32 revision_id;
633         u32 pin_based_exec_ctrl;
634         u32 cpu_based_exec_ctrl;
635         u32 cpu_based_2nd_exec_ctrl;
636         u32 vmexit_ctrl;
637         u32 vmentry_ctrl;
638 } vmcs_config;
639
640 static struct vmx_capability {
641         u32 ept;
642         u32 vpid;
643 } vmx_capability;
644
645 #define VMX_SEGMENT_FIELD(seg)                                  \
646         [VCPU_SREG_##seg] = {                                   \
647                 .selector = GUEST_##seg##_SELECTOR,             \
648                 .base = GUEST_##seg##_BASE,                     \
649                 .limit = GUEST_##seg##_LIMIT,                   \
650                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
651         }
652
653 static struct kvm_vmx_segment_field {
654         unsigned selector;
655         unsigned base;
656         unsigned limit;
657         unsigned ar_bytes;
658 } kvm_vmx_segment_fields[] = {
659         VMX_SEGMENT_FIELD(CS),
660         VMX_SEGMENT_FIELD(DS),
661         VMX_SEGMENT_FIELD(ES),
662         VMX_SEGMENT_FIELD(FS),
663         VMX_SEGMENT_FIELD(GS),
664         VMX_SEGMENT_FIELD(SS),
665         VMX_SEGMENT_FIELD(TR),
666         VMX_SEGMENT_FIELD(LDTR),
667 };
668
669 static u64 host_efer;
670
671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
672
673 /*
674  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
675  * away by decrementing the array size.
676  */
677 static const u32 vmx_msr_index[] = {
678 #ifdef CONFIG_X86_64
679         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
680 #endif
681         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
682 };
683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
684
685 static inline bool is_page_fault(u32 intr_info)
686 {
687         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
688                              INTR_INFO_VALID_MASK)) ==
689                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
690 }
691
692 static inline bool is_no_device(u32 intr_info)
693 {
694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
695                              INTR_INFO_VALID_MASK)) ==
696                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
697 }
698
699 static inline bool is_invalid_opcode(u32 intr_info)
700 {
701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
702                              INTR_INFO_VALID_MASK)) ==
703                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
704 }
705
706 static inline bool is_external_interrupt(u32 intr_info)
707 {
708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
709                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
710 }
711
712 static inline bool is_machine_check(u32 intr_info)
713 {
714         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715                              INTR_INFO_VALID_MASK)) ==
716                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
717 }
718
719 static inline bool cpu_has_vmx_msr_bitmap(void)
720 {
721         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
722 }
723
724 static inline bool cpu_has_vmx_tpr_shadow(void)
725 {
726         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
727 }
728
729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
730 {
731         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
732 }
733
734 static inline bool cpu_has_secondary_exec_ctrls(void)
735 {
736         return vmcs_config.cpu_based_exec_ctrl &
737                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
738 }
739
740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
741 {
742         return vmcs_config.cpu_based_2nd_exec_ctrl &
743                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
744 }
745
746 static inline bool cpu_has_vmx_flexpriority(void)
747 {
748         return cpu_has_vmx_tpr_shadow() &&
749                 cpu_has_vmx_virtualize_apic_accesses();
750 }
751
752 static inline bool cpu_has_vmx_ept_execute_only(void)
753 {
754         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
755 }
756
757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
758 {
759         return vmx_capability.ept & VMX_EPTP_UC_BIT;
760 }
761
762 static inline bool cpu_has_vmx_eptp_writeback(void)
763 {
764         return vmx_capability.ept & VMX_EPTP_WB_BIT;
765 }
766
767 static inline bool cpu_has_vmx_ept_2m_page(void)
768 {
769         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
770 }
771
772 static inline bool cpu_has_vmx_ept_1g_page(void)
773 {
774         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
775 }
776
777 static inline bool cpu_has_vmx_ept_4levels(void)
778 {
779         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
780 }
781
782 static inline bool cpu_has_vmx_invept_individual_addr(void)
783 {
784         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
785 }
786
787 static inline bool cpu_has_vmx_invept_context(void)
788 {
789         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
790 }
791
792 static inline bool cpu_has_vmx_invept_global(void)
793 {
794         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
795 }
796
797 static inline bool cpu_has_vmx_invvpid_single(void)
798 {
799         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
800 }
801
802 static inline bool cpu_has_vmx_invvpid_global(void)
803 {
804         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
805 }
806
807 static inline bool cpu_has_vmx_ept(void)
808 {
809         return vmcs_config.cpu_based_2nd_exec_ctrl &
810                 SECONDARY_EXEC_ENABLE_EPT;
811 }
812
813 static inline bool cpu_has_vmx_unrestricted_guest(void)
814 {
815         return vmcs_config.cpu_based_2nd_exec_ctrl &
816                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
817 }
818
819 static inline bool cpu_has_vmx_ple(void)
820 {
821         return vmcs_config.cpu_based_2nd_exec_ctrl &
822                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
823 }
824
825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
826 {
827         return flexpriority_enabled && irqchip_in_kernel(kvm);
828 }
829
830 static inline bool cpu_has_vmx_vpid(void)
831 {
832         return vmcs_config.cpu_based_2nd_exec_ctrl &
833                 SECONDARY_EXEC_ENABLE_VPID;
834 }
835
836 static inline bool cpu_has_vmx_rdtscp(void)
837 {
838         return vmcs_config.cpu_based_2nd_exec_ctrl &
839                 SECONDARY_EXEC_RDTSCP;
840 }
841
842 static inline bool cpu_has_virtual_nmis(void)
843 {
844         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
845 }
846
847 static inline bool cpu_has_vmx_wbinvd_exit(void)
848 {
849         return vmcs_config.cpu_based_2nd_exec_ctrl &
850                 SECONDARY_EXEC_WBINVD_EXITING;
851 }
852
853 static inline bool report_flexpriority(void)
854 {
855         return flexpriority_enabled;
856 }
857
858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
859 {
860         return vmcs12->cpu_based_vm_exec_control & bit;
861 }
862
863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
864 {
865         return (vmcs12->cpu_based_vm_exec_control &
866                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
867                 (vmcs12->secondary_vm_exec_control & bit);
868 }
869
870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
871         struct kvm_vcpu *vcpu)
872 {
873         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
874 }
875
876 static inline bool is_exception(u32 intr_info)
877 {
878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
880 }
881
882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
884                         struct vmcs12 *vmcs12,
885                         u32 reason, unsigned long qualification);
886
887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
888 {
889         int i;
890
891         for (i = 0; i < vmx->nmsrs; ++i)
892                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
893                         return i;
894         return -1;
895 }
896
897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
898 {
899     struct {
900         u64 vpid : 16;
901         u64 rsvd : 48;
902         u64 gva;
903     } operand = { vpid, 0, gva };
904
905     asm volatile (__ex(ASM_VMX_INVVPID)
906                   /* CF==1 or ZF==1 --> rc = -1 */
907                   "; ja 1f ; ud2 ; 1:"
908                   : : "a"(&operand), "c"(ext) : "cc", "memory");
909 }
910
911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
912 {
913         struct {
914                 u64 eptp, gpa;
915         } operand = {eptp, gpa};
916
917         asm volatile (__ex(ASM_VMX_INVEPT)
918                         /* CF==1 or ZF==1 --> rc = -1 */
919                         "; ja 1f ; ud2 ; 1:\n"
920                         : : "a" (&operand), "c" (ext) : "cc", "memory");
921 }
922
923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
924 {
925         int i;
926
927         i = __find_msr_index(vmx, msr);
928         if (i >= 0)
929                 return &vmx->guest_msrs[i];
930         return NULL;
931 }
932
933 static void vmcs_clear(struct vmcs *vmcs)
934 {
935         u64 phys_addr = __pa(vmcs);
936         u8 error;
937
938         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
939                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
940                       : "cc", "memory");
941         if (error)
942                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
943                        vmcs, phys_addr);
944 }
945
946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
947 {
948         vmcs_clear(loaded_vmcs->vmcs);
949         loaded_vmcs->cpu = -1;
950         loaded_vmcs->launched = 0;
951 }
952
953 static void vmcs_load(struct vmcs *vmcs)
954 {
955         u64 phys_addr = __pa(vmcs);
956         u8 error;
957
958         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
959                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
960                         : "cc", "memory");
961         if (error)
962                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
963                        vmcs, phys_addr);
964 }
965
966 static void __loaded_vmcs_clear(void *arg)
967 {
968         struct loaded_vmcs *loaded_vmcs = arg;
969         int cpu = raw_smp_processor_id();
970
971         if (loaded_vmcs->cpu != cpu)
972                 return; /* vcpu migration can race with cpu offline */
973         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
974                 per_cpu(current_vmcs, cpu) = NULL;
975         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
976         loaded_vmcs_init(loaded_vmcs);
977 }
978
979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
980 {
981         if (loaded_vmcs->cpu != -1)
982                 smp_call_function_single(
983                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
984 }
985
986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
987 {
988         if (vmx->vpid == 0)
989                 return;
990
991         if (cpu_has_vmx_invvpid_single())
992                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
993 }
994
995 static inline void vpid_sync_vcpu_global(void)
996 {
997         if (cpu_has_vmx_invvpid_global())
998                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
999 }
1000
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002 {
1003         if (cpu_has_vmx_invvpid_single())
1004                 vpid_sync_vcpu_single(vmx);
1005         else
1006                 vpid_sync_vcpu_global();
1007 }
1008
1009 static inline void ept_sync_global(void)
1010 {
1011         if (cpu_has_vmx_invept_global())
1012                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013 }
1014
1015 static inline void ept_sync_context(u64 eptp)
1016 {
1017         if (enable_ept) {
1018                 if (cpu_has_vmx_invept_context())
1019                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020                 else
1021                         ept_sync_global();
1022         }
1023 }
1024
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026 {
1027         if (enable_ept) {
1028                 if (cpu_has_vmx_invept_individual_addr())
1029                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030                                         eptp, gpa);
1031                 else
1032                         ept_sync_context(eptp);
1033         }
1034 }
1035
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1037 {
1038         unsigned long value;
1039
1040         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041                       : "=a"(value) : "d"(field) : "cc");
1042         return value;
1043 }
1044
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1046 {
1047         return vmcs_readl(field);
1048 }
1049
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1051 {
1052         return vmcs_readl(field);
1053 }
1054
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1056 {
1057 #ifdef CONFIG_X86_64
1058         return vmcs_readl(field);
1059 #else
1060         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061 #endif
1062 }
1063
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065 {
1066         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068         dump_stack();
1069 }
1070
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1072 {
1073         u8 error;
1074
1075         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1077         if (unlikely(error))
1078                 vmwrite_error(field, value);
1079 }
1080
1081 static void vmcs_write16(unsigned long field, u16 value)
1082 {
1083         vmcs_writel(field, value);
1084 }
1085
1086 static void vmcs_write32(unsigned long field, u32 value)
1087 {
1088         vmcs_writel(field, value);
1089 }
1090
1091 static void vmcs_write64(unsigned long field, u64 value)
1092 {
1093         vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1095         asm volatile ("");
1096         vmcs_writel(field+1, value >> 32);
1097 #endif
1098 }
1099
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1101 {
1102         vmcs_writel(field, vmcs_readl(field) & ~mask);
1103 }
1104
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1106 {
1107         vmcs_writel(field, vmcs_readl(field) | mask);
1108 }
1109
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111 {
1112         vmx->segment_cache.bitmask = 0;
1113 }
1114
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116                                        unsigned field)
1117 {
1118         bool ret;
1119         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123                 vmx->segment_cache.bitmask = 0;
1124         }
1125         ret = vmx->segment_cache.bitmask & mask;
1126         vmx->segment_cache.bitmask |= mask;
1127         return ret;
1128 }
1129
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131 {
1132         u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136         return *p;
1137 }
1138
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140 {
1141         ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145         return *p;
1146 }
1147
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149 {
1150         u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154         return *p;
1155 }
1156
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163         return *p;
1164 }
1165
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167 {
1168         u32 eb;
1169
1170         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172         if ((vcpu->guest_debug &
1173              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175                 eb |= 1u << BP_VECTOR;
1176         if (to_vmx(vcpu)->rmode.vm86_active)
1177                 eb = ~0;
1178         if (enable_ept)
1179                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180         if (vcpu->fpu_active)
1181                 eb &= ~(1u << NM_VECTOR);
1182
1183         /* When we are running a nested L2 guest and L1 specified for it a
1184          * certain exception bitmap, we must trap the same exceptions and pass
1185          * them to L1. When running L2, we will only handle the exceptions
1186          * specified above if L1 did not want them.
1187          */
1188         if (is_guest_mode(vcpu))
1189                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1190
1191         vmcs_write32(EXCEPTION_BITMAP, eb);
1192 }
1193
1194 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1195 {
1196         unsigned i;
1197         struct msr_autoload *m = &vmx->msr_autoload;
1198
1199         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1200                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1201                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1202                 return;
1203         }
1204
1205         for (i = 0; i < m->nr; ++i)
1206                 if (m->guest[i].index == msr)
1207                         break;
1208
1209         if (i == m->nr)
1210                 return;
1211         --m->nr;
1212         m->guest[i] = m->guest[m->nr];
1213         m->host[i] = m->host[m->nr];
1214         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1215         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1216 }
1217
1218 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1219                                   u64 guest_val, u64 host_val)
1220 {
1221         unsigned i;
1222         struct msr_autoload *m = &vmx->msr_autoload;
1223
1224         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1225                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1226                 vmcs_write64(HOST_IA32_EFER, host_val);
1227                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1228                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1229                 return;
1230         }
1231
1232         for (i = 0; i < m->nr; ++i)
1233                 if (m->guest[i].index == msr)
1234                         break;
1235
1236         if (i == m->nr) {
1237                 ++m->nr;
1238                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1239                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1240         }
1241
1242         m->guest[i].index = msr;
1243         m->guest[i].value = guest_val;
1244         m->host[i].index = msr;
1245         m->host[i].value = host_val;
1246 }
1247
1248 static void reload_tss(void)
1249 {
1250         /*
1251          * VT restores TR but not its size.  Useless.
1252          */
1253         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1254         struct desc_struct *descs;
1255
1256         descs = (void *)gdt->address;
1257         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1258         load_TR_desc();
1259 }
1260
1261 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1262 {
1263         u64 guest_efer;
1264         u64 ignore_bits;
1265
1266         guest_efer = vmx->vcpu.arch.efer;
1267
1268         /*
1269          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1270          * outside long mode
1271          */
1272         ignore_bits = EFER_NX | EFER_SCE;
1273 #ifdef CONFIG_X86_64
1274         ignore_bits |= EFER_LMA | EFER_LME;
1275         /* SCE is meaningful only in long mode on Intel */
1276         if (guest_efer & EFER_LMA)
1277                 ignore_bits &= ~(u64)EFER_SCE;
1278 #endif
1279         guest_efer &= ~ignore_bits;
1280         guest_efer |= host_efer & ignore_bits;
1281         vmx->guest_msrs[efer_offset].data = guest_efer;
1282         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1283
1284         clear_atomic_switch_msr(vmx, MSR_EFER);
1285         /* On ept, can't emulate nx, and must switch nx atomically */
1286         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1287                 guest_efer = vmx->vcpu.arch.efer;
1288                 if (!(guest_efer & EFER_LMA))
1289                         guest_efer &= ~EFER_LME;
1290                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1291                 return false;
1292         }
1293
1294         return true;
1295 }
1296
1297 static unsigned long segment_base(u16 selector)
1298 {
1299         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1300         struct desc_struct *d;
1301         unsigned long table_base;
1302         unsigned long v;
1303
1304         if (!(selector & ~3))
1305                 return 0;
1306
1307         table_base = gdt->address;
1308
1309         if (selector & 4) {           /* from ldt */
1310                 u16 ldt_selector = kvm_read_ldt();
1311
1312                 if (!(ldt_selector & ~3))
1313                         return 0;
1314
1315                 table_base = segment_base(ldt_selector);
1316         }
1317         d = (struct desc_struct *)(table_base + (selector & ~7));
1318         v = get_desc_base(d);
1319 #ifdef CONFIG_X86_64
1320        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1321                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1322 #endif
1323         return v;
1324 }
1325
1326 static inline unsigned long kvm_read_tr_base(void)
1327 {
1328         u16 tr;
1329         asm("str %0" : "=g"(tr));
1330         return segment_base(tr);
1331 }
1332
1333 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1334 {
1335         struct vcpu_vmx *vmx = to_vmx(vcpu);
1336         int i;
1337
1338         if (vmx->host_state.loaded)
1339                 return;
1340
1341         vmx->host_state.loaded = 1;
1342         /*
1343          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1344          * allow segment selectors with cpl > 0 or ti == 1.
1345          */
1346         vmx->host_state.ldt_sel = kvm_read_ldt();
1347         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1348         savesegment(fs, vmx->host_state.fs_sel);
1349         if (!(vmx->host_state.fs_sel & 7)) {
1350                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1351                 vmx->host_state.fs_reload_needed = 0;
1352         } else {
1353                 vmcs_write16(HOST_FS_SELECTOR, 0);
1354                 vmx->host_state.fs_reload_needed = 1;
1355         }
1356         savesegment(gs, vmx->host_state.gs_sel);
1357         if (!(vmx->host_state.gs_sel & 7))
1358                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1359         else {
1360                 vmcs_write16(HOST_GS_SELECTOR, 0);
1361                 vmx->host_state.gs_ldt_reload_needed = 1;
1362         }
1363
1364 #ifdef CONFIG_X86_64
1365         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1366         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1367 #else
1368         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1369         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1370 #endif
1371
1372 #ifdef CONFIG_X86_64
1373         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1374         if (is_long_mode(&vmx->vcpu))
1375                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1376 #endif
1377         for (i = 0; i < vmx->save_nmsrs; ++i)
1378                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1379                                    vmx->guest_msrs[i].data,
1380                                    vmx->guest_msrs[i].mask);
1381 }
1382
1383 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1384 {
1385         if (!vmx->host_state.loaded)
1386                 return;
1387
1388         ++vmx->vcpu.stat.host_state_reload;
1389         vmx->host_state.loaded = 0;
1390 #ifdef CONFIG_X86_64
1391         if (is_long_mode(&vmx->vcpu))
1392                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1393 #endif
1394         if (vmx->host_state.gs_ldt_reload_needed) {
1395                 kvm_load_ldt(vmx->host_state.ldt_sel);
1396 #ifdef CONFIG_X86_64
1397                 load_gs_index(vmx->host_state.gs_sel);
1398 #else
1399                 loadsegment(gs, vmx->host_state.gs_sel);
1400 #endif
1401         }
1402         if (vmx->host_state.fs_reload_needed)
1403                 loadsegment(fs, vmx->host_state.fs_sel);
1404         reload_tss();
1405 #ifdef CONFIG_X86_64
1406         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1407 #endif
1408         if (current_thread_info()->status & TS_USEDFPU)
1409                 clts();
1410         load_gdt(&__get_cpu_var(host_gdt));
1411 }
1412
1413 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1414 {
1415         preempt_disable();
1416         __vmx_load_host_state(vmx);
1417         preempt_enable();
1418 }
1419
1420 /*
1421  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1422  * vcpu mutex is already taken.
1423  */
1424 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1425 {
1426         struct vcpu_vmx *vmx = to_vmx(vcpu);
1427         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1428
1429         if (!vmm_exclusive)
1430                 kvm_cpu_vmxon(phys_addr);
1431         else if (vmx->loaded_vmcs->cpu != cpu)
1432                 loaded_vmcs_clear(vmx->loaded_vmcs);
1433
1434         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1435                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1436                 vmcs_load(vmx->loaded_vmcs->vmcs);
1437         }
1438
1439         if (vmx->loaded_vmcs->cpu != cpu) {
1440                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1441                 unsigned long sysenter_esp;
1442
1443                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1444                 local_irq_disable();
1445                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1446                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1447                 local_irq_enable();
1448
1449                 /*
1450                  * Linux uses per-cpu TSS and GDT, so set these when switching
1451                  * processors.
1452                  */
1453                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1454                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1455
1456                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1457                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1458                 vmx->loaded_vmcs->cpu = cpu;
1459         }
1460 }
1461
1462 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1463 {
1464         __vmx_load_host_state(to_vmx(vcpu));
1465         if (!vmm_exclusive) {
1466                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1467                 vcpu->cpu = -1;
1468                 kvm_cpu_vmxoff();
1469         }
1470 }
1471
1472 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1473 {
1474         ulong cr0;
1475
1476         if (vcpu->fpu_active)
1477                 return;
1478         vcpu->fpu_active = 1;
1479         cr0 = vmcs_readl(GUEST_CR0);
1480         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1481         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1482         vmcs_writel(GUEST_CR0, cr0);
1483         update_exception_bitmap(vcpu);
1484         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1485         if (is_guest_mode(vcpu))
1486                 vcpu->arch.cr0_guest_owned_bits &=
1487                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1488         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1489 }
1490
1491 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1492
1493 /*
1494  * Return the cr0 value that a nested guest would read. This is a combination
1495  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1496  * its hypervisor (cr0_read_shadow).
1497  */
1498 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1499 {
1500         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1501                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1502 }
1503 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1504 {
1505         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1506                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1507 }
1508
1509 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1510 {
1511         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1512          * set this *before* calling this function.
1513          */
1514         vmx_decache_cr0_guest_bits(vcpu);
1515         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1516         update_exception_bitmap(vcpu);
1517         vcpu->arch.cr0_guest_owned_bits = 0;
1518         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1519         if (is_guest_mode(vcpu)) {
1520                 /*
1521                  * L1's specified read shadow might not contain the TS bit,
1522                  * so now that we turned on shadowing of this bit, we need to
1523                  * set this bit of the shadow. Like in nested_vmx_run we need
1524                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1525                  * up-to-date here because we just decached cr0.TS (and we'll
1526                  * only update vmcs12->guest_cr0 on nested exit).
1527                  */
1528                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1529                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1530                         (vcpu->arch.cr0 & X86_CR0_TS);
1531                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1532         } else
1533                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1534 }
1535
1536 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1537 {
1538         unsigned long rflags, save_rflags;
1539
1540         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1541                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1542                 rflags = vmcs_readl(GUEST_RFLAGS);
1543                 if (to_vmx(vcpu)->rmode.vm86_active) {
1544                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1545                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1546                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1547                 }
1548                 to_vmx(vcpu)->rflags = rflags;
1549         }
1550         return to_vmx(vcpu)->rflags;
1551 }
1552
1553 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1554 {
1555         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1556         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1557         to_vmx(vcpu)->rflags = rflags;
1558         if (to_vmx(vcpu)->rmode.vm86_active) {
1559                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1560                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1561         }
1562         vmcs_writel(GUEST_RFLAGS, rflags);
1563 }
1564
1565 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1566 {
1567         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1568         int ret = 0;
1569
1570         if (interruptibility & GUEST_INTR_STATE_STI)
1571                 ret |= KVM_X86_SHADOW_INT_STI;
1572         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1573                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1574
1575         return ret & mask;
1576 }
1577
1578 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1579 {
1580         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1581         u32 interruptibility = interruptibility_old;
1582
1583         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1584
1585         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1586                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1587         else if (mask & KVM_X86_SHADOW_INT_STI)
1588                 interruptibility |= GUEST_INTR_STATE_STI;
1589
1590         if ((interruptibility != interruptibility_old))
1591                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1592 }
1593
1594 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1595 {
1596         unsigned long rip;
1597
1598         rip = kvm_rip_read(vcpu);
1599         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1600         kvm_rip_write(vcpu, rip);
1601
1602         /* skipping an emulated instruction also counts */
1603         vmx_set_interrupt_shadow(vcpu, 0);
1604 }
1605
1606 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1607 {
1608         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1609          * explicitly skip the instruction because if the HLT state is set, then
1610          * the instruction is already executing and RIP has already been
1611          * advanced. */
1612         if (!yield_on_hlt &&
1613             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1614                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1615 }
1616
1617 /*
1618  * KVM wants to inject page-faults which it got to the guest. This function
1619  * checks whether in a nested guest, we need to inject them to L1 or L2.
1620  * This function assumes it is called with the exit reason in vmcs02 being
1621  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1622  * is running).
1623  */
1624 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1625 {
1626         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1627
1628         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1629         if (!(vmcs12->exception_bitmap & PF_VECTOR))
1630                 return 0;
1631
1632         nested_vmx_vmexit(vcpu);
1633         return 1;
1634 }
1635
1636 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1637                                 bool has_error_code, u32 error_code,
1638                                 bool reinject)
1639 {
1640         struct vcpu_vmx *vmx = to_vmx(vcpu);
1641         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1642
1643         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1644                 nested_pf_handled(vcpu))
1645                 return;
1646
1647         if (has_error_code) {
1648                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1649                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1650         }
1651
1652         if (vmx->rmode.vm86_active) {
1653                 int inc_eip = 0;
1654                 if (kvm_exception_is_soft(nr))
1655                         inc_eip = vcpu->arch.event_exit_inst_len;
1656                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1657                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1658                 return;
1659         }
1660
1661         if (kvm_exception_is_soft(nr)) {
1662                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1663                              vmx->vcpu.arch.event_exit_inst_len);
1664                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1665         } else
1666                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1667
1668         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1669         vmx_clear_hlt(vcpu);
1670 }
1671
1672 static bool vmx_rdtscp_supported(void)
1673 {
1674         return cpu_has_vmx_rdtscp();
1675 }
1676
1677 /*
1678  * Swap MSR entry in host/guest MSR entry array.
1679  */
1680 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1681 {
1682         struct shared_msr_entry tmp;
1683
1684         tmp = vmx->guest_msrs[to];
1685         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1686         vmx->guest_msrs[from] = tmp;
1687 }
1688
1689 /*
1690  * Set up the vmcs to automatically save and restore system
1691  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1692  * mode, as fiddling with msrs is very expensive.
1693  */
1694 static void setup_msrs(struct vcpu_vmx *vmx)
1695 {
1696         int save_nmsrs, index;
1697         unsigned long *msr_bitmap;
1698
1699         vmx_load_host_state(vmx);
1700         save_nmsrs = 0;
1701 #ifdef CONFIG_X86_64
1702         if (is_long_mode(&vmx->vcpu)) {
1703                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1704                 if (index >= 0)
1705                         move_msr_up(vmx, index, save_nmsrs++);
1706                 index = __find_msr_index(vmx, MSR_LSTAR);
1707                 if (index >= 0)
1708                         move_msr_up(vmx, index, save_nmsrs++);
1709                 index = __find_msr_index(vmx, MSR_CSTAR);
1710                 if (index >= 0)
1711                         move_msr_up(vmx, index, save_nmsrs++);
1712                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1713                 if (index >= 0 && vmx->rdtscp_enabled)
1714                         move_msr_up(vmx, index, save_nmsrs++);
1715                 /*
1716                  * MSR_STAR is only needed on long mode guests, and only
1717                  * if efer.sce is enabled.
1718                  */
1719                 index = __find_msr_index(vmx, MSR_STAR);
1720                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1721                         move_msr_up(vmx, index, save_nmsrs++);
1722         }
1723 #endif
1724         index = __find_msr_index(vmx, MSR_EFER);
1725         if (index >= 0 && update_transition_efer(vmx, index))
1726                 move_msr_up(vmx, index, save_nmsrs++);
1727
1728         vmx->save_nmsrs = save_nmsrs;
1729
1730         if (cpu_has_vmx_msr_bitmap()) {
1731                 if (is_long_mode(&vmx->vcpu))
1732                         msr_bitmap = vmx_msr_bitmap_longmode;
1733                 else
1734                         msr_bitmap = vmx_msr_bitmap_legacy;
1735
1736                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1737         }
1738 }
1739
1740 /*
1741  * reads and returns guest's timestamp counter "register"
1742  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1743  */
1744 static u64 guest_read_tsc(void)
1745 {
1746         u64 host_tsc, tsc_offset;
1747
1748         rdtscll(host_tsc);
1749         tsc_offset = vmcs_read64(TSC_OFFSET);
1750         return host_tsc + tsc_offset;
1751 }
1752
1753 /*
1754  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1755  * ioctl. In this case the call-back should update internal vmx state to make
1756  * the changes effective.
1757  */
1758 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1759 {
1760         /* Nothing to do here */
1761 }
1762
1763 /*
1764  * writes 'offset' into guest's timestamp counter offset register
1765  */
1766 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1767 {
1768         vmcs_write64(TSC_OFFSET, offset);
1769         if (is_guest_mode(vcpu))
1770                 /*
1771                  * We're here if L1 chose not to trap the TSC MSR. Since
1772                  * prepare_vmcs12() does not copy tsc_offset, we need to also
1773                  * set the vmcs12 field here.
1774                  */
1775                 get_vmcs12(vcpu)->tsc_offset = offset -
1776                         to_vmx(vcpu)->nested.vmcs01_tsc_offset;
1777 }
1778
1779 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1780 {
1781         u64 offset = vmcs_read64(TSC_OFFSET);
1782         vmcs_write64(TSC_OFFSET, offset + adjustment);
1783         if (is_guest_mode(vcpu)) {
1784                 /* Even when running L2, the adjustment needs to apply to L1 */
1785                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1786         }
1787 }
1788
1789 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1790 {
1791         return target_tsc - native_read_tsc();
1792 }
1793
1794 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1795 {
1796         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1797         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1798 }
1799
1800 /*
1801  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1802  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1803  * all guests if the "nested" module option is off, and can also be disabled
1804  * for a single guest by disabling its VMX cpuid bit.
1805  */
1806 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1807 {
1808         return nested && guest_cpuid_has_vmx(vcpu);
1809 }
1810
1811 /*
1812  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1813  * returned for the various VMX controls MSRs when nested VMX is enabled.
1814  * The same values should also be used to verify that vmcs12 control fields are
1815  * valid during nested entry from L1 to L2.
1816  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1817  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1818  * bit in the high half is on if the corresponding bit in the control field
1819  * may be on. See also vmx_control_verify().
1820  * TODO: allow these variables to be modified (downgraded) by module options
1821  * or other means.
1822  */
1823 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1824 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1825 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1826 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1827 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1828 static __init void nested_vmx_setup_ctls_msrs(void)
1829 {
1830         /*
1831          * Note that as a general rule, the high half of the MSRs (bits in
1832          * the control fields which may be 1) should be initialized by the
1833          * intersection of the underlying hardware's MSR (i.e., features which
1834          * can be supported) and the list of features we want to expose -
1835          * because they are known to be properly supported in our code.
1836          * Also, usually, the low half of the MSRs (bits which must be 1) can
1837          * be set to 0, meaning that L1 may turn off any of these bits. The
1838          * reason is that if one of these bits is necessary, it will appear
1839          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1840          * fields of vmcs01 and vmcs02, will turn these bits off - and
1841          * nested_vmx_exit_handled() will not pass related exits to L1.
1842          * These rules have exceptions below.
1843          */
1844
1845         /* pin-based controls */
1846         /*
1847          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1848          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1849          */
1850         nested_vmx_pinbased_ctls_low = 0x16 ;
1851         nested_vmx_pinbased_ctls_high = 0x16 |
1852                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1853                 PIN_BASED_VIRTUAL_NMIS;
1854
1855         /* exit controls */
1856         nested_vmx_exit_ctls_low = 0;
1857         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1858 #ifdef CONFIG_X86_64
1859         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1860 #else
1861         nested_vmx_exit_ctls_high = 0;
1862 #endif
1863
1864         /* entry controls */
1865         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1866                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1867         nested_vmx_entry_ctls_low = 0;
1868         nested_vmx_entry_ctls_high &=
1869                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1870
1871         /* cpu-based controls */
1872         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1873                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1874         nested_vmx_procbased_ctls_low = 0;
1875         nested_vmx_procbased_ctls_high &=
1876                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1877                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1878                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1879                 CPU_BASED_CR3_STORE_EXITING |
1880 #ifdef CONFIG_X86_64
1881                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1882 #endif
1883                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1884                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1885                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1886         /*
1887          * We can allow some features even when not supported by the
1888          * hardware. For example, L1 can specify an MSR bitmap - and we
1889          * can use it to avoid exits to L1 - even when L0 runs L2
1890          * without MSR bitmaps.
1891          */
1892         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1893
1894         /* secondary cpu-based controls */
1895         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1896                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1897         nested_vmx_secondary_ctls_low = 0;
1898         nested_vmx_secondary_ctls_high &=
1899                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1900 }
1901
1902 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1903 {
1904         /*
1905          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1906          */
1907         return ((control & high) | low) == control;
1908 }
1909
1910 static inline u64 vmx_control_msr(u32 low, u32 high)
1911 {
1912         return low | ((u64)high << 32);
1913 }
1914
1915 /*
1916  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1917  * also let it use VMX-specific MSRs.
1918  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1919  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1920  * like all other MSRs).
1921  */
1922 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1923 {
1924         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1925                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1926                 /*
1927                  * According to the spec, processors which do not support VMX
1928                  * should throw a #GP(0) when VMX capability MSRs are read.
1929                  */
1930                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1931                 return 1;
1932         }
1933
1934         switch (msr_index) {
1935         case MSR_IA32_FEATURE_CONTROL:
1936                 *pdata = 0;
1937                 break;
1938         case MSR_IA32_VMX_BASIC:
1939                 /*
1940                  * This MSR reports some information about VMX support. We
1941                  * should return information about the VMX we emulate for the
1942                  * guest, and the VMCS structure we give it - not about the
1943                  * VMX support of the underlying hardware.
1944                  */
1945                 *pdata = VMCS12_REVISION |
1946                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1947                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1948                 break;
1949         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1950         case MSR_IA32_VMX_PINBASED_CTLS:
1951                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1952                                         nested_vmx_pinbased_ctls_high);
1953                 break;
1954         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1955         case MSR_IA32_VMX_PROCBASED_CTLS:
1956                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1957                                         nested_vmx_procbased_ctls_high);
1958                 break;
1959         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1960         case MSR_IA32_VMX_EXIT_CTLS:
1961                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1962                                         nested_vmx_exit_ctls_high);
1963                 break;
1964         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1965         case MSR_IA32_VMX_ENTRY_CTLS:
1966                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1967                                         nested_vmx_entry_ctls_high);
1968                 break;
1969         case MSR_IA32_VMX_MISC:
1970                 *pdata = 0;
1971                 break;
1972         /*
1973          * These MSRs specify bits which the guest must keep fixed (on or off)
1974          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1975          * We picked the standard core2 setting.
1976          */
1977 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1978 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
1979         case MSR_IA32_VMX_CR0_FIXED0:
1980                 *pdata = VMXON_CR0_ALWAYSON;
1981                 break;
1982         case MSR_IA32_VMX_CR0_FIXED1:
1983                 *pdata = -1ULL;
1984                 break;
1985         case MSR_IA32_VMX_CR4_FIXED0:
1986                 *pdata = VMXON_CR4_ALWAYSON;
1987                 break;
1988         case MSR_IA32_VMX_CR4_FIXED1:
1989                 *pdata = -1ULL;
1990                 break;
1991         case MSR_IA32_VMX_VMCS_ENUM:
1992                 *pdata = 0x1f;
1993                 break;
1994         case MSR_IA32_VMX_PROCBASED_CTLS2:
1995                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1996                                         nested_vmx_secondary_ctls_high);
1997                 break;
1998         case MSR_IA32_VMX_EPT_VPID_CAP:
1999                 /* Currently, no nested ept or nested vpid */
2000                 *pdata = 0;
2001                 break;
2002         default:
2003                 return 0;
2004         }
2005
2006         return 1;
2007 }
2008
2009 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2010 {
2011         if (!nested_vmx_allowed(vcpu))
2012                 return 0;
2013
2014         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2015                 /* TODO: the right thing. */
2016                 return 1;
2017         /*
2018          * No need to treat VMX capability MSRs specially: If we don't handle
2019          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2020          */
2021         return 0;
2022 }
2023
2024 /*
2025  * Reads an msr value (of 'msr_index') into 'pdata'.
2026  * Returns 0 on success, non-0 otherwise.
2027  * Assumes vcpu_load() was already called.
2028  */
2029 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2030 {
2031         u64 data;
2032         struct shared_msr_entry *msr;
2033
2034         if (!pdata) {
2035                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2036                 return -EINVAL;
2037         }
2038
2039         switch (msr_index) {
2040 #ifdef CONFIG_X86_64
2041         case MSR_FS_BASE:
2042                 data = vmcs_readl(GUEST_FS_BASE);
2043                 break;
2044         case MSR_GS_BASE:
2045                 data = vmcs_readl(GUEST_GS_BASE);
2046                 break;
2047         case MSR_KERNEL_GS_BASE:
2048                 vmx_load_host_state(to_vmx(vcpu));
2049                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2050                 break;
2051 #endif
2052         case MSR_EFER:
2053                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2054         case MSR_IA32_TSC:
2055                 data = guest_read_tsc();
2056                 break;
2057         case MSR_IA32_SYSENTER_CS:
2058                 data = vmcs_read32(GUEST_SYSENTER_CS);
2059                 break;
2060         case MSR_IA32_SYSENTER_EIP:
2061                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2062                 break;
2063         case MSR_IA32_SYSENTER_ESP:
2064                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2065                 break;
2066         case MSR_TSC_AUX:
2067                 if (!to_vmx(vcpu)->rdtscp_enabled)
2068                         return 1;
2069                 /* Otherwise falls through */
2070         default:
2071                 vmx_load_host_state(to_vmx(vcpu));
2072                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2073                         return 0;
2074                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2075                 if (msr) {
2076                         vmx_load_host_state(to_vmx(vcpu));
2077                         data = msr->data;
2078                         break;
2079                 }
2080                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2081         }
2082
2083         *pdata = data;
2084         return 0;
2085 }
2086
2087 /*
2088  * Writes msr value into into the appropriate "register".
2089  * Returns 0 on success, non-0 otherwise.
2090  * Assumes vcpu_load() was already called.
2091  */
2092 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2093 {
2094         struct vcpu_vmx *vmx = to_vmx(vcpu);
2095         struct shared_msr_entry *msr;
2096         int ret = 0;
2097
2098         switch (msr_index) {
2099         case MSR_EFER:
2100                 vmx_load_host_state(vmx);
2101                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2102                 break;
2103 #ifdef CONFIG_X86_64
2104         case MSR_FS_BASE:
2105                 vmx_segment_cache_clear(vmx);
2106                 vmcs_writel(GUEST_FS_BASE, data);
2107                 break;
2108         case MSR_GS_BASE:
2109                 vmx_segment_cache_clear(vmx);
2110                 vmcs_writel(GUEST_GS_BASE, data);
2111                 break;
2112         case MSR_KERNEL_GS_BASE:
2113                 vmx_load_host_state(vmx);
2114                 vmx->msr_guest_kernel_gs_base = data;
2115                 break;
2116 #endif
2117         case MSR_IA32_SYSENTER_CS:
2118                 vmcs_write32(GUEST_SYSENTER_CS, data);
2119                 break;
2120         case MSR_IA32_SYSENTER_EIP:
2121                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2122                 break;
2123         case MSR_IA32_SYSENTER_ESP:
2124                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2125                 break;
2126         case MSR_IA32_TSC:
2127                 kvm_write_tsc(vcpu, data);
2128                 break;
2129         case MSR_IA32_CR_PAT:
2130                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2131                         vmcs_write64(GUEST_IA32_PAT, data);
2132                         vcpu->arch.pat = data;
2133                         break;
2134                 }
2135                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2136                 break;
2137         case MSR_TSC_AUX:
2138                 if (!vmx->rdtscp_enabled)
2139                         return 1;
2140                 /* Check reserved bit, higher 32 bits should be zero */
2141                 if ((data >> 32) != 0)
2142                         return 1;
2143                 /* Otherwise falls through */
2144         default:
2145                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2146                         break;
2147                 msr = find_msr_entry(vmx, msr_index);
2148                 if (msr) {
2149                         vmx_load_host_state(vmx);
2150                         msr->data = data;
2151                         break;
2152                 }
2153                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2154         }
2155
2156         return ret;
2157 }
2158
2159 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2160 {
2161         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2162         switch (reg) {
2163         case VCPU_REGS_RSP:
2164                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2165                 break;
2166         case VCPU_REGS_RIP:
2167                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2168                 break;
2169         case VCPU_EXREG_PDPTR:
2170                 if (enable_ept)
2171                         ept_save_pdptrs(vcpu);
2172                 break;
2173         default:
2174                 break;
2175         }
2176 }
2177
2178 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2179 {
2180         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2181                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2182         else
2183                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2184
2185         update_exception_bitmap(vcpu);
2186 }
2187
2188 static __init int cpu_has_kvm_support(void)
2189 {
2190         return cpu_has_vmx();
2191 }
2192
2193 static __init int vmx_disabled_by_bios(void)
2194 {
2195         u64 msr;
2196
2197         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2198         if (msr & FEATURE_CONTROL_LOCKED) {
2199                 /* launched w/ TXT and VMX disabled */
2200                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2201                         && tboot_enabled())
2202                         return 1;
2203                 /* launched w/o TXT and VMX only enabled w/ TXT */
2204                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2205                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2206                         && !tboot_enabled()) {
2207                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2208                                 "activate TXT before enabling KVM\n");
2209                         return 1;
2210                 }
2211                 /* launched w/o TXT and VMX disabled */
2212                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2213                         && !tboot_enabled())
2214                         return 1;
2215         }
2216
2217         return 0;
2218 }
2219
2220 static void kvm_cpu_vmxon(u64 addr)
2221 {
2222         asm volatile (ASM_VMX_VMXON_RAX
2223                         : : "a"(&addr), "m"(addr)
2224                         : "memory", "cc");
2225 }
2226
2227 static int hardware_enable(void *garbage)
2228 {
2229         int cpu = raw_smp_processor_id();
2230         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2231         u64 old, test_bits;
2232
2233         if (read_cr4() & X86_CR4_VMXE)
2234                 return -EBUSY;
2235
2236         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2237         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2238
2239         test_bits = FEATURE_CONTROL_LOCKED;
2240         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2241         if (tboot_enabled())
2242                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2243
2244         if ((old & test_bits) != test_bits) {
2245                 /* enable and lock */
2246                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2247         }
2248         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2249
2250         if (vmm_exclusive) {
2251                 kvm_cpu_vmxon(phys_addr);
2252                 ept_sync_global();
2253         }
2254
2255         store_gdt(&__get_cpu_var(host_gdt));
2256
2257         return 0;
2258 }
2259
2260 static void vmclear_local_loaded_vmcss(void)
2261 {
2262         int cpu = raw_smp_processor_id();
2263         struct loaded_vmcs *v, *n;
2264
2265         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2266                                  loaded_vmcss_on_cpu_link)
2267                 __loaded_vmcs_clear(v);
2268 }
2269
2270
2271 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2272  * tricks.
2273  */
2274 static void kvm_cpu_vmxoff(void)
2275 {
2276         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2277 }
2278
2279 static void hardware_disable(void *garbage)
2280 {
2281         if (vmm_exclusive) {
2282                 vmclear_local_loaded_vmcss();
2283                 kvm_cpu_vmxoff();
2284         }
2285         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2286 }
2287
2288 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2289                                       u32 msr, u32 *result)
2290 {
2291         u32 vmx_msr_low, vmx_msr_high;
2292         u32 ctl = ctl_min | ctl_opt;
2293
2294         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2295
2296         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2297         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2298
2299         /* Ensure minimum (required) set of control bits are supported. */
2300         if (ctl_min & ~ctl)
2301                 return -EIO;
2302
2303         *result = ctl;
2304         return 0;
2305 }
2306
2307 static __init bool allow_1_setting(u32 msr, u32 ctl)
2308 {
2309         u32 vmx_msr_low, vmx_msr_high;
2310
2311         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2312         return vmx_msr_high & ctl;
2313 }
2314
2315 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2316 {
2317         u32 vmx_msr_low, vmx_msr_high;
2318         u32 min, opt, min2, opt2;
2319         u32 _pin_based_exec_control = 0;
2320         u32 _cpu_based_exec_control = 0;
2321         u32 _cpu_based_2nd_exec_control = 0;
2322         u32 _vmexit_control = 0;
2323         u32 _vmentry_control = 0;
2324
2325         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2326         opt = PIN_BASED_VIRTUAL_NMIS;
2327         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2328                                 &_pin_based_exec_control) < 0)
2329                 return -EIO;
2330
2331         min =
2332 #ifdef CONFIG_X86_64
2333               CPU_BASED_CR8_LOAD_EXITING |
2334               CPU_BASED_CR8_STORE_EXITING |
2335 #endif
2336               CPU_BASED_CR3_LOAD_EXITING |
2337               CPU_BASED_CR3_STORE_EXITING |
2338               CPU_BASED_USE_IO_BITMAPS |
2339               CPU_BASED_MOV_DR_EXITING |
2340               CPU_BASED_USE_TSC_OFFSETING |
2341               CPU_BASED_MWAIT_EXITING |
2342               CPU_BASED_MONITOR_EXITING |
2343               CPU_BASED_INVLPG_EXITING;
2344
2345         if (yield_on_hlt)
2346                 min |= CPU_BASED_HLT_EXITING;
2347
2348         opt = CPU_BASED_TPR_SHADOW |
2349               CPU_BASED_USE_MSR_BITMAPS |
2350               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2351         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2352                                 &_cpu_based_exec_control) < 0)
2353                 return -EIO;
2354 #ifdef CONFIG_X86_64
2355         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2356                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2357                                            ~CPU_BASED_CR8_STORE_EXITING;
2358 #endif
2359         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2360                 min2 = 0;
2361                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2362                         SECONDARY_EXEC_WBINVD_EXITING |
2363                         SECONDARY_EXEC_ENABLE_VPID |
2364                         SECONDARY_EXEC_ENABLE_EPT |
2365                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2366                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2367                         SECONDARY_EXEC_RDTSCP;
2368                 if (adjust_vmx_controls(min2, opt2,
2369                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2370                                         &_cpu_based_2nd_exec_control) < 0)
2371                         return -EIO;
2372         }
2373 #ifndef CONFIG_X86_64
2374         if (!(_cpu_based_2nd_exec_control &
2375                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2376                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2377 #endif
2378         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2379                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2380                    enabled */
2381                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2382                                              CPU_BASED_CR3_STORE_EXITING |
2383                                              CPU_BASED_INVLPG_EXITING);
2384                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2385                       vmx_capability.ept, vmx_capability.vpid);
2386         }
2387
2388         min = 0;
2389 #ifdef CONFIG_X86_64
2390         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2391 #endif
2392         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2393         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2394                                 &_vmexit_control) < 0)
2395                 return -EIO;
2396
2397         min = 0;
2398         opt = VM_ENTRY_LOAD_IA32_PAT;
2399         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2400                                 &_vmentry_control) < 0)
2401                 return -EIO;
2402
2403         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2404
2405         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2406         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2407                 return -EIO;
2408
2409 #ifdef CONFIG_X86_64
2410         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2411         if (vmx_msr_high & (1u<<16))
2412                 return -EIO;
2413 #endif
2414
2415         /* Require Write-Back (WB) memory type for VMCS accesses. */
2416         if (((vmx_msr_high >> 18) & 15) != 6)
2417                 return -EIO;
2418
2419         vmcs_conf->size = vmx_msr_high & 0x1fff;
2420         vmcs_conf->order = get_order(vmcs_config.size);
2421         vmcs_conf->revision_id = vmx_msr_low;
2422
2423         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2424         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2425         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2426         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2427         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2428
2429         cpu_has_load_ia32_efer =
2430                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2431                                 VM_ENTRY_LOAD_IA32_EFER)
2432                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2433                                    VM_EXIT_LOAD_IA32_EFER);
2434
2435         return 0;
2436 }
2437
2438 static struct vmcs *alloc_vmcs_cpu(int cpu)
2439 {
2440         int node = cpu_to_node(cpu);
2441         struct page *pages;
2442         struct vmcs *vmcs;
2443
2444         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2445         if (!pages)
2446                 return NULL;
2447         vmcs = page_address(pages);
2448         memset(vmcs, 0, vmcs_config.size);
2449         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2450         return vmcs;
2451 }
2452
2453 static struct vmcs *alloc_vmcs(void)
2454 {
2455         return alloc_vmcs_cpu(raw_smp_processor_id());
2456 }
2457
2458 static void free_vmcs(struct vmcs *vmcs)
2459 {
2460         free_pages((unsigned long)vmcs, vmcs_config.order);
2461 }
2462
2463 /*
2464  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2465  */
2466 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2467 {
2468         if (!loaded_vmcs->vmcs)
2469                 return;
2470         loaded_vmcs_clear(loaded_vmcs);
2471         free_vmcs(loaded_vmcs->vmcs);
2472         loaded_vmcs->vmcs = NULL;
2473 }
2474
2475 static void free_kvm_area(void)
2476 {
2477         int cpu;
2478
2479         for_each_possible_cpu(cpu) {
2480                 free_vmcs(per_cpu(vmxarea, cpu));
2481                 per_cpu(vmxarea, cpu) = NULL;
2482         }
2483 }
2484
2485 static __init int alloc_kvm_area(void)
2486 {
2487         int cpu;
2488
2489         for_each_possible_cpu(cpu) {
2490                 struct vmcs *vmcs;
2491
2492                 vmcs = alloc_vmcs_cpu(cpu);
2493                 if (!vmcs) {
2494                         free_kvm_area();
2495                         return -ENOMEM;
2496                 }
2497
2498                 per_cpu(vmxarea, cpu) = vmcs;
2499         }
2500         return 0;
2501 }
2502
2503 static __init int hardware_setup(void)
2504 {
2505         if (setup_vmcs_config(&vmcs_config) < 0)
2506                 return -EIO;
2507
2508         if (boot_cpu_has(X86_FEATURE_NX))
2509                 kvm_enable_efer_bits(EFER_NX);
2510
2511         if (!cpu_has_vmx_vpid())
2512                 enable_vpid = 0;
2513
2514         if (!cpu_has_vmx_ept() ||
2515             !cpu_has_vmx_ept_4levels()) {
2516                 enable_ept = 0;
2517                 enable_unrestricted_guest = 0;
2518         }
2519
2520         if (!cpu_has_vmx_unrestricted_guest())
2521                 enable_unrestricted_guest = 0;
2522
2523         if (!cpu_has_vmx_flexpriority())
2524                 flexpriority_enabled = 0;
2525
2526         if (!cpu_has_vmx_tpr_shadow())
2527                 kvm_x86_ops->update_cr8_intercept = NULL;
2528
2529         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2530                 kvm_disable_largepages();
2531
2532         if (!cpu_has_vmx_ple())
2533                 ple_gap = 0;
2534
2535         if (nested)
2536                 nested_vmx_setup_ctls_msrs();
2537
2538         return alloc_kvm_area();
2539 }
2540
2541 static __exit void hardware_unsetup(void)
2542 {
2543         free_kvm_area();
2544 }
2545
2546 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2547 {
2548         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2549
2550         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2551                 vmcs_write16(sf->selector, save->selector);
2552                 vmcs_writel(sf->base, save->base);
2553                 vmcs_write32(sf->limit, save->limit);
2554                 vmcs_write32(sf->ar_bytes, save->ar);
2555         } else {
2556                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2557                         << AR_DPL_SHIFT;
2558                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2559         }
2560 }
2561
2562 static void enter_pmode(struct kvm_vcpu *vcpu)
2563 {
2564         unsigned long flags;
2565         struct vcpu_vmx *vmx = to_vmx(vcpu);
2566
2567         vmx->emulation_required = 1;
2568         vmx->rmode.vm86_active = 0;
2569
2570         vmx_segment_cache_clear(vmx);
2571
2572         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2573         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2574         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2575         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2576
2577         flags = vmcs_readl(GUEST_RFLAGS);
2578         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2579         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2580         vmcs_writel(GUEST_RFLAGS, flags);
2581
2582         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2583                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2584
2585         update_exception_bitmap(vcpu);
2586
2587         if (emulate_invalid_guest_state)
2588                 return;
2589
2590         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2591         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2592         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2593         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2594
2595         vmx_segment_cache_clear(vmx);
2596
2597         vmcs_write16(GUEST_SS_SELECTOR, 0);
2598         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2599
2600         vmcs_write16(GUEST_CS_SELECTOR,
2601                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2602         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2603 }
2604
2605 static gva_t rmode_tss_base(struct kvm *kvm)
2606 {
2607         if (!kvm->arch.tss_addr) {
2608                 struct kvm_memslots *slots;
2609                 gfn_t base_gfn;
2610
2611                 slots = kvm_memslots(kvm);
2612                 base_gfn = slots->memslots[0].base_gfn +
2613                                  kvm->memslots->memslots[0].npages - 3;
2614                 return base_gfn << PAGE_SHIFT;
2615         }
2616         return kvm->arch.tss_addr;
2617 }
2618
2619 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2620 {
2621         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2622
2623         save->selector = vmcs_read16(sf->selector);
2624         save->base = vmcs_readl(sf->base);
2625         save->limit = vmcs_read32(sf->limit);
2626         save->ar = vmcs_read32(sf->ar_bytes);
2627         vmcs_write16(sf->selector, save->base >> 4);
2628         vmcs_write32(sf->base, save->base & 0xffff0);
2629         vmcs_write32(sf->limit, 0xffff);
2630         vmcs_write32(sf->ar_bytes, 0xf3);
2631         if (save->base & 0xf)
2632                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2633                             " aligned when entering protected mode (seg=%d)",
2634                             seg);
2635 }
2636
2637 static void enter_rmode(struct kvm_vcpu *vcpu)
2638 {
2639         unsigned long flags;
2640         struct vcpu_vmx *vmx = to_vmx(vcpu);
2641
2642         if (enable_unrestricted_guest)
2643                 return;
2644
2645         vmx->emulation_required = 1;
2646         vmx->rmode.vm86_active = 1;
2647
2648         /*
2649          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2650          * vcpu. Call it here with phys address pointing 16M below 4G.
2651          */
2652         if (!vcpu->kvm->arch.tss_addr) {
2653                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2654                              "called before entering vcpu\n");
2655                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2656                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2657                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2658         }
2659
2660         vmx_segment_cache_clear(vmx);
2661
2662         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2663         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2664         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2665
2666         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2667         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2668
2669         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2670         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2671
2672         flags = vmcs_readl(GUEST_RFLAGS);
2673         vmx->rmode.save_rflags = flags;
2674
2675         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2676
2677         vmcs_writel(GUEST_RFLAGS, flags);
2678         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2679         update_exception_bitmap(vcpu);
2680
2681         if (emulate_invalid_guest_state)
2682                 goto continue_rmode;
2683
2684         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2685         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2686         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2687
2688         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2689         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2690         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2691                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2692         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2693
2694         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2695         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2696         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2697         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2698
2699 continue_rmode:
2700         kvm_mmu_reset_context(vcpu);
2701 }
2702
2703 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2704 {
2705         struct vcpu_vmx *vmx = to_vmx(vcpu);
2706         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2707
2708         if (!msr)
2709                 return;
2710
2711         /*
2712          * Force kernel_gs_base reloading before EFER changes, as control
2713          * of this msr depends on is_long_mode().
2714          */
2715         vmx_load_host_state(to_vmx(vcpu));
2716         vcpu->arch.efer = efer;
2717         if (efer & EFER_LMA) {
2718                 vmcs_write32(VM_ENTRY_CONTROLS,
2719                              vmcs_read32(VM_ENTRY_CONTROLS) |
2720                              VM_ENTRY_IA32E_MODE);
2721                 msr->data = efer;
2722         } else {
2723                 vmcs_write32(VM_ENTRY_CONTROLS,
2724                              vmcs_read32(VM_ENTRY_CONTROLS) &
2725                              ~VM_ENTRY_IA32E_MODE);
2726
2727                 msr->data = efer & ~EFER_LME;
2728         }
2729         setup_msrs(vmx);
2730 }
2731
2732 #ifdef CONFIG_X86_64
2733
2734 static void enter_lmode(struct kvm_vcpu *vcpu)
2735 {
2736         u32 guest_tr_ar;
2737
2738         vmx_segment_cache_clear(to_vmx(vcpu));
2739
2740         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2741         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2742                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
2743                        __func__);
2744                 vmcs_write32(GUEST_TR_AR_BYTES,
2745                              (guest_tr_ar & ~AR_TYPE_MASK)
2746                              | AR_TYPE_BUSY_64_TSS);
2747         }
2748         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2749 }
2750
2751 static void exit_lmode(struct kvm_vcpu *vcpu)
2752 {
2753         vmcs_write32(VM_ENTRY_CONTROLS,
2754                      vmcs_read32(VM_ENTRY_CONTROLS)
2755                      & ~VM_ENTRY_IA32E_MODE);
2756         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2757 }
2758
2759 #endif
2760
2761 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2762 {
2763         vpid_sync_context(to_vmx(vcpu));
2764         if (enable_ept) {
2765                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2766                         return;
2767                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2768         }
2769 }
2770
2771 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2772 {
2773         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2774
2775         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2776         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2777 }
2778
2779 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2780 {
2781         if (enable_ept && is_paging(vcpu))
2782                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2783         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2784 }
2785
2786 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2787 {
2788         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2789
2790         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2791         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2792 }
2793
2794 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2795 {
2796         if (!test_bit(VCPU_EXREG_PDPTR,
2797                       (unsigned long *)&vcpu->arch.regs_dirty))
2798                 return;
2799
2800         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2801                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2802                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2803                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2804                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2805         }
2806 }
2807
2808 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2809 {
2810         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2811                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2812                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2813                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2814                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2815         }
2816
2817         __set_bit(VCPU_EXREG_PDPTR,
2818                   (unsigned long *)&vcpu->arch.regs_avail);
2819         __set_bit(VCPU_EXREG_PDPTR,
2820                   (unsigned long *)&vcpu->arch.regs_dirty);
2821 }
2822
2823 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2824
2825 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2826                                         unsigned long cr0,
2827                                         struct kvm_vcpu *vcpu)
2828 {
2829         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2830                 vmx_decache_cr3(vcpu);
2831         if (!(cr0 & X86_CR0_PG)) {
2832                 /* From paging/starting to nonpaging */
2833                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2834                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2835                              (CPU_BASED_CR3_LOAD_EXITING |
2836                               CPU_BASED_CR3_STORE_EXITING));
2837                 vcpu->arch.cr0 = cr0;
2838                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2839         } else if (!is_paging(vcpu)) {
2840                 /* From nonpaging to paging */
2841                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2842                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2843                              ~(CPU_BASED_CR3_LOAD_EXITING |
2844                                CPU_BASED_CR3_STORE_EXITING));
2845                 vcpu->arch.cr0 = cr0;
2846                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2847         }
2848
2849         if (!(cr0 & X86_CR0_WP))
2850                 *hw_cr0 &= ~X86_CR0_WP;
2851 }
2852
2853 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2854 {
2855         struct vcpu_vmx *vmx = to_vmx(vcpu);
2856         unsigned long hw_cr0;
2857
2858         if (enable_unrestricted_guest)
2859                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2860                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2861         else
2862                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2863
2864         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2865                 enter_pmode(vcpu);
2866
2867         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2868                 enter_rmode(vcpu);
2869
2870 #ifdef CONFIG_X86_64
2871         if (vcpu->arch.efer & EFER_LME) {
2872                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2873                         enter_lmode(vcpu);
2874                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2875                         exit_lmode(vcpu);
2876         }
2877 #endif
2878
2879         if (enable_ept)
2880                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2881
2882         if (!vcpu->fpu_active)
2883                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2884
2885         vmcs_writel(CR0_READ_SHADOW, cr0);
2886         vmcs_writel(GUEST_CR0, hw_cr0);
2887         vcpu->arch.cr0 = cr0;
2888         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2889 }
2890
2891 static u64 construct_eptp(unsigned long root_hpa)
2892 {
2893         u64 eptp;
2894
2895         /* TODO write the value reading from MSR */
2896         eptp = VMX_EPT_DEFAULT_MT |
2897                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2898         eptp |= (root_hpa & PAGE_MASK);
2899
2900         return eptp;
2901 }
2902
2903 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2904 {
2905         unsigned long guest_cr3;
2906         u64 eptp;
2907
2908         guest_cr3 = cr3;
2909         if (enable_ept) {
2910                 eptp = construct_eptp(cr3);
2911                 vmcs_write64(EPT_POINTER, eptp);
2912                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2913                         vcpu->kvm->arch.ept_identity_map_addr;
2914                 ept_load_pdptrs(vcpu);
2915         }
2916
2917         vmx_flush_tlb(vcpu);
2918         vmcs_writel(GUEST_CR3, guest_cr3);
2919 }
2920
2921 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2922 {
2923         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2924                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2925
2926         if (cr4 & X86_CR4_VMXE) {
2927                 /*
2928                  * To use VMXON (and later other VMX instructions), a guest
2929                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2930                  * So basically the check on whether to allow nested VMX
2931                  * is here.
2932                  */
2933                 if (!nested_vmx_allowed(vcpu))
2934                         return 1;
2935         } else if (to_vmx(vcpu)->nested.vmxon)
2936                 return 1;
2937
2938         vcpu->arch.cr4 = cr4;
2939         if (enable_ept) {
2940                 if (!is_paging(vcpu)) {
2941                         hw_cr4 &= ~X86_CR4_PAE;
2942                         hw_cr4 |= X86_CR4_PSE;
2943                 } else if (!(cr4 & X86_CR4_PAE)) {
2944                         hw_cr4 &= ~X86_CR4_PAE;
2945                 }
2946         }
2947
2948         vmcs_writel(CR4_READ_SHADOW, cr4);
2949         vmcs_writel(GUEST_CR4, hw_cr4);
2950         return 0;
2951 }
2952
2953 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2954                             struct kvm_segment *var, int seg)
2955 {
2956         struct vcpu_vmx *vmx = to_vmx(vcpu);
2957         struct kvm_save_segment *save;
2958         u32 ar;
2959
2960         if (vmx->rmode.vm86_active
2961             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2962                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2963                 || seg == VCPU_SREG_GS)
2964             && !emulate_invalid_guest_state) {
2965                 switch (seg) {
2966                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2967                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2968                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2969                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2970                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2971                 default: BUG();
2972                 }
2973                 var->selector = save->selector;
2974                 var->base = save->base;
2975                 var->limit = save->limit;
2976                 ar = save->ar;
2977                 if (seg == VCPU_SREG_TR
2978                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
2979                         goto use_saved_rmode_seg;
2980         }
2981         var->base = vmx_read_guest_seg_base(vmx, seg);
2982         var->limit = vmx_read_guest_seg_limit(vmx, seg);
2983         var->selector = vmx_read_guest_seg_selector(vmx, seg);
2984         ar = vmx_read_guest_seg_ar(vmx, seg);
2985 use_saved_rmode_seg:
2986         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2987                 ar = 0;
2988         var->type = ar & 15;
2989         var->s = (ar >> 4) & 1;
2990         var->dpl = (ar >> 5) & 3;
2991         var->present = (ar >> 7) & 1;
2992         var->avl = (ar >> 12) & 1;
2993         var->l = (ar >> 13) & 1;
2994         var->db = (ar >> 14) & 1;
2995         var->g = (ar >> 15) & 1;
2996         var->unusable = (ar >> 16) & 1;
2997 }
2998
2999 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3000 {
3001         struct kvm_segment s;
3002
3003         if (to_vmx(vcpu)->rmode.vm86_active) {
3004                 vmx_get_segment(vcpu, &s, seg);
3005                 return s.base;
3006         }
3007         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3008 }
3009
3010 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3011 {
3012         if (!is_protmode(vcpu))
3013                 return 0;
3014
3015         if (!is_long_mode(vcpu)
3016             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3017                 return 3;
3018
3019         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3020 }
3021
3022 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3023 {
3024         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3025                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3026                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3027         }
3028         return to_vmx(vcpu)->cpl;
3029 }
3030
3031
3032 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3033 {
3034         u32 ar;
3035
3036         if (var->unusable)
3037                 ar = 1 << 16;
3038         else {
3039                 ar = var->type & 15;
3040                 ar |= (var->s & 1) << 4;
3041                 ar |= (var->dpl & 3) << 5;
3042                 ar |= (var->present & 1) << 7;
3043                 ar |= (var->avl & 1) << 12;
3044                 ar |= (var->l & 1) << 13;
3045                 ar |= (var->db & 1) << 14;
3046                 ar |= (var->g & 1) << 15;
3047         }
3048         if (ar == 0) /* a 0 value means unusable */
3049                 ar = AR_UNUSABLE_MASK;
3050
3051         return ar;
3052 }
3053
3054 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3055                             struct kvm_segment *var, int seg)
3056 {
3057         struct vcpu_vmx *vmx = to_vmx(vcpu);
3058         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3059         u32 ar;
3060
3061         vmx_segment_cache_clear(vmx);
3062
3063         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3064                 vmcs_write16(sf->selector, var->selector);
3065                 vmx->rmode.tr.selector = var->selector;
3066                 vmx->rmode.tr.base = var->base;
3067                 vmx->rmode.tr.limit = var->limit;
3068                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3069                 return;
3070         }
3071         vmcs_writel(sf->base, var->base);
3072         vmcs_write32(sf->limit, var->limit);
3073         vmcs_write16(sf->selector, var->selector);
3074         if (vmx->rmode.vm86_active && var->s) {
3075                 /*
3076                  * Hack real-mode segments into vm86 compatibility.
3077                  */
3078                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3079                         vmcs_writel(sf->base, 0xf0000);
3080                 ar = 0xf3;
3081         } else
3082                 ar = vmx_segment_access_rights(var);
3083
3084         /*
3085          *   Fix the "Accessed" bit in AR field of segment registers for older
3086          * qemu binaries.
3087          *   IA32 arch specifies that at the time of processor reset the
3088          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3089          * is setting it to 0 in the usedland code. This causes invalid guest
3090          * state vmexit when "unrestricted guest" mode is turned on.
3091          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3092          * tree. Newer qemu binaries with that qemu fix would not need this
3093          * kvm hack.
3094          */
3095         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3096                 ar |= 0x1; /* Accessed */
3097
3098         vmcs_write32(sf->ar_bytes, ar);
3099         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3100 }
3101
3102 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3103 {
3104         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3105
3106         *db = (ar >> 14) & 1;
3107         *l = (ar >> 13) & 1;
3108 }
3109
3110 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3111 {
3112         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3113         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3114 }
3115
3116 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3117 {
3118         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3119         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3120 }
3121
3122 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3123 {
3124         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3125         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3126 }
3127
3128 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3129 {
3130         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3131         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3132 }
3133
3134 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3135 {
3136         struct kvm_segment var;
3137         u32 ar;
3138
3139         vmx_get_segment(vcpu, &var, seg);
3140         ar = vmx_segment_access_rights(&var);
3141
3142         if (var.base != (var.selector << 4))
3143                 return false;
3144         if (var.limit != 0xffff)
3145                 return false;
3146         if (ar != 0xf3)
3147                 return false;
3148
3149         return true;
3150 }
3151
3152 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3153 {
3154         struct kvm_segment cs;
3155         unsigned int cs_rpl;
3156
3157         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3158         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3159
3160         if (cs.unusable)
3161                 return false;
3162         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3163                 return false;
3164         if (!cs.s)
3165                 return false;
3166         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3167                 if (cs.dpl > cs_rpl)
3168                         return false;
3169         } else {
3170                 if (cs.dpl != cs_rpl)
3171                         return false;
3172         }
3173         if (!cs.present)
3174                 return false;
3175
3176         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3177         return true;
3178 }
3179
3180 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3181 {
3182         struct kvm_segment ss;
3183         unsigned int ss_rpl;
3184
3185         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3186         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3187
3188         if (ss.unusable)
3189                 return true;
3190         if (ss.type != 3 && ss.type != 7)
3191                 return false;
3192         if (!ss.s)
3193                 return false;
3194         if (ss.dpl != ss_rpl) /* DPL != RPL */
3195                 return false;
3196         if (!ss.present)
3197                 return false;
3198
3199         return true;
3200 }
3201
3202 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3203 {
3204         struct kvm_segment var;
3205         unsigned int rpl;
3206
3207         vmx_get_segment(vcpu, &var, seg);
3208         rpl = var.selector & SELECTOR_RPL_MASK;
3209
3210         if (var.unusable)
3211                 return true;
3212         if (!var.s)
3213                 return false;
3214         if (!var.present)
3215                 return false;
3216         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3217                 if (var.dpl < rpl) /* DPL < RPL */
3218                         return false;
3219         }
3220
3221         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3222          * rights flags
3223          */
3224         return true;
3225 }
3226
3227 static bool tr_valid(struct kvm_vcpu *vcpu)
3228 {
3229         struct kvm_segment tr;
3230
3231         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3232
3233         if (tr.unusable)
3234                 return false;
3235         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3236                 return false;
3237         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3238                 return false;
3239         if (!tr.present)
3240                 return false;
3241
3242         return true;
3243 }
3244
3245 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3246 {
3247         struct kvm_segment ldtr;
3248
3249         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3250
3251         if (ldtr.unusable)
3252                 return true;
3253         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3254                 return false;
3255         if (ldtr.type != 2)
3256                 return false;
3257         if (!ldtr.present)
3258                 return false;
3259
3260         return true;
3261 }
3262
3263 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3264 {
3265         struct kvm_segment cs, ss;
3266
3267         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3268         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3269
3270         return ((cs.selector & SELECTOR_RPL_MASK) ==
3271                  (ss.selector & SELECTOR_RPL_MASK));
3272 }
3273
3274 /*
3275  * Check if guest state is valid. Returns true if valid, false if
3276  * not.
3277  * We assume that registers are always usable
3278  */
3279 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3280 {
3281         /* real mode guest state checks */
3282         if (!is_protmode(vcpu)) {
3283                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3284                         return false;
3285                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3286                         return false;
3287                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3288                         return false;
3289                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3290                         return false;
3291                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3292                         return false;
3293                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3294                         return false;
3295         } else {
3296         /* protected mode guest state checks */
3297                 if (!cs_ss_rpl_check(vcpu))
3298                         return false;
3299                 if (!code_segment_valid(vcpu))
3300                         return false;
3301                 if (!stack_segment_valid(vcpu))
3302                         return false;
3303                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3304                         return false;
3305                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3306                         return false;
3307                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3308                         return false;
3309                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3310                         return false;
3311                 if (!tr_valid(vcpu))
3312                         return false;
3313                 if (!ldtr_valid(vcpu))
3314                         return false;
3315         }
3316         /* TODO:
3317          * - Add checks on RIP
3318          * - Add checks on RFLAGS
3319          */
3320
3321         return true;
3322 }
3323
3324 static int init_rmode_tss(struct kvm *kvm)
3325 {
3326         gfn_t fn;
3327         u16 data = 0;
3328         int r, idx, ret = 0;
3329
3330         idx = srcu_read_lock(&kvm->srcu);
3331         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3332         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3333         if (r < 0)
3334                 goto out;
3335         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3336         r = kvm_write_guest_page(kvm, fn++, &data,
3337                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3338         if (r < 0)
3339                 goto out;
3340         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3341         if (r < 0)
3342                 goto out;
3343         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3344         if (r < 0)
3345                 goto out;
3346         data = ~0;
3347         r = kvm_write_guest_page(kvm, fn, &data,
3348                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3349                                  sizeof(u8));
3350         if (r < 0)
3351                 goto out;
3352
3353         ret = 1;
3354 out:
3355         srcu_read_unlock(&kvm->srcu, idx);
3356         return ret;
3357 }
3358
3359 static int init_rmode_identity_map(struct kvm *kvm)
3360 {
3361         int i, idx, r, ret;
3362         pfn_t identity_map_pfn;
3363         u32 tmp;
3364
3365         if (!enable_ept)
3366                 return 1;
3367         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3368                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3369                         "haven't been allocated!\n");
3370                 return 0;
3371         }
3372         if (likely(kvm->arch.ept_identity_pagetable_done))
3373                 return 1;
3374         ret = 0;
3375         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3376         idx = srcu_read_lock(&kvm->srcu);
3377         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3378         if (r < 0)
3379                 goto out;
3380         /* Set up identity-mapping pagetable for EPT in real mode */
3381         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3382                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3383                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3384                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3385                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3386                 if (r < 0)
3387                         goto out;
3388         }
3389         kvm->arch.ept_identity_pagetable_done = true;
3390         ret = 1;
3391 out:
3392         srcu_read_unlock(&kvm->srcu, idx);
3393         return ret;
3394 }
3395
3396 static void seg_setup(int seg)
3397 {
3398         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3399         unsigned int ar;
3400
3401         vmcs_write16(sf->selector, 0);
3402         vmcs_writel(sf->base, 0);
3403         vmcs_write32(sf->limit, 0xffff);
3404         if (enable_unrestricted_guest) {
3405                 ar = 0x93;
3406                 if (seg == VCPU_SREG_CS)
3407                         ar |= 0x08; /* code segment */
3408         } else
3409                 ar = 0xf3;
3410
3411         vmcs_write32(sf->ar_bytes, ar);
3412 }
3413
3414 static int alloc_apic_access_page(struct kvm *kvm)
3415 {
3416         struct kvm_userspace_memory_region kvm_userspace_mem;
3417         int r = 0;
3418
3419         mutex_lock(&kvm->slots_lock);
3420         if (kvm->arch.apic_access_page)
3421                 goto out;
3422         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3423         kvm_userspace_mem.flags = 0;
3424         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3425         kvm_userspace_mem.memory_size = PAGE_SIZE;
3426         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3427         if (r)
3428                 goto out;
3429
3430         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3431 out:
3432         mutex_unlock(&kvm->slots_lock);
3433         return r;
3434 }
3435
3436 static int alloc_identity_pagetable(struct kvm *kvm)
3437 {
3438         struct kvm_userspace_memory_region kvm_userspace_mem;
3439         int r = 0;
3440
3441         mutex_lock(&kvm->slots_lock);
3442         if (kvm->arch.ept_identity_pagetable)
3443                 goto out;
3444         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3445         kvm_userspace_mem.flags = 0;
3446         kvm_userspace_mem.guest_phys_addr =
3447                 kvm->arch.ept_identity_map_addr;
3448         kvm_userspace_mem.memory_size = PAGE_SIZE;
3449         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3450         if (r)
3451                 goto out;
3452
3453         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3454                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3455 out:
3456         mutex_unlock(&kvm->slots_lock);
3457         return r;
3458 }
3459
3460 static void allocate_vpid(struct vcpu_vmx *vmx)
3461 {
3462         int vpid;
3463
3464         vmx->vpid = 0;
3465         if (!enable_vpid)
3466                 return;
3467         spin_lock(&vmx_vpid_lock);
3468         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3469         if (vpid < VMX_NR_VPIDS) {
3470                 vmx->vpid = vpid;
3471                 __set_bit(vpid, vmx_vpid_bitmap);
3472         }
3473         spin_unlock(&vmx_vpid_lock);
3474 }
3475
3476 static void free_vpid(struct vcpu_vmx *vmx)
3477 {
3478         if (!enable_vpid)
3479                 return;
3480         spin_lock(&vmx_vpid_lock);
3481         if (vmx->vpid != 0)
3482                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3483         spin_unlock(&vmx_vpid_lock);
3484 }
3485
3486 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3487 {
3488         int f = sizeof(unsigned long);
3489
3490         if (!cpu_has_vmx_msr_bitmap())
3491                 return;
3492
3493         /*
3494          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3495          * have the write-low and read-high bitmap offsets the wrong way round.
3496          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3497          */
3498         if (msr <= 0x1fff) {
3499                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3500                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3501         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3502                 msr &= 0x1fff;
3503                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3504                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3505         }
3506 }
3507
3508 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3509 {
3510         if (!longmode_only)
3511                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3512         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3513 }
3514
3515 /*
3516  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3517  * will not change in the lifetime of the guest.
3518  * Note that host-state that does change is set elsewhere. E.g., host-state
3519  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3520  */
3521 static void vmx_set_constant_host_state(void)
3522 {
3523         u32 low32, high32;
3524         unsigned long tmpl;
3525         struct desc_ptr dt;
3526
3527         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3528         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3529         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3530
3531         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3532         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3533         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3534         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3535         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3536
3537         native_store_idt(&dt);
3538         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3539
3540         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3541         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3542
3543         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3544         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3545         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3546         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3547
3548         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3549                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3550                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3551         }
3552 }
3553
3554 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3555 {
3556         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3557         if (enable_ept)
3558                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3559         if (is_guest_mode(&vmx->vcpu))
3560                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3561                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3562         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3563 }
3564
3565 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3566 {
3567         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3568         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3569                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3570 #ifdef CONFIG_X86_64
3571                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3572                                 CPU_BASED_CR8_LOAD_EXITING;
3573 #endif
3574         }
3575         if (!enable_ept)
3576                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3577                                 CPU_BASED_CR3_LOAD_EXITING  |
3578                                 CPU_BASED_INVLPG_EXITING;
3579         return exec_control;
3580 }
3581
3582 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3583 {
3584         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3585         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3586                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3587         if (vmx->vpid == 0)
3588                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3589         if (!enable_ept) {
3590                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3591                 enable_unrestricted_guest = 0;
3592         }
3593         if (!enable_unrestricted_guest)
3594                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3595         if (!ple_gap)
3596                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3597         return exec_control;
3598 }
3599
3600 /*
3601  * Sets up the vmcs for emulated real mode.
3602  */
3603 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3604 {
3605 #ifdef CONFIG_X86_64
3606         unsigned long a;
3607 #endif
3608         int i;
3609
3610         /* I/O */
3611         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3612         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3613
3614         if (cpu_has_vmx_msr_bitmap())
3615                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3616
3617         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3618
3619         /* Control */
3620         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3621                 vmcs_config.pin_based_exec_ctrl);
3622
3623         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3624
3625         if (cpu_has_secondary_exec_ctrls()) {
3626                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3627                                 vmx_secondary_exec_control(vmx));
3628         }
3629
3630         if (ple_gap) {
3631                 vmcs_write32(PLE_GAP, ple_gap);
3632                 vmcs_write32(PLE_WINDOW, ple_window);
3633         }
3634
3635         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3636         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
3637         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3638
3639         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3640         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3641         vmx_set_constant_host_state();
3642 #ifdef CONFIG_X86_64
3643         rdmsrl(MSR_FS_BASE, a);
3644         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3645         rdmsrl(MSR_GS_BASE, a);
3646         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3647 #else
3648         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3649         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3650 #endif
3651
3652         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3653         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3654         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3655         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3656         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3657
3658         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3659                 u32 msr_low, msr_high;
3660                 u64 host_pat;
3661                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3662                 host_pat = msr_low | ((u64) msr_high << 32);
3663                 /* Write the default value follow host pat */
3664                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3665                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3666                 vmx->vcpu.arch.pat = host_pat;
3667         }
3668
3669         for (i = 0; i < NR_VMX_MSR; ++i) {
3670                 u32 index = vmx_msr_index[i];
3671                 u32 data_low, data_high;
3672                 int j = vmx->nmsrs;
3673
3674                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3675                         continue;
3676                 if (wrmsr_safe(index, data_low, data_high) < 0)
3677                         continue;
3678                 vmx->guest_msrs[j].index = i;
3679                 vmx->guest_msrs[j].data = 0;
3680                 vmx->guest_msrs[j].mask = -1ull;
3681                 ++vmx->nmsrs;
3682         }
3683
3684         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3685
3686         /* 22.2.1, 20.8.1 */
3687         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3688
3689         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3690         set_cr4_guest_host_mask(vmx);
3691
3692         kvm_write_tsc(&vmx->vcpu, 0);
3693
3694         return 0;
3695 }
3696
3697 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3698 {
3699         struct vcpu_vmx *vmx = to_vmx(vcpu);
3700         u64 msr;
3701         int ret;
3702
3703         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3704
3705         vmx->rmode.vm86_active = 0;
3706
3707         vmx->soft_vnmi_blocked = 0;
3708
3709         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3710         kvm_set_cr8(&vmx->vcpu, 0);
3711         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3712         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3713                 msr |= MSR_IA32_APICBASE_BSP;
3714         kvm_set_apic_base(&vmx->vcpu, msr);
3715
3716         ret = fx_init(&vmx->vcpu);
3717         if (ret != 0)
3718                 goto out;
3719
3720         vmx_segment_cache_clear(vmx);
3721
3722         seg_setup(VCPU_SREG_CS);
3723         /*
3724          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3725          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3726          */
3727         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3728                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3729                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3730         } else {
3731                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3732                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3733         }
3734
3735         seg_setup(VCPU_SREG_DS);
3736         seg_setup(VCPU_SREG_ES);
3737         seg_setup(VCPU_SREG_FS);
3738         seg_setup(VCPU_SREG_GS);
3739         seg_setup(VCPU_SREG_SS);
3740
3741         vmcs_write16(GUEST_TR_SELECTOR, 0);
3742         vmcs_writel(GUEST_TR_BASE, 0);
3743         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3744         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3745
3746         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3747         vmcs_writel(GUEST_LDTR_BASE, 0);
3748         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3749         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3750
3751         vmcs_write32(GUEST_SYSENTER_CS, 0);
3752         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3753         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3754
3755         vmcs_writel(GUEST_RFLAGS, 0x02);
3756         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3757                 kvm_rip_write(vcpu, 0xfff0);
3758         else
3759                 kvm_rip_write(vcpu, 0);
3760         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3761
3762         vmcs_writel(GUEST_DR7, 0x400);
3763
3764         vmcs_writel(GUEST_GDTR_BASE, 0);
3765         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3766
3767         vmcs_writel(GUEST_IDTR_BASE, 0);
3768         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3769
3770         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3771         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3772         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3773
3774         /* Special registers */
3775         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3776
3777         setup_msrs(vmx);
3778
3779         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3780
3781         if (cpu_has_vmx_tpr_shadow()) {
3782                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3783                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3784                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3785                                      __pa(vmx->vcpu.arch.apic->regs));
3786                 vmcs_write32(TPR_THRESHOLD, 0);
3787         }
3788
3789         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3790                 vmcs_write64(APIC_ACCESS_ADDR,
3791                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3792
3793         if (vmx->vpid != 0)
3794                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3795
3796         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3797         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3798         vmx_set_cr4(&vmx->vcpu, 0);
3799         vmx_set_efer(&vmx->vcpu, 0);
3800         vmx_fpu_activate(&vmx->vcpu);
3801         update_exception_bitmap(&vmx->vcpu);
3802
3803         vpid_sync_context(vmx);
3804
3805         ret = 0;
3806
3807         /* HACK: Don't enable emulation on guest boot/reset */
3808         vmx->emulation_required = 0;
3809
3810 out:
3811         return ret;
3812 }
3813
3814 /*
3815  * In nested virtualization, check if L1 asked to exit on external interrupts.
3816  * For most existing hypervisors, this will always return true.
3817  */
3818 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3819 {
3820         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3821                 PIN_BASED_EXT_INTR_MASK;
3822 }
3823
3824 static void enable_irq_window(struct kvm_vcpu *vcpu)
3825 {
3826         u32 cpu_based_vm_exec_control;
3827         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3828                 /* We can get here when nested_run_pending caused
3829                  * vmx_interrupt_allowed() to return false. In this case, do
3830                  * nothing - the interrupt will be injected later.
3831                  */
3832                 return;
3833
3834         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3835         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3836         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3837 }
3838
3839 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3840 {
3841         u32 cpu_based_vm_exec_control;
3842
3843         if (!cpu_has_virtual_nmis()) {
3844                 enable_irq_window(vcpu);
3845                 return;
3846         }
3847
3848         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3849                 enable_irq_window(vcpu);
3850                 return;
3851         }
3852         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3853         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3854         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3855 }
3856
3857 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3858 {
3859         struct vcpu_vmx *vmx = to_vmx(vcpu);
3860         uint32_t intr;
3861         int irq = vcpu->arch.interrupt.nr;
3862
3863         trace_kvm_inj_virq(irq);
3864
3865         ++vcpu->stat.irq_injections;
3866         if (vmx->rmode.vm86_active) {
3867                 int inc_eip = 0;
3868                 if (vcpu->arch.interrupt.soft)
3869                         inc_eip = vcpu->arch.event_exit_inst_len;
3870                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3871                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3872                 return;
3873         }
3874         intr = irq | INTR_INFO_VALID_MASK;
3875         if (vcpu->arch.interrupt.soft) {
3876                 intr |= INTR_TYPE_SOFT_INTR;
3877                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3878                              vmx->vcpu.arch.event_exit_inst_len);
3879         } else
3880                 intr |= INTR_TYPE_EXT_INTR;
3881         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3882         vmx_clear_hlt(vcpu);
3883 }
3884
3885 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3886 {
3887         struct vcpu_vmx *vmx = to_vmx(vcpu);
3888
3889         if (is_guest_mode(vcpu))
3890                 return;
3891
3892         if (!cpu_has_virtual_nmis()) {
3893                 /*
3894                  * Tracking the NMI-blocked state in software is built upon
3895                  * finding the next open IRQ window. This, in turn, depends on
3896                  * well-behaving guests: They have to keep IRQs disabled at
3897                  * least as long as the NMI handler runs. Otherwise we may
3898                  * cause NMI nesting, maybe breaking the guest. But as this is
3899                  * highly unlikely, we can live with the residual risk.
3900                  */
3901                 vmx->soft_vnmi_blocked = 1;
3902                 vmx->vnmi_blocked_time = 0;
3903         }
3904
3905         ++vcpu->stat.nmi_injections;
3906         vmx->nmi_known_unmasked = false;
3907         if (vmx->rmode.vm86_active) {
3908                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3909                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3910                 return;
3911         }
3912         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3913                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3914         vmx_clear_hlt(vcpu);
3915 }
3916
3917 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3918 {
3919         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3920                 return 0;
3921
3922         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3923                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3924                    | GUEST_INTR_STATE_NMI));
3925 }
3926
3927 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3928 {
3929         if (!cpu_has_virtual_nmis())
3930                 return to_vmx(vcpu)->soft_vnmi_blocked;
3931         if (to_vmx(vcpu)->nmi_known_unmasked)
3932                 return false;
3933         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3934 }
3935
3936 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3937 {
3938         struct vcpu_vmx *vmx = to_vmx(vcpu);
3939
3940         if (!cpu_has_virtual_nmis()) {
3941                 if (vmx->soft_vnmi_blocked != masked) {
3942                         vmx->soft_vnmi_blocked = masked;
3943                         vmx->vnmi_blocked_time = 0;
3944                 }
3945         } else {
3946                 vmx->nmi_known_unmasked = !masked;
3947                 if (masked)
3948                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3949                                       GUEST_INTR_STATE_NMI);
3950                 else
3951                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3952                                         GUEST_INTR_STATE_NMI);
3953         }
3954 }
3955
3956 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3957 {
3958         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3959                 struct vmcs12 *vmcs12;
3960                 if (to_vmx(vcpu)->nested.nested_run_pending)
3961                         return 0;
3962                 nested_vmx_vmexit(vcpu);
3963                 vmcs12 = get_vmcs12(vcpu);
3964                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3965                 vmcs12->vm_exit_intr_info = 0;
3966                 /* fall through to normal code, but now in L1, not L2 */
3967         }
3968
3969         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3970                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3971                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
3972 }
3973
3974 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3975 {
3976         int ret;
3977         struct kvm_userspace_memory_region tss_mem = {
3978                 .slot = TSS_PRIVATE_MEMSLOT,
3979                 .guest_phys_addr = addr,
3980                 .memory_size = PAGE_SIZE * 3,
3981                 .flags = 0,
3982         };
3983
3984         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3985         if (ret)
3986                 return ret;
3987         kvm->arch.tss_addr = addr;
3988         if (!init_rmode_tss(kvm))
3989                 return  -ENOMEM;
3990
3991         return 0;
3992 }
3993
3994 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3995                                   int vec, u32 err_code)
3996 {
3997         /*
3998          * Instruction with address size override prefix opcode 0x67
3999          * Cause the #SS fault with 0 error code in VM86 mode.
4000          */
4001         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4002                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4003                         return 1;
4004         /*
4005          * Forward all other exceptions that are valid in real mode.
4006          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4007          *        the required debugging infrastructure rework.
4008          */
4009         switch (vec) {
4010         case DB_VECTOR:
4011                 if (vcpu->guest_debug &
4012                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4013                         return 0;
4014                 kvm_queue_exception(vcpu, vec);
4015                 return 1;
4016         case BP_VECTOR:
4017                 /*
4018                  * Update instruction length as we may reinject the exception
4019                  * from user space while in guest debugging mode.
4020                  */
4021                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4022                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4023                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4024                         return 0;
4025                 /* fall through */
4026         case DE_VECTOR:
4027         case OF_VECTOR:
4028         case BR_VECTOR:
4029         case UD_VECTOR:
4030         case DF_VECTOR:
4031         case SS_VECTOR:
4032         case GP_VECTOR:
4033         case MF_VECTOR:
4034                 kvm_queue_exception(vcpu, vec);
4035                 return 1;
4036         }
4037         return 0;
4038 }
4039
4040 /*
4041  * Trigger machine check on the host. We assume all the MSRs are already set up
4042  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4043  * We pass a fake environment to the machine check handler because we want
4044  * the guest to be always treated like user space, no matter what context
4045  * it used internally.
4046  */
4047 static void kvm_machine_check(void)
4048 {
4049 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4050         struct pt_regs regs = {
4051                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4052                 .flags = X86_EFLAGS_IF,
4053         };
4054
4055         do_machine_check(&regs, 0);
4056 #endif
4057 }
4058
4059 static int handle_machine_check(struct kvm_vcpu *vcpu)
4060 {
4061         /* already handled by vcpu_run */
4062         return 1;
4063 }
4064
4065 static int handle_exception(struct kvm_vcpu *vcpu)
4066 {
4067         struct vcpu_vmx *vmx = to_vmx(vcpu);
4068         struct kvm_run *kvm_run = vcpu->run;
4069         u32 intr_info, ex_no, error_code;
4070         unsigned long cr2, rip, dr6;
4071         u32 vect_info;
4072         enum emulation_result er;
4073
4074         vect_info = vmx->idt_vectoring_info;
4075         intr_info = vmx->exit_intr_info;
4076
4077         if (is_machine_check(intr_info))
4078                 return handle_machine_check(vcpu);
4079
4080         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4081             !is_page_fault(intr_info)) {
4082                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4083                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4084                 vcpu->run->internal.ndata = 2;
4085                 vcpu->run->internal.data[0] = vect_info;
4086                 vcpu->run->internal.data[1] = intr_info;
4087                 return 0;
4088         }
4089
4090         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4091                 return 1;  /* already handled by vmx_vcpu_run() */
4092
4093         if (is_no_device(intr_info)) {
4094                 vmx_fpu_activate(vcpu);
4095                 return 1;
4096         }
4097
4098         if (is_invalid_opcode(intr_info)) {
4099                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4100                 if (er != EMULATE_DONE)
4101                         kvm_queue_exception(vcpu, UD_VECTOR);
4102                 return 1;
4103         }
4104
4105         error_code = 0;
4106         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4107                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4108         if (is_page_fault(intr_info)) {
4109                 /* EPT won't cause page fault directly */
4110                 if (enable_ept)
4111                         BUG();
4112                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4113                 trace_kvm_page_fault(cr2, error_code);
4114
4115                 if (kvm_event_needs_reinjection(vcpu))
4116                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4117                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4118         }
4119
4120         if (vmx->rmode.vm86_active &&
4121             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4122                                                                 error_code)) {
4123                 if (vcpu->arch.halt_request) {
4124                         vcpu->arch.halt_request = 0;
4125                         return kvm_emulate_halt(vcpu);
4126                 }
4127                 return 1;
4128         }
4129
4130         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4131         switch (ex_no) {
4132         case DB_VECTOR:
4133                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4134                 if (!(vcpu->guest_debug &
4135                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4136                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4137                         kvm_queue_exception(vcpu, DB_VECTOR);
4138                         return 1;
4139                 }
4140                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4141                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4142                 /* fall through */
4143         case BP_VECTOR:
4144                 /*
4145                  * Update instruction length as we may reinject #BP from
4146                  * user space while in guest debugging mode. Reading it for
4147                  * #DB as well causes no harm, it is not used in that case.
4148                  */
4149                 vmx->vcpu.arch.event_exit_inst_len =
4150                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4151                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4152                 rip = kvm_rip_read(vcpu);
4153                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4154                 kvm_run->debug.arch.exception = ex_no;
4155                 break;
4156         default:
4157                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4158                 kvm_run->ex.exception = ex_no;
4159                 kvm_run->ex.error_code = error_code;
4160                 break;
4161         }
4162         return 0;
4163 }
4164
4165 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4166 {
4167         ++vcpu->stat.irq_exits;
4168         return 1;
4169 }
4170
4171 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4172 {
4173         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4174         return 0;
4175 }
4176
4177 static int handle_io(struct kvm_vcpu *vcpu)
4178 {
4179         unsigned long exit_qualification;
4180         int size, in, string;
4181         unsigned port;
4182
4183         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4184         string = (exit_qualification & 16) != 0;
4185         in = (exit_qualification & 8) != 0;
4186
4187         ++vcpu->stat.io_exits;
4188
4189         if (string || in)
4190                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4191
4192         port = exit_qualification >> 16;
4193         size = (exit_qualification & 7) + 1;
4194         skip_emulated_instruction(vcpu);
4195
4196         return kvm_fast_pio_out(vcpu, size, port);
4197 }
4198
4199 static void
4200 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4201 {
4202         /*
4203          * Patch in the VMCALL instruction:
4204          */
4205         hypercall[0] = 0x0f;
4206         hypercall[1] = 0x01;
4207         hypercall[2] = 0xc1;
4208 }
4209
4210 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4211 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4212 {
4213         if (to_vmx(vcpu)->nested.vmxon &&
4214             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4215                 return 1;
4216
4217         if (is_guest_mode(vcpu)) {
4218                 /*
4219                  * We get here when L2 changed cr0 in a way that did not change
4220                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4221                  * but did change L0 shadowed bits. This can currently happen
4222                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4223                  * loading) while pretending to allow the guest to change it.
4224                  */
4225                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4226                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4227                         return 1;
4228                 vmcs_writel(CR0_READ_SHADOW, val);
4229                 return 0;
4230         } else
4231                 return kvm_set_cr0(vcpu, val);
4232 }
4233
4234 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4235 {
4236         if (is_guest_mode(vcpu)) {
4237                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4238                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4239                         return 1;
4240                 vmcs_writel(CR4_READ_SHADOW, val);
4241                 return 0;
4242         } else
4243                 return kvm_set_cr4(vcpu, val);
4244 }
4245
4246 /* called to set cr0 as approriate for clts instruction exit. */
4247 static void handle_clts(struct kvm_vcpu *vcpu)
4248 {
4249         if (is_guest_mode(vcpu)) {
4250                 /*
4251                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4252                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4253                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4254                  */
4255                 vmcs_writel(CR0_READ_SHADOW,
4256                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4257                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4258         } else
4259                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4260 }
4261
4262 static int handle_cr(struct kvm_vcpu *vcpu)
4263 {
4264         unsigned long exit_qualification, val;
4265         int cr;
4266         int reg;
4267         int err;
4268
4269         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4270         cr = exit_qualification & 15;
4271         reg = (exit_qualification >> 8) & 15;
4272         switch ((exit_qualification >> 4) & 3) {
4273         case 0: /* mov to cr */
4274                 val = kvm_register_read(vcpu, reg);
4275                 trace_kvm_cr_write(cr, val);
4276                 switch (cr) {
4277                 case 0:
4278                         err = handle_set_cr0(vcpu, val);
4279                         kvm_complete_insn_gp(vcpu, err);
4280                         return 1;
4281                 case 3:
4282                         err = kvm_set_cr3(vcpu, val);
4283                         kvm_complete_insn_gp(vcpu, err);
4284                         return 1;
4285                 case 4:
4286                         err = handle_set_cr4(vcpu, val);
4287                         kvm_complete_insn_gp(vcpu, err);
4288                         return 1;
4289                 case 8: {
4290                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4291                                 u8 cr8 = kvm_register_read(vcpu, reg);
4292                                 err = kvm_set_cr8(vcpu, cr8);
4293                                 kvm_complete_insn_gp(vcpu, err);
4294                                 if (irqchip_in_kernel(vcpu->kvm))
4295                                         return 1;
4296                                 if (cr8_prev <= cr8)
4297                                         return 1;
4298                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4299                                 return 0;
4300                         }
4301                 };
4302                 break;
4303         case 2: /* clts */
4304                 handle_clts(vcpu);
4305                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4306                 skip_emulated_instruction(vcpu);
4307                 vmx_fpu_activate(vcpu);
4308                 return 1;
4309         case 1: /*mov from cr*/
4310                 switch (cr) {
4311                 case 3:
4312                         val = kvm_read_cr3(vcpu);
4313                         kvm_register_write(vcpu, reg, val);
4314                         trace_kvm_cr_read(cr, val);
4315                         skip_emulated_instruction(vcpu);
4316                         return 1;
4317                 case 8:
4318                         val = kvm_get_cr8(vcpu);
4319                         kvm_register_write(vcpu, reg, val);
4320                         trace_kvm_cr_read(cr, val);
4321                         skip_emulated_instruction(vcpu);
4322                         return 1;
4323                 }
4324                 break;
4325         case 3: /* lmsw */
4326                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4327                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4328                 kvm_lmsw(vcpu, val);
4329
4330                 skip_emulated_instruction(vcpu);
4331                 return 1;
4332         default:
4333                 break;
4334         }
4335         vcpu->run->exit_reason = 0;
4336         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4337                (int)(exit_qualification >> 4) & 3, cr);
4338         return 0;
4339 }
4340
4341 static int handle_dr(struct kvm_vcpu *vcpu)
4342 {
4343         unsigned long exit_qualification;
4344         int dr, reg;
4345
4346         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4347         if (!kvm_require_cpl(vcpu, 0))
4348                 return 1;
4349         dr = vmcs_readl(GUEST_DR7);
4350         if (dr & DR7_GD) {
4351                 /*
4352                  * As the vm-exit takes precedence over the debug trap, we
4353                  * need to emulate the latter, either for the host or the
4354                  * guest debugging itself.
4355                  */
4356                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4357                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4358                         vcpu->run->debug.arch.dr7 = dr;
4359                         vcpu->run->debug.arch.pc =
4360                                 vmcs_readl(GUEST_CS_BASE) +
4361                                 vmcs_readl(GUEST_RIP);
4362                         vcpu->run->debug.arch.exception = DB_VECTOR;
4363                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4364                         return 0;
4365                 } else {
4366                         vcpu->arch.dr7 &= ~DR7_GD;
4367                         vcpu->arch.dr6 |= DR6_BD;
4368                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4369                         kvm_queue_exception(vcpu, DB_VECTOR);
4370                         return 1;
4371                 }
4372         }
4373
4374         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4375         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4376         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4377         if (exit_qualification & TYPE_MOV_FROM_DR) {
4378                 unsigned long val;
4379                 if (!kvm_get_dr(vcpu, dr, &val))
4380                         kvm_register_write(vcpu, reg, val);
4381         } else
4382                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4383         skip_emulated_instruction(vcpu);
4384         return 1;
4385 }
4386
4387 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4388 {
4389         vmcs_writel(GUEST_DR7, val);
4390 }
4391
4392 static int handle_cpuid(struct kvm_vcpu *vcpu)
4393 {
4394         kvm_emulate_cpuid(vcpu);
4395         return 1;
4396 }
4397
4398 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4399 {
4400         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4401         u64 data;
4402
4403         if (vmx_get_msr(vcpu, ecx, &data)) {
4404                 trace_kvm_msr_read_ex(ecx);
4405                 kvm_inject_gp(vcpu, 0);
4406                 return 1;
4407         }
4408
4409         trace_kvm_msr_read(ecx, data);
4410
4411         /* FIXME: handling of bits 32:63 of rax, rdx */
4412         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4413         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4414         skip_emulated_instruction(vcpu);
4415         return 1;
4416 }
4417
4418 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4419 {
4420         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4421         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4422                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4423
4424         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4425                 trace_kvm_msr_write_ex(ecx, data);
4426                 kvm_inject_gp(vcpu, 0);
4427                 return 1;
4428         }
4429
4430         trace_kvm_msr_write(ecx, data);
4431         skip_emulated_instruction(vcpu);
4432         return 1;
4433 }
4434
4435 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4436 {
4437         kvm_make_request(KVM_REQ_EVENT, vcpu);
4438         return 1;
4439 }
4440
4441 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4442 {
4443         u32 cpu_based_vm_exec_control;
4444
4445         /* clear pending irq */
4446         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4447         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4448         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4449
4450         kvm_make_request(KVM_REQ_EVENT, vcpu);
4451
4452         ++vcpu->stat.irq_window_exits;
4453
4454         /*
4455          * If the user space waits to inject interrupts, exit as soon as
4456          * possible
4457          */
4458         if (!irqchip_in_kernel(vcpu->kvm) &&
4459             vcpu->run->request_interrupt_window &&
4460             !kvm_cpu_has_interrupt(vcpu)) {
4461                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4462                 return 0;
4463         }
4464         return 1;
4465 }
4466
4467 static int handle_halt(struct kvm_vcpu *vcpu)
4468 {
4469         skip_emulated_instruction(vcpu);
4470         return kvm_emulate_halt(vcpu);
4471 }
4472
4473 static int handle_vmcall(struct kvm_vcpu *vcpu)
4474 {
4475         skip_emulated_instruction(vcpu);
4476         kvm_emulate_hypercall(vcpu);
4477         return 1;
4478 }
4479
4480 static int handle_invd(struct kvm_vcpu *vcpu)
4481 {
4482         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4483 }
4484
4485 static int handle_invlpg(struct kvm_vcpu *vcpu)
4486 {
4487         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4488
4489         kvm_mmu_invlpg(vcpu, exit_qualification);
4490         skip_emulated_instruction(vcpu);
4491         return 1;
4492 }
4493
4494 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4495 {
4496         skip_emulated_instruction(vcpu);
4497         kvm_emulate_wbinvd(vcpu);
4498         return 1;
4499 }
4500
4501 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4502 {
4503         u64 new_bv = kvm_read_edx_eax(vcpu);
4504         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4505
4506         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4507                 skip_emulated_instruction(vcpu);
4508         return 1;
4509 }
4510
4511 static int handle_apic_access(struct kvm_vcpu *vcpu)
4512 {
4513         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4514 }
4515
4516 static int handle_task_switch(struct kvm_vcpu *vcpu)
4517 {
4518         struct vcpu_vmx *vmx = to_vmx(vcpu);
4519         unsigned long exit_qualification;
4520         bool has_error_code = false;
4521         u32 error_code = 0;
4522         u16 tss_selector;
4523         int reason, type, idt_v;
4524
4525         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4526         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4527
4528         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4529
4530         reason = (u32)exit_qualification >> 30;
4531         if (reason == TASK_SWITCH_GATE && idt_v) {
4532                 switch (type) {
4533                 case INTR_TYPE_NMI_INTR:
4534                         vcpu->arch.nmi_injected = false;
4535                         vmx_set_nmi_mask(vcpu, true);
4536                         break;
4537                 case INTR_TYPE_EXT_INTR:
4538                 case INTR_TYPE_SOFT_INTR:
4539                         kvm_clear_interrupt_queue(vcpu);
4540                         break;
4541                 case INTR_TYPE_HARD_EXCEPTION:
4542                         if (vmx->idt_vectoring_info &
4543                             VECTORING_INFO_DELIVER_CODE_MASK) {
4544                                 has_error_code = true;
4545                                 error_code =
4546                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4547                         }
4548                         /* fall through */
4549                 case INTR_TYPE_SOFT_EXCEPTION:
4550                         kvm_clear_exception_queue(vcpu);
4551                         break;
4552                 default:
4553                         break;
4554                 }
4555         }
4556         tss_selector = exit_qualification;
4557
4558         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4559                        type != INTR_TYPE_EXT_INTR &&
4560                        type != INTR_TYPE_NMI_INTR))
4561                 skip_emulated_instruction(vcpu);
4562
4563         if (kvm_task_switch(vcpu, tss_selector, reason,
4564                                 has_error_code, error_code) == EMULATE_FAIL) {
4565                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4566                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4567                 vcpu->run->internal.ndata = 0;
4568                 return 0;
4569         }
4570
4571         /* clear all local breakpoint enable flags */
4572         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4573
4574         /*
4575          * TODO: What about debug traps on tss switch?
4576          *       Are we supposed to inject them and update dr6?
4577          */
4578
4579         return 1;
4580 }
4581
4582 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4583 {
4584         unsigned long exit_qualification;
4585         gpa_t gpa;
4586         int gla_validity;
4587
4588         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4589
4590         if (exit_qualification & (1 << 6)) {
4591                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4592                 return -EINVAL;
4593         }
4594
4595         gla_validity = (exit_qualification >> 7) & 0x3;
4596         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4597                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4598                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4599                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4600                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4601                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4602                         (long unsigned int)exit_qualification);
4603                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4604                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4605                 return 0;
4606         }
4607
4608         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4609         trace_kvm_page_fault(gpa, exit_qualification);
4610         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4611 }
4612
4613 static u64 ept_rsvd_mask(u64 spte, int level)
4614 {
4615         int i;
4616         u64 mask = 0;
4617
4618         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4619                 mask |= (1ULL << i);
4620
4621         if (level > 2)
4622                 /* bits 7:3 reserved */
4623                 mask |= 0xf8;
4624         else if (level == 2) {
4625                 if (spte & (1ULL << 7))
4626                         /* 2MB ref, bits 20:12 reserved */
4627                         mask |= 0x1ff000;
4628                 else
4629                         /* bits 6:3 reserved */
4630                         mask |= 0x78;
4631         }
4632
4633         return mask;
4634 }
4635
4636 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4637                                        int level)
4638 {
4639         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4640
4641         /* 010b (write-only) */
4642         WARN_ON((spte & 0x7) == 0x2);
4643
4644         /* 110b (write/execute) */
4645         WARN_ON((spte & 0x7) == 0x6);
4646
4647         /* 100b (execute-only) and value not supported by logical processor */
4648         if (!cpu_has_vmx_ept_execute_only())
4649                 WARN_ON((spte & 0x7) == 0x4);
4650
4651         /* not 000b */
4652         if ((spte & 0x7)) {
4653                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4654
4655                 if (rsvd_bits != 0) {
4656                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4657                                          __func__, rsvd_bits);
4658                         WARN_ON(1);
4659                 }
4660
4661                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4662                         u64 ept_mem_type = (spte & 0x38) >> 3;
4663
4664                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4665                             ept_mem_type == 7) {
4666                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4667                                                 __func__, ept_mem_type);
4668                                 WARN_ON(1);
4669                         }
4670                 }
4671         }
4672 }
4673
4674 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4675 {
4676         u64 sptes[4];
4677         int nr_sptes, i;
4678         gpa_t gpa;
4679
4680         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4681
4682         printk(KERN_ERR "EPT: Misconfiguration.\n");
4683         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4684
4685         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4686
4687         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4688                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4689
4690         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4691         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4692
4693         return 0;
4694 }
4695
4696 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4697 {
4698         u32 cpu_based_vm_exec_control;
4699
4700         /* clear pending NMI */
4701         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4702         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4703         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4704         ++vcpu->stat.nmi_window_exits;
4705         kvm_make_request(KVM_REQ_EVENT, vcpu);
4706
4707         return 1;
4708 }
4709
4710 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4711 {
4712         struct vcpu_vmx *vmx = to_vmx(vcpu);
4713         enum emulation_result err = EMULATE_DONE;
4714         int ret = 1;
4715         u32 cpu_exec_ctrl;
4716         bool intr_window_requested;
4717
4718         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4719         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4720
4721         while (!guest_state_valid(vcpu)) {
4722                 if (intr_window_requested
4723                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4724                         return handle_interrupt_window(&vmx->vcpu);
4725
4726                 err = emulate_instruction(vcpu, 0);
4727
4728                 if (err == EMULATE_DO_MMIO) {
4729                         ret = 0;
4730                         goto out;
4731                 }
4732
4733                 if (err != EMULATE_DONE)
4734                         return 0;
4735
4736                 if (signal_pending(current))
4737                         goto out;
4738                 if (need_resched())
4739                         schedule();
4740         }
4741
4742         vmx->emulation_required = 0;
4743 out:
4744         return ret;
4745 }
4746
4747 /*
4748  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4749  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4750  */
4751 static int handle_pause(struct kvm_vcpu *vcpu)
4752 {
4753         skip_emulated_instruction(vcpu);
4754         kvm_vcpu_on_spin(vcpu);
4755
4756         return 1;
4757 }
4758
4759 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4760 {
4761         kvm_queue_exception(vcpu, UD_VECTOR);
4762         return 1;
4763 }
4764
4765 /*
4766  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4767  * We could reuse a single VMCS for all the L2 guests, but we also want the
4768  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4769  * allows keeping them loaded on the processor, and in the future will allow
4770  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4771  * every entry if they never change.
4772  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4773  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4774  *
4775  * The following functions allocate and free a vmcs02 in this pool.
4776  */
4777
4778 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4779 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4780 {
4781         struct vmcs02_list *item;
4782         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4783                 if (item->vmptr == vmx->nested.current_vmptr) {
4784                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4785                         return &item->vmcs02;
4786                 }
4787
4788         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4789                 /* Recycle the least recently used VMCS. */
4790                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4791                         struct vmcs02_list, list);
4792                 item->vmptr = vmx->nested.current_vmptr;
4793                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4794                 return &item->vmcs02;
4795         }
4796
4797         /* Create a new VMCS */
4798         item = (struct vmcs02_list *)
4799                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4800         if (!item)
4801                 return NULL;
4802         item->vmcs02.vmcs = alloc_vmcs();
4803         if (!item->vmcs02.vmcs) {
4804                 kfree(item);
4805                 return NULL;
4806         }
4807         loaded_vmcs_init(&item->vmcs02);
4808         item->vmptr = vmx->nested.current_vmptr;
4809         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4810         vmx->nested.vmcs02_num++;
4811         return &item->vmcs02;
4812 }
4813
4814 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4815 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4816 {
4817         struct vmcs02_list *item;
4818         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4819                 if (item->vmptr == vmptr) {
4820                         free_loaded_vmcs(&item->vmcs02);
4821                         list_del(&item->list);
4822                         kfree(item);
4823                         vmx->nested.vmcs02_num--;
4824                         return;
4825                 }
4826 }
4827
4828 /*
4829  * Free all VMCSs saved for this vcpu, except the one pointed by
4830  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4831  * currently used, if running L2), and vmcs01 when running L2.
4832  */
4833 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4834 {
4835         struct vmcs02_list *item, *n;
4836         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4837                 if (vmx->loaded_vmcs != &item->vmcs02)
4838                         free_loaded_vmcs(&item->vmcs02);
4839                 list_del(&item->list);
4840                 kfree(item);
4841         }
4842         vmx->nested.vmcs02_num = 0;
4843
4844         if (vmx->loaded_vmcs != &vmx->vmcs01)
4845                 free_loaded_vmcs(&vmx->vmcs01);
4846 }
4847
4848 /*
4849  * Emulate the VMXON instruction.
4850  * Currently, we just remember that VMX is active, and do not save or even
4851  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4852  * do not currently need to store anything in that guest-allocated memory
4853  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4854  * argument is different from the VMXON pointer (which the spec says they do).
4855  */
4856 static int handle_vmon(struct kvm_vcpu *vcpu)
4857 {
4858         struct kvm_segment cs;
4859         struct vcpu_vmx *vmx = to_vmx(vcpu);
4860
4861         /* The Intel VMX Instruction Reference lists a bunch of bits that
4862          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4863          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4864          * Otherwise, we should fail with #UD. We test these now:
4865          */
4866         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4867             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4868             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4869                 kvm_queue_exception(vcpu, UD_VECTOR);
4870                 return 1;
4871         }
4872
4873         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4874         if (is_long_mode(vcpu) && !cs.l) {
4875                 kvm_queue_exception(vcpu, UD_VECTOR);
4876                 return 1;
4877         }
4878
4879         if (vmx_get_cpl(vcpu)) {
4880                 kvm_inject_gp(vcpu, 0);
4881                 return 1;
4882         }
4883
4884         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4885         vmx->nested.vmcs02_num = 0;
4886
4887         vmx->nested.vmxon = true;
4888
4889         skip_emulated_instruction(vcpu);
4890         return 1;
4891 }
4892
4893 /*
4894  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4895  * for running VMX instructions (except VMXON, whose prerequisites are
4896  * slightly different). It also specifies what exception to inject otherwise.
4897  */
4898 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4899 {
4900         struct kvm_segment cs;
4901         struct vcpu_vmx *vmx = to_vmx(vcpu);
4902
4903         if (!vmx->nested.vmxon) {
4904                 kvm_queue_exception(vcpu, UD_VECTOR);
4905                 return 0;
4906         }
4907
4908         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4909         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4910             (is_long_mode(vcpu) && !cs.l)) {
4911                 kvm_queue_exception(vcpu, UD_VECTOR);
4912                 return 0;
4913         }
4914
4915         if (vmx_get_cpl(vcpu)) {
4916                 kvm_inject_gp(vcpu, 0);
4917                 return 0;
4918         }
4919
4920         return 1;
4921 }
4922
4923 /*
4924  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4925  * just stops using VMX.
4926  */
4927 static void free_nested(struct vcpu_vmx *vmx)
4928 {
4929         if (!vmx->nested.vmxon)
4930                 return;
4931         vmx->nested.vmxon = false;
4932         if (vmx->nested.current_vmptr != -1ull) {
4933                 kunmap(vmx->nested.current_vmcs12_page);
4934                 nested_release_page(vmx->nested.current_vmcs12_page);
4935                 vmx->nested.current_vmptr = -1ull;
4936                 vmx->nested.current_vmcs12 = NULL;
4937         }
4938         /* Unpin physical memory we referred to in current vmcs02 */
4939         if (vmx->nested.apic_access_page) {
4940                 nested_release_page(vmx->nested.apic_access_page);
4941                 vmx->nested.apic_access_page = 0;
4942         }
4943
4944         nested_free_all_saved_vmcss(vmx);
4945 }
4946
4947 /* Emulate the VMXOFF instruction */
4948 static int handle_vmoff(struct kvm_vcpu *vcpu)
4949 {
4950         if (!nested_vmx_check_permission(vcpu))
4951                 return 1;
4952         free_nested(to_vmx(vcpu));
4953         skip_emulated_instruction(vcpu);
4954         return 1;
4955 }
4956
4957 /*
4958  * Decode the memory-address operand of a vmx instruction, as recorded on an
4959  * exit caused by such an instruction (run by a guest hypervisor).
4960  * On success, returns 0. When the operand is invalid, returns 1 and throws
4961  * #UD or #GP.
4962  */
4963 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4964                                  unsigned long exit_qualification,
4965                                  u32 vmx_instruction_info, gva_t *ret)
4966 {
4967         /*
4968          * According to Vol. 3B, "Information for VM Exits Due to Instruction
4969          * Execution", on an exit, vmx_instruction_info holds most of the
4970          * addressing components of the operand. Only the displacement part
4971          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4972          * For how an actual address is calculated from all these components,
4973          * refer to Vol. 1, "Operand Addressing".
4974          */
4975         int  scaling = vmx_instruction_info & 3;
4976         int  addr_size = (vmx_instruction_info >> 7) & 7;
4977         bool is_reg = vmx_instruction_info & (1u << 10);
4978         int  seg_reg = (vmx_instruction_info >> 15) & 7;
4979         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
4980         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4981         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
4982         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
4983
4984         if (is_reg) {
4985                 kvm_queue_exception(vcpu, UD_VECTOR);
4986                 return 1;
4987         }
4988
4989         /* Addr = segment_base + offset */
4990         /* offset = base + [index * scale] + displacement */
4991         *ret = vmx_get_segment_base(vcpu, seg_reg);
4992         if (base_is_valid)
4993                 *ret += kvm_register_read(vcpu, base_reg);
4994         if (index_is_valid)
4995                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4996         *ret += exit_qualification; /* holds the displacement */
4997
4998         if (addr_size == 1) /* 32 bit */
4999                 *ret &= 0xffffffff;
5000
5001         /*
5002          * TODO: throw #GP (and return 1) in various cases that the VM*
5003          * instructions require it - e.g., offset beyond segment limit,
5004          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5005          * address, and so on. Currently these are not checked.
5006          */
5007         return 0;
5008 }
5009
5010 /*
5011  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5012  * set the success or error code of an emulated VMX instruction, as specified
5013  * by Vol 2B, VMX Instruction Reference, "Conventions".
5014  */
5015 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5016 {
5017         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5018                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5019                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5020 }
5021
5022 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5023 {
5024         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5025                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5026                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5027                         | X86_EFLAGS_CF);
5028 }
5029
5030 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5031                                         u32 vm_instruction_error)
5032 {
5033         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5034                 /*
5035                  * failValid writes the error number to the current VMCS, which
5036                  * can't be done there isn't a current VMCS.
5037                  */
5038                 nested_vmx_failInvalid(vcpu);
5039                 return;
5040         }
5041         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5042                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5043                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5044                         | X86_EFLAGS_ZF);
5045         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5046 }
5047
5048 /* Emulate the VMCLEAR instruction */
5049 static int handle_vmclear(struct kvm_vcpu *vcpu)
5050 {
5051         struct vcpu_vmx *vmx = to_vmx(vcpu);
5052         gva_t gva;
5053         gpa_t vmptr;
5054         struct vmcs12 *vmcs12;
5055         struct page *page;
5056         struct x86_exception e;
5057
5058         if (!nested_vmx_check_permission(vcpu))
5059                 return 1;
5060
5061         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5062                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5063                 return 1;
5064
5065         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5066                                 sizeof(vmptr), &e)) {
5067                 kvm_inject_page_fault(vcpu, &e);
5068                 return 1;
5069         }
5070
5071         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5072                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5073                 skip_emulated_instruction(vcpu);
5074                 return 1;
5075         }
5076
5077         if (vmptr == vmx->nested.current_vmptr) {
5078                 kunmap(vmx->nested.current_vmcs12_page);
5079                 nested_release_page(vmx->nested.current_vmcs12_page);
5080                 vmx->nested.current_vmptr = -1ull;
5081                 vmx->nested.current_vmcs12 = NULL;
5082         }
5083
5084         page = nested_get_page(vcpu, vmptr);
5085         if (page == NULL) {
5086                 /*
5087                  * For accurate processor emulation, VMCLEAR beyond available
5088                  * physical memory should do nothing at all. However, it is
5089                  * possible that a nested vmx bug, not a guest hypervisor bug,
5090                  * resulted in this case, so let's shut down before doing any
5091                  * more damage:
5092                  */
5093                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5094                 return 1;
5095         }
5096         vmcs12 = kmap(page);
5097         vmcs12->launch_state = 0;
5098         kunmap(page);
5099         nested_release_page(page);
5100
5101         nested_free_vmcs02(vmx, vmptr);
5102
5103         skip_emulated_instruction(vcpu);
5104         nested_vmx_succeed(vcpu);
5105         return 1;
5106 }
5107
5108 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5109
5110 /* Emulate the VMLAUNCH instruction */
5111 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5112 {
5113         return nested_vmx_run(vcpu, true);
5114 }
5115
5116 /* Emulate the VMRESUME instruction */
5117 static int handle_vmresume(struct kvm_vcpu *vcpu)
5118 {
5119
5120         return nested_vmx_run(vcpu, false);
5121 }
5122
5123 enum vmcs_field_type {
5124         VMCS_FIELD_TYPE_U16 = 0,
5125         VMCS_FIELD_TYPE_U64 = 1,
5126         VMCS_FIELD_TYPE_U32 = 2,
5127         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5128 };
5129
5130 static inline int vmcs_field_type(unsigned long field)
5131 {
5132         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5133                 return VMCS_FIELD_TYPE_U32;
5134         return (field >> 13) & 0x3 ;
5135 }
5136
5137 static inline int vmcs_field_readonly(unsigned long field)
5138 {
5139         return (((field >> 10) & 0x3) == 1);
5140 }
5141
5142 /*
5143  * Read a vmcs12 field. Since these can have varying lengths and we return
5144  * one type, we chose the biggest type (u64) and zero-extend the return value
5145  * to that size. Note that the caller, handle_vmread, might need to use only
5146  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5147  * 64-bit fields are to be returned).
5148  */
5149 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5150                                         unsigned long field, u64 *ret)
5151 {
5152         short offset = vmcs_field_to_offset(field);
5153         char *p;
5154
5155         if (offset < 0)
5156                 return 0;
5157
5158         p = ((char *)(get_vmcs12(vcpu))) + offset;
5159
5160         switch (vmcs_field_type(field)) {
5161         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5162                 *ret = *((natural_width *)p);
5163                 return 1;
5164         case VMCS_FIELD_TYPE_U16:
5165                 *ret = *((u16 *)p);
5166                 return 1;
5167         case VMCS_FIELD_TYPE_U32:
5168                 *ret = *((u32 *)p);
5169                 return 1;
5170         case VMCS_FIELD_TYPE_U64:
5171                 *ret = *((u64 *)p);
5172                 return 1;
5173         default:
5174                 return 0; /* can never happen. */
5175         }
5176 }
5177
5178 /*
5179  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5180  * used before) all generate the same failure when it is missing.
5181  */
5182 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5183 {
5184         struct vcpu_vmx *vmx = to_vmx(vcpu);
5185         if (vmx->nested.current_vmptr == -1ull) {
5186                 nested_vmx_failInvalid(vcpu);
5187                 skip_emulated_instruction(vcpu);
5188                 return 0;
5189         }
5190         return 1;
5191 }
5192
5193 static int handle_vmread(struct kvm_vcpu *vcpu)
5194 {
5195         unsigned long field;
5196         u64 field_value;
5197         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5198         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5199         gva_t gva = 0;
5200
5201         if (!nested_vmx_check_permission(vcpu) ||
5202             !nested_vmx_check_vmcs12(vcpu))
5203                 return 1;
5204
5205         /* Decode instruction info and find the field to read */
5206         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5207         /* Read the field, zero-extended to a u64 field_value */
5208         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5209                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5210                 skip_emulated_instruction(vcpu);
5211                 return 1;
5212         }
5213         /*
5214          * Now copy part of this value to register or memory, as requested.
5215          * Note that the number of bits actually copied is 32 or 64 depending
5216          * on the guest's mode (32 or 64 bit), not on the given field's length.
5217          */
5218         if (vmx_instruction_info & (1u << 10)) {
5219                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5220                         field_value);
5221         } else {
5222                 if (get_vmx_mem_address(vcpu, exit_qualification,
5223                                 vmx_instruction_info, &gva))
5224                         return 1;
5225                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5226                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5227                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5228         }
5229
5230         nested_vmx_succeed(vcpu);
5231         skip_emulated_instruction(vcpu);
5232         return 1;
5233 }
5234
5235
5236 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5237 {
5238         unsigned long field;
5239         gva_t gva;
5240         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5241         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5242         char *p;
5243         short offset;
5244         /* The value to write might be 32 or 64 bits, depending on L1's long
5245          * mode, and eventually we need to write that into a field of several
5246          * possible lengths. The code below first zero-extends the value to 64
5247          * bit (field_value), and then copies only the approriate number of
5248          * bits into the vmcs12 field.
5249          */
5250         u64 field_value = 0;
5251         struct x86_exception e;
5252
5253         if (!nested_vmx_check_permission(vcpu) ||
5254             !nested_vmx_check_vmcs12(vcpu))
5255                 return 1;
5256
5257         if (vmx_instruction_info & (1u << 10))
5258                 field_value = kvm_register_read(vcpu,
5259                         (((vmx_instruction_info) >> 3) & 0xf));
5260         else {
5261                 if (get_vmx_mem_address(vcpu, exit_qualification,
5262                                 vmx_instruction_info, &gva))
5263                         return 1;
5264                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5265                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5266                         kvm_inject_page_fault(vcpu, &e);
5267                         return 1;
5268                 }
5269         }
5270
5271
5272         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5273         if (vmcs_field_readonly(field)) {
5274                 nested_vmx_failValid(vcpu,
5275                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5276                 skip_emulated_instruction(vcpu);
5277                 return 1;
5278         }
5279
5280         offset = vmcs_field_to_offset(field);
5281         if (offset < 0) {
5282                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5283                 skip_emulated_instruction(vcpu);
5284                 return 1;
5285         }
5286         p = ((char *) get_vmcs12(vcpu)) + offset;
5287
5288         switch (vmcs_field_type(field)) {
5289         case VMCS_FIELD_TYPE_U16:
5290                 *(u16 *)p = field_value;
5291                 break;
5292         case VMCS_FIELD_TYPE_U32:
5293                 *(u32 *)p = field_value;
5294                 break;
5295         case VMCS_FIELD_TYPE_U64:
5296                 *(u64 *)p = field_value;
5297                 break;
5298         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5299                 *(natural_width *)p = field_value;
5300                 break;
5301         default:
5302                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5303                 skip_emulated_instruction(vcpu);
5304                 return 1;
5305         }
5306
5307         nested_vmx_succeed(vcpu);
5308         skip_emulated_instruction(vcpu);
5309         return 1;
5310 }
5311
5312 /* Emulate the VMPTRLD instruction */
5313 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5314 {
5315         struct vcpu_vmx *vmx = to_vmx(vcpu);
5316         gva_t gva;
5317         gpa_t vmptr;
5318         struct x86_exception e;
5319
5320         if (!nested_vmx_check_permission(vcpu))
5321                 return 1;
5322
5323         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5324                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5325                 return 1;
5326
5327         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5328                                 sizeof(vmptr), &e)) {
5329                 kvm_inject_page_fault(vcpu, &e);
5330                 return 1;
5331         }
5332
5333         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5334                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5335                 skip_emulated_instruction(vcpu);
5336                 return 1;
5337         }
5338
5339         if (vmx->nested.current_vmptr != vmptr) {
5340                 struct vmcs12 *new_vmcs12;
5341                 struct page *page;
5342                 page = nested_get_page(vcpu, vmptr);
5343                 if (page == NULL) {
5344                         nested_vmx_failInvalid(vcpu);
5345                         skip_emulated_instruction(vcpu);
5346                         return 1;
5347                 }
5348                 new_vmcs12 = kmap(page);
5349                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5350                         kunmap(page);
5351                         nested_release_page_clean(page);
5352                         nested_vmx_failValid(vcpu,
5353                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5354                         skip_emulated_instruction(vcpu);
5355                         return 1;
5356                 }
5357                 if (vmx->nested.current_vmptr != -1ull) {
5358                         kunmap(vmx->nested.current_vmcs12_page);
5359                         nested_release_page(vmx->nested.current_vmcs12_page);
5360                 }
5361
5362                 vmx->nested.current_vmptr = vmptr;
5363                 vmx->nested.current_vmcs12 = new_vmcs12;
5364                 vmx->nested.current_vmcs12_page = page;
5365         }
5366
5367         nested_vmx_succeed(vcpu);
5368         skip_emulated_instruction(vcpu);
5369         return 1;
5370 }
5371
5372 /* Emulate the VMPTRST instruction */
5373 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5374 {
5375         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5376         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5377         gva_t vmcs_gva;
5378         struct x86_exception e;
5379
5380         if (!nested_vmx_check_permission(vcpu))
5381                 return 1;
5382
5383         if (get_vmx_mem_address(vcpu, exit_qualification,
5384                         vmx_instruction_info, &vmcs_gva))
5385                 return 1;
5386         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5387         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5388                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5389                                  sizeof(u64), &e)) {
5390                 kvm_inject_page_fault(vcpu, &e);
5391                 return 1;
5392         }
5393         nested_vmx_succeed(vcpu);
5394         skip_emulated_instruction(vcpu);
5395         return 1;
5396 }
5397
5398 /*
5399  * The exit handlers return 1 if the exit was handled fully and guest execution
5400  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5401  * to be done to userspace and return 0.
5402  */
5403 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5404         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5405         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5406         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5407         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5408         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5409         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5410         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5411         [EXIT_REASON_CPUID]                   = handle_cpuid,
5412         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5413         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5414         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5415         [EXIT_REASON_HLT]                     = handle_halt,
5416         [EXIT_REASON_INVD]                    = handle_invd,
5417         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5418         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5419         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5420         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5421         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5422         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5423         [EXIT_REASON_VMREAD]                  = handle_vmread,
5424         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5425         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5426         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5427         [EXIT_REASON_VMON]                    = handle_vmon,
5428         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5429         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5430         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5431         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5432         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5433         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5434         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5435         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5436         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5437         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5438         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5439 };
5440
5441 static const int kvm_vmx_max_exit_handlers =
5442         ARRAY_SIZE(kvm_vmx_exit_handlers);
5443
5444 /*
5445  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5446  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5447  * disinterest in the current event (read or write a specific MSR) by using an
5448  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5449  */
5450 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5451         struct vmcs12 *vmcs12, u32 exit_reason)
5452 {
5453         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5454         gpa_t bitmap;
5455
5456         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5457                 return 1;
5458
5459         /*
5460          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5461          * for the four combinations of read/write and low/high MSR numbers.
5462          * First we need to figure out which of the four to use:
5463          */
5464         bitmap = vmcs12->msr_bitmap;
5465         if (exit_reason == EXIT_REASON_MSR_WRITE)
5466                 bitmap += 2048;
5467         if (msr_index >= 0xc0000000) {
5468                 msr_index -= 0xc0000000;
5469                 bitmap += 1024;
5470         }
5471
5472         /* Then read the msr_index'th bit from this bitmap: */
5473         if (msr_index < 1024*8) {
5474                 unsigned char b;
5475                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5476                 return 1 & (b >> (msr_index & 7));
5477         } else
5478                 return 1; /* let L1 handle the wrong parameter */
5479 }
5480
5481 /*
5482  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5483  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5484  * intercept (via guest_host_mask etc.) the current event.
5485  */
5486 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5487         struct vmcs12 *vmcs12)
5488 {
5489         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5490         int cr = exit_qualification & 15;
5491         int reg = (exit_qualification >> 8) & 15;
5492         unsigned long val = kvm_register_read(vcpu, reg);
5493
5494         switch ((exit_qualification >> 4) & 3) {
5495         case 0: /* mov to cr */
5496                 switch (cr) {
5497                 case 0:
5498                         if (vmcs12->cr0_guest_host_mask &
5499                             (val ^ vmcs12->cr0_read_shadow))
5500                                 return 1;
5501                         break;
5502                 case 3:
5503                         if ((vmcs12->cr3_target_count >= 1 &&
5504                                         vmcs12->cr3_target_value0 == val) ||
5505                                 (vmcs12->cr3_target_count >= 2 &&
5506                                         vmcs12->cr3_target_value1 == val) ||
5507                                 (vmcs12->cr3_target_count >= 3 &&
5508                                         vmcs12->cr3_target_value2 == val) ||
5509                                 (vmcs12->cr3_target_count >= 4 &&
5510                                         vmcs12->cr3_target_value3 == val))
5511                                 return 0;
5512                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5513                                 return 1;
5514                         break;
5515                 case 4:
5516                         if (vmcs12->cr4_guest_host_mask &
5517                             (vmcs12->cr4_read_shadow ^ val))
5518                                 return 1;
5519                         break;
5520                 case 8:
5521                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5522                                 return 1;
5523                         break;
5524                 }
5525                 break;
5526         case 2: /* clts */
5527                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5528                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5529                         return 1;
5530                 break;
5531         case 1: /* mov from cr */
5532                 switch (cr) {
5533                 case 3:
5534                         if (vmcs12->cpu_based_vm_exec_control &
5535                             CPU_BASED_CR3_STORE_EXITING)
5536                                 return 1;
5537                         break;
5538                 case 8:
5539                         if (vmcs12->cpu_based_vm_exec_control &
5540                             CPU_BASED_CR8_STORE_EXITING)
5541                                 return 1;
5542                         break;
5543                 }
5544                 break;
5545         case 3: /* lmsw */
5546                 /*
5547                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5548                  * cr0. Other attempted changes are ignored, with no exit.
5549                  */
5550                 if (vmcs12->cr0_guest_host_mask & 0xe &
5551                     (val ^ vmcs12->cr0_read_shadow))
5552                         return 1;
5553                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5554                     !(vmcs12->cr0_read_shadow & 0x1) &&
5555                     (val & 0x1))
5556                         return 1;
5557                 break;
5558         }
5559         return 0;
5560 }
5561
5562 /*
5563  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5564  * should handle it ourselves in L0 (and then continue L2). Only call this
5565  * when in is_guest_mode (L2).
5566  */
5567 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5568 {
5569         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5570         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5571         struct vcpu_vmx *vmx = to_vmx(vcpu);
5572         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5573
5574         if (vmx->nested.nested_run_pending)
5575                 return 0;
5576
5577         if (unlikely(vmx->fail)) {
5578                 printk(KERN_INFO "%s failed vm entry %x\n",
5579                        __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5580                 return 1;
5581         }
5582
5583         switch (exit_reason) {
5584         case EXIT_REASON_EXCEPTION_NMI:
5585                 if (!is_exception(intr_info))
5586                         return 0;
5587                 else if (is_page_fault(intr_info))
5588                         return enable_ept;
5589                 return vmcs12->exception_bitmap &
5590                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5591         case EXIT_REASON_EXTERNAL_INTERRUPT:
5592                 return 0;
5593         case EXIT_REASON_TRIPLE_FAULT:
5594                 return 1;
5595         case EXIT_REASON_PENDING_INTERRUPT:
5596         case EXIT_REASON_NMI_WINDOW:
5597                 /*
5598                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5599                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5600                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5601                  * Same for NMI Window Exiting.
5602                  */
5603                 return 1;
5604         case EXIT_REASON_TASK_SWITCH:
5605                 return 1;
5606         case EXIT_REASON_CPUID:
5607                 return 1;
5608         case EXIT_REASON_HLT:
5609                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5610         case EXIT_REASON_INVD:
5611                 return 1;
5612         case EXIT_REASON_INVLPG:
5613                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5614         case EXIT_REASON_RDPMC:
5615                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5616         case EXIT_REASON_RDTSC:
5617                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5618         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5619         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5620         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5621         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5622         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5623                 /*
5624                  * VMX instructions trap unconditionally. This allows L1 to
5625                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5626                  */
5627                 return 1;
5628         case EXIT_REASON_CR_ACCESS:
5629                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5630         case EXIT_REASON_DR_ACCESS:
5631                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5632         case EXIT_REASON_IO_INSTRUCTION:
5633                 /* TODO: support IO bitmaps */
5634                 return 1;
5635         case EXIT_REASON_MSR_READ:
5636         case EXIT_REASON_MSR_WRITE:
5637                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5638         case EXIT_REASON_INVALID_STATE:
5639                 return 1;
5640         case EXIT_REASON_MWAIT_INSTRUCTION:
5641                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5642         case EXIT_REASON_MONITOR_INSTRUCTION:
5643                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5644         case EXIT_REASON_PAUSE_INSTRUCTION:
5645                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5646                         nested_cpu_has2(vmcs12,
5647                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5648         case EXIT_REASON_MCE_DURING_VMENTRY:
5649                 return 0;
5650         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5651                 return 1;
5652         case EXIT_REASON_APIC_ACCESS:
5653                 return nested_cpu_has2(vmcs12,
5654                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5655         case EXIT_REASON_EPT_VIOLATION:
5656         case EXIT_REASON_EPT_MISCONFIG:
5657                 return 0;
5658         case EXIT_REASON_WBINVD:
5659                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5660         case EXIT_REASON_XSETBV:
5661                 return 1;
5662         default:
5663                 return 1;
5664         }
5665 }
5666
5667 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5668 {
5669         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5670         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5671 }
5672
5673 /*
5674  * The guest has exited.  See if we can fix it or if we need userspace
5675  * assistance.
5676  */
5677 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5678 {
5679         struct vcpu_vmx *vmx = to_vmx(vcpu);
5680         u32 exit_reason = vmx->exit_reason;
5681         u32 vectoring_info = vmx->idt_vectoring_info;
5682
5683         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
5684
5685         /* If guest state is invalid, start emulating */
5686         if (vmx->emulation_required && emulate_invalid_guest_state)
5687                 return handle_invalid_guest_state(vcpu);
5688
5689         /*
5690          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5691          * we did not inject a still-pending event to L1 now because of
5692          * nested_run_pending, we need to re-enable this bit.
5693          */
5694         if (vmx->nested.nested_run_pending)
5695                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5696
5697         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5698             exit_reason == EXIT_REASON_VMRESUME))
5699                 vmx->nested.nested_run_pending = 1;
5700         else
5701                 vmx->nested.nested_run_pending = 0;
5702
5703         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5704                 nested_vmx_vmexit(vcpu);
5705                 return 1;
5706         }
5707
5708         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5709                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5710                 vcpu->run->fail_entry.hardware_entry_failure_reason
5711                         = exit_reason;
5712                 return 0;
5713         }
5714
5715         if (unlikely(vmx->fail)) {
5716                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5717                 vcpu->run->fail_entry.hardware_entry_failure_reason
5718                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5719                 return 0;
5720         }
5721
5722         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5723                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5724                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5725                         exit_reason != EXIT_REASON_TASK_SWITCH))
5726                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5727                        "(0x%x) and exit reason is 0x%x\n",
5728                        __func__, vectoring_info, exit_reason);
5729
5730         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5731             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5732                                         get_vmcs12(vcpu), vcpu)))) {
5733                 if (vmx_interrupt_allowed(vcpu)) {
5734                         vmx->soft_vnmi_blocked = 0;
5735                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5736                            vcpu->arch.nmi_pending) {
5737                         /*
5738                          * This CPU don't support us in finding the end of an
5739                          * NMI-blocked window if the guest runs with IRQs
5740                          * disabled. So we pull the trigger after 1 s of
5741                          * futile waiting, but inform the user about this.
5742                          */
5743                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5744                                "state on VCPU %d after 1 s timeout\n",
5745                                __func__, vcpu->vcpu_id);
5746                         vmx->soft_vnmi_blocked = 0;
5747                 }
5748         }
5749
5750         if (exit_reason < kvm_vmx_max_exit_handlers
5751             && kvm_vmx_exit_handlers[exit_reason])
5752                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5753         else {
5754                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5755                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5756         }
5757         return 0;
5758 }
5759
5760 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5761 {
5762         if (irr == -1 || tpr < irr) {
5763                 vmcs_write32(TPR_THRESHOLD, 0);
5764                 return;
5765         }
5766
5767         vmcs_write32(TPR_THRESHOLD, irr);
5768 }
5769
5770 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5771 {
5772         u32 exit_intr_info;
5773
5774         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5775               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5776                 return;
5777
5778         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5779         exit_intr_info = vmx->exit_intr_info;
5780
5781         /* Handle machine checks before interrupts are enabled */
5782         if (is_machine_check(exit_intr_info))
5783                 kvm_machine_check();
5784
5785         /* We need to handle NMIs before interrupts are enabled */
5786         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5787             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5788                 kvm_before_handle_nmi(&vmx->vcpu);
5789                 asm("int $2");
5790                 kvm_after_handle_nmi(&vmx->vcpu);
5791         }
5792 }
5793
5794 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5795 {
5796         u32 exit_intr_info;
5797         bool unblock_nmi;
5798         u8 vector;
5799         bool idtv_info_valid;
5800
5801         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5802
5803         if (cpu_has_virtual_nmis()) {
5804                 if (vmx->nmi_known_unmasked)
5805                         return;
5806                 /*
5807                  * Can't use vmx->exit_intr_info since we're not sure what
5808                  * the exit reason is.
5809                  */
5810                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5811                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5812                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5813                 /*
5814                  * SDM 3: 27.7.1.2 (September 2008)
5815                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5816                  * a guest IRET fault.
5817                  * SDM 3: 23.2.2 (September 2008)
5818                  * Bit 12 is undefined in any of the following cases:
5819                  *  If the VM exit sets the valid bit in the IDT-vectoring
5820                  *   information field.
5821                  *  If the VM exit is due to a double fault.
5822                  */
5823                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5824                     vector != DF_VECTOR && !idtv_info_valid)
5825                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5826                                       GUEST_INTR_STATE_NMI);
5827                 else
5828                         vmx->nmi_known_unmasked =
5829                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5830                                   & GUEST_INTR_STATE_NMI);
5831         } else if (unlikely(vmx->soft_vnmi_blocked))
5832                 vmx->vnmi_blocked_time +=
5833                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5834 }
5835
5836 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5837                                       u32 idt_vectoring_info,
5838                                       int instr_len_field,
5839                                       int error_code_field)
5840 {
5841         u8 vector;
5842         int type;
5843         bool idtv_info_valid;
5844
5845         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5846
5847         vmx->vcpu.arch.nmi_injected = false;
5848         kvm_clear_exception_queue(&vmx->vcpu);
5849         kvm_clear_interrupt_queue(&vmx->vcpu);
5850
5851         if (!idtv_info_valid)
5852                 return;
5853
5854         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5855
5856         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5857         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5858
5859         switch (type) {
5860         case INTR_TYPE_NMI_INTR:
5861                 vmx->vcpu.arch.nmi_injected = true;
5862                 /*
5863                  * SDM 3: 27.7.1.2 (September 2008)
5864                  * Clear bit "block by NMI" before VM entry if a NMI
5865                  * delivery faulted.
5866                  */
5867                 vmx_set_nmi_mask(&vmx->vcpu, false);
5868                 break;
5869         case INTR_TYPE_SOFT_EXCEPTION:
5870                 vmx->vcpu.arch.event_exit_inst_len =
5871                         vmcs_read32(instr_len_field);
5872                 /* fall through */
5873         case INTR_TYPE_HARD_EXCEPTION:
5874                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5875                         u32 err = vmcs_read32(error_code_field);
5876                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
5877                 } else
5878                         kvm_queue_exception(&vmx->vcpu, vector);
5879                 break;
5880         case INTR_TYPE_SOFT_INTR:
5881                 vmx->vcpu.arch.event_exit_inst_len =
5882                         vmcs_read32(instr_len_field);
5883                 /* fall through */
5884         case INTR_TYPE_EXT_INTR:
5885                 kvm_queue_interrupt(&vmx->vcpu, vector,
5886                         type == INTR_TYPE_SOFT_INTR);
5887                 break;
5888         default:
5889                 break;
5890         }
5891 }
5892
5893 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5894 {
5895         if (is_guest_mode(&vmx->vcpu))
5896                 return;
5897         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5898                                   VM_EXIT_INSTRUCTION_LEN,
5899                                   IDT_VECTORING_ERROR_CODE);
5900 }
5901
5902 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5903 {
5904         if (is_guest_mode(vcpu))
5905                 return;
5906         __vmx_complete_interrupts(to_vmx(vcpu),
5907                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5908                                   VM_ENTRY_INSTRUCTION_LEN,
5909                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
5910
5911         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5912 }
5913
5914 #ifdef CONFIG_X86_64
5915 #define R "r"
5916 #define Q "q"
5917 #else
5918 #define R "e"
5919 #define Q "l"
5920 #endif
5921
5922 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5923 {
5924         struct vcpu_vmx *vmx = to_vmx(vcpu);
5925
5926         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
5927                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5928                 if (vmcs12->idt_vectoring_info_field &
5929                                 VECTORING_INFO_VALID_MASK) {
5930                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5931                                 vmcs12->idt_vectoring_info_field);
5932                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5933                                 vmcs12->vm_exit_instruction_len);
5934                         if (vmcs12->idt_vectoring_info_field &
5935                                         VECTORING_INFO_DELIVER_CODE_MASK)
5936                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5937                                         vmcs12->idt_vectoring_error_code);
5938                 }
5939         }
5940
5941         /* Record the guest's net vcpu time for enforced NMI injections. */
5942         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5943                 vmx->entry_time = ktime_get();
5944
5945         /* Don't enter VMX if guest state is invalid, let the exit handler
5946            start emulation until we arrive back to a valid state */
5947         if (vmx->emulation_required && emulate_invalid_guest_state)
5948                 return;
5949
5950         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5951                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5952         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5953                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5954
5955         /* When single-stepping over STI and MOV SS, we must clear the
5956          * corresponding interruptibility bits in the guest state. Otherwise
5957          * vmentry fails as it then expects bit 14 (BS) in pending debug
5958          * exceptions being set, but that's not correct for the guest debugging
5959          * case. */
5960         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5961                 vmx_set_interrupt_shadow(vcpu, 0);
5962
5963         vmx->__launched = vmx->loaded_vmcs->launched;
5964         asm(
5965                 /* Store host registers */
5966                 "push %%"R"dx; push %%"R"bp;"
5967                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
5968                 "push %%"R"cx \n\t"
5969                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5970                 "je 1f \n\t"
5971                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
5972                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
5973                 "1: \n\t"
5974                 /* Reload cr2 if changed */
5975                 "mov %c[cr2](%0), %%"R"ax \n\t"
5976                 "mov %%cr2, %%"R"dx \n\t"
5977                 "cmp %%"R"ax, %%"R"dx \n\t"
5978                 "je 2f \n\t"
5979                 "mov %%"R"ax, %%cr2 \n\t"
5980                 "2: \n\t"
5981                 /* Check if vmlaunch of vmresume is needed */
5982                 "cmpl $0, %c[launched](%0) \n\t"
5983                 /* Load guest registers.  Don't clobber flags. */
5984                 "mov %c[rax](%0), %%"R"ax \n\t"
5985                 "mov %c[rbx](%0), %%"R"bx \n\t"
5986                 "mov %c[rdx](%0), %%"R"dx \n\t"
5987                 "mov %c[rsi](%0), %%"R"si \n\t"
5988                 "mov %c[rdi](%0), %%"R"di \n\t"
5989                 "mov %c[rbp](%0), %%"R"bp \n\t"
5990 #ifdef CONFIG_X86_64
5991                 "mov %c[r8](%0),  %%r8  \n\t"
5992                 "mov %c[r9](%0),  %%r9  \n\t"
5993                 "mov %c[r10](%0), %%r10 \n\t"
5994                 "mov %c[r11](%0), %%r11 \n\t"
5995                 "mov %c[r12](%0), %%r12 \n\t"
5996                 "mov %c[r13](%0), %%r13 \n\t"
5997                 "mov %c[r14](%0), %%r14 \n\t"
5998                 "mov %c[r15](%0), %%r15 \n\t"
5999 #endif
6000                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6001
6002                 /* Enter guest mode */
6003                 "jne .Llaunched \n\t"
6004                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6005                 "jmp .Lkvm_vmx_return \n\t"
6006                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6007                 ".Lkvm_vmx_return: "
6008                 /* Save guest registers, load host registers, keep flags */
6009                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6010                 "pop %0 \n\t"
6011                 "mov %%"R"ax, %c[rax](%0) \n\t"
6012                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6013                 "pop"Q" %c[rcx](%0) \n\t"
6014                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6015                 "mov %%"R"si, %c[rsi](%0) \n\t"
6016                 "mov %%"R"di, %c[rdi](%0) \n\t"
6017                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6018 #ifdef CONFIG_X86_64
6019                 "mov %%r8,  %c[r8](%0) \n\t"
6020                 "mov %%r9,  %c[r9](%0) \n\t"
6021                 "mov %%r10, %c[r10](%0) \n\t"
6022                 "mov %%r11, %c[r11](%0) \n\t"
6023                 "mov %%r12, %c[r12](%0) \n\t"
6024                 "mov %%r13, %c[r13](%0) \n\t"
6025                 "mov %%r14, %c[r14](%0) \n\t"
6026                 "mov %%r15, %c[r15](%0) \n\t"
6027 #endif
6028                 "mov %%cr2, %%"R"ax   \n\t"
6029                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6030
6031                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6032                 "setbe %c[fail](%0) \n\t"
6033               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6034                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6035                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6036                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6037                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6038                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6039                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6040                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6041                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6042                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6043                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6044 #ifdef CONFIG_X86_64
6045                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6046                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6047                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6048                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6049                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6050                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6051                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6052                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6053 #endif
6054                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6055                 [wordsize]"i"(sizeof(ulong))
6056               : "cc", "memory"
6057                 , R"ax", R"bx", R"di", R"si"
6058 #ifdef CONFIG_X86_64
6059                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6060 #endif
6061               );
6062
6063         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6064                                   | (1 << VCPU_EXREG_RFLAGS)
6065                                   | (1 << VCPU_EXREG_CPL)
6066                                   | (1 << VCPU_EXREG_PDPTR)
6067                                   | (1 << VCPU_EXREG_SEGMENTS)
6068                                   | (1 << VCPU_EXREG_CR3));
6069         vcpu->arch.regs_dirty = 0;
6070
6071         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6072
6073         if (is_guest_mode(vcpu)) {
6074                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6075                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6076                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6077                         vmcs12->idt_vectoring_error_code =
6078                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6079                         vmcs12->vm_exit_instruction_len =
6080                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6081                 }
6082         }
6083
6084         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6085         vmx->loaded_vmcs->launched = 1;
6086
6087         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6088
6089         vmx_complete_atomic_exit(vmx);
6090         vmx_recover_nmi_blocking(vmx);
6091         vmx_complete_interrupts(vmx);
6092 }
6093
6094 #undef R
6095 #undef Q
6096
6097 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6098 {
6099         struct vcpu_vmx *vmx = to_vmx(vcpu);
6100
6101         free_vpid(vmx);
6102         free_nested(vmx);
6103         free_loaded_vmcs(vmx->loaded_vmcs);
6104         kfree(vmx->guest_msrs);
6105         kvm_vcpu_uninit(vcpu);
6106         kmem_cache_free(kvm_vcpu_cache, vmx);
6107 }
6108
6109 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6110 {
6111         int err;
6112         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6113         int cpu;
6114
6115         if (!vmx)
6116                 return ERR_PTR(-ENOMEM);
6117
6118         allocate_vpid(vmx);
6119
6120         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6121         if (err)
6122                 goto free_vcpu;
6123
6124         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6125         err = -ENOMEM;
6126         if (!vmx->guest_msrs) {
6127                 goto uninit_vcpu;
6128         }
6129
6130         vmx->loaded_vmcs = &vmx->vmcs01;
6131         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6132         if (!vmx->loaded_vmcs->vmcs)
6133                 goto free_msrs;
6134         if (!vmm_exclusive)
6135                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6136         loaded_vmcs_init(vmx->loaded_vmcs);
6137         if (!vmm_exclusive)
6138                 kvm_cpu_vmxoff();
6139
6140         cpu = get_cpu();
6141         vmx_vcpu_load(&vmx->vcpu, cpu);
6142         vmx->vcpu.cpu = cpu;
6143         err = vmx_vcpu_setup(vmx);
6144         vmx_vcpu_put(&vmx->vcpu);
6145         put_cpu();
6146         if (err)
6147                 goto free_vmcs;
6148         if (vm_need_virtualize_apic_accesses(kvm))
6149                 err = alloc_apic_access_page(kvm);
6150                 if (err)
6151                         goto free_vmcs;
6152
6153         if (enable_ept) {
6154                 if (!kvm->arch.ept_identity_map_addr)
6155                         kvm->arch.ept_identity_map_addr =
6156                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6157                 err = -ENOMEM;
6158                 if (alloc_identity_pagetable(kvm) != 0)
6159                         goto free_vmcs;
6160                 if (!init_rmode_identity_map(kvm))
6161                         goto free_vmcs;
6162         }
6163
6164         vmx->nested.current_vmptr = -1ull;
6165         vmx->nested.current_vmcs12 = NULL;
6166
6167         return &vmx->vcpu;
6168
6169 free_vmcs:
6170         free_vmcs(vmx->loaded_vmcs->vmcs);
6171 free_msrs:
6172         kfree(vmx->guest_msrs);
6173 uninit_vcpu:
6174         kvm_vcpu_uninit(&vmx->vcpu);
6175 free_vcpu:
6176         free_vpid(vmx);
6177         kmem_cache_free(kvm_vcpu_cache, vmx);
6178         return ERR_PTR(err);
6179 }
6180
6181 static void __init vmx_check_processor_compat(void *rtn)
6182 {
6183         struct vmcs_config vmcs_conf;
6184
6185         *(int *)rtn = 0;
6186         if (setup_vmcs_config(&vmcs_conf) < 0)
6187                 *(int *)rtn = -EIO;
6188         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6189                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6190                                 smp_processor_id());
6191                 *(int *)rtn = -EIO;
6192         }
6193 }
6194
6195 static int get_ept_level(void)
6196 {
6197         return VMX_EPT_DEFAULT_GAW + 1;
6198 }
6199
6200 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6201 {
6202         u64 ret;
6203
6204         /* For VT-d and EPT combination
6205          * 1. MMIO: always map as UC
6206          * 2. EPT with VT-d:
6207          *   a. VT-d without snooping control feature: can't guarantee the
6208          *      result, try to trust guest.
6209          *   b. VT-d with snooping control feature: snooping control feature of
6210          *      VT-d engine can guarantee the cache correctness. Just set it
6211          *      to WB to keep consistent with host. So the same as item 3.
6212          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6213          *    consistent with host MTRR
6214          */
6215         if (is_mmio)
6216                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6217         else if (vcpu->kvm->arch.iommu_domain &&
6218                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6219                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6220                       VMX_EPT_MT_EPTE_SHIFT;
6221         else
6222                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6223                         | VMX_EPT_IPAT_BIT;
6224
6225         return ret;
6226 }
6227
6228 #define _ER(x) { EXIT_REASON_##x, #x }
6229
6230 static const struct trace_print_flags vmx_exit_reasons_str[] = {
6231         _ER(EXCEPTION_NMI),
6232         _ER(EXTERNAL_INTERRUPT),
6233         _ER(TRIPLE_FAULT),
6234         _ER(PENDING_INTERRUPT),
6235         _ER(NMI_WINDOW),
6236         _ER(TASK_SWITCH),
6237         _ER(CPUID),
6238         _ER(HLT),
6239         _ER(INVLPG),
6240         _ER(RDPMC),
6241         _ER(RDTSC),
6242         _ER(VMCALL),
6243         _ER(VMCLEAR),
6244         _ER(VMLAUNCH),
6245         _ER(VMPTRLD),
6246         _ER(VMPTRST),
6247         _ER(VMREAD),
6248         _ER(VMRESUME),
6249         _ER(VMWRITE),
6250         _ER(VMOFF),
6251         _ER(VMON),
6252         _ER(CR_ACCESS),
6253         _ER(DR_ACCESS),
6254         _ER(IO_INSTRUCTION),
6255         _ER(MSR_READ),
6256         _ER(MSR_WRITE),
6257         _ER(MWAIT_INSTRUCTION),
6258         _ER(MONITOR_INSTRUCTION),
6259         _ER(PAUSE_INSTRUCTION),
6260         _ER(MCE_DURING_VMENTRY),
6261         _ER(TPR_BELOW_THRESHOLD),
6262         _ER(APIC_ACCESS),
6263         _ER(EPT_VIOLATION),
6264         _ER(EPT_MISCONFIG),
6265         _ER(WBINVD),
6266         { -1, NULL }
6267 };
6268
6269 #undef _ER
6270
6271 static int vmx_get_lpage_level(void)
6272 {
6273         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6274                 return PT_DIRECTORY_LEVEL;
6275         else
6276                 /* For shadow and EPT supported 1GB page */
6277                 return PT_PDPE_LEVEL;
6278 }
6279
6280 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6281 {
6282         struct kvm_cpuid_entry2 *best;
6283         struct vcpu_vmx *vmx = to_vmx(vcpu);
6284         u32 exec_control;
6285
6286         vmx->rdtscp_enabled = false;
6287         if (vmx_rdtscp_supported()) {
6288                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6289                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6290                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6291                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6292                                 vmx->rdtscp_enabled = true;
6293                         else {
6294                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6295                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6296                                                 exec_control);
6297                         }
6298                 }
6299         }
6300 }
6301
6302 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6303 {
6304         if (func == 1 && nested)
6305                 entry->ecx |= bit(X86_FEATURE_VMX);
6306 }
6307
6308 /*
6309  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6310  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6311  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6312  * guest in a way that will both be appropriate to L1's requests, and our
6313  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6314  * function also has additional necessary side-effects, like setting various
6315  * vcpu->arch fields.
6316  */
6317 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6318 {
6319         struct vcpu_vmx *vmx = to_vmx(vcpu);
6320         u32 exec_control;
6321
6322         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6323         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6324         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6325         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6326         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6327         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6328         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6329         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6330         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6331         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6332         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6333         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6334         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6335         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6336         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6337         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6338         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6339         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6340         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6341         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6342         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6343         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6344         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6345         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6346         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6347         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6348         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6349        &