KVM: remove the usage of the mmap_sem for the protection of the memory slots.
[linux-2.6.git] / arch / x86 / kvm / vmx.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * Copyright (C) 2006 Qumranet, Inc.
8  *
9  * Authors:
10  *   Avi Kivity   <avi@qumranet.com>
11  *   Yaniv Kamay  <yaniv@qumranet.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2.  See
14  * the COPYING file in the top-level directory.
15  *
16  */
17
18 #include "irq.h"
19 #include "vmx.h"
20 #include "segment_descriptor.h"
21 #include "mmu.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33
34 MODULE_AUTHOR("Qumranet");
35 MODULE_LICENSE("GPL");
36
37 static int bypass_guest_pf = 1;
38 module_param(bypass_guest_pf, bool, 0);
39
40 struct vmcs {
41         u32 revision_id;
42         u32 abort;
43         char data[0];
44 };
45
46 struct vcpu_vmx {
47         struct kvm_vcpu       vcpu;
48         int                   launched;
49         u8                    fail;
50         u32                   idt_vectoring_info;
51         struct kvm_msr_entry *guest_msrs;
52         struct kvm_msr_entry *host_msrs;
53         int                   nmsrs;
54         int                   save_nmsrs;
55         int                   msr_offset_efer;
56 #ifdef CONFIG_X86_64
57         int                   msr_offset_kernel_gs_base;
58 #endif
59         struct vmcs          *vmcs;
60         struct {
61                 int           loaded;
62                 u16           fs_sel, gs_sel, ldt_sel;
63                 int           gs_ldt_reload_needed;
64                 int           fs_reload_needed;
65                 int           guest_efer_loaded;
66         } host_state;
67         struct {
68                 struct {
69                         bool pending;
70                         u8 vector;
71                         unsigned rip;
72                 } irq;
73         } rmode;
74 };
75
76 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
77 {
78         return container_of(vcpu, struct vcpu_vmx, vcpu);
79 }
80
81 static int init_rmode_tss(struct kvm *kvm);
82
83 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
84 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
85
86 static struct page *vmx_io_bitmap_a;
87 static struct page *vmx_io_bitmap_b;
88
89 static struct vmcs_config {
90         int size;
91         int order;
92         u32 revision_id;
93         u32 pin_based_exec_ctrl;
94         u32 cpu_based_exec_ctrl;
95         u32 cpu_based_2nd_exec_ctrl;
96         u32 vmexit_ctrl;
97         u32 vmentry_ctrl;
98 } vmcs_config;
99
100 #define VMX_SEGMENT_FIELD(seg)                                  \
101         [VCPU_SREG_##seg] = {                                   \
102                 .selector = GUEST_##seg##_SELECTOR,             \
103                 .base = GUEST_##seg##_BASE,                     \
104                 .limit = GUEST_##seg##_LIMIT,                   \
105                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
106         }
107
108 static struct kvm_vmx_segment_field {
109         unsigned selector;
110         unsigned base;
111         unsigned limit;
112         unsigned ar_bytes;
113 } kvm_vmx_segment_fields[] = {
114         VMX_SEGMENT_FIELD(CS),
115         VMX_SEGMENT_FIELD(DS),
116         VMX_SEGMENT_FIELD(ES),
117         VMX_SEGMENT_FIELD(FS),
118         VMX_SEGMENT_FIELD(GS),
119         VMX_SEGMENT_FIELD(SS),
120         VMX_SEGMENT_FIELD(TR),
121         VMX_SEGMENT_FIELD(LDTR),
122 };
123
124 /*
125  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
126  * away by decrementing the array size.
127  */
128 static const u32 vmx_msr_index[] = {
129 #ifdef CONFIG_X86_64
130         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
131 #endif
132         MSR_EFER, MSR_K6_STAR,
133 };
134 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
135
136 static void load_msrs(struct kvm_msr_entry *e, int n)
137 {
138         int i;
139
140         for (i = 0; i < n; ++i)
141                 wrmsrl(e[i].index, e[i].data);
142 }
143
144 static void save_msrs(struct kvm_msr_entry *e, int n)
145 {
146         int i;
147
148         for (i = 0; i < n; ++i)
149                 rdmsrl(e[i].index, e[i].data);
150 }
151
152 static inline int is_page_fault(u32 intr_info)
153 {
154         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
155                              INTR_INFO_VALID_MASK)) ==
156                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
157 }
158
159 static inline int is_no_device(u32 intr_info)
160 {
161         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
162                              INTR_INFO_VALID_MASK)) ==
163                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
164 }
165
166 static inline int is_invalid_opcode(u32 intr_info)
167 {
168         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
169                              INTR_INFO_VALID_MASK)) ==
170                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
171 }
172
173 static inline int is_external_interrupt(u32 intr_info)
174 {
175         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
176                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
177 }
178
179 static inline int cpu_has_vmx_tpr_shadow(void)
180 {
181         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
182 }
183
184 static inline int vm_need_tpr_shadow(struct kvm *kvm)
185 {
186         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
187 }
188
189 static inline int cpu_has_secondary_exec_ctrls(void)
190 {
191         return (vmcs_config.cpu_based_exec_ctrl &
192                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
193 }
194
195 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
196 {
197         return (vmcs_config.cpu_based_2nd_exec_ctrl &
198                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
199 }
200
201 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
202 {
203         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
204                 (irqchip_in_kernel(kvm)));
205 }
206
207 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
208 {
209         int i;
210
211         for (i = 0; i < vmx->nmsrs; ++i)
212                 if (vmx->guest_msrs[i].index == msr)
213                         return i;
214         return -1;
215 }
216
217 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
218 {
219         int i;
220
221         i = __find_msr_index(vmx, msr);
222         if (i >= 0)
223                 return &vmx->guest_msrs[i];
224         return NULL;
225 }
226
227 static void vmcs_clear(struct vmcs *vmcs)
228 {
229         u64 phys_addr = __pa(vmcs);
230         u8 error;
231
232         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
233                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
234                       : "cc", "memory");
235         if (error)
236                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
237                        vmcs, phys_addr);
238 }
239
240 static void __vcpu_clear(void *arg)
241 {
242         struct vcpu_vmx *vmx = arg;
243         int cpu = raw_smp_processor_id();
244
245         if (vmx->vcpu.cpu == cpu)
246                 vmcs_clear(vmx->vmcs);
247         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
248                 per_cpu(current_vmcs, cpu) = NULL;
249         rdtscll(vmx->vcpu.arch.host_tsc);
250 }
251
252 static void vcpu_clear(struct vcpu_vmx *vmx)
253 {
254         if (vmx->vcpu.cpu == -1)
255                 return;
256         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
257         vmx->launched = 0;
258 }
259
260 static unsigned long vmcs_readl(unsigned long field)
261 {
262         unsigned long value;
263
264         asm volatile (ASM_VMX_VMREAD_RDX_RAX
265                       : "=a"(value) : "d"(field) : "cc");
266         return value;
267 }
268
269 static u16 vmcs_read16(unsigned long field)
270 {
271         return vmcs_readl(field);
272 }
273
274 static u32 vmcs_read32(unsigned long field)
275 {
276         return vmcs_readl(field);
277 }
278
279 static u64 vmcs_read64(unsigned long field)
280 {
281 #ifdef CONFIG_X86_64
282         return vmcs_readl(field);
283 #else
284         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
285 #endif
286 }
287
288 static noinline void vmwrite_error(unsigned long field, unsigned long value)
289 {
290         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
291                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
292         dump_stack();
293 }
294
295 static void vmcs_writel(unsigned long field, unsigned long value)
296 {
297         u8 error;
298
299         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
300                        : "=q"(error) : "a"(value), "d"(field) : "cc");
301         if (unlikely(error))
302                 vmwrite_error(field, value);
303 }
304
305 static void vmcs_write16(unsigned long field, u16 value)
306 {
307         vmcs_writel(field, value);
308 }
309
310 static void vmcs_write32(unsigned long field, u32 value)
311 {
312         vmcs_writel(field, value);
313 }
314
315 static void vmcs_write64(unsigned long field, u64 value)
316 {
317 #ifdef CONFIG_X86_64
318         vmcs_writel(field, value);
319 #else
320         vmcs_writel(field, value);
321         asm volatile ("");
322         vmcs_writel(field+1, value >> 32);
323 #endif
324 }
325
326 static void vmcs_clear_bits(unsigned long field, u32 mask)
327 {
328         vmcs_writel(field, vmcs_readl(field) & ~mask);
329 }
330
331 static void vmcs_set_bits(unsigned long field, u32 mask)
332 {
333         vmcs_writel(field, vmcs_readl(field) | mask);
334 }
335
336 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
337 {
338         u32 eb;
339
340         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
341         if (!vcpu->fpu_active)
342                 eb |= 1u << NM_VECTOR;
343         if (vcpu->guest_debug.enabled)
344                 eb |= 1u << 1;
345         if (vcpu->arch.rmode.active)
346                 eb = ~0;
347         vmcs_write32(EXCEPTION_BITMAP, eb);
348 }
349
350 static void reload_tss(void)
351 {
352 #ifndef CONFIG_X86_64
353
354         /*
355          * VT restores TR but not its size.  Useless.
356          */
357         struct descriptor_table gdt;
358         struct segment_descriptor *descs;
359
360         get_gdt(&gdt);
361         descs = (void *)gdt.base;
362         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
363         load_TR_desc();
364 #endif
365 }
366
367 static void load_transition_efer(struct vcpu_vmx *vmx)
368 {
369         int efer_offset = vmx->msr_offset_efer;
370         u64 host_efer = vmx->host_msrs[efer_offset].data;
371         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
372         u64 ignore_bits;
373
374         if (efer_offset < 0)
375                 return;
376         /*
377          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
378          * outside long mode
379          */
380         ignore_bits = EFER_NX | EFER_SCE;
381 #ifdef CONFIG_X86_64
382         ignore_bits |= EFER_LMA | EFER_LME;
383         /* SCE is meaningful only in long mode on Intel */
384         if (guest_efer & EFER_LMA)
385                 ignore_bits &= ~(u64)EFER_SCE;
386 #endif
387         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
388                 return;
389
390         vmx->host_state.guest_efer_loaded = 1;
391         guest_efer &= ~ignore_bits;
392         guest_efer |= host_efer & ignore_bits;
393         wrmsrl(MSR_EFER, guest_efer);
394         vmx->vcpu.stat.efer_reload++;
395 }
396
397 static void reload_host_efer(struct vcpu_vmx *vmx)
398 {
399         if (vmx->host_state.guest_efer_loaded) {
400                 vmx->host_state.guest_efer_loaded = 0;
401                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
402         }
403 }
404
405 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
406 {
407         struct vcpu_vmx *vmx = to_vmx(vcpu);
408
409         if (vmx->host_state.loaded)
410                 return;
411
412         vmx->host_state.loaded = 1;
413         /*
414          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
415          * allow segment selectors with cpl > 0 or ti == 1.
416          */
417         vmx->host_state.ldt_sel = read_ldt();
418         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
419         vmx->host_state.fs_sel = read_fs();
420         if (!(vmx->host_state.fs_sel & 7)) {
421                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
422                 vmx->host_state.fs_reload_needed = 0;
423         } else {
424                 vmcs_write16(HOST_FS_SELECTOR, 0);
425                 vmx->host_state.fs_reload_needed = 1;
426         }
427         vmx->host_state.gs_sel = read_gs();
428         if (!(vmx->host_state.gs_sel & 7))
429                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
430         else {
431                 vmcs_write16(HOST_GS_SELECTOR, 0);
432                 vmx->host_state.gs_ldt_reload_needed = 1;
433         }
434
435 #ifdef CONFIG_X86_64
436         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
437         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
438 #else
439         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
440         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
441 #endif
442
443 #ifdef CONFIG_X86_64
444         if (is_long_mode(&vmx->vcpu))
445                 save_msrs(vmx->host_msrs +
446                           vmx->msr_offset_kernel_gs_base, 1);
447
448 #endif
449         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
450         load_transition_efer(vmx);
451 }
452
453 static void vmx_load_host_state(struct vcpu_vmx *vmx)
454 {
455         unsigned long flags;
456
457         if (!vmx->host_state.loaded)
458                 return;
459
460         ++vmx->vcpu.stat.host_state_reload;
461         vmx->host_state.loaded = 0;
462         if (vmx->host_state.fs_reload_needed)
463                 load_fs(vmx->host_state.fs_sel);
464         if (vmx->host_state.gs_ldt_reload_needed) {
465                 load_ldt(vmx->host_state.ldt_sel);
466                 /*
467                  * If we have to reload gs, we must take care to
468                  * preserve our gs base.
469                  */
470                 local_irq_save(flags);
471                 load_gs(vmx->host_state.gs_sel);
472 #ifdef CONFIG_X86_64
473                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
474 #endif
475                 local_irq_restore(flags);
476         }
477         reload_tss();
478         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
479         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
480         reload_host_efer(vmx);
481 }
482
483 /*
484  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
485  * vcpu mutex is already taken.
486  */
487 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
488 {
489         struct vcpu_vmx *vmx = to_vmx(vcpu);
490         u64 phys_addr = __pa(vmx->vmcs);
491         u64 tsc_this, delta;
492
493         if (vcpu->cpu != cpu) {
494                 vcpu_clear(vmx);
495                 kvm_migrate_apic_timer(vcpu);
496         }
497
498         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
499                 u8 error;
500
501                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
502                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
503                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
504                               : "cc");
505                 if (error)
506                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
507                                vmx->vmcs, phys_addr);
508         }
509
510         if (vcpu->cpu != cpu) {
511                 struct descriptor_table dt;
512                 unsigned long sysenter_esp;
513
514                 vcpu->cpu = cpu;
515                 /*
516                  * Linux uses per-cpu TSS and GDT, so set these when switching
517                  * processors.
518                  */
519                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
520                 get_gdt(&dt);
521                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
522
523                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
524                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
525
526                 /*
527                  * Make sure the time stamp counter is monotonous.
528                  */
529                 rdtscll(tsc_this);
530                 delta = vcpu->arch.host_tsc - tsc_this;
531                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
532         }
533 }
534
535 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
536 {
537         vmx_load_host_state(to_vmx(vcpu));
538 }
539
540 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
541 {
542         if (vcpu->fpu_active)
543                 return;
544         vcpu->fpu_active = 1;
545         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
546         if (vcpu->arch.cr0 & X86_CR0_TS)
547                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
548         update_exception_bitmap(vcpu);
549 }
550
551 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
552 {
553         if (!vcpu->fpu_active)
554                 return;
555         vcpu->fpu_active = 0;
556         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
557         update_exception_bitmap(vcpu);
558 }
559
560 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
561 {
562         vcpu_clear(to_vmx(vcpu));
563 }
564
565 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
566 {
567         return vmcs_readl(GUEST_RFLAGS);
568 }
569
570 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
571 {
572         if (vcpu->arch.rmode.active)
573                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
574         vmcs_writel(GUEST_RFLAGS, rflags);
575 }
576
577 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
578 {
579         unsigned long rip;
580         u32 interruptibility;
581
582         rip = vmcs_readl(GUEST_RIP);
583         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
584         vmcs_writel(GUEST_RIP, rip);
585
586         /*
587          * We emulated an instruction, so temporary interrupt blocking
588          * should be removed, if set.
589          */
590         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
591         if (interruptibility & 3)
592                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
593                              interruptibility & ~3);
594         vcpu->arch.interrupt_window_open = 1;
595 }
596
597 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
598                                 bool has_error_code, u32 error_code)
599 {
600         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
601                      nr | INTR_TYPE_EXCEPTION
602                      | (has_error_code ? INTR_INFO_DELIEVER_CODE_MASK : 0)
603                      | INTR_INFO_VALID_MASK);
604         if (has_error_code)
605                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
606 }
607
608 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
609 {
610         struct vcpu_vmx *vmx = to_vmx(vcpu);
611
612         return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
613 }
614
615 /*
616  * Swap MSR entry in host/guest MSR entry array.
617  */
618 #ifdef CONFIG_X86_64
619 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
620 {
621         struct kvm_msr_entry tmp;
622
623         tmp = vmx->guest_msrs[to];
624         vmx->guest_msrs[to] = vmx->guest_msrs[from];
625         vmx->guest_msrs[from] = tmp;
626         tmp = vmx->host_msrs[to];
627         vmx->host_msrs[to] = vmx->host_msrs[from];
628         vmx->host_msrs[from] = tmp;
629 }
630 #endif
631
632 /*
633  * Set up the vmcs to automatically save and restore system
634  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
635  * mode, as fiddling with msrs is very expensive.
636  */
637 static void setup_msrs(struct vcpu_vmx *vmx)
638 {
639         int save_nmsrs;
640
641         save_nmsrs = 0;
642 #ifdef CONFIG_X86_64
643         if (is_long_mode(&vmx->vcpu)) {
644                 int index;
645
646                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
647                 if (index >= 0)
648                         move_msr_up(vmx, index, save_nmsrs++);
649                 index = __find_msr_index(vmx, MSR_LSTAR);
650                 if (index >= 0)
651                         move_msr_up(vmx, index, save_nmsrs++);
652                 index = __find_msr_index(vmx, MSR_CSTAR);
653                 if (index >= 0)
654                         move_msr_up(vmx, index, save_nmsrs++);
655                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
656                 if (index >= 0)
657                         move_msr_up(vmx, index, save_nmsrs++);
658                 /*
659                  * MSR_K6_STAR is only needed on long mode guests, and only
660                  * if efer.sce is enabled.
661                  */
662                 index = __find_msr_index(vmx, MSR_K6_STAR);
663                 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
664                         move_msr_up(vmx, index, save_nmsrs++);
665         }
666 #endif
667         vmx->save_nmsrs = save_nmsrs;
668
669 #ifdef CONFIG_X86_64
670         vmx->msr_offset_kernel_gs_base =
671                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
672 #endif
673         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
674 }
675
676 /*
677  * reads and returns guest's timestamp counter "register"
678  * guest_tsc = host_tsc + tsc_offset    -- 21.3
679  */
680 static u64 guest_read_tsc(void)
681 {
682         u64 host_tsc, tsc_offset;
683
684         rdtscll(host_tsc);
685         tsc_offset = vmcs_read64(TSC_OFFSET);
686         return host_tsc + tsc_offset;
687 }
688
689 /*
690  * writes 'guest_tsc' into guest's timestamp counter "register"
691  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
692  */
693 static void guest_write_tsc(u64 guest_tsc)
694 {
695         u64 host_tsc;
696
697         rdtscll(host_tsc);
698         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
699 }
700
701 /*
702  * Reads an msr value (of 'msr_index') into 'pdata'.
703  * Returns 0 on success, non-0 otherwise.
704  * Assumes vcpu_load() was already called.
705  */
706 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
707 {
708         u64 data;
709         struct kvm_msr_entry *msr;
710
711         if (!pdata) {
712                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
713                 return -EINVAL;
714         }
715
716         switch (msr_index) {
717 #ifdef CONFIG_X86_64
718         case MSR_FS_BASE:
719                 data = vmcs_readl(GUEST_FS_BASE);
720                 break;
721         case MSR_GS_BASE:
722                 data = vmcs_readl(GUEST_GS_BASE);
723                 break;
724         case MSR_EFER:
725                 return kvm_get_msr_common(vcpu, msr_index, pdata);
726 #endif
727         case MSR_IA32_TIME_STAMP_COUNTER:
728                 data = guest_read_tsc();
729                 break;
730         case MSR_IA32_SYSENTER_CS:
731                 data = vmcs_read32(GUEST_SYSENTER_CS);
732                 break;
733         case MSR_IA32_SYSENTER_EIP:
734                 data = vmcs_readl(GUEST_SYSENTER_EIP);
735                 break;
736         case MSR_IA32_SYSENTER_ESP:
737                 data = vmcs_readl(GUEST_SYSENTER_ESP);
738                 break;
739         default:
740                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
741                 if (msr) {
742                         data = msr->data;
743                         break;
744                 }
745                 return kvm_get_msr_common(vcpu, msr_index, pdata);
746         }
747
748         *pdata = data;
749         return 0;
750 }
751
752 /*
753  * Writes msr value into into the appropriate "register".
754  * Returns 0 on success, non-0 otherwise.
755  * Assumes vcpu_load() was already called.
756  */
757 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
758 {
759         struct vcpu_vmx *vmx = to_vmx(vcpu);
760         struct kvm_msr_entry *msr;
761         int ret = 0;
762
763         switch (msr_index) {
764 #ifdef CONFIG_X86_64
765         case MSR_EFER:
766                 ret = kvm_set_msr_common(vcpu, msr_index, data);
767                 if (vmx->host_state.loaded) {
768                         reload_host_efer(vmx);
769                         load_transition_efer(vmx);
770                 }
771                 break;
772         case MSR_FS_BASE:
773                 vmcs_writel(GUEST_FS_BASE, data);
774                 break;
775         case MSR_GS_BASE:
776                 vmcs_writel(GUEST_GS_BASE, data);
777                 break;
778 #endif
779         case MSR_IA32_SYSENTER_CS:
780                 vmcs_write32(GUEST_SYSENTER_CS, data);
781                 break;
782         case MSR_IA32_SYSENTER_EIP:
783                 vmcs_writel(GUEST_SYSENTER_EIP, data);
784                 break;
785         case MSR_IA32_SYSENTER_ESP:
786                 vmcs_writel(GUEST_SYSENTER_ESP, data);
787                 break;
788         case MSR_IA32_TIME_STAMP_COUNTER:
789                 guest_write_tsc(data);
790                 break;
791         default:
792                 msr = find_msr_entry(vmx, msr_index);
793                 if (msr) {
794                         msr->data = data;
795                         if (vmx->host_state.loaded)
796                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
797                         break;
798                 }
799                 ret = kvm_set_msr_common(vcpu, msr_index, data);
800         }
801
802         return ret;
803 }
804
805 /*
806  * Sync the rsp and rip registers into the vcpu structure.  This allows
807  * registers to be accessed by indexing vcpu->arch.regs.
808  */
809 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
810 {
811         vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
812         vcpu->arch.rip = vmcs_readl(GUEST_RIP);
813 }
814
815 /*
816  * Syncs rsp and rip back into the vmcs.  Should be called after possible
817  * modification.
818  */
819 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
820 {
821         vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
822         vmcs_writel(GUEST_RIP, vcpu->arch.rip);
823 }
824
825 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
826 {
827         unsigned long dr7 = 0x400;
828         int old_singlestep;
829
830         old_singlestep = vcpu->guest_debug.singlestep;
831
832         vcpu->guest_debug.enabled = dbg->enabled;
833         if (vcpu->guest_debug.enabled) {
834                 int i;
835
836                 dr7 |= 0x200;  /* exact */
837                 for (i = 0; i < 4; ++i) {
838                         if (!dbg->breakpoints[i].enabled)
839                                 continue;
840                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
841                         dr7 |= 2 << (i*2);    /* global enable */
842                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
843                 }
844
845                 vcpu->guest_debug.singlestep = dbg->singlestep;
846         } else
847                 vcpu->guest_debug.singlestep = 0;
848
849         if (old_singlestep && !vcpu->guest_debug.singlestep) {
850                 unsigned long flags;
851
852                 flags = vmcs_readl(GUEST_RFLAGS);
853                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
854                 vmcs_writel(GUEST_RFLAGS, flags);
855         }
856
857         update_exception_bitmap(vcpu);
858         vmcs_writel(GUEST_DR7, dr7);
859
860         return 0;
861 }
862
863 static int vmx_get_irq(struct kvm_vcpu *vcpu)
864 {
865         struct vcpu_vmx *vmx = to_vmx(vcpu);
866         u32 idtv_info_field;
867
868         idtv_info_field = vmx->idt_vectoring_info;
869         if (idtv_info_field & INTR_INFO_VALID_MASK) {
870                 if (is_external_interrupt(idtv_info_field))
871                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
872                 else
873                         printk(KERN_DEBUG "pending exception: not handled yet\n");
874         }
875         return -1;
876 }
877
878 static __init int cpu_has_kvm_support(void)
879 {
880         unsigned long ecx = cpuid_ecx(1);
881         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
882 }
883
884 static __init int vmx_disabled_by_bios(void)
885 {
886         u64 msr;
887
888         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
889         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
890                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
891             == MSR_IA32_FEATURE_CONTROL_LOCKED;
892         /* locked but not enabled */
893 }
894
895 static void hardware_enable(void *garbage)
896 {
897         int cpu = raw_smp_processor_id();
898         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
899         u64 old;
900
901         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
902         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
903                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
904             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
905                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
906                 /* enable and lock */
907                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
908                        MSR_IA32_FEATURE_CONTROL_LOCKED |
909                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
910         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
911         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
912                       : "memory", "cc");
913 }
914
915 static void hardware_disable(void *garbage)
916 {
917         asm volatile (ASM_VMX_VMXOFF : : : "cc");
918 }
919
920 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
921                                       u32 msr, u32 *result)
922 {
923         u32 vmx_msr_low, vmx_msr_high;
924         u32 ctl = ctl_min | ctl_opt;
925
926         rdmsr(msr, vmx_msr_low, vmx_msr_high);
927
928         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
929         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
930
931         /* Ensure minimum (required) set of control bits are supported. */
932         if (ctl_min & ~ctl)
933                 return -EIO;
934
935         *result = ctl;
936         return 0;
937 }
938
939 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
940 {
941         u32 vmx_msr_low, vmx_msr_high;
942         u32 min, opt;
943         u32 _pin_based_exec_control = 0;
944         u32 _cpu_based_exec_control = 0;
945         u32 _cpu_based_2nd_exec_control = 0;
946         u32 _vmexit_control = 0;
947         u32 _vmentry_control = 0;
948
949         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
950         opt = 0;
951         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
952                                 &_pin_based_exec_control) < 0)
953                 return -EIO;
954
955         min = CPU_BASED_HLT_EXITING |
956 #ifdef CONFIG_X86_64
957               CPU_BASED_CR8_LOAD_EXITING |
958               CPU_BASED_CR8_STORE_EXITING |
959 #endif
960               CPU_BASED_USE_IO_BITMAPS |
961               CPU_BASED_MOV_DR_EXITING |
962               CPU_BASED_USE_TSC_OFFSETING;
963         opt = CPU_BASED_TPR_SHADOW |
964               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
965         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
966                                 &_cpu_based_exec_control) < 0)
967                 return -EIO;
968 #ifdef CONFIG_X86_64
969         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
970                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
971                                            ~CPU_BASED_CR8_STORE_EXITING;
972 #endif
973         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
974                 min = 0;
975                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
976                         SECONDARY_EXEC_WBINVD_EXITING;
977                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
978                                         &_cpu_based_2nd_exec_control) < 0)
979                         return -EIO;
980         }
981 #ifndef CONFIG_X86_64
982         if (!(_cpu_based_2nd_exec_control &
983                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
984                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
985 #endif
986
987         min = 0;
988 #ifdef CONFIG_X86_64
989         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
990 #endif
991         opt = 0;
992         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
993                                 &_vmexit_control) < 0)
994                 return -EIO;
995
996         min = opt = 0;
997         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
998                                 &_vmentry_control) < 0)
999                 return -EIO;
1000
1001         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1002
1003         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1004         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1005                 return -EIO;
1006
1007 #ifdef CONFIG_X86_64
1008         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1009         if (vmx_msr_high & (1u<<16))
1010                 return -EIO;
1011 #endif
1012
1013         /* Require Write-Back (WB) memory type for VMCS accesses. */
1014         if (((vmx_msr_high >> 18) & 15) != 6)
1015                 return -EIO;
1016
1017         vmcs_conf->size = vmx_msr_high & 0x1fff;
1018         vmcs_conf->order = get_order(vmcs_config.size);
1019         vmcs_conf->revision_id = vmx_msr_low;
1020
1021         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1022         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1023         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1024         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1025         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1026
1027         return 0;
1028 }
1029
1030 static struct vmcs *alloc_vmcs_cpu(int cpu)
1031 {
1032         int node = cpu_to_node(cpu);
1033         struct page *pages;
1034         struct vmcs *vmcs;
1035
1036         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1037         if (!pages)
1038                 return NULL;
1039         vmcs = page_address(pages);
1040         memset(vmcs, 0, vmcs_config.size);
1041         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1042         return vmcs;
1043 }
1044
1045 static struct vmcs *alloc_vmcs(void)
1046 {
1047         return alloc_vmcs_cpu(raw_smp_processor_id());
1048 }
1049
1050 static void free_vmcs(struct vmcs *vmcs)
1051 {
1052         free_pages((unsigned long)vmcs, vmcs_config.order);
1053 }
1054
1055 static void free_kvm_area(void)
1056 {
1057         int cpu;
1058
1059         for_each_online_cpu(cpu)
1060                 free_vmcs(per_cpu(vmxarea, cpu));
1061 }
1062
1063 static __init int alloc_kvm_area(void)
1064 {
1065         int cpu;
1066
1067         for_each_online_cpu(cpu) {
1068                 struct vmcs *vmcs;
1069
1070                 vmcs = alloc_vmcs_cpu(cpu);
1071                 if (!vmcs) {
1072                         free_kvm_area();
1073                         return -ENOMEM;
1074                 }
1075
1076                 per_cpu(vmxarea, cpu) = vmcs;
1077         }
1078         return 0;
1079 }
1080
1081 static __init int hardware_setup(void)
1082 {
1083         if (setup_vmcs_config(&vmcs_config) < 0)
1084                 return -EIO;
1085         return alloc_kvm_area();
1086 }
1087
1088 static __exit void hardware_unsetup(void)
1089 {
1090         free_kvm_area();
1091 }
1092
1093 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1094 {
1095         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1096
1097         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1098                 vmcs_write16(sf->selector, save->selector);
1099                 vmcs_writel(sf->base, save->base);
1100                 vmcs_write32(sf->limit, save->limit);
1101                 vmcs_write32(sf->ar_bytes, save->ar);
1102         } else {
1103                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1104                         << AR_DPL_SHIFT;
1105                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1106         }
1107 }
1108
1109 static void enter_pmode(struct kvm_vcpu *vcpu)
1110 {
1111         unsigned long flags;
1112
1113         vcpu->arch.rmode.active = 0;
1114
1115         vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1116         vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1117         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1118
1119         flags = vmcs_readl(GUEST_RFLAGS);
1120         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1121         flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1122         vmcs_writel(GUEST_RFLAGS, flags);
1123
1124         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1125                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1126
1127         update_exception_bitmap(vcpu);
1128
1129         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1130         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1131         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1132         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1133
1134         vmcs_write16(GUEST_SS_SELECTOR, 0);
1135         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1136
1137         vmcs_write16(GUEST_CS_SELECTOR,
1138                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1139         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1140 }
1141
1142 static gva_t rmode_tss_base(struct kvm *kvm)
1143 {
1144         if (!kvm->arch.tss_addr) {
1145                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1146                                  kvm->memslots[0].npages - 3;
1147                 return base_gfn << PAGE_SHIFT;
1148         }
1149         return kvm->arch.tss_addr;
1150 }
1151
1152 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1153 {
1154         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1155
1156         save->selector = vmcs_read16(sf->selector);
1157         save->base = vmcs_readl(sf->base);
1158         save->limit = vmcs_read32(sf->limit);
1159         save->ar = vmcs_read32(sf->ar_bytes);
1160         vmcs_write16(sf->selector, save->base >> 4);
1161         vmcs_write32(sf->base, save->base & 0xfffff);
1162         vmcs_write32(sf->limit, 0xffff);
1163         vmcs_write32(sf->ar_bytes, 0xf3);
1164 }
1165
1166 static void enter_rmode(struct kvm_vcpu *vcpu)
1167 {
1168         unsigned long flags;
1169
1170         vcpu->arch.rmode.active = 1;
1171
1172         vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1173         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1174
1175         vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1176         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1177
1178         vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1179         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1180
1181         flags = vmcs_readl(GUEST_RFLAGS);
1182         vcpu->arch.rmode.save_iopl
1183                 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1184
1185         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1186
1187         vmcs_writel(GUEST_RFLAGS, flags);
1188         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1189         update_exception_bitmap(vcpu);
1190
1191         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1192         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1193         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1194
1195         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1196         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1197         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1198                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1199         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1200
1201         fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1202         fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1203         fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1204         fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1205
1206         kvm_mmu_reset_context(vcpu);
1207         init_rmode_tss(vcpu->kvm);
1208 }
1209
1210 #ifdef CONFIG_X86_64
1211
1212 static void enter_lmode(struct kvm_vcpu *vcpu)
1213 {
1214         u32 guest_tr_ar;
1215
1216         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1217         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1218                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1219                        __FUNCTION__);
1220                 vmcs_write32(GUEST_TR_AR_BYTES,
1221                              (guest_tr_ar & ~AR_TYPE_MASK)
1222                              | AR_TYPE_BUSY_64_TSS);
1223         }
1224
1225         vcpu->arch.shadow_efer |= EFER_LMA;
1226
1227         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1228         vmcs_write32(VM_ENTRY_CONTROLS,
1229                      vmcs_read32(VM_ENTRY_CONTROLS)
1230                      | VM_ENTRY_IA32E_MODE);
1231 }
1232
1233 static void exit_lmode(struct kvm_vcpu *vcpu)
1234 {
1235         vcpu->arch.shadow_efer &= ~EFER_LMA;
1236
1237         vmcs_write32(VM_ENTRY_CONTROLS,
1238                      vmcs_read32(VM_ENTRY_CONTROLS)
1239                      & ~VM_ENTRY_IA32E_MODE);
1240 }
1241
1242 #endif
1243
1244 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1245 {
1246         vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1247         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1248 }
1249
1250 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1251 {
1252         vmx_fpu_deactivate(vcpu);
1253
1254         if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1255                 enter_pmode(vcpu);
1256
1257         if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1258                 enter_rmode(vcpu);
1259
1260 #ifdef CONFIG_X86_64
1261         if (vcpu->arch.shadow_efer & EFER_LME) {
1262                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1263                         enter_lmode(vcpu);
1264                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1265                         exit_lmode(vcpu);
1266         }
1267 #endif
1268
1269         vmcs_writel(CR0_READ_SHADOW, cr0);
1270         vmcs_writel(GUEST_CR0,
1271                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1272         vcpu->arch.cr0 = cr0;
1273
1274         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1275                 vmx_fpu_activate(vcpu);
1276 }
1277
1278 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1279 {
1280         vmcs_writel(GUEST_CR3, cr3);
1281         if (vcpu->arch.cr0 & X86_CR0_PE)
1282                 vmx_fpu_deactivate(vcpu);
1283 }
1284
1285 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1286 {
1287         vmcs_writel(CR4_READ_SHADOW, cr4);
1288         vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
1289                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1290         vcpu->arch.cr4 = cr4;
1291 }
1292
1293 #ifdef CONFIG_X86_64
1294
1295 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1296 {
1297         struct vcpu_vmx *vmx = to_vmx(vcpu);
1298         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1299
1300         vcpu->arch.shadow_efer = efer;
1301         if (efer & EFER_LMA) {
1302                 vmcs_write32(VM_ENTRY_CONTROLS,
1303                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1304                                      VM_ENTRY_IA32E_MODE);
1305                 msr->data = efer;
1306
1307         } else {
1308                 vmcs_write32(VM_ENTRY_CONTROLS,
1309                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1310                                      ~VM_ENTRY_IA32E_MODE);
1311
1312                 msr->data = efer & ~EFER_LME;
1313         }
1314         setup_msrs(vmx);
1315 }
1316
1317 #endif
1318
1319 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1320 {
1321         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1322
1323         return vmcs_readl(sf->base);
1324 }
1325
1326 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1327                             struct kvm_segment *var, int seg)
1328 {
1329         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1330         u32 ar;
1331
1332         var->base = vmcs_readl(sf->base);
1333         var->limit = vmcs_read32(sf->limit);
1334         var->selector = vmcs_read16(sf->selector);
1335         ar = vmcs_read32(sf->ar_bytes);
1336         if (ar & AR_UNUSABLE_MASK)
1337                 ar = 0;
1338         var->type = ar & 15;
1339         var->s = (ar >> 4) & 1;
1340         var->dpl = (ar >> 5) & 3;
1341         var->present = (ar >> 7) & 1;
1342         var->avl = (ar >> 12) & 1;
1343         var->l = (ar >> 13) & 1;
1344         var->db = (ar >> 14) & 1;
1345         var->g = (ar >> 15) & 1;
1346         var->unusable = (ar >> 16) & 1;
1347 }
1348
1349 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1350 {
1351         u32 ar;
1352
1353         if (var->unusable)
1354                 ar = 1 << 16;
1355         else {
1356                 ar = var->type & 15;
1357                 ar |= (var->s & 1) << 4;
1358                 ar |= (var->dpl & 3) << 5;
1359                 ar |= (var->present & 1) << 7;
1360                 ar |= (var->avl & 1) << 12;
1361                 ar |= (var->l & 1) << 13;
1362                 ar |= (var->db & 1) << 14;
1363                 ar |= (var->g & 1) << 15;
1364         }
1365         if (ar == 0) /* a 0 value means unusable */
1366                 ar = AR_UNUSABLE_MASK;
1367
1368         return ar;
1369 }
1370
1371 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1372                             struct kvm_segment *var, int seg)
1373 {
1374         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1375         u32 ar;
1376
1377         if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1378                 vcpu->arch.rmode.tr.selector = var->selector;
1379                 vcpu->arch.rmode.tr.base = var->base;
1380                 vcpu->arch.rmode.tr.limit = var->limit;
1381                 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1382                 return;
1383         }
1384         vmcs_writel(sf->base, var->base);
1385         vmcs_write32(sf->limit, var->limit);
1386         vmcs_write16(sf->selector, var->selector);
1387         if (vcpu->arch.rmode.active && var->s) {
1388                 /*
1389                  * Hack real-mode segments into vm86 compatibility.
1390                  */
1391                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1392                         vmcs_writel(sf->base, 0xf0000);
1393                 ar = 0xf3;
1394         } else
1395                 ar = vmx_segment_access_rights(var);
1396         vmcs_write32(sf->ar_bytes, ar);
1397 }
1398
1399 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1400 {
1401         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1402
1403         *db = (ar >> 14) & 1;
1404         *l = (ar >> 13) & 1;
1405 }
1406
1407 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1408 {
1409         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1410         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1411 }
1412
1413 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1414 {
1415         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1416         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1417 }
1418
1419 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1420 {
1421         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1422         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1423 }
1424
1425 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1426 {
1427         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1428         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1429 }
1430
1431 static int init_rmode_tss(struct kvm *kvm)
1432 {
1433         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1434         u16 data = 0;
1435         int ret = 0;
1436         int r;
1437
1438         down_read(&current->mm->mmap_sem);
1439         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1440         if (r < 0)
1441                 goto out;
1442         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1443         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1444         if (r < 0)
1445                 goto out;
1446         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1447         if (r < 0)
1448                 goto out;
1449         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1450         if (r < 0)
1451                 goto out;
1452         data = ~0;
1453         r = kvm_write_guest_page(kvm, fn, &data,
1454                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1455                                  sizeof(u8));
1456         if (r < 0)
1457                 goto out;
1458
1459         ret = 1;
1460 out:
1461         up_read(&current->mm->mmap_sem);
1462         return ret;
1463 }
1464
1465 static void seg_setup(int seg)
1466 {
1467         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1468
1469         vmcs_write16(sf->selector, 0);
1470         vmcs_writel(sf->base, 0);
1471         vmcs_write32(sf->limit, 0xffff);
1472         vmcs_write32(sf->ar_bytes, 0x93);
1473 }
1474
1475 static int alloc_apic_access_page(struct kvm *kvm)
1476 {
1477         struct kvm_userspace_memory_region kvm_userspace_mem;
1478         int r = 0;
1479
1480         down_write(&kvm->slots_lock);
1481         if (kvm->arch.apic_access_page)
1482                 goto out;
1483         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1484         kvm_userspace_mem.flags = 0;
1485         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1486         kvm_userspace_mem.memory_size = PAGE_SIZE;
1487         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1488         if (r)
1489                 goto out;
1490
1491         down_read(&current->mm->mmap_sem);
1492         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1493         up_read(&current->mm->mmap_sem);
1494 out:
1495         up_write(&kvm->slots_lock);
1496         return r;
1497 }
1498
1499 /*
1500  * Sets up the vmcs for emulated real mode.
1501  */
1502 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1503 {
1504         u32 host_sysenter_cs;
1505         u32 junk;
1506         unsigned long a;
1507         struct descriptor_table dt;
1508         int i;
1509         unsigned long kvm_vmx_return;
1510         u32 exec_control;
1511
1512         /* I/O */
1513         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1514         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1515
1516         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1517
1518         /* Control */
1519         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1520                 vmcs_config.pin_based_exec_ctrl);
1521
1522         exec_control = vmcs_config.cpu_based_exec_ctrl;
1523         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1524                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1525 #ifdef CONFIG_X86_64
1526                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1527                                 CPU_BASED_CR8_LOAD_EXITING;
1528 #endif
1529         }
1530         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1531
1532         if (cpu_has_secondary_exec_ctrls()) {
1533                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1534                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1535                         exec_control &=
1536                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1537                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1538         }
1539
1540         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1541         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1542         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1543
1544         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1545         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1546         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1547
1548         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1549         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1550         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1551         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1552         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1553         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1554 #ifdef CONFIG_X86_64
1555         rdmsrl(MSR_FS_BASE, a);
1556         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1557         rdmsrl(MSR_GS_BASE, a);
1558         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1559 #else
1560         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1561         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1562 #endif
1563
1564         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1565
1566         get_idt(&dt);
1567         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1568
1569         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1570         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1571         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1572         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1573         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1574
1575         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1576         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1577         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1578         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1579         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1580         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1581
1582         for (i = 0; i < NR_VMX_MSR; ++i) {
1583                 u32 index = vmx_msr_index[i];
1584                 u32 data_low, data_high;
1585                 u64 data;
1586                 int j = vmx->nmsrs;
1587
1588                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1589                         continue;
1590                 if (wrmsr_safe(index, data_low, data_high) < 0)
1591                         continue;
1592                 data = data_low | ((u64)data_high << 32);
1593                 vmx->host_msrs[j].index = index;
1594                 vmx->host_msrs[j].reserved = 0;
1595                 vmx->host_msrs[j].data = data;
1596                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1597                 ++vmx->nmsrs;
1598         }
1599
1600         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1601
1602         /* 22.2.1, 20.8.1 */
1603         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1604
1605         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1606         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1607
1608         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1609                 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1610                         return -ENOMEM;
1611
1612         return 0;
1613 }
1614
1615 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1616 {
1617         struct vcpu_vmx *vmx = to_vmx(vcpu);
1618         u64 msr;
1619         int ret;
1620
1621         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1622                 ret = -ENOMEM;
1623                 goto out;
1624         }
1625
1626         vmx->vcpu.arch.rmode.active = 0;
1627
1628         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1629         set_cr8(&vmx->vcpu, 0);
1630         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1631         if (vmx->vcpu.vcpu_id == 0)
1632                 msr |= MSR_IA32_APICBASE_BSP;
1633         kvm_set_apic_base(&vmx->vcpu, msr);
1634
1635         fx_init(&vmx->vcpu);
1636
1637         /*
1638          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1639          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1640          */
1641         if (vmx->vcpu.vcpu_id == 0) {
1642                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1643                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1644         } else {
1645                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1646                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
1647         }
1648         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1649         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1650
1651         seg_setup(VCPU_SREG_DS);
1652         seg_setup(VCPU_SREG_ES);
1653         seg_setup(VCPU_SREG_FS);
1654         seg_setup(VCPU_SREG_GS);
1655         seg_setup(VCPU_SREG_SS);
1656
1657         vmcs_write16(GUEST_TR_SELECTOR, 0);
1658         vmcs_writel(GUEST_TR_BASE, 0);
1659         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1660         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1661
1662         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1663         vmcs_writel(GUEST_LDTR_BASE, 0);
1664         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1665         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1666
1667         vmcs_write32(GUEST_SYSENTER_CS, 0);
1668         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1669         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1670
1671         vmcs_writel(GUEST_RFLAGS, 0x02);
1672         if (vmx->vcpu.vcpu_id == 0)
1673                 vmcs_writel(GUEST_RIP, 0xfff0);
1674         else
1675                 vmcs_writel(GUEST_RIP, 0);
1676         vmcs_writel(GUEST_RSP, 0);
1677
1678         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1679         vmcs_writel(GUEST_DR7, 0x400);
1680
1681         vmcs_writel(GUEST_GDTR_BASE, 0);
1682         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1683
1684         vmcs_writel(GUEST_IDTR_BASE, 0);
1685         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1686
1687         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1688         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1689         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1690
1691         guest_write_tsc(0);
1692
1693         /* Special registers */
1694         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1695
1696         setup_msrs(vmx);
1697
1698         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1699
1700         if (cpu_has_vmx_tpr_shadow()) {
1701                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1702                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1703                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1704                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
1705                 vmcs_write32(TPR_THRESHOLD, 0);
1706         }
1707
1708         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1709                 vmcs_write64(APIC_ACCESS_ADDR,
1710                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
1711
1712         vmx->vcpu.arch.cr0 = 0x60000010;
1713         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
1714         vmx_set_cr4(&vmx->vcpu, 0);
1715 #ifdef CONFIG_X86_64
1716         vmx_set_efer(&vmx->vcpu, 0);
1717 #endif
1718         vmx_fpu_activate(&vmx->vcpu);
1719         update_exception_bitmap(&vmx->vcpu);
1720
1721         return 0;
1722
1723 out:
1724         return ret;
1725 }
1726
1727 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1728 {
1729         struct vcpu_vmx *vmx = to_vmx(vcpu);
1730
1731         if (vcpu->arch.rmode.active) {
1732                 vmx->rmode.irq.pending = true;
1733                 vmx->rmode.irq.vector = irq;
1734                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1735                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1736                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1737                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1738                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1739                 return;
1740         }
1741         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1742                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1743 }
1744
1745 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1746 {
1747         int word_index = __ffs(vcpu->arch.irq_summary);
1748         int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1749         int irq = word_index * BITS_PER_LONG + bit_index;
1750
1751         clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1752         if (!vcpu->arch.irq_pending[word_index])
1753                 clear_bit(word_index, &vcpu->arch.irq_summary);
1754         vmx_inject_irq(vcpu, irq);
1755 }
1756
1757
1758 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1759                                        struct kvm_run *kvm_run)
1760 {
1761         u32 cpu_based_vm_exec_control;
1762
1763         vcpu->arch.interrupt_window_open =
1764                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1765                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1766
1767         if (vcpu->arch.interrupt_window_open &&
1768             vcpu->arch.irq_summary &&
1769             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1770                 /*
1771                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1772                  */
1773                 kvm_do_inject_irq(vcpu);
1774
1775         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1776         if (!vcpu->arch.interrupt_window_open &&
1777             (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
1778                 /*
1779                  * Interrupts blocked.  Wait for unblock.
1780                  */
1781                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1782         else
1783                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1784         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1785 }
1786
1787 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1788 {
1789         int ret;
1790         struct kvm_userspace_memory_region tss_mem = {
1791                 .slot = 8,
1792                 .guest_phys_addr = addr,
1793                 .memory_size = PAGE_SIZE * 3,
1794                 .flags = 0,
1795         };
1796
1797         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1798         if (ret)
1799                 return ret;
1800         kvm->arch.tss_addr = addr;
1801         return 0;
1802 }
1803
1804 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1805 {
1806         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1807
1808         set_debugreg(dbg->bp[0], 0);
1809         set_debugreg(dbg->bp[1], 1);
1810         set_debugreg(dbg->bp[2], 2);
1811         set_debugreg(dbg->bp[3], 3);
1812
1813         if (dbg->singlestep) {
1814                 unsigned long flags;
1815
1816                 flags = vmcs_readl(GUEST_RFLAGS);
1817                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1818                 vmcs_writel(GUEST_RFLAGS, flags);
1819         }
1820 }
1821
1822 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1823                                   int vec, u32 err_code)
1824 {
1825         if (!vcpu->arch.rmode.active)
1826                 return 0;
1827
1828         /*
1829          * Instruction with address size override prefix opcode 0x67
1830          * Cause the #SS fault with 0 error code in VM86 mode.
1831          */
1832         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1833                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1834                         return 1;
1835         return 0;
1836 }
1837
1838 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1839 {
1840         struct vcpu_vmx *vmx = to_vmx(vcpu);
1841         u32 intr_info, error_code;
1842         unsigned long cr2, rip;
1843         u32 vect_info;
1844         enum emulation_result er;
1845
1846         vect_info = vmx->idt_vectoring_info;
1847         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1848
1849         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1850                                                 !is_page_fault(intr_info))
1851                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1852                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1853
1854         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1855                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1856                 set_bit(irq, vcpu->arch.irq_pending);
1857                 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
1858         }
1859
1860         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1861                 return 1;  /* already handled by vmx_vcpu_run() */
1862
1863         if (is_no_device(intr_info)) {
1864                 vmx_fpu_activate(vcpu);
1865                 return 1;
1866         }
1867
1868         if (is_invalid_opcode(intr_info)) {
1869                 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1870                 if (er != EMULATE_DONE)
1871                         kvm_queue_exception(vcpu, UD_VECTOR);
1872                 return 1;
1873         }
1874
1875         error_code = 0;
1876         rip = vmcs_readl(GUEST_RIP);
1877         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1878                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1879         if (is_page_fault(intr_info)) {
1880                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1881                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1882         }
1883
1884         if (vcpu->arch.rmode.active &&
1885             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1886                                                                 error_code)) {
1887                 if (vcpu->arch.halt_request) {
1888                         vcpu->arch.halt_request = 0;
1889                         return kvm_emulate_halt(vcpu);
1890                 }
1891                 return 1;
1892         }
1893
1894         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1895             (INTR_TYPE_EXCEPTION | 1)) {
1896                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1897                 return 0;
1898         }
1899         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1900         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1901         kvm_run->ex.error_code = error_code;
1902         return 0;
1903 }
1904
1905 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1906                                      struct kvm_run *kvm_run)
1907 {
1908         ++vcpu->stat.irq_exits;
1909         return 1;
1910 }
1911
1912 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1913 {
1914         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1915         return 0;
1916 }
1917
1918 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1919 {
1920         unsigned long exit_qualification;
1921         int size, down, in, string, rep;
1922         unsigned port;
1923
1924         ++vcpu->stat.io_exits;
1925         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1926         string = (exit_qualification & 16) != 0;
1927
1928         if (string) {
1929                 if (emulate_instruction(vcpu,
1930                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1931                         return 0;
1932                 return 1;
1933         }
1934
1935         size = (exit_qualification & 7) + 1;
1936         in = (exit_qualification & 8) != 0;
1937         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1938         rep = (exit_qualification & 32) != 0;
1939         port = exit_qualification >> 16;
1940
1941         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1942 }
1943
1944 static void
1945 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1946 {
1947         /*
1948          * Patch in the VMCALL instruction:
1949          */
1950         hypercall[0] = 0x0f;
1951         hypercall[1] = 0x01;
1952         hypercall[2] = 0xc1;
1953 }
1954
1955 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1956 {
1957         unsigned long exit_qualification;
1958         int cr;
1959         int reg;
1960
1961         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1962         cr = exit_qualification & 15;
1963         reg = (exit_qualification >> 8) & 15;
1964         switch ((exit_qualification >> 4) & 3) {
1965         case 0: /* mov to cr */
1966                 switch (cr) {
1967                 case 0:
1968                         vcpu_load_rsp_rip(vcpu);
1969                         set_cr0(vcpu, vcpu->arch.regs[reg]);
1970                         skip_emulated_instruction(vcpu);
1971                         return 1;
1972                 case 3:
1973                         vcpu_load_rsp_rip(vcpu);
1974                         set_cr3(vcpu, vcpu->arch.regs[reg]);
1975                         skip_emulated_instruction(vcpu);
1976                         return 1;
1977                 case 4:
1978                         vcpu_load_rsp_rip(vcpu);
1979                         set_cr4(vcpu, vcpu->arch.regs[reg]);
1980                         skip_emulated_instruction(vcpu);
1981                         return 1;
1982                 case 8:
1983                         vcpu_load_rsp_rip(vcpu);
1984                         set_cr8(vcpu, vcpu->arch.regs[reg]);
1985                         skip_emulated_instruction(vcpu);
1986                         if (irqchip_in_kernel(vcpu->kvm))
1987                                 return 1;
1988                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1989                         return 0;
1990                 };
1991                 break;
1992         case 2: /* clts */
1993                 vcpu_load_rsp_rip(vcpu);
1994                 vmx_fpu_deactivate(vcpu);
1995                 vcpu->arch.cr0 &= ~X86_CR0_TS;
1996                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1997                 vmx_fpu_activate(vcpu);
1998                 skip_emulated_instruction(vcpu);
1999                 return 1;
2000         case 1: /*mov from cr*/
2001                 switch (cr) {
2002                 case 3:
2003                         vcpu_load_rsp_rip(vcpu);
2004                         vcpu->arch.regs[reg] = vcpu->arch.cr3;
2005                         vcpu_put_rsp_rip(vcpu);
2006                         skip_emulated_instruction(vcpu);
2007                         return 1;
2008                 case 8:
2009                         vcpu_load_rsp_rip(vcpu);
2010                         vcpu->arch.regs[reg] = get_cr8(vcpu);
2011                         vcpu_put_rsp_rip(vcpu);
2012                         skip_emulated_instruction(vcpu);
2013                         return 1;
2014                 }
2015                 break;
2016         case 3: /* lmsw */
2017                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2018
2019                 skip_emulated_instruction(vcpu);
2020                 return 1;
2021         default:
2022                 break;
2023         }
2024         kvm_run->exit_reason = 0;
2025         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2026                (int)(exit_qualification >> 4) & 3, cr);
2027         return 0;
2028 }
2029
2030 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2031 {
2032         unsigned long exit_qualification;
2033         unsigned long val;
2034         int dr, reg;
2035
2036         /*
2037          * FIXME: this code assumes the host is debugging the guest.
2038          *        need to deal with guest debugging itself too.
2039          */
2040         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2041         dr = exit_qualification & 7;
2042         reg = (exit_qualification >> 8) & 15;
2043         vcpu_load_rsp_rip(vcpu);
2044         if (exit_qualification & 16) {
2045                 /* mov from dr */
2046                 switch (dr) {
2047                 case 6:
2048                         val = 0xffff0ff0;
2049                         break;
2050                 case 7:
2051                         val = 0x400;
2052                         break;
2053                 default:
2054                         val = 0;
2055                 }
2056                 vcpu->arch.regs[reg] = val;
2057         } else {
2058                 /* mov to dr */
2059         }
2060         vcpu_put_rsp_rip(vcpu);
2061         skip_emulated_instruction(vcpu);
2062         return 1;
2063 }
2064
2065 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2066 {
2067         kvm_emulate_cpuid(vcpu);
2068         return 1;
2069 }
2070
2071 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2072 {
2073         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2074         u64 data;
2075
2076         if (vmx_get_msr(vcpu, ecx, &data)) {
2077                 kvm_inject_gp(vcpu, 0);
2078                 return 1;
2079         }
2080
2081         /* FIXME: handling of bits 32:63 of rax, rdx */
2082         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2083         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2084         skip_emulated_instruction(vcpu);
2085         return 1;
2086 }
2087
2088 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2089 {
2090         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2091         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2092                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2093
2094         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2095                 kvm_inject_gp(vcpu, 0);
2096                 return 1;
2097         }
2098
2099         skip_emulated_instruction(vcpu);
2100         return 1;
2101 }
2102
2103 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2104                                       struct kvm_run *kvm_run)
2105 {
2106         return 1;
2107 }
2108
2109 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2110                                    struct kvm_run *kvm_run)
2111 {
2112         u32 cpu_based_vm_exec_control;
2113
2114         /* clear pending irq */
2115         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2116         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2117         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2118         /*
2119          * If the user space waits to inject interrupts, exit as soon as
2120          * possible
2121          */
2122         if (kvm_run->request_interrupt_window &&
2123             !vcpu->arch.irq_summary) {
2124                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2125                 ++vcpu->stat.irq_window_exits;
2126                 return 0;
2127         }
2128         return 1;
2129 }
2130
2131 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2132 {
2133         skip_emulated_instruction(vcpu);
2134         return kvm_emulate_halt(vcpu);
2135 }
2136
2137 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2138 {
2139         skip_emulated_instruction(vcpu);
2140         kvm_emulate_hypercall(vcpu);
2141         return 1;
2142 }
2143
2144 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2145 {
2146         skip_emulated_instruction(vcpu);
2147         /* TODO: Add support for VT-d/pass-through device */
2148         return 1;
2149 }
2150
2151 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2152 {
2153         u64 exit_qualification;
2154         enum emulation_result er;
2155         unsigned long offset;
2156
2157         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2158         offset = exit_qualification & 0xffful;
2159
2160         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2161
2162         if (er !=  EMULATE_DONE) {
2163                 printk(KERN_ERR
2164                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2165                        offset);
2166                 return -ENOTSUPP;
2167         }
2168         return 1;
2169 }
2170
2171 /*
2172  * The exit handlers return 1 if the exit was handled fully and guest execution
2173  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2174  * to be done to userspace and return 0.
2175  */
2176 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2177                                       struct kvm_run *kvm_run) = {
2178         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2179         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2180         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2181         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2182         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2183         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2184         [EXIT_REASON_CPUID]                   = handle_cpuid,
2185         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2186         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2187         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2188         [EXIT_REASON_HLT]                     = handle_halt,
2189         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2190         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2191         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2192         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2193 };
2194
2195 static const int kvm_vmx_max_exit_handlers =
2196         ARRAY_SIZE(kvm_vmx_exit_handlers);
2197
2198 /*
2199  * The guest has exited.  See if we can fix it or if we need userspace
2200  * assistance.
2201  */
2202 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2203 {
2204         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2205         struct vcpu_vmx *vmx = to_vmx(vcpu);
2206         u32 vectoring_info = vmx->idt_vectoring_info;
2207
2208         if (unlikely(vmx->fail)) {
2209                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2210                 kvm_run->fail_entry.hardware_entry_failure_reason
2211                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2212                 return 0;
2213         }
2214
2215         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2216                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2217                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2218                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2219         if (exit_reason < kvm_vmx_max_exit_handlers
2220             && kvm_vmx_exit_handlers[exit_reason])
2221                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2222         else {
2223                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2224                 kvm_run->hw.hardware_exit_reason = exit_reason;
2225         }
2226         return 0;
2227 }
2228
2229 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2230 {
2231 }
2232
2233 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2234 {
2235         int max_irr, tpr;
2236
2237         if (!vm_need_tpr_shadow(vcpu->kvm))
2238                 return;
2239
2240         if (!kvm_lapic_enabled(vcpu) ||
2241             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2242                 vmcs_write32(TPR_THRESHOLD, 0);
2243                 return;
2244         }
2245
2246         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2247         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2248 }
2249
2250 static void enable_irq_window(struct kvm_vcpu *vcpu)
2251 {
2252         u32 cpu_based_vm_exec_control;
2253
2254         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2255         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2256         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2257 }
2258
2259 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2260 {
2261         struct vcpu_vmx *vmx = to_vmx(vcpu);
2262         u32 idtv_info_field, intr_info_field;
2263         int has_ext_irq, interrupt_window_open;
2264         int vector;
2265
2266         update_tpr_threshold(vcpu);
2267
2268         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2269         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2270         idtv_info_field = vmx->idt_vectoring_info;
2271         if (intr_info_field & INTR_INFO_VALID_MASK) {
2272                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2273                         /* TODO: fault when IDT_Vectoring */
2274                         if (printk_ratelimit())
2275                                 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2276                 }
2277                 if (has_ext_irq)
2278                         enable_irq_window(vcpu);
2279                 return;
2280         }
2281         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2282                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2283                     == INTR_TYPE_EXT_INTR
2284                     && vcpu->arch.rmode.active) {
2285                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2286
2287                         vmx_inject_irq(vcpu, vect);
2288                         if (unlikely(has_ext_irq))
2289                                 enable_irq_window(vcpu);
2290                         return;
2291                 }
2292
2293                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2294                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2295                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2296
2297                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2298                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2299                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2300                 if (unlikely(has_ext_irq))
2301                         enable_irq_window(vcpu);
2302                 return;
2303         }
2304         if (!has_ext_irq)
2305                 return;
2306         interrupt_window_open =
2307                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2308                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2309         if (interrupt_window_open) {
2310                 vector = kvm_cpu_get_interrupt(vcpu);
2311                 vmx_inject_irq(vcpu, vector);
2312                 kvm_timer_intr_post(vcpu, vector);
2313         } else
2314                 enable_irq_window(vcpu);
2315 }
2316
2317 /*
2318  * Failure to inject an interrupt should give us the information
2319  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2320  * when fetching the interrupt redirection bitmap in the real-mode
2321  * tss, this doesn't happen.  So we do it ourselves.
2322  */
2323 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2324 {
2325         vmx->rmode.irq.pending = 0;
2326         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2327                 return;
2328         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2329         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2330                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2331                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2332                 return;
2333         }
2334         vmx->idt_vectoring_info =
2335                 VECTORING_INFO_VALID_MASK
2336                 | INTR_TYPE_EXT_INTR
2337                 | vmx->rmode.irq.vector;
2338 }
2339
2340 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2341 {
2342         struct vcpu_vmx *vmx = to_vmx(vcpu);
2343         u32 intr_info;
2344
2345         /*
2346          * Loading guest fpu may have cleared host cr0.ts
2347          */
2348         vmcs_writel(HOST_CR0, read_cr0());
2349
2350         asm(
2351                 /* Store host registers */
2352 #ifdef CONFIG_X86_64
2353                 "push %%rdx; push %%rbp;"
2354                 "push %%rcx \n\t"
2355 #else
2356                 "push %%edx; push %%ebp;"
2357                 "push %%ecx \n\t"
2358 #endif
2359                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2360                 /* Check if vmlaunch of vmresume is needed */
2361                 "cmpl $0, %c[launched](%0) \n\t"
2362                 /* Load guest registers.  Don't clobber flags. */
2363 #ifdef CONFIG_X86_64
2364                 "mov %c[cr2](%0), %%rax \n\t"
2365                 "mov %%rax, %%cr2 \n\t"
2366                 "mov %c[rax](%0), %%rax \n\t"
2367                 "mov %c[rbx](%0), %%rbx \n\t"
2368                 "mov %c[rdx](%0), %%rdx \n\t"
2369                 "mov %c[rsi](%0), %%rsi \n\t"
2370                 "mov %c[rdi](%0), %%rdi \n\t"
2371                 "mov %c[rbp](%0), %%rbp \n\t"
2372                 "mov %c[r8](%0),  %%r8  \n\t"
2373                 "mov %c[r9](%0),  %%r9  \n\t"
2374                 "mov %c[r10](%0), %%r10 \n\t"
2375                 "mov %c[r11](%0), %%r11 \n\t"
2376                 "mov %c[r12](%0), %%r12 \n\t"
2377                 "mov %c[r13](%0), %%r13 \n\t"
2378                 "mov %c[r14](%0), %%r14 \n\t"
2379                 "mov %c[r15](%0), %%r15 \n\t"
2380                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2381 #else
2382                 "mov %c[cr2](%0), %%eax \n\t"
2383                 "mov %%eax,   %%cr2 \n\t"
2384                 "mov %c[rax](%0), %%eax \n\t"
2385                 "mov %c[rbx](%0), %%ebx \n\t"
2386                 "mov %c[rdx](%0), %%edx \n\t"
2387                 "mov %c[rsi](%0), %%esi \n\t"
2388                 "mov %c[rdi](%0), %%edi \n\t"
2389                 "mov %c[rbp](%0), %%ebp \n\t"
2390                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2391 #endif
2392                 /* Enter guest mode */
2393                 "jne .Llaunched \n\t"
2394                 ASM_VMX_VMLAUNCH "\n\t"
2395                 "jmp .Lkvm_vmx_return \n\t"
2396                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2397                 ".Lkvm_vmx_return: "
2398                 /* Save guest registers, load host registers, keep flags */
2399 #ifdef CONFIG_X86_64
2400                 "xchg %0,     (%%rsp) \n\t"
2401                 "mov %%rax, %c[rax](%0) \n\t"
2402                 "mov %%rbx, %c[rbx](%0) \n\t"
2403                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2404                 "mov %%rdx, %c[rdx](%0) \n\t"
2405                 "mov %%rsi, %c[rsi](%0) \n\t"
2406                 "mov %%rdi, %c[rdi](%0) \n\t"
2407                 "mov %%rbp, %c[rbp](%0) \n\t"
2408                 "mov %%r8,  %c[r8](%0) \n\t"
2409                 "mov %%r9,  %c[r9](%0) \n\t"
2410                 "mov %%r10, %c[r10](%0) \n\t"
2411                 "mov %%r11, %c[r11](%0) \n\t"
2412                 "mov %%r12, %c[r12](%0) \n\t"
2413                 "mov %%r13, %c[r13](%0) \n\t"
2414                 "mov %%r14, %c[r14](%0) \n\t"
2415                 "mov %%r15, %c[r15](%0) \n\t"
2416                 "mov %%cr2, %%rax   \n\t"
2417                 "mov %%rax, %c[cr2](%0) \n\t"
2418
2419                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2420 #else
2421                 "xchg %0, (%%esp) \n\t"
2422                 "mov %%eax, %c[rax](%0) \n\t"
2423                 "mov %%ebx, %c[rbx](%0) \n\t"
2424                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2425                 "mov %%edx, %c[rdx](%0) \n\t"
2426                 "mov %%esi, %c[rsi](%0) \n\t"
2427                 "mov %%edi, %c[rdi](%0) \n\t"
2428                 "mov %%ebp, %c[rbp](%0) \n\t"
2429                 "mov %%cr2, %%eax  \n\t"
2430                 "mov %%eax, %c[cr2](%0) \n\t"
2431
2432                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2433 #endif
2434                 "setbe %c[fail](%0) \n\t"
2435               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2436                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2437                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2438                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2439                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2440                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2441                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2442                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2443                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2444                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
2445 #ifdef CONFIG_X86_64
2446                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2447                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2448                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2449                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2450                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2451                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2452                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2453                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
2454 #endif
2455                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
2456               : "cc", "memory"
2457 #ifdef CONFIG_X86_64
2458                 , "rbx", "rdi", "rsi"
2459                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2460 #else
2461                 , "ebx", "edi", "rsi"
2462 #endif
2463               );
2464
2465         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2466         if (vmx->rmode.irq.pending)
2467                 fixup_rmode_irq(vmx);
2468
2469         vcpu->arch.interrupt_window_open =
2470                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2471
2472         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2473         vmx->launched = 1;
2474
2475         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2476
2477         /* We need to handle NMIs before interrupts are enabled */
2478         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2479                 asm("int $2");
2480 }
2481
2482 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2483 {
2484         struct vcpu_vmx *vmx = to_vmx(vcpu);
2485
2486         if (vmx->vmcs) {
2487                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2488                 free_vmcs(vmx->vmcs);
2489                 vmx->vmcs = NULL;
2490         }
2491 }
2492
2493 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2494 {
2495         struct vcpu_vmx *vmx = to_vmx(vcpu);
2496
2497         vmx_free_vmcs(vcpu);
2498         kfree(vmx->host_msrs);
2499         kfree(vmx->guest_msrs);
2500         kvm_vcpu_uninit(vcpu);
2501         kmem_cache_free(kvm_vcpu_cache, vmx);
2502 }
2503
2504 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2505 {
2506         int err;
2507         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2508         int cpu;
2509
2510         if (!vmx)
2511                 return ERR_PTR(-ENOMEM);
2512
2513         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2514         if (err)
2515                 goto free_vcpu;
2516
2517         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2518         if (!vmx->guest_msrs) {
2519                 err = -ENOMEM;
2520                 goto uninit_vcpu;
2521         }
2522
2523         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2524         if (!vmx->host_msrs)
2525                 goto free_guest_msrs;
2526
2527         vmx->vmcs = alloc_vmcs();
2528         if (!vmx->vmcs)
2529                 goto free_msrs;
2530
2531         vmcs_clear(vmx->vmcs);
2532
2533         cpu = get_cpu();
2534         vmx_vcpu_load(&vmx->vcpu, cpu);
2535         err = vmx_vcpu_setup(vmx);
2536         vmx_vcpu_put(&vmx->vcpu);
2537         put_cpu();
2538         if (err)
2539                 goto free_vmcs;
2540
2541         return &vmx->vcpu;
2542
2543 free_vmcs:
2544         free_vmcs(vmx->vmcs);
2545 free_msrs:
2546         kfree(vmx->host_msrs);
2547 free_guest_msrs:
2548         kfree(vmx->guest_msrs);
2549 uninit_vcpu:
2550         kvm_vcpu_uninit(&vmx->vcpu);
2551 free_vcpu:
2552         kmem_cache_free(kvm_vcpu_cache, vmx);
2553         return ERR_PTR(err);
2554 }
2555
2556 static void __init vmx_check_processor_compat(void *rtn)
2557 {
2558         struct vmcs_config vmcs_conf;
2559
2560         *(int *)rtn = 0;
2561         if (setup_vmcs_config(&vmcs_conf) < 0)
2562                 *(int *)rtn = -EIO;
2563         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2564                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2565                                 smp_processor_id());
2566                 *(int *)rtn = -EIO;
2567         }
2568 }
2569
2570 static struct kvm_x86_ops vmx_x86_ops = {
2571         .cpu_has_kvm_support = cpu_has_kvm_support,
2572         .disabled_by_bios = vmx_disabled_by_bios,
2573         .hardware_setup = hardware_setup,
2574         .hardware_unsetup = hardware_unsetup,
2575         .check_processor_compatibility = vmx_check_processor_compat,
2576         .hardware_enable = hardware_enable,
2577         .hardware_disable = hardware_disable,
2578         .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
2579
2580         .vcpu_create = vmx_create_vcpu,
2581         .vcpu_free = vmx_free_vcpu,
2582         .vcpu_reset = vmx_vcpu_reset,
2583
2584         .prepare_guest_switch = vmx_save_host_state,
2585         .vcpu_load = vmx_vcpu_load,
2586         .vcpu_put = vmx_vcpu_put,
2587         .vcpu_decache = vmx_vcpu_decache,
2588
2589         .set_guest_debug = set_guest_debug,
2590         .guest_debug_pre = kvm_guest_debug_pre,
2591         .get_msr = vmx_get_msr,
2592         .set_msr = vmx_set_msr,
2593         .get_segment_base = vmx_get_segment_base,
2594         .get_segment = vmx_get_segment,
2595         .set_segment = vmx_set_segment,
2596         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2597         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2598         .set_cr0 = vmx_set_cr0,
2599         .set_cr3 = vmx_set_cr3,
2600         .set_cr4 = vmx_set_cr4,
2601 #ifdef CONFIG_X86_64
2602         .set_efer = vmx_set_efer,
2603 #endif
2604         .get_idt = vmx_get_idt,
2605         .set_idt = vmx_set_idt,
2606         .get_gdt = vmx_get_gdt,
2607         .set_gdt = vmx_set_gdt,
2608         .cache_regs = vcpu_load_rsp_rip,
2609         .decache_regs = vcpu_put_rsp_rip,
2610         .get_rflags = vmx_get_rflags,
2611         .set_rflags = vmx_set_rflags,
2612
2613         .tlb_flush = vmx_flush_tlb,
2614
2615         .run = vmx_vcpu_run,
2616         .handle_exit = kvm_handle_exit,
2617         .skip_emulated_instruction = skip_emulated_instruction,
2618         .patch_hypercall = vmx_patch_hypercall,
2619         .get_irq = vmx_get_irq,
2620         .set_irq = vmx_inject_irq,
2621         .queue_exception = vmx_queue_exception,
2622         .exception_injected = vmx_exception_injected,
2623         .inject_pending_irq = vmx_intr_assist,
2624         .inject_pending_vectors = do_interrupt_requests,
2625
2626         .set_tss_addr = vmx_set_tss_addr,
2627 };
2628
2629 static int __init vmx_init(void)
2630 {
2631         void *iova;
2632         int r;
2633
2634         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2635         if (!vmx_io_bitmap_a)
2636                 return -ENOMEM;
2637
2638         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2639         if (!vmx_io_bitmap_b) {
2640                 r = -ENOMEM;
2641                 goto out;
2642         }
2643
2644         /*
2645          * Allow direct access to the PC debug port (it is often used for I/O
2646          * delays, but the vmexits simply slow things down).
2647          */
2648         iova = kmap(vmx_io_bitmap_a);
2649         memset(iova, 0xff, PAGE_SIZE);
2650         clear_bit(0x80, iova);
2651         kunmap(vmx_io_bitmap_a);
2652
2653         iova = kmap(vmx_io_bitmap_b);
2654         memset(iova, 0xff, PAGE_SIZE);
2655         kunmap(vmx_io_bitmap_b);
2656
2657         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2658         if (r)
2659                 goto out1;
2660
2661         if (bypass_guest_pf)
2662                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2663
2664         return 0;
2665
2666 out1:
2667         __free_page(vmx_io_bitmap_b);
2668 out:
2669         __free_page(vmx_io_bitmap_a);
2670         return r;
2671 }
2672
2673 static void __exit vmx_exit(void)
2674 {
2675         __free_page(vmx_io_bitmap_b);
2676         __free_page(vmx_io_bitmap_a);
2677
2678         kvm_exit();
2679 }
2680
2681 module_init(vmx_init)
2682 module_exit(vmx_exit)