KVM: SVM: check for progress after IRET interception
[linux-2.6.git] / arch / x86 / kvm / svm.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * AMD SVM support
5  *
6  * Copyright (C) 2006 Qumranet, Inc.
7  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8  *
9  * Authors:
10  *   Yaniv Kamay  <yaniv@qumranet.com>
11  *   Avi Kivity   <avi@qumranet.com>
12  *
13  * This work is licensed under the terms of the GNU GPL, version 2.  See
14  * the COPYING file in the top-level directory.
15  *
16  */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT            (1 <<  0)
51 #define SVM_FEATURE_LBRV           (1 <<  1)
52 #define SVM_FEATURE_SVML           (1 <<  2)
53 #define SVM_FEATURE_NRIP           (1 <<  3)
54 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
55 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
56 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
57 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
58 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
59
60 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
61 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
62 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
63
64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
65
66 static bool erratum_383_found __read_mostly;
67
68 static const u32 host_save_user_msrs[] = {
69 #ifdef CONFIG_X86_64
70         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
71         MSR_FS_BASE,
72 #endif
73         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
74 };
75
76 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
77
78 struct kvm_vcpu;
79
80 struct nested_state {
81         struct vmcb *hsave;
82         u64 hsave_msr;
83         u64 vm_cr_msr;
84         u64 vmcb;
85
86         /* These are the merged vectors */
87         u32 *msrpm;
88
89         /* gpa pointers to the real vectors */
90         u64 vmcb_msrpm;
91         u64 vmcb_iopm;
92
93         /* A VMEXIT is required but not yet emulated */
94         bool exit_required;
95
96         /*
97          * If we vmexit during an instruction emulation we need this to restore
98          * the l1 guest rip after the emulation
99          */
100         unsigned long vmexit_rip;
101         unsigned long vmexit_rsp;
102         unsigned long vmexit_rax;
103
104         /* cache for intercepts of the guest */
105         u32 intercept_cr;
106         u32 intercept_dr;
107         u32 intercept_exceptions;
108         u64 intercept;
109
110         /* Nested Paging related state */
111         u64 nested_cr3;
112 };
113
114 #define MSRPM_OFFSETS   16
115 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
116
117 struct vcpu_svm {
118         struct kvm_vcpu vcpu;
119         struct vmcb *vmcb;
120         unsigned long vmcb_pa;
121         struct svm_cpu_data *svm_data;
122         uint64_t asid_generation;
123         uint64_t sysenter_esp;
124         uint64_t sysenter_eip;
125
126         u64 next_rip;
127
128         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
129         struct {
130                 u16 fs;
131                 u16 gs;
132                 u16 ldt;
133                 u64 gs_base;
134         } host;
135
136         u32 *msrpm;
137
138         ulong nmi_iret_rip;
139
140         struct nested_state nested;
141
142         bool nmi_singlestep;
143
144         unsigned int3_injected;
145         unsigned long int3_rip;
146         u32 apf_reason;
147 };
148
149 #define MSR_INVALID                     0xffffffffU
150
151 static struct svm_direct_access_msrs {
152         u32 index;   /* Index of the MSR */
153         bool always; /* True if intercept is always on */
154 } direct_access_msrs[] = {
155         { .index = MSR_STAR,                            .always = true  },
156         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
157 #ifdef CONFIG_X86_64
158         { .index = MSR_GS_BASE,                         .always = true  },
159         { .index = MSR_FS_BASE,                         .always = true  },
160         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
161         { .index = MSR_LSTAR,                           .always = true  },
162         { .index = MSR_CSTAR,                           .always = true  },
163         { .index = MSR_SYSCALL_MASK,                    .always = true  },
164 #endif
165         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
166         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
167         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
168         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
169         { .index = MSR_INVALID,                         .always = false },
170 };
171
172 /* enable NPT for AMD64 and X86 with PAE */
173 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
174 static bool npt_enabled = true;
175 #else
176 static bool npt_enabled;
177 #endif
178 static int npt = 1;
179
180 module_param(npt, int, S_IRUGO);
181
182 static int nested = 1;
183 module_param(nested, int, S_IRUGO);
184
185 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
186 static void svm_complete_interrupts(struct vcpu_svm *svm);
187
188 static int nested_svm_exit_handled(struct vcpu_svm *svm);
189 static int nested_svm_intercept(struct vcpu_svm *svm);
190 static int nested_svm_vmexit(struct vcpu_svm *svm);
191 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
192                                       bool has_error_code, u32 error_code);
193
194 enum {
195         VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
196                             pause filter count */
197         VMCB_PERM_MAP,   /* IOPM Base and MSRPM Base */
198         VMCB_ASID,       /* ASID */
199         VMCB_INTR,       /* int_ctl, int_vector */
200         VMCB_NPT,        /* npt_en, nCR3, gPAT */
201         VMCB_CR,         /* CR0, CR3, CR4, EFER */
202         VMCB_DR,         /* DR6, DR7 */
203         VMCB_DT,         /* GDT, IDT */
204         VMCB_SEG,        /* CS, DS, SS, ES, CPL */
205         VMCB_CR2,        /* CR2 only */
206         VMCB_LBR,        /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
207         VMCB_DIRTY_MAX,
208 };
209
210 /* TPR and CR2 are always written before VMRUN */
211 #define VMCB_ALWAYS_DIRTY_MASK  ((1U << VMCB_INTR) | (1U << VMCB_CR2))
212
213 static inline void mark_all_dirty(struct vmcb *vmcb)
214 {
215         vmcb->control.clean = 0;
216 }
217
218 static inline void mark_all_clean(struct vmcb *vmcb)
219 {
220         vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
221                                & ~VMCB_ALWAYS_DIRTY_MASK;
222 }
223
224 static inline void mark_dirty(struct vmcb *vmcb, int bit)
225 {
226         vmcb->control.clean &= ~(1 << bit);
227 }
228
229 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
230 {
231         return container_of(vcpu, struct vcpu_svm, vcpu);
232 }
233
234 static void recalc_intercepts(struct vcpu_svm *svm)
235 {
236         struct vmcb_control_area *c, *h;
237         struct nested_state *g;
238
239         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
240
241         if (!is_guest_mode(&svm->vcpu))
242                 return;
243
244         c = &svm->vmcb->control;
245         h = &svm->nested.hsave->control;
246         g = &svm->nested;
247
248         c->intercept_cr = h->intercept_cr | g->intercept_cr;
249         c->intercept_dr = h->intercept_dr | g->intercept_dr;
250         c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
251         c->intercept = h->intercept | g->intercept;
252 }
253
254 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
255 {
256         if (is_guest_mode(&svm->vcpu))
257                 return svm->nested.hsave;
258         else
259                 return svm->vmcb;
260 }
261
262 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
263 {
264         struct vmcb *vmcb = get_host_vmcb(svm);
265
266         vmcb->control.intercept_cr |= (1U << bit);
267
268         recalc_intercepts(svm);
269 }
270
271 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
272 {
273         struct vmcb *vmcb = get_host_vmcb(svm);
274
275         vmcb->control.intercept_cr &= ~(1U << bit);
276
277         recalc_intercepts(svm);
278 }
279
280 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
281 {
282         struct vmcb *vmcb = get_host_vmcb(svm);
283
284         return vmcb->control.intercept_cr & (1U << bit);
285 }
286
287 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
288 {
289         struct vmcb *vmcb = get_host_vmcb(svm);
290
291         vmcb->control.intercept_dr |= (1U << bit);
292
293         recalc_intercepts(svm);
294 }
295
296 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
297 {
298         struct vmcb *vmcb = get_host_vmcb(svm);
299
300         vmcb->control.intercept_dr &= ~(1U << bit);
301
302         recalc_intercepts(svm);
303 }
304
305 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
306 {
307         struct vmcb *vmcb = get_host_vmcb(svm);
308
309         vmcb->control.intercept_exceptions |= (1U << bit);
310
311         recalc_intercepts(svm);
312 }
313
314 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
315 {
316         struct vmcb *vmcb = get_host_vmcb(svm);
317
318         vmcb->control.intercept_exceptions &= ~(1U << bit);
319
320         recalc_intercepts(svm);
321 }
322
323 static inline void set_intercept(struct vcpu_svm *svm, int bit)
324 {
325         struct vmcb *vmcb = get_host_vmcb(svm);
326
327         vmcb->control.intercept |= (1ULL << bit);
328
329         recalc_intercepts(svm);
330 }
331
332 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
333 {
334         struct vmcb *vmcb = get_host_vmcb(svm);
335
336         vmcb->control.intercept &= ~(1ULL << bit);
337
338         recalc_intercepts(svm);
339 }
340
341 static inline void enable_gif(struct vcpu_svm *svm)
342 {
343         svm->vcpu.arch.hflags |= HF_GIF_MASK;
344 }
345
346 static inline void disable_gif(struct vcpu_svm *svm)
347 {
348         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
349 }
350
351 static inline bool gif_set(struct vcpu_svm *svm)
352 {
353         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
354 }
355
356 static unsigned long iopm_base;
357
358 struct kvm_ldttss_desc {
359         u16 limit0;
360         u16 base0;
361         unsigned base1:8, type:5, dpl:2, p:1;
362         unsigned limit1:4, zero0:3, g:1, base2:8;
363         u32 base3;
364         u32 zero1;
365 } __attribute__((packed));
366
367 struct svm_cpu_data {
368         int cpu;
369
370         u64 asid_generation;
371         u32 max_asid;
372         u32 next_asid;
373         struct kvm_ldttss_desc *tss_desc;
374
375         struct page *save_area;
376 };
377
378 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
379 static uint32_t svm_features;
380
381 struct svm_init_data {
382         int cpu;
383         int r;
384 };
385
386 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
387
388 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
389 #define MSRS_RANGE_SIZE 2048
390 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
391
392 static u32 svm_msrpm_offset(u32 msr)
393 {
394         u32 offset;
395         int i;
396
397         for (i = 0; i < NUM_MSR_MAPS; i++) {
398                 if (msr < msrpm_ranges[i] ||
399                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
400                         continue;
401
402                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
403                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
404
405                 /* Now we have the u8 offset - but need the u32 offset */
406                 return offset / 4;
407         }
408
409         /* MSR not in any range */
410         return MSR_INVALID;
411 }
412
413 #define MAX_INST_SIZE 15
414
415 static inline void clgi(void)
416 {
417         asm volatile (__ex(SVM_CLGI));
418 }
419
420 static inline void stgi(void)
421 {
422         asm volatile (__ex(SVM_STGI));
423 }
424
425 static inline void invlpga(unsigned long addr, u32 asid)
426 {
427         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
428 }
429
430 static int get_npt_level(void)
431 {
432 #ifdef CONFIG_X86_64
433         return PT64_ROOT_LEVEL;
434 #else
435         return PT32E_ROOT_LEVEL;
436 #endif
437 }
438
439 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
440 {
441         vcpu->arch.efer = efer;
442         if (!npt_enabled && !(efer & EFER_LMA))
443                 efer &= ~EFER_LME;
444
445         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
446         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
447 }
448
449 static int is_external_interrupt(u32 info)
450 {
451         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
452         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
453 }
454
455 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
456 {
457         struct vcpu_svm *svm = to_svm(vcpu);
458         u32 ret = 0;
459
460         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
461                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
462         return ret & mask;
463 }
464
465 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
466 {
467         struct vcpu_svm *svm = to_svm(vcpu);
468
469         if (mask == 0)
470                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
471         else
472                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
473
474 }
475
476 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
477 {
478         struct vcpu_svm *svm = to_svm(vcpu);
479
480         if (svm->vmcb->control.next_rip != 0)
481                 svm->next_rip = svm->vmcb->control.next_rip;
482
483         if (!svm->next_rip) {
484                 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
485                                 EMULATE_DONE)
486                         printk(KERN_DEBUG "%s: NOP\n", __func__);
487                 return;
488         }
489         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
490                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
491                        __func__, kvm_rip_read(vcpu), svm->next_rip);
492
493         kvm_rip_write(vcpu, svm->next_rip);
494         svm_set_interrupt_shadow(vcpu, 0);
495 }
496
497 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
498                                 bool has_error_code, u32 error_code,
499                                 bool reinject)
500 {
501         struct vcpu_svm *svm = to_svm(vcpu);
502
503         /*
504          * If we are within a nested VM we'd better #VMEXIT and let the guest
505          * handle the exception
506          */
507         if (!reinject &&
508             nested_svm_check_exception(svm, nr, has_error_code, error_code))
509                 return;
510
511         if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
512                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
513
514                 /*
515                  * For guest debugging where we have to reinject #BP if some
516                  * INT3 is guest-owned:
517                  * Emulate nRIP by moving RIP forward. Will fail if injection
518                  * raises a fault that is not intercepted. Still better than
519                  * failing in all cases.
520                  */
521                 skip_emulated_instruction(&svm->vcpu);
522                 rip = kvm_rip_read(&svm->vcpu);
523                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
524                 svm->int3_injected = rip - old_rip;
525         }
526
527         svm->vmcb->control.event_inj = nr
528                 | SVM_EVTINJ_VALID
529                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
530                 | SVM_EVTINJ_TYPE_EXEPT;
531         svm->vmcb->control.event_inj_err = error_code;
532 }
533
534 static void svm_init_erratum_383(void)
535 {
536         u32 low, high;
537         int err;
538         u64 val;
539
540         if (!cpu_has_amd_erratum(amd_erratum_383))
541                 return;
542
543         /* Use _safe variants to not break nested virtualization */
544         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
545         if (err)
546                 return;
547
548         val |= (1ULL << 47);
549
550         low  = lower_32_bits(val);
551         high = upper_32_bits(val);
552
553         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
554
555         erratum_383_found = true;
556 }
557
558 static int has_svm(void)
559 {
560         const char *msg;
561
562         if (!cpu_has_svm(&msg)) {
563                 printk(KERN_INFO "has_svm: %s\n", msg);
564                 return 0;
565         }
566
567         return 1;
568 }
569
570 static void svm_hardware_disable(void *garbage)
571 {
572         cpu_svm_disable();
573 }
574
575 static int svm_hardware_enable(void *garbage)
576 {
577
578         struct svm_cpu_data *sd;
579         uint64_t efer;
580         struct desc_ptr gdt_descr;
581         struct desc_struct *gdt;
582         int me = raw_smp_processor_id();
583
584         rdmsrl(MSR_EFER, efer);
585         if (efer & EFER_SVME)
586                 return -EBUSY;
587
588         if (!has_svm()) {
589                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
590                        me);
591                 return -EINVAL;
592         }
593         sd = per_cpu(svm_data, me);
594
595         if (!sd) {
596                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
597                        me);
598                 return -EINVAL;
599         }
600
601         sd->asid_generation = 1;
602         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
603         sd->next_asid = sd->max_asid + 1;
604
605         native_store_gdt(&gdt_descr);
606         gdt = (struct desc_struct *)gdt_descr.address;
607         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
608
609         wrmsrl(MSR_EFER, efer | EFER_SVME);
610
611         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
612
613         svm_init_erratum_383();
614
615         return 0;
616 }
617
618 static void svm_cpu_uninit(int cpu)
619 {
620         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
621
622         if (!sd)
623                 return;
624
625         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
626         __free_page(sd->save_area);
627         kfree(sd);
628 }
629
630 static int svm_cpu_init(int cpu)
631 {
632         struct svm_cpu_data *sd;
633         int r;
634
635         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
636         if (!sd)
637                 return -ENOMEM;
638         sd->cpu = cpu;
639         sd->save_area = alloc_page(GFP_KERNEL);
640         r = -ENOMEM;
641         if (!sd->save_area)
642                 goto err_1;
643
644         per_cpu(svm_data, cpu) = sd;
645
646         return 0;
647
648 err_1:
649         kfree(sd);
650         return r;
651
652 }
653
654 static bool valid_msr_intercept(u32 index)
655 {
656         int i;
657
658         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
659                 if (direct_access_msrs[i].index == index)
660                         return true;
661
662         return false;
663 }
664
665 static void set_msr_interception(u32 *msrpm, unsigned msr,
666                                  int read, int write)
667 {
668         u8 bit_read, bit_write;
669         unsigned long tmp;
670         u32 offset;
671
672         /*
673          * If this warning triggers extend the direct_access_msrs list at the
674          * beginning of the file
675          */
676         WARN_ON(!valid_msr_intercept(msr));
677
678         offset    = svm_msrpm_offset(msr);
679         bit_read  = 2 * (msr & 0x0f);
680         bit_write = 2 * (msr & 0x0f) + 1;
681         tmp       = msrpm[offset];
682
683         BUG_ON(offset == MSR_INVALID);
684
685         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
686         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
687
688         msrpm[offset] = tmp;
689 }
690
691 static void svm_vcpu_init_msrpm(u32 *msrpm)
692 {
693         int i;
694
695         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
696
697         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
698                 if (!direct_access_msrs[i].always)
699                         continue;
700
701                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
702         }
703 }
704
705 static void add_msr_offset(u32 offset)
706 {
707         int i;
708
709         for (i = 0; i < MSRPM_OFFSETS; ++i) {
710
711                 /* Offset already in list? */
712                 if (msrpm_offsets[i] == offset)
713                         return;
714
715                 /* Slot used by another offset? */
716                 if (msrpm_offsets[i] != MSR_INVALID)
717                         continue;
718
719                 /* Add offset to list */
720                 msrpm_offsets[i] = offset;
721
722                 return;
723         }
724
725         /*
726          * If this BUG triggers the msrpm_offsets table has an overflow. Just
727          * increase MSRPM_OFFSETS in this case.
728          */
729         BUG();
730 }
731
732 static void init_msrpm_offsets(void)
733 {
734         int i;
735
736         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
737
738         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
739                 u32 offset;
740
741                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
742                 BUG_ON(offset == MSR_INVALID);
743
744                 add_msr_offset(offset);
745         }
746 }
747
748 static void svm_enable_lbrv(struct vcpu_svm *svm)
749 {
750         u32 *msrpm = svm->msrpm;
751
752         svm->vmcb->control.lbr_ctl = 1;
753         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
754         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
755         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
756         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
757 }
758
759 static void svm_disable_lbrv(struct vcpu_svm *svm)
760 {
761         u32 *msrpm = svm->msrpm;
762
763         svm->vmcb->control.lbr_ctl = 0;
764         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
765         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
766         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
767         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
768 }
769
770 static __init int svm_hardware_setup(void)
771 {
772         int cpu;
773         struct page *iopm_pages;
774         void *iopm_va;
775         int r;
776
777         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
778
779         if (!iopm_pages)
780                 return -ENOMEM;
781
782         iopm_va = page_address(iopm_pages);
783         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
784         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
785
786         init_msrpm_offsets();
787
788         if (boot_cpu_has(X86_FEATURE_NX))
789                 kvm_enable_efer_bits(EFER_NX);
790
791         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
792                 kvm_enable_efer_bits(EFER_FFXSR);
793
794         if (nested) {
795                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
796                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
797         }
798
799         for_each_possible_cpu(cpu) {
800                 r = svm_cpu_init(cpu);
801                 if (r)
802                         goto err;
803         }
804
805         svm_features = cpuid_edx(SVM_CPUID_FUNC);
806
807         if (!boot_cpu_has(X86_FEATURE_NPT))
808                 npt_enabled = false;
809
810         if (npt_enabled && !npt) {
811                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
812                 npt_enabled = false;
813         }
814
815         if (npt_enabled) {
816                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
817                 kvm_enable_tdp();
818         } else
819                 kvm_disable_tdp();
820
821         return 0;
822
823 err:
824         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
825         iopm_base = 0;
826         return r;
827 }
828
829 static __exit void svm_hardware_unsetup(void)
830 {
831         int cpu;
832
833         for_each_possible_cpu(cpu)
834                 svm_cpu_uninit(cpu);
835
836         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
837         iopm_base = 0;
838 }
839
840 static void init_seg(struct vmcb_seg *seg)
841 {
842         seg->selector = 0;
843         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
844                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
845         seg->limit = 0xffff;
846         seg->base = 0;
847 }
848
849 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
850 {
851         seg->selector = 0;
852         seg->attrib = SVM_SELECTOR_P_MASK | type;
853         seg->limit = 0xffff;
854         seg->base = 0;
855 }
856
857 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
858 {
859         struct vcpu_svm *svm = to_svm(vcpu);
860         u64 g_tsc_offset = 0;
861
862         if (is_guest_mode(vcpu)) {
863                 g_tsc_offset = svm->vmcb->control.tsc_offset -
864                                svm->nested.hsave->control.tsc_offset;
865                 svm->nested.hsave->control.tsc_offset = offset;
866         }
867
868         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
869
870         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
871 }
872
873 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
874 {
875         struct vcpu_svm *svm = to_svm(vcpu);
876
877         svm->vmcb->control.tsc_offset += adjustment;
878         if (is_guest_mode(vcpu))
879                 svm->nested.hsave->control.tsc_offset += adjustment;
880         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
881 }
882
883 static void init_vmcb(struct vcpu_svm *svm)
884 {
885         struct vmcb_control_area *control = &svm->vmcb->control;
886         struct vmcb_save_area *save = &svm->vmcb->save;
887
888         svm->vcpu.fpu_active = 1;
889         svm->vcpu.arch.hflags = 0;
890
891         set_cr_intercept(svm, INTERCEPT_CR0_READ);
892         set_cr_intercept(svm, INTERCEPT_CR3_READ);
893         set_cr_intercept(svm, INTERCEPT_CR4_READ);
894         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
895         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
896         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
897         set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
898
899         set_dr_intercept(svm, INTERCEPT_DR0_READ);
900         set_dr_intercept(svm, INTERCEPT_DR1_READ);
901         set_dr_intercept(svm, INTERCEPT_DR2_READ);
902         set_dr_intercept(svm, INTERCEPT_DR3_READ);
903         set_dr_intercept(svm, INTERCEPT_DR4_READ);
904         set_dr_intercept(svm, INTERCEPT_DR5_READ);
905         set_dr_intercept(svm, INTERCEPT_DR6_READ);
906         set_dr_intercept(svm, INTERCEPT_DR7_READ);
907
908         set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
909         set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
910         set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
911         set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
912         set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
913         set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
914         set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
915         set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
916
917         set_exception_intercept(svm, PF_VECTOR);
918         set_exception_intercept(svm, UD_VECTOR);
919         set_exception_intercept(svm, MC_VECTOR);
920
921         set_intercept(svm, INTERCEPT_INTR);
922         set_intercept(svm, INTERCEPT_NMI);
923         set_intercept(svm, INTERCEPT_SMI);
924         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
925         set_intercept(svm, INTERCEPT_CPUID);
926         set_intercept(svm, INTERCEPT_INVD);
927         set_intercept(svm, INTERCEPT_HLT);
928         set_intercept(svm, INTERCEPT_INVLPG);
929         set_intercept(svm, INTERCEPT_INVLPGA);
930         set_intercept(svm, INTERCEPT_IOIO_PROT);
931         set_intercept(svm, INTERCEPT_MSR_PROT);
932         set_intercept(svm, INTERCEPT_TASK_SWITCH);
933         set_intercept(svm, INTERCEPT_SHUTDOWN);
934         set_intercept(svm, INTERCEPT_VMRUN);
935         set_intercept(svm, INTERCEPT_VMMCALL);
936         set_intercept(svm, INTERCEPT_VMLOAD);
937         set_intercept(svm, INTERCEPT_VMSAVE);
938         set_intercept(svm, INTERCEPT_STGI);
939         set_intercept(svm, INTERCEPT_CLGI);
940         set_intercept(svm, INTERCEPT_SKINIT);
941         set_intercept(svm, INTERCEPT_WBINVD);
942         set_intercept(svm, INTERCEPT_MONITOR);
943         set_intercept(svm, INTERCEPT_MWAIT);
944         set_intercept(svm, INTERCEPT_XSETBV);
945
946         control->iopm_base_pa = iopm_base;
947         control->msrpm_base_pa = __pa(svm->msrpm);
948         control->int_ctl = V_INTR_MASKING_MASK;
949
950         init_seg(&save->es);
951         init_seg(&save->ss);
952         init_seg(&save->ds);
953         init_seg(&save->fs);
954         init_seg(&save->gs);
955
956         save->cs.selector = 0xf000;
957         /* Executable/Readable Code Segment */
958         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
959                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
960         save->cs.limit = 0xffff;
961         /*
962          * cs.base should really be 0xffff0000, but vmx can't handle that, so
963          * be consistent with it.
964          *
965          * Replace when we have real mode working for vmx.
966          */
967         save->cs.base = 0xf0000;
968
969         save->gdtr.limit = 0xffff;
970         save->idtr.limit = 0xffff;
971
972         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
973         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
974
975         svm_set_efer(&svm->vcpu, 0);
976         save->dr6 = 0xffff0ff0;
977         save->dr7 = 0x400;
978         save->rflags = 2;
979         save->rip = 0x0000fff0;
980         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
981
982         /*
983          * This is the guest-visible cr0 value.
984          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
985          */
986         svm->vcpu.arch.cr0 = 0;
987         (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
988
989         save->cr4 = X86_CR4_PAE;
990         /* rdx = ?? */
991
992         if (npt_enabled) {
993                 /* Setup VMCB for Nested Paging */
994                 control->nested_ctl = 1;
995                 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
996                 clr_intercept(svm, INTERCEPT_INVLPG);
997                 clr_exception_intercept(svm, PF_VECTOR);
998                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
999                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1000                 save->g_pat = 0x0007040600070406ULL;
1001                 save->cr3 = 0;
1002                 save->cr4 = 0;
1003         }
1004         svm->asid_generation = 0;
1005
1006         svm->nested.vmcb = 0;
1007         svm->vcpu.arch.hflags = 0;
1008
1009         if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1010                 control->pause_filter_count = 3000;
1011                 set_intercept(svm, INTERCEPT_PAUSE);
1012         }
1013
1014         mark_all_dirty(svm->vmcb);
1015
1016         enable_gif(svm);
1017 }
1018
1019 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1020 {
1021         struct vcpu_svm *svm = to_svm(vcpu);
1022
1023         init_vmcb(svm);
1024
1025         if (!kvm_vcpu_is_bsp(vcpu)) {
1026                 kvm_rip_write(vcpu, 0);
1027                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1028                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1029         }
1030         vcpu->arch.regs_avail = ~0;
1031         vcpu->arch.regs_dirty = ~0;
1032
1033         return 0;
1034 }
1035
1036 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1037 {
1038         struct vcpu_svm *svm;
1039         struct page *page;
1040         struct page *msrpm_pages;
1041         struct page *hsave_page;
1042         struct page *nested_msrpm_pages;
1043         int err;
1044
1045         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1046         if (!svm) {
1047                 err = -ENOMEM;
1048                 goto out;
1049         }
1050
1051         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1052         if (err)
1053                 goto free_svm;
1054
1055         err = -ENOMEM;
1056         page = alloc_page(GFP_KERNEL);
1057         if (!page)
1058                 goto uninit;
1059
1060         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1061         if (!msrpm_pages)
1062                 goto free_page1;
1063
1064         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1065         if (!nested_msrpm_pages)
1066                 goto free_page2;
1067
1068         hsave_page = alloc_page(GFP_KERNEL);
1069         if (!hsave_page)
1070                 goto free_page3;
1071
1072         svm->nested.hsave = page_address(hsave_page);
1073
1074         svm->msrpm = page_address(msrpm_pages);
1075         svm_vcpu_init_msrpm(svm->msrpm);
1076
1077         svm->nested.msrpm = page_address(nested_msrpm_pages);
1078         svm_vcpu_init_msrpm(svm->nested.msrpm);
1079
1080         svm->vmcb = page_address(page);
1081         clear_page(svm->vmcb);
1082         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1083         svm->asid_generation = 0;
1084         init_vmcb(svm);
1085         kvm_write_tsc(&svm->vcpu, 0);
1086
1087         err = fx_init(&svm->vcpu);
1088         if (err)
1089                 goto free_page4;
1090
1091         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1092         if (kvm_vcpu_is_bsp(&svm->vcpu))
1093                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1094
1095         return &svm->vcpu;
1096
1097 free_page4:
1098         __free_page(hsave_page);
1099 free_page3:
1100         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1101 free_page2:
1102         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1103 free_page1:
1104         __free_page(page);
1105 uninit:
1106         kvm_vcpu_uninit(&svm->vcpu);
1107 free_svm:
1108         kmem_cache_free(kvm_vcpu_cache, svm);
1109 out:
1110         return ERR_PTR(err);
1111 }
1112
1113 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1114 {
1115         struct vcpu_svm *svm = to_svm(vcpu);
1116
1117         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1118         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1119         __free_page(virt_to_page(svm->nested.hsave));
1120         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1121         kvm_vcpu_uninit(vcpu);
1122         kmem_cache_free(kvm_vcpu_cache, svm);
1123 }
1124
1125 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1126 {
1127         struct vcpu_svm *svm = to_svm(vcpu);
1128         int i;
1129
1130         if (unlikely(cpu != vcpu->cpu)) {
1131                 svm->asid_generation = 0;
1132                 mark_all_dirty(svm->vmcb);
1133         }
1134
1135 #ifdef CONFIG_X86_64
1136         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1137 #endif
1138         savesegment(fs, svm->host.fs);
1139         savesegment(gs, svm->host.gs);
1140         svm->host.ldt = kvm_read_ldt();
1141
1142         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1143                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1144 }
1145
1146 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1147 {
1148         struct vcpu_svm *svm = to_svm(vcpu);
1149         int i;
1150
1151         ++vcpu->stat.host_state_reload;
1152         kvm_load_ldt(svm->host.ldt);
1153 #ifdef CONFIG_X86_64
1154         loadsegment(fs, svm->host.fs);
1155         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1156         load_gs_index(svm->host.gs);
1157 #else
1158         loadsegment(gs, svm->host.gs);
1159 #endif
1160         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1161                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1162 }
1163
1164 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1165 {
1166         return to_svm(vcpu)->vmcb->save.rflags;
1167 }
1168
1169 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1170 {
1171         to_svm(vcpu)->vmcb->save.rflags = rflags;
1172 }
1173
1174 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1175 {
1176         switch (reg) {
1177         case VCPU_EXREG_PDPTR:
1178                 BUG_ON(!npt_enabled);
1179                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1180                 break;
1181         default:
1182                 BUG();
1183         }
1184 }
1185
1186 static void svm_set_vintr(struct vcpu_svm *svm)
1187 {
1188         set_intercept(svm, INTERCEPT_VINTR);
1189 }
1190
1191 static void svm_clear_vintr(struct vcpu_svm *svm)
1192 {
1193         clr_intercept(svm, INTERCEPT_VINTR);
1194 }
1195
1196 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1197 {
1198         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1199
1200         switch (seg) {
1201         case VCPU_SREG_CS: return &save->cs;
1202         case VCPU_SREG_DS: return &save->ds;
1203         case VCPU_SREG_ES: return &save->es;
1204         case VCPU_SREG_FS: return &save->fs;
1205         case VCPU_SREG_GS: return &save->gs;
1206         case VCPU_SREG_SS: return &save->ss;
1207         case VCPU_SREG_TR: return &save->tr;
1208         case VCPU_SREG_LDTR: return &save->ldtr;
1209         }
1210         BUG();
1211         return NULL;
1212 }
1213
1214 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1215 {
1216         struct vmcb_seg *s = svm_seg(vcpu, seg);
1217
1218         return s->base;
1219 }
1220
1221 static void svm_get_segment(struct kvm_vcpu *vcpu,
1222                             struct kvm_segment *var, int seg)
1223 {
1224         struct vmcb_seg *s = svm_seg(vcpu, seg);
1225
1226         var->base = s->base;
1227         var->limit = s->limit;
1228         var->selector = s->selector;
1229         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1230         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1231         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1232         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1233         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1234         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1235         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1236         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1237
1238         /*
1239          * AMD's VMCB does not have an explicit unusable field, so emulate it
1240          * for cross vendor migration purposes by "not present"
1241          */
1242         var->unusable = !var->present || (var->type == 0);
1243
1244         switch (seg) {
1245         case VCPU_SREG_CS:
1246                 /*
1247                  * SVM always stores 0 for the 'G' bit in the CS selector in
1248                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1249                  * Intel's VMENTRY has a check on the 'G' bit.
1250                  */
1251                 var->g = s->limit > 0xfffff;
1252                 break;
1253         case VCPU_SREG_TR:
1254                 /*
1255                  * Work around a bug where the busy flag in the tr selector
1256                  * isn't exposed
1257                  */
1258                 var->type |= 0x2;
1259                 break;
1260         case VCPU_SREG_DS:
1261         case VCPU_SREG_ES:
1262         case VCPU_SREG_FS:
1263         case VCPU_SREG_GS:
1264                 /*
1265                  * The accessed bit must always be set in the segment
1266                  * descriptor cache, although it can be cleared in the
1267                  * descriptor, the cached bit always remains at 1. Since
1268                  * Intel has a check on this, set it here to support
1269                  * cross-vendor migration.
1270                  */
1271                 if (!var->unusable)
1272                         var->type |= 0x1;
1273                 break;
1274         case VCPU_SREG_SS:
1275                 /*
1276                  * On AMD CPUs sometimes the DB bit in the segment
1277                  * descriptor is left as 1, although the whole segment has
1278                  * been made unusable. Clear it here to pass an Intel VMX
1279                  * entry check when cross vendor migrating.
1280                  */
1281                 if (var->unusable)
1282                         var->db = 0;
1283                 break;
1284         }
1285 }
1286
1287 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1288 {
1289         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1290
1291         return save->cpl;
1292 }
1293
1294 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1295 {
1296         struct vcpu_svm *svm = to_svm(vcpu);
1297
1298         dt->size = svm->vmcb->save.idtr.limit;
1299         dt->address = svm->vmcb->save.idtr.base;
1300 }
1301
1302 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1303 {
1304         struct vcpu_svm *svm = to_svm(vcpu);
1305
1306         svm->vmcb->save.idtr.limit = dt->size;
1307         svm->vmcb->save.idtr.base = dt->address ;
1308         mark_dirty(svm->vmcb, VMCB_DT);
1309 }
1310
1311 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1312 {
1313         struct vcpu_svm *svm = to_svm(vcpu);
1314
1315         dt->size = svm->vmcb->save.gdtr.limit;
1316         dt->address = svm->vmcb->save.gdtr.base;
1317 }
1318
1319 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1320 {
1321         struct vcpu_svm *svm = to_svm(vcpu);
1322
1323         svm->vmcb->save.gdtr.limit = dt->size;
1324         svm->vmcb->save.gdtr.base = dt->address ;
1325         mark_dirty(svm->vmcb, VMCB_DT);
1326 }
1327
1328 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1329 {
1330 }
1331
1332 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1333 {
1334 }
1335
1336 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1337 {
1338 }
1339
1340 static void update_cr0_intercept(struct vcpu_svm *svm)
1341 {
1342         ulong gcr0 = svm->vcpu.arch.cr0;
1343         u64 *hcr0 = &svm->vmcb->save.cr0;
1344
1345         if (!svm->vcpu.fpu_active)
1346                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1347         else
1348                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1349                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1350
1351         mark_dirty(svm->vmcb, VMCB_CR);
1352
1353         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1354                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1355                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1356         } else {
1357                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1358                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1359         }
1360 }
1361
1362 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1363 {
1364         struct vcpu_svm *svm = to_svm(vcpu);
1365
1366         if (is_guest_mode(vcpu)) {
1367                 /*
1368                  * We are here because we run in nested mode, the host kvm
1369                  * intercepts cr0 writes but the l1 hypervisor does not.
1370                  * But the L1 hypervisor may intercept selective cr0 writes.
1371                  * This needs to be checked here.
1372                  */
1373                 unsigned long old, new;
1374
1375                 /* Remove bits that would trigger a real cr0 write intercept */
1376                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1377                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1378
1379                 if (old == new) {
1380                         /* cr0 write with ts and mp unchanged */
1381                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1382                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1383                                 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1384                                 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1385                                 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1386                                 return;
1387                         }
1388                 }
1389         }
1390
1391 #ifdef CONFIG_X86_64
1392         if (vcpu->arch.efer & EFER_LME) {
1393                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1394                         vcpu->arch.efer |= EFER_LMA;
1395                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1396                 }
1397
1398                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1399                         vcpu->arch.efer &= ~EFER_LMA;
1400                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1401                 }
1402         }
1403 #endif
1404         vcpu->arch.cr0 = cr0;
1405
1406         if (!npt_enabled)
1407                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1408
1409         if (!vcpu->fpu_active)
1410                 cr0 |= X86_CR0_TS;
1411         /*
1412          * re-enable caching here because the QEMU bios
1413          * does not do it - this results in some delay at
1414          * reboot
1415          */
1416         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1417         svm->vmcb->save.cr0 = cr0;
1418         mark_dirty(svm->vmcb, VMCB_CR);
1419         update_cr0_intercept(svm);
1420 }
1421
1422 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1423 {
1424         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1425         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1426
1427         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1428                 svm_flush_tlb(vcpu);
1429
1430         vcpu->arch.cr4 = cr4;
1431         if (!npt_enabled)
1432                 cr4 |= X86_CR4_PAE;
1433         cr4 |= host_cr4_mce;
1434         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1435         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1436 }
1437
1438 static void svm_set_segment(struct kvm_vcpu *vcpu,
1439                             struct kvm_segment *var, int seg)
1440 {
1441         struct vcpu_svm *svm = to_svm(vcpu);
1442         struct vmcb_seg *s = svm_seg(vcpu, seg);
1443
1444         s->base = var->base;
1445         s->limit = var->limit;
1446         s->selector = var->selector;
1447         if (var->unusable)
1448                 s->attrib = 0;
1449         else {
1450                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1451                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1452                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1453                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1454                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1455                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1456                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1457                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1458         }
1459         if (seg == VCPU_SREG_CS)
1460                 svm->vmcb->save.cpl
1461                         = (svm->vmcb->save.cs.attrib
1462                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1463
1464         mark_dirty(svm->vmcb, VMCB_SEG);
1465 }
1466
1467 static void update_db_intercept(struct kvm_vcpu *vcpu)
1468 {
1469         struct vcpu_svm *svm = to_svm(vcpu);
1470
1471         clr_exception_intercept(svm, DB_VECTOR);
1472         clr_exception_intercept(svm, BP_VECTOR);
1473
1474         if (svm->nmi_singlestep)
1475                 set_exception_intercept(svm, DB_VECTOR);
1476
1477         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1478                 if (vcpu->guest_debug &
1479                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1480                         set_exception_intercept(svm, DB_VECTOR);
1481                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1482                         set_exception_intercept(svm, BP_VECTOR);
1483         } else
1484                 vcpu->guest_debug = 0;
1485 }
1486
1487 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1488 {
1489         struct vcpu_svm *svm = to_svm(vcpu);
1490
1491         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1492                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1493         else
1494                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1495
1496         mark_dirty(svm->vmcb, VMCB_DR);
1497
1498         update_db_intercept(vcpu);
1499 }
1500
1501 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1502 {
1503         if (sd->next_asid > sd->max_asid) {
1504                 ++sd->asid_generation;
1505                 sd->next_asid = 1;
1506                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1507         }
1508
1509         svm->asid_generation = sd->asid_generation;
1510         svm->vmcb->control.asid = sd->next_asid++;
1511
1512         mark_dirty(svm->vmcb, VMCB_ASID);
1513 }
1514
1515 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1516 {
1517         struct vcpu_svm *svm = to_svm(vcpu);
1518
1519         svm->vmcb->save.dr7 = value;
1520         mark_dirty(svm->vmcb, VMCB_DR);
1521 }
1522
1523 static int pf_interception(struct vcpu_svm *svm)
1524 {
1525         u64 fault_address = svm->vmcb->control.exit_info_2;
1526         u32 error_code;
1527         int r = 1;
1528
1529         switch (svm->apf_reason) {
1530         default:
1531                 error_code = svm->vmcb->control.exit_info_1;
1532
1533                 trace_kvm_page_fault(fault_address, error_code);
1534                 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1535                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1536                 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1537                         svm->vmcb->control.insn_bytes,
1538                         svm->vmcb->control.insn_len);
1539                 break;
1540         case KVM_PV_REASON_PAGE_NOT_PRESENT:
1541                 svm->apf_reason = 0;
1542                 local_irq_disable();
1543                 kvm_async_pf_task_wait(fault_address);
1544                 local_irq_enable();
1545                 break;
1546         case KVM_PV_REASON_PAGE_READY:
1547                 svm->apf_reason = 0;
1548                 local_irq_disable();
1549                 kvm_async_pf_task_wake(fault_address);
1550                 local_irq_enable();
1551                 break;
1552         }
1553         return r;
1554 }
1555
1556 static int db_interception(struct vcpu_svm *svm)
1557 {
1558         struct kvm_run *kvm_run = svm->vcpu.run;
1559
1560         if (!(svm->vcpu.guest_debug &
1561               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1562                 !svm->nmi_singlestep) {
1563                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1564                 return 1;
1565         }
1566
1567         if (svm->nmi_singlestep) {
1568                 svm->nmi_singlestep = false;
1569                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1570                         svm->vmcb->save.rflags &=
1571                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1572                 update_db_intercept(&svm->vcpu);
1573         }
1574
1575         if (svm->vcpu.guest_debug &
1576             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1577                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1578                 kvm_run->debug.arch.pc =
1579                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1580                 kvm_run->debug.arch.exception = DB_VECTOR;
1581                 return 0;
1582         }
1583
1584         return 1;
1585 }
1586
1587 static int bp_interception(struct vcpu_svm *svm)
1588 {
1589         struct kvm_run *kvm_run = svm->vcpu.run;
1590
1591         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1592         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1593         kvm_run->debug.arch.exception = BP_VECTOR;
1594         return 0;
1595 }
1596
1597 static int ud_interception(struct vcpu_svm *svm)
1598 {
1599         int er;
1600
1601         er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1602         if (er != EMULATE_DONE)
1603                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1604         return 1;
1605 }
1606
1607 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1608 {
1609         struct vcpu_svm *svm = to_svm(vcpu);
1610
1611         clr_exception_intercept(svm, NM_VECTOR);
1612
1613         svm->vcpu.fpu_active = 1;
1614         update_cr0_intercept(svm);
1615 }
1616
1617 static int nm_interception(struct vcpu_svm *svm)
1618 {
1619         svm_fpu_activate(&svm->vcpu);
1620         return 1;
1621 }
1622
1623 static bool is_erratum_383(void)
1624 {
1625         int err, i;
1626         u64 value;
1627
1628         if (!erratum_383_found)
1629                 return false;
1630
1631         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1632         if (err)
1633                 return false;
1634
1635         /* Bit 62 may or may not be set for this mce */
1636         value &= ~(1ULL << 62);
1637
1638         if (value != 0xb600000000010015ULL)
1639                 return false;
1640
1641         /* Clear MCi_STATUS registers */
1642         for (i = 0; i < 6; ++i)
1643                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1644
1645         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1646         if (!err) {
1647                 u32 low, high;
1648
1649                 value &= ~(1ULL << 2);
1650                 low    = lower_32_bits(value);
1651                 high   = upper_32_bits(value);
1652
1653                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1654         }
1655
1656         /* Flush tlb to evict multi-match entries */
1657         __flush_tlb_all();
1658
1659         return true;
1660 }
1661
1662 static void svm_handle_mce(struct vcpu_svm *svm)
1663 {
1664         if (is_erratum_383()) {
1665                 /*
1666                  * Erratum 383 triggered. Guest state is corrupt so kill the
1667                  * guest.
1668                  */
1669                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1670
1671                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1672
1673                 return;
1674         }
1675
1676         /*
1677          * On an #MC intercept the MCE handler is not called automatically in
1678          * the host. So do it by hand here.
1679          */
1680         asm volatile (
1681                 "int $0x12\n");
1682         /* not sure if we ever come back to this point */
1683
1684         return;
1685 }
1686
1687 static int mc_interception(struct vcpu_svm *svm)
1688 {
1689         return 1;
1690 }
1691
1692 static int shutdown_interception(struct vcpu_svm *svm)
1693 {
1694         struct kvm_run *kvm_run = svm->vcpu.run;
1695
1696         /*
1697          * VMCB is undefined after a SHUTDOWN intercept
1698          * so reinitialize it.
1699          */
1700         clear_page(svm->vmcb);
1701         init_vmcb(svm);
1702
1703         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1704         return 0;
1705 }
1706
1707 static int io_interception(struct vcpu_svm *svm)
1708 {
1709         struct kvm_vcpu *vcpu = &svm->vcpu;
1710         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1711         int size, in, string;
1712         unsigned port;
1713
1714         ++svm->vcpu.stat.io_exits;
1715         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1716         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1717         if (string || in)
1718                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1719
1720         port = io_info >> 16;
1721         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1722         svm->next_rip = svm->vmcb->control.exit_info_2;
1723         skip_emulated_instruction(&svm->vcpu);
1724
1725         return kvm_fast_pio_out(vcpu, size, port);
1726 }
1727
1728 static int nmi_interception(struct vcpu_svm *svm)
1729 {
1730         return 1;
1731 }
1732
1733 static int intr_interception(struct vcpu_svm *svm)
1734 {
1735         ++svm->vcpu.stat.irq_exits;
1736         return 1;
1737 }
1738
1739 static int nop_on_interception(struct vcpu_svm *svm)
1740 {
1741         return 1;
1742 }
1743
1744 static int halt_interception(struct vcpu_svm *svm)
1745 {
1746         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1747         skip_emulated_instruction(&svm->vcpu);
1748         return kvm_emulate_halt(&svm->vcpu);
1749 }
1750
1751 static int vmmcall_interception(struct vcpu_svm *svm)
1752 {
1753         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1754         skip_emulated_instruction(&svm->vcpu);
1755         kvm_emulate_hypercall(&svm->vcpu);
1756         return 1;
1757 }
1758
1759 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1760 {
1761         struct vcpu_svm *svm = to_svm(vcpu);
1762
1763         return svm->nested.nested_cr3;
1764 }
1765
1766 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1767                                    unsigned long root)
1768 {
1769         struct vcpu_svm *svm = to_svm(vcpu);
1770
1771         svm->vmcb->control.nested_cr3 = root;
1772         mark_dirty(svm->vmcb, VMCB_NPT);
1773         svm_flush_tlb(vcpu);
1774 }
1775
1776 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1777                                        struct x86_exception *fault)
1778 {
1779         struct vcpu_svm *svm = to_svm(vcpu);
1780
1781         svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1782         svm->vmcb->control.exit_code_hi = 0;
1783         svm->vmcb->control.exit_info_1 = fault->error_code;
1784         svm->vmcb->control.exit_info_2 = fault->address;
1785
1786         nested_svm_vmexit(svm);
1787 }
1788
1789 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1790 {
1791         int r;
1792
1793         r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1794
1795         vcpu->arch.mmu.set_cr3           = nested_svm_set_tdp_cr3;
1796         vcpu->arch.mmu.get_cr3           = nested_svm_get_tdp_cr3;
1797         vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1798         vcpu->arch.mmu.shadow_root_level = get_npt_level();
1799         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
1800
1801         return r;
1802 }
1803
1804 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1805 {
1806         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1807 }
1808
1809 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1810 {
1811         if (!(svm->vcpu.arch.efer & EFER_SVME)
1812             || !is_paging(&svm->vcpu)) {
1813                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1814                 return 1;
1815         }
1816
1817         if (svm->vmcb->save.cpl) {
1818                 kvm_inject_gp(&svm->vcpu, 0);
1819                 return 1;
1820         }
1821
1822        return 0;
1823 }
1824
1825 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1826                                       bool has_error_code, u32 error_code)
1827 {
1828         int vmexit;
1829
1830         if (!is_guest_mode(&svm->vcpu))
1831                 return 0;
1832
1833         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1834         svm->vmcb->control.exit_code_hi = 0;
1835         svm->vmcb->control.exit_info_1 = error_code;
1836         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1837
1838         vmexit = nested_svm_intercept(svm);
1839         if (vmexit == NESTED_EXIT_DONE)
1840                 svm->nested.exit_required = true;
1841
1842         return vmexit;
1843 }
1844
1845 /* This function returns true if it is save to enable the irq window */
1846 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1847 {
1848         if (!is_guest_mode(&svm->vcpu))
1849                 return true;
1850
1851         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1852                 return true;
1853
1854         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1855                 return false;
1856
1857         /*
1858          * if vmexit was already requested (by intercepted exception
1859          * for instance) do not overwrite it with "external interrupt"
1860          * vmexit.
1861          */
1862         if (svm->nested.exit_required)
1863                 return false;
1864
1865         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1866         svm->vmcb->control.exit_info_1 = 0;
1867         svm->vmcb->control.exit_info_2 = 0;
1868
1869         if (svm->nested.intercept & 1ULL) {
1870                 /*
1871                  * The #vmexit can't be emulated here directly because this
1872                  * code path runs with irqs and preemtion disabled. A
1873                  * #vmexit emulation might sleep. Only signal request for
1874                  * the #vmexit here.
1875                  */
1876                 svm->nested.exit_required = true;
1877                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1878                 return false;
1879         }
1880
1881         return true;
1882 }
1883
1884 /* This function returns true if it is save to enable the nmi window */
1885 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1886 {
1887         if (!is_guest_mode(&svm->vcpu))
1888                 return true;
1889
1890         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1891                 return true;
1892
1893         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1894         svm->nested.exit_required = true;
1895
1896         return false;
1897 }
1898
1899 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1900 {
1901         struct page *page;
1902
1903         might_sleep();
1904
1905         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1906         if (is_error_page(page))
1907                 goto error;
1908
1909         *_page = page;
1910
1911         return kmap(page);
1912
1913 error:
1914         kvm_release_page_clean(page);
1915         kvm_inject_gp(&svm->vcpu, 0);
1916
1917         return NULL;
1918 }
1919
1920 static void nested_svm_unmap(struct page *page)
1921 {
1922         kunmap(page);
1923         kvm_release_page_dirty(page);
1924 }
1925
1926 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1927 {
1928         unsigned port;
1929         u8 val, bit;
1930         u64 gpa;
1931
1932         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1933                 return NESTED_EXIT_HOST;
1934
1935         port = svm->vmcb->control.exit_info_1 >> 16;
1936         gpa  = svm->nested.vmcb_iopm + (port / 8);
1937         bit  = port % 8;
1938         val  = 0;
1939
1940         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1941                 val &= (1 << bit);
1942
1943         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1944 }
1945
1946 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1947 {
1948         u32 offset, msr, value;
1949         int write, mask;
1950
1951         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1952                 return NESTED_EXIT_HOST;
1953
1954         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1955         offset = svm_msrpm_offset(msr);
1956         write  = svm->vmcb->control.exit_info_1 & 1;
1957         mask   = 1 << ((2 * (msr & 0xf)) + write);
1958
1959         if (offset == MSR_INVALID)
1960                 return NESTED_EXIT_DONE;
1961
1962         /* Offset is in 32 bit units but need in 8 bit units */
1963         offset *= 4;
1964
1965         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1966                 return NESTED_EXIT_DONE;
1967
1968         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1969 }
1970
1971 static int nested_svm_exit_special(struct vcpu_svm *svm)
1972 {
1973         u32 exit_code = svm->vmcb->control.exit_code;
1974
1975         switch (exit_code) {
1976         case SVM_EXIT_INTR:
1977         case SVM_EXIT_NMI:
1978         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1979                 return NESTED_EXIT_HOST;
1980         case SVM_EXIT_NPF:
1981                 /* For now we are always handling NPFs when using them */
1982                 if (npt_enabled)
1983                         return NESTED_EXIT_HOST;
1984                 break;
1985         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1986                 /* When we're shadowing, trap PFs, but not async PF */
1987                 if (!npt_enabled && svm->apf_reason == 0)
1988                         return NESTED_EXIT_HOST;
1989                 break;
1990         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1991                 nm_interception(svm);
1992                 break;
1993         default:
1994                 break;
1995         }
1996
1997         return NESTED_EXIT_CONTINUE;
1998 }
1999
2000 /*
2001  * If this function returns true, this #vmexit was already handled
2002  */
2003 static int nested_svm_intercept(struct vcpu_svm *svm)
2004 {
2005         u32 exit_code = svm->vmcb->control.exit_code;
2006         int vmexit = NESTED_EXIT_HOST;
2007
2008         switch (exit_code) {
2009         case SVM_EXIT_MSR:
2010                 vmexit = nested_svm_exit_handled_msr(svm);
2011                 break;
2012         case SVM_EXIT_IOIO:
2013                 vmexit = nested_svm_intercept_ioio(svm);
2014                 break;
2015         case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2016                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2017                 if (svm->nested.intercept_cr & bit)
2018                         vmexit = NESTED_EXIT_DONE;
2019                 break;
2020         }
2021         case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2022                 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2023                 if (svm->nested.intercept_dr & bit)
2024                         vmexit = NESTED_EXIT_DONE;
2025                 break;
2026         }
2027         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2028                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2029                 if (svm->nested.intercept_exceptions & excp_bits)
2030                         vmexit = NESTED_EXIT_DONE;
2031                 /* async page fault always cause vmexit */
2032                 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2033                          svm->apf_reason != 0)
2034                         vmexit = NESTED_EXIT_DONE;
2035                 break;
2036         }
2037         case SVM_EXIT_ERR: {
2038                 vmexit = NESTED_EXIT_DONE;
2039                 break;
2040         }
2041         default: {
2042                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2043                 if (svm->nested.intercept & exit_bits)
2044                         vmexit = NESTED_EXIT_DONE;
2045         }
2046         }
2047
2048         return vmexit;
2049 }
2050
2051 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2052 {
2053         int vmexit;
2054
2055         vmexit = nested_svm_intercept(svm);
2056
2057         if (vmexit == NESTED_EXIT_DONE)
2058                 nested_svm_vmexit(svm);
2059
2060         return vmexit;
2061 }
2062
2063 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2064 {
2065         struct vmcb_control_area *dst  = &dst_vmcb->control;
2066         struct vmcb_control_area *from = &from_vmcb->control;
2067
2068         dst->intercept_cr         = from->intercept_cr;
2069         dst->intercept_dr         = from->intercept_dr;
2070         dst->intercept_exceptions = from->intercept_exceptions;
2071         dst->intercept            = from->intercept;
2072         dst->iopm_base_pa         = from->iopm_base_pa;
2073         dst->msrpm_base_pa        = from->msrpm_base_pa;
2074         dst->tsc_offset           = from->tsc_offset;
2075         dst->asid                 = from->asid;
2076         dst->tlb_ctl              = from->tlb_ctl;
2077         dst->int_ctl              = from->int_ctl;
2078         dst->int_vector           = from->int_vector;
2079         dst->int_state            = from->int_state;
2080         dst->exit_code            = from->exit_code;
2081         dst->exit_code_hi         = from->exit_code_hi;
2082         dst->exit_info_1          = from->exit_info_1;
2083         dst->exit_info_2          = from->exit_info_2;
2084         dst->exit_int_info        = from->exit_int_info;
2085         dst->exit_int_info_err    = from->exit_int_info_err;
2086         dst->nested_ctl           = from->nested_ctl;
2087         dst->event_inj            = from->event_inj;
2088         dst->event_inj_err        = from->event_inj_err;
2089         dst->nested_cr3           = from->nested_cr3;
2090         dst->lbr_ctl              = from->lbr_ctl;
2091 }
2092
2093 static int nested_svm_vmexit(struct vcpu_svm *svm)
2094 {
2095         struct vmcb *nested_vmcb;
2096         struct vmcb *hsave = svm->nested.hsave;
2097         struct vmcb *vmcb = svm->vmcb;
2098         struct page *page;
2099
2100         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2101                                        vmcb->control.exit_info_1,
2102                                        vmcb->control.exit_info_2,
2103                                        vmcb->control.exit_int_info,
2104                                        vmcb->control.exit_int_info_err);
2105
2106         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2107         if (!nested_vmcb)
2108                 return 1;
2109
2110         /* Exit Guest-Mode */
2111         leave_guest_mode(&svm->vcpu);
2112         svm->nested.vmcb = 0;
2113
2114         /* Give the current vmcb to the guest */
2115         disable_gif(svm);
2116
2117         nested_vmcb->save.es     = vmcb->save.es;
2118         nested_vmcb->save.cs     = vmcb->save.cs;
2119         nested_vmcb->save.ss     = vmcb->save.ss;
2120         nested_vmcb->save.ds     = vmcb->save.ds;
2121         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
2122         nested_vmcb->save.idtr   = vmcb->save.idtr;
2123         nested_vmcb->save.efer   = svm->vcpu.arch.efer;
2124         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
2125         nested_vmcb->save.cr3    = kvm_read_cr3(&svm->vcpu);
2126         nested_vmcb->save.cr2    = vmcb->save.cr2;
2127         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
2128         nested_vmcb->save.rflags = vmcb->save.rflags;
2129         nested_vmcb->save.rip    = vmcb->save.rip;
2130         nested_vmcb->save.rsp    = vmcb->save.rsp;
2131         nested_vmcb->save.rax    = vmcb->save.rax;
2132         nested_vmcb->save.dr7    = vmcb->save.dr7;
2133         nested_vmcb->save.dr6    = vmcb->save.dr6;
2134         nested_vmcb->save.cpl    = vmcb->save.cpl;
2135
2136         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
2137         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
2138         nested_vmcb->control.int_state         = vmcb->control.int_state;
2139         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
2140         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
2141         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
2142         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
2143         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
2144         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2145         nested_vmcb->control.next_rip          = vmcb->control.next_rip;
2146
2147         /*
2148          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2149          * to make sure that we do not lose injected events. So check event_inj
2150          * here and copy it to exit_int_info if it is valid.
2151          * Exit_int_info and event_inj can't be both valid because the case
2152          * below only happens on a VMRUN instruction intercept which has
2153          * no valid exit_int_info set.
2154          */
2155         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2156                 struct vmcb_control_area *nc = &nested_vmcb->control;
2157
2158                 nc->exit_int_info     = vmcb->control.event_inj;
2159                 nc->exit_int_info_err = vmcb->control.event_inj_err;
2160         }
2161
2162         nested_vmcb->control.tlb_ctl           = 0;
2163         nested_vmcb->control.event_inj         = 0;
2164         nested_vmcb->control.event_inj_err     = 0;
2165
2166         /* We always set V_INTR_MASKING and remember the old value in hflags */
2167         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2168                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2169
2170         /* Restore the original control entries */
2171         copy_vmcb_control_area(vmcb, hsave);
2172
2173         kvm_clear_exception_queue(&svm->vcpu);
2174         kvm_clear_interrupt_queue(&svm->vcpu);
2175
2176         svm->nested.nested_cr3 = 0;
2177
2178         /* Restore selected save entries */
2179         svm->vmcb->save.es = hsave->save.es;
2180         svm->vmcb->save.cs = hsave->save.cs;
2181         svm->vmcb->save.ss = hsave->save.ss;
2182         svm->vmcb->save.ds = hsave->save.ds;
2183         svm->vmcb->save.gdtr = hsave->save.gdtr;
2184         svm->vmcb->save.idtr = hsave->save.idtr;
2185         svm->vmcb->save.rflags = hsave->save.rflags;
2186         svm_set_efer(&svm->vcpu, hsave->save.efer);
2187         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2188         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2189         if (npt_enabled) {
2190                 svm->vmcb->save.cr3 = hsave->save.cr3;
2191                 svm->vcpu.arch.cr3 = hsave->save.cr3;
2192         } else {
2193                 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2194         }
2195         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2196         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2197         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2198         svm->vmcb->save.dr7 = 0;
2199         svm->vmcb->save.cpl = 0;
2200         svm->vmcb->control.exit_int_info = 0;
2201
2202         mark_all_dirty(svm->vmcb);
2203
2204         nested_svm_unmap(page);
2205
2206         nested_svm_uninit_mmu_context(&svm->vcpu);
2207         kvm_mmu_reset_context(&svm->vcpu);
2208         kvm_mmu_load(&svm->vcpu);
2209
2210         return 0;
2211 }
2212
2213 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2214 {
2215         /*
2216          * This function merges the msr permission bitmaps of kvm and the
2217          * nested vmcb. It is omptimized in that it only merges the parts where
2218          * the kvm msr permission bitmap may contain zero bits
2219          */
2220         int i;
2221
2222         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2223                 return true;
2224
2225         for (i = 0; i < MSRPM_OFFSETS; i++) {
2226                 u32 value, p;
2227                 u64 offset;
2228
2229                 if (msrpm_offsets[i] == 0xffffffff)
2230                         break;
2231
2232                 p      = msrpm_offsets[i];
2233                 offset = svm->nested.vmcb_msrpm + (p * 4);
2234
2235                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2236                         return false;
2237
2238                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2239         }
2240
2241         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2242
2243         return true;
2244 }
2245
2246 static bool nested_vmcb_checks(struct vmcb *vmcb)
2247 {
2248         if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2249                 return false;
2250
2251         if (vmcb->control.asid == 0)
2252                 return false;
2253
2254         if (vmcb->control.nested_ctl && !npt_enabled)
2255                 return false;
2256
2257         return true;
2258 }
2259
2260 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2261 {
2262         struct vmcb *nested_vmcb;
2263         struct vmcb *hsave = svm->nested.hsave;
2264         struct vmcb *vmcb = svm->vmcb;
2265         struct page *page;
2266         u64 vmcb_gpa;
2267
2268         vmcb_gpa = svm->vmcb->save.rax;
2269
2270         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2271         if (!nested_vmcb)
2272                 return false;
2273
2274         if (!nested_vmcb_checks(nested_vmcb)) {
2275                 nested_vmcb->control.exit_code    = SVM_EXIT_ERR;
2276                 nested_vmcb->control.exit_code_hi = 0;
2277                 nested_vmcb->control.exit_info_1  = 0;
2278                 nested_vmcb->control.exit_info_2  = 0;
2279
2280                 nested_svm_unmap(page);
2281
2282                 return false;
2283         }
2284
2285         trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2286                                nested_vmcb->save.rip,
2287                                nested_vmcb->control.int_ctl,
2288                                nested_vmcb->control.event_inj,
2289                                nested_vmcb->control.nested_ctl);
2290
2291         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2292                                     nested_vmcb->control.intercept_cr >> 16,
2293                                     nested_vmcb->control.intercept_exceptions,
2294                                     nested_vmcb->control.intercept);
2295
2296         /* Clear internal status */
2297         kvm_clear_exception_queue(&svm->vcpu);
2298         kvm_clear_interrupt_queue(&svm->vcpu);
2299
2300         /*
2301          * Save the old vmcb, so we don't need to pick what we save, but can
2302          * restore everything when a VMEXIT occurs
2303          */
2304         hsave->save.es     = vmcb->save.es;
2305         hsave->save.cs     = vmcb->save.cs;
2306         hsave->save.ss     = vmcb->save.ss;
2307         hsave->save.ds     = vmcb->save.ds;
2308         hsave->save.gdtr   = vmcb->save.gdtr;
2309         hsave->save.idtr   = vmcb->save.idtr;
2310         hsave->save.efer   = svm->vcpu.arch.efer;
2311         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
2312         hsave->save.cr4    = svm->vcpu.arch.cr4;
2313         hsave->save.rflags = vmcb->save.rflags;
2314         hsave->save.rip    = kvm_rip_read(&svm->vcpu);
2315         hsave->save.rsp    = vmcb->save.rsp;
2316         hsave->save.rax    = vmcb->save.rax;
2317         if (npt_enabled)
2318                 hsave->save.cr3    = vmcb->save.cr3;
2319         else
2320                 hsave->save.cr3    = kvm_read_cr3(&svm->vcpu);
2321
2322         copy_vmcb_control_area(hsave, vmcb);
2323
2324         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2325                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2326         else
2327                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2328
2329         if (nested_vmcb->control.nested_ctl) {
2330                 kvm_mmu_unload(&svm->vcpu);
2331                 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2332                 nested_svm_init_mmu_context(&svm->vcpu);
2333         }
2334
2335         /* Load the nested guest state */
2336         svm->vmcb->save.es = nested_vmcb->save.es;
2337         svm->vmcb->save.cs = nested_vmcb->save.cs;
2338         svm->vmcb->save.ss = nested_vmcb->save.ss;
2339         svm->vmcb->save.ds = nested_vmcb->save.ds;
2340         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2341         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2342         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2343         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2344         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2345         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2346         if (npt_enabled) {
2347                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2348                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2349         } else
2350                 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2351
2352         /* Guest paging mode is active - reset mmu */
2353         kvm_mmu_reset_context(&svm->vcpu);
2354
2355         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2356         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2357         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2358         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2359
2360         /* In case we don't even reach vcpu_run, the fields are not updated */
2361         svm->vmcb->save.rax = nested_vmcb->save.rax;
2362         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2363         svm->vmcb->save.rip = nested_vmcb->save.rip;
2364         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2365         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2366         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2367
2368         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2369         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2370
2371         /* cache intercepts */
2372         svm->nested.intercept_cr         = nested_vmcb->control.intercept_cr;
2373         svm->nested.intercept_dr         = nested_vmcb->control.intercept_dr;
2374         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2375         svm->nested.intercept            = nested_vmcb->control.intercept;
2376
2377         svm_flush_tlb(&svm->vcpu);
2378         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2379         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2380                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2381         else
2382                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2383
2384         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2385                 /* We only want the cr8 intercept bits of the guest */
2386                 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2387                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2388         }
2389
2390         /* We don't want to see VMMCALLs from a nested guest */
2391         clr_intercept(svm, INTERCEPT_VMMCALL);
2392
2393         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2394         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2395         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2396         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2397         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2398         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2399
2400         nested_svm_unmap(page);
2401
2402         /* Enter Guest-Mode */
2403         enter_guest_mode(&svm->vcpu);
2404
2405         /*
2406          * Merge guest and host intercepts - must be called  with vcpu in
2407          * guest-mode to take affect here
2408          */
2409         recalc_intercepts(svm);
2410
2411         svm->nested.vmcb = vmcb_gpa;
2412
2413         enable_gif(svm);
2414
2415         mark_all_dirty(svm->vmcb);
2416
2417         return true;
2418 }
2419
2420 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2421 {
2422         to_vmcb->save.fs = from_vmcb->save.fs;
2423         to_vmcb->save.gs = from_vmcb->save.gs;
2424         to_vmcb->save.tr = from_vmcb->save.tr;
2425         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2426         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2427         to_vmcb->save.star = from_vmcb->save.star;
2428         to_vmcb->save.lstar = from_vmcb->save.lstar;
2429         to_vmcb->save.cstar = from_vmcb->save.cstar;
2430         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2431         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2432         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2433         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2434 }
2435
2436 static int vmload_interception(struct vcpu_svm *svm)
2437 {
2438         struct vmcb *nested_vmcb;
2439         struct page *page;
2440
2441         if (nested_svm_check_permissions(svm))
2442                 return 1;
2443
2444         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2445         skip_emulated_instruction(&svm->vcpu);
2446
2447         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2448         if (!nested_vmcb)
2449                 return 1;
2450
2451         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2452         nested_svm_unmap(page);
2453
2454         return 1;
2455 }
2456
2457 static int vmsave_interception(struct vcpu_svm *svm)
2458 {
2459         struct vmcb *nested_vmcb;
2460         struct page *page;
2461
2462         if (nested_svm_check_permissions(svm))
2463                 return 1;
2464
2465         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2466         skip_emulated_instruction(&svm->vcpu);
2467
2468         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2469         if (!nested_vmcb)
2470                 return 1;
2471
2472         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2473         nested_svm_unmap(page);
2474
2475         return 1;
2476 }
2477
2478 static int vmrun_interception(struct vcpu_svm *svm)
2479 {
2480         if (nested_svm_check_permissions(svm))
2481                 return 1;
2482
2483         /* Save rip after vmrun instruction */
2484         kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2485
2486         if (!nested_svm_vmrun(svm))
2487                 return 1;
2488
2489         if (!nested_svm_vmrun_msrpm(svm))
2490                 goto failed;
2491
2492         return 1;
2493
2494 failed:
2495
2496         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2497         svm->vmcb->control.exit_code_hi = 0;
2498         svm->vmcb->control.exit_info_1  = 0;
2499         svm->vmcb->control.exit_info_2  = 0;
2500
2501         nested_svm_vmexit(svm);
2502
2503         return 1;
2504 }
2505
2506 static int stgi_interception(struct vcpu_svm *svm)
2507 {
2508         if (nested_svm_check_permissions(svm))
2509                 return 1;
2510
2511         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2512         skip_emulated_instruction(&svm->vcpu);
2513         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2514
2515         enable_gif(svm);
2516
2517         return 1;
2518 }
2519
2520 static int clgi_interception(struct vcpu_svm *svm)
2521 {
2522         if (nested_svm_check_permissions(svm))
2523                 return 1;
2524
2525         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2526         skip_emulated_instruction(&svm->vcpu);
2527
2528         disable_gif(svm);
2529
2530         /* After a CLGI no interrupts should come */
2531         svm_clear_vintr(svm);
2532         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2533
2534         mark_dirty(svm->vmcb, VMCB_INTR);
2535
2536         return 1;
2537 }
2538
2539 static int invlpga_interception(struct vcpu_svm *svm)
2540 {
2541         struct kvm_vcpu *vcpu = &svm->vcpu;
2542
2543         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2544                           vcpu->arch.regs[VCPU_REGS_RAX]);
2545
2546         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2547         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2548
2549         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2550         skip_emulated_instruction(&svm->vcpu);
2551         return 1;
2552 }
2553
2554 static int skinit_interception(struct vcpu_svm *svm)
2555 {
2556         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2557
2558         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2559         return 1;
2560 }
2561
2562 static int xsetbv_interception(struct vcpu_svm *svm)
2563 {
2564         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2565         u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2566
2567         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2568                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2569                 skip_emulated_instruction(&svm->vcpu);
2570         }
2571
2572         return 1;
2573 }
2574
2575 static int invalid_op_interception(struct vcpu_svm *svm)
2576 {
2577         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2578         return 1;
2579 }
2580
2581 static int task_switch_interception(struct vcpu_svm *svm)
2582 {
2583         u16 tss_selector;
2584         int reason;
2585         int int_type = svm->vmcb->control.exit_int_info &
2586                 SVM_EXITINTINFO_TYPE_MASK;
2587         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2588         uint32_t type =
2589                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2590         uint32_t idt_v =
2591                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2592         bool has_error_code = false;
2593         u32 error_code = 0;
2594
2595         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2596
2597         if (svm->vmcb->control.exit_info_2 &
2598             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2599                 reason = TASK_SWITCH_IRET;
2600         else if (svm->vmcb->control.exit_info_2 &
2601                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2602                 reason = TASK_SWITCH_JMP;
2603         else if (idt_v)
2604                 reason = TASK_SWITCH_GATE;
2605         else
2606                 reason = TASK_SWITCH_CALL;
2607
2608         if (reason == TASK_SWITCH_GATE) {
2609                 switch (type) {
2610                 case SVM_EXITINTINFO_TYPE_NMI:
2611                         svm->vcpu.arch.nmi_injected = false;
2612                         break;
2613                 case SVM_EXITINTINFO_TYPE_EXEPT:
2614                         if (svm->vmcb->control.exit_info_2 &
2615                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2616                                 has_error_code = true;
2617                                 error_code =
2618                                         (u32)svm->vmcb->control.exit_info_2;
2619                         }
2620                         kvm_clear_exception_queue(&svm->vcpu);
2621                         break;
2622                 case SVM_EXITINTINFO_TYPE_INTR:
2623                         kvm_clear_interrupt_queue(&svm->vcpu);
2624                         break;
2625                 default:
2626                         break;
2627                 }
2628         }
2629
2630         if (reason != TASK_SWITCH_GATE ||
2631             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2632             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2633              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2634                 skip_emulated_instruction(&svm->vcpu);
2635
2636         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2637                                 has_error_code, error_code) == EMULATE_FAIL) {
2638                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2639                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2640                 svm->vcpu.run->internal.ndata = 0;
2641                 return 0;
2642         }
2643         return 1;
2644 }
2645
2646 static int cpuid_interception(struct vcpu_svm *svm)
2647 {
2648         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2649         kvm_emulate_cpuid(&svm->vcpu);
2650         return 1;
2651 }
2652
2653 static int iret_interception(struct vcpu_svm *svm)
2654 {
2655         ++svm->vcpu.stat.nmi_window_exits;
2656         clr_intercept(svm, INTERCEPT_IRET);
2657         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2658         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2659         return 1;
2660 }
2661
2662 static int invlpg_interception(struct vcpu_svm *svm)
2663 {
2664         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2665                 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2666
2667         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2668         skip_emulated_instruction(&svm->vcpu);
2669         return 1;
2670 }
2671
2672 static int emulate_on_interception(struct vcpu_svm *svm)
2673 {
2674         return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2675 }
2676
2677 #define CR_VALID (1ULL << 63)
2678
2679 static int cr_interception(struct vcpu_svm *svm)
2680 {
2681         int reg, cr;
2682         unsigned long val;
2683         int err;
2684
2685         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2686                 return emulate_on_interception(svm);
2687
2688         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2689                 return emulate_on_interception(svm);
2690
2691         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2692         cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2693
2694         err = 0;
2695         if (cr >= 16) { /* mov to cr */
2696                 cr -= 16;
2697                 val = kvm_register_read(&svm->vcpu, reg);
2698                 switch (cr) {
2699                 case 0:
2700                         err = kvm_set_cr0(&svm->vcpu, val);
2701                         break;
2702                 case 3:
2703                         err = kvm_set_cr3(&svm->vcpu, val);
2704                         break;
2705                 case 4:
2706                         err = kvm_set_cr4(&svm->vcpu, val);
2707                         break;
2708                 case 8:
2709                         err = kvm_set_cr8(&svm->vcpu, val);
2710                         break;
2711                 default:
2712                         WARN(1, "unhandled write to CR%d", cr);
2713                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2714                         return 1;
2715                 }
2716         } else { /* mov from cr */
2717                 switch (cr) {
2718                 case 0:
2719                         val = kvm_read_cr0(&svm->vcpu);
2720                         break;
2721                 case 2:
2722                         val = svm->vcpu.arch.cr2;
2723                         break;
2724                 case 3:
2725                         val = kvm_read_cr3(&svm->vcpu);
2726                         break;
2727                 case 4:
2728                         val = kvm_read_cr4(&svm->vcpu);
2729                         break;
2730                 case 8:
2731                         val = kvm_get_cr8(&svm->vcpu);
2732                         break;
2733                 default:
2734                         WARN(1, "unhandled read from CR%d", cr);
2735                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2736                         return 1;
2737                 }
2738                 kvm_register_write(&svm->vcpu, reg, val);
2739         }
2740         kvm_complete_insn_gp(&svm->vcpu, err);
2741
2742         return 1;
2743 }
2744
2745 static int cr0_write_interception(struct vcpu_svm *svm)
2746 {
2747         struct kvm_vcpu *vcpu = &svm->vcpu;
2748         int r;
2749
2750         r = cr_interception(svm);
2751
2752         if (svm->nested.vmexit_rip) {
2753                 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2754                 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2755                 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2756                 svm->nested.vmexit_rip = 0;
2757         }
2758
2759         return r;
2760 }
2761
2762 static int dr_interception(struct vcpu_svm *svm)
2763 {
2764         int reg, dr;
2765         unsigned long val;
2766         int err;
2767
2768         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2769                 return emulate_on_interception(svm);
2770
2771         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2772         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2773
2774         if (dr >= 16) { /* mov to DRn */
2775                 val = kvm_register_read(&svm->vcpu, reg);
2776                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2777         } else {
2778                 err = kvm_get_dr(&svm->vcpu, dr, &val);
2779                 if (!err)
2780                         kvm_register_write(&svm->vcpu, reg, val);
2781         }
2782
2783         skip_emulated_instruction(&svm->vcpu);
2784
2785         return 1;
2786 }
2787
2788 static int cr8_write_interception(struct vcpu_svm *svm)
2789 {
2790         struct kvm_run *kvm_run = svm->vcpu.run;
2791         int r;
2792
2793         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2794         /* instruction emulation calls kvm_set_cr8() */
2795         r = cr_interception(svm);
2796         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2797                 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2798                 return r;
2799         }
2800         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2801                 return r;
2802         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2803         return 0;
2804 }
2805
2806 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2807 {
2808         struct vcpu_svm *svm = to_svm(vcpu);
2809
2810         switch (ecx) {
2811         case MSR_IA32_TSC: {
2812                 struct vmcb *vmcb = get_host_vmcb(svm);
2813
2814                 *data = vmcb->control.tsc_offset + native_read_tsc();
2815                 break;
2816         }
2817         case MSR_STAR:
2818                 *data = svm->vmcb->save.star;
2819                 break;
2820 #ifdef CONFIG_X86_64
2821         case MSR_LSTAR:
2822                 *data = svm->vmcb->save.lstar;
2823                 break;
2824         case MSR_CSTAR:
2825                 *data = svm->vmcb->save.cstar;
2826                 break;
2827         case MSR_KERNEL_GS_BASE:
2828                 *data = svm->vmcb->save.kernel_gs_base;
2829                 break;
2830         case MSR_SYSCALL_MASK:
2831                 *data = svm->vmcb->save.sfmask;
2832                 break;
2833 #endif
2834         case MSR_IA32_SYSENTER_CS:
2835                 *data = svm->vmcb->save.sysenter_cs;
2836                 break;
2837         case MSR_IA32_SYSENTER_EIP:
2838                 *data = svm->sysenter_eip;
2839                 break;
2840         case MSR_IA32_SYSENTER_ESP:
2841                 *data = svm->sysenter_esp;
2842                 break;
2843         /*
2844          * Nobody will change the following 5 values in the VMCB so we can
2845          * safely return them on rdmsr. They will always be 0 until LBRV is
2846          * implemented.
2847          */
2848         case MSR_IA32_DEBUGCTLMSR:
2849                 *data = svm->vmcb->save.dbgctl;
2850                 break;
2851         case MSR_IA32_LASTBRANCHFROMIP:
2852                 *data = svm->vmcb->save.br_from;
2853                 break;
2854         case MSR_IA32_LASTBRANCHTOIP:
2855                 *data = svm->vmcb->save.br_to;
2856                 break;
2857         case MSR_IA32_LASTINTFROMIP:
2858                 *data = svm->vmcb->save.last_excp_from;
2859                 break;
2860         case MSR_IA32_LASTINTTOIP:
2861                 *data = svm->vmcb->save.last_excp_to;
2862                 break;
2863         case MSR_VM_HSAVE_PA:
2864                 *data = svm->nested.hsave_msr;
2865                 break;
2866         case MSR_VM_CR:
2867                 *data = svm->nested.vm_cr_msr;
2868                 break;
2869         case MSR_IA32_UCODE_REV:
2870                 *data = 0x01000065;
2871                 break;
2872         default:
2873                 return kvm_get_msr_common(vcpu, ecx, data);
2874         }
2875         return 0;
2876 }
2877
2878 static int rdmsr_interception(struct vcpu_svm *svm)
2879 {
2880         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2881         u64 data;
2882
2883         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2884                 trace_kvm_msr_read_ex(ecx);
2885                 kvm_inject_gp(&svm->vcpu, 0);
2886         } else {
2887                 trace_kvm_msr_read(ecx, data);
2888
2889                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2890                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2891                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2892                 skip_emulated_instruction(&svm->vcpu);
2893         }
2894         return 1;
2895 }
2896
2897 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2898 {
2899         struct vcpu_svm *svm = to_svm(vcpu);
2900         int svm_dis, chg_mask;
2901
2902         if (data & ~SVM_VM_CR_VALID_MASK)
2903                 return 1;
2904
2905         chg_mask = SVM_VM_CR_VALID_MASK;
2906
2907         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2908                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2909
2910         svm->nested.vm_cr_msr &= ~chg_mask;
2911         svm->nested.vm_cr_msr |= (data & chg_mask);
2912
2913         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2914
2915         /* check for svm_disable while efer.svme is set */
2916         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2917                 return 1;
2918
2919         return 0;
2920 }
2921
2922 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2923 {
2924         struct vcpu_svm *svm = to_svm(vcpu);
2925
2926         switch (ecx) {
2927         case MSR_IA32_TSC:
2928                 kvm_write_tsc(vcpu, data);
2929                 break;
2930         case MSR_STAR:
2931                 svm->vmcb->save.star = data;
2932                 break;
2933 #ifdef CONFIG_X86_64
2934         case MSR_LSTAR:
2935                 svm->vmcb->save.lstar = data;
2936                 break;
2937         case MSR_CSTAR:
2938                 svm->vmcb->save.cstar = data;
2939                 break;
2940         case MSR_KERNEL_GS_BASE:
2941                 svm->vmcb->save.kernel_gs_base = data;
2942                 break;
2943         case MSR_SYSCALL_MASK:
2944                 svm->vmcb->save.sfmask = data;
2945                 break;
2946 #endif
2947         case MSR_IA32_SYSENTER_CS:
2948                 svm->vmcb->save.sysenter_cs = data;
2949                 break;
2950         case MSR_IA32_SYSENTER_EIP:
2951                 svm->sysenter_eip = data;
2952                 svm->vmcb->save.sysenter_eip = data;
2953                 break;
2954         case MSR_IA32_SYSENTER_ESP:
2955                 svm->sysenter_esp = data;
2956                 svm->vmcb->save.sysenter_esp = data;
2957                 break;
2958         case MSR_IA32_DEBUGCTLMSR:
2959                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2960                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2961                                         __func__, data);
2962                         break;
2963                 }
2964                 if (data & DEBUGCTL_RESERVED_BITS)
2965                         return 1;
2966
2967                 svm->vmcb->save.dbgctl = data;
2968                 mark_dirty(svm->vmcb, VMCB_LBR);
2969                 if (data & (1ULL<<0))
2970                         svm_enable_lbrv(svm);
2971                 else
2972                         svm_disable_lbrv(svm);
2973                 break;
2974         case MSR_VM_HSAVE_PA:
2975                 svm->nested.hsave_msr = data;
2976                 break;
2977         case MSR_VM_CR:
2978                 return svm_set_vm_cr(vcpu, data);
2979         case MSR_VM_IGNNE:
2980                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2981                 break;
2982         default:
2983                 return kvm_set_msr_common(vcpu, ecx, data);
2984         }
2985         return 0;
2986 }
2987
2988 static int wrmsr_interception(struct vcpu_svm *svm)
2989 {
2990         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2991         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2992                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2993
2994
2995         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2996         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2997                 trace_kvm_msr_write_ex(ecx, data);
2998                 kvm_inject_gp(&svm->vcpu, 0);
2999         } else {
3000                 trace_kvm_msr_write(ecx, data);
3001                 skip_emulated_instruction(&svm->vcpu);
3002         }
3003         return 1;
3004 }
3005
3006 static int msr_interception(struct vcpu_svm *svm)
3007 {
3008         if (svm->vmcb->control.exit_info_1)
3009                 return wrmsr_interception(svm);
3010         else
3011                 return rdmsr_interception(svm);
3012 }
3013
3014 static int interrupt_window_interception(struct vcpu_svm *svm)
3015 {
3016         struct kvm_run *kvm_run = svm->vcpu.run;
3017
3018         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3019         svm_clear_vintr(svm);
3020         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3021         mark_dirty(svm->vmcb, VMCB_INTR);
3022         /*
3023          * If the user space waits to inject interrupts, exit as soon as
3024          * possible
3025          */
3026         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3027             kvm_run->request_interrupt_window &&
3028             !kvm_cpu_has_interrupt(&svm->vcpu)) {
3029                 ++svm->vcpu.stat.irq_window_exits;
3030                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3031                 return 0;
3032         }
3033
3034         return 1;
3035 }
3036
3037 static int pause_interception(struct vcpu_svm *svm)
3038 {
3039         kvm_vcpu_on_spin(&(svm->vcpu));
3040         return 1;
3041 }
3042
3043 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3044         [SVM_EXIT_READ_CR0]                     = cr_interception,
3045         [SVM_EXIT_READ_CR3]                     = cr_interception,
3046         [SVM_EXIT_READ_CR4]                     = cr_interception,
3047         [SVM_EXIT_READ_CR8]                     = cr_interception,
3048         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
3049         [SVM_EXIT_WRITE_CR0]                    = cr0_write_interception,
3050         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3051         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3052         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3053         [SVM_EXIT_READ_DR0]                     = dr_interception,
3054         [SVM_EXIT_READ_DR1]                     = dr_interception,
3055         [SVM_EXIT_READ_DR2]                     = dr_interception,
3056         [SVM_EXIT_READ_DR3]                     = dr_interception,
3057         [SVM_EXIT_READ_DR4]                     = dr_interception,
3058         [SVM_EXIT_READ_DR5]                     = dr_interception,
3059         [SVM_EXIT_READ_DR6]                     = dr_interception,
3060         [SVM_EXIT_READ_DR7]                     = dr_interception,
3061         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3062         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3063         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3064         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3065         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3066         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3067         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3068         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3069         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3070         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3071         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3072         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3073         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
3074         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3075         [SVM_EXIT_INTR]                         = intr_interception,
3076         [SVM_EXIT_NMI]                          = nmi_interception,
3077         [SVM_EXIT_SMI]                          = nop_on_interception,
3078         [SVM_EXIT_INIT]                         = nop_on_interception,
3079         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3080         [SVM_EXIT_CPUID]                        = cpuid_interception,
3081         [SVM_EXIT_IRET]                         = iret_interception,
3082         [SVM_EXIT_INVD]                         = emulate_on_interception,
3083         [SVM_EXIT_PAUSE]                        = pause_interception,
3084         [SVM_EXIT_HLT]                          = halt_interception,
3085         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3086         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3087         [SVM_EXIT_IOIO]                         = io_interception,
3088         [SVM_EXIT_MSR]                          = msr_interception,
3089         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3090         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3091         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3092         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3093         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3094         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3095         [SVM_EXIT_STGI]                         = stgi_interception,
3096         [SVM_EXIT_CLGI]                         = clgi_interception,
3097         [SVM_EXIT_SKINIT]                       = skinit_interception,
3098         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
3099         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
3100         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
3101         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3102         [SVM_EXIT_NPF]                          = pf_interception,
3103 };
3104
3105 void dump_vmcb(struct kvm_vcpu *vcpu)
3106 {
3107         struct vcpu_svm *svm = to_svm(vcpu);
3108         struct vmcb_control_area *control = &svm->vmcb->control;
3109         struct vmcb_save_area *save = &svm->vmcb->save;
3110
3111         pr_err("VMCB Control Area:\n");
3112         pr_err("cr_read:            %04x\n", control->intercept_cr & 0xffff);
3113         pr_err("cr_write:           %04x\n", control->intercept_cr >> 16);
3114         pr_err("dr_read:            %04x\n", control->intercept_dr & 0xffff);
3115         pr_err("dr_write:           %04x\n", control->intercept_dr >> 16);
3116         pr_err("exceptions:         %08x\n", control->intercept_exceptions);
3117         pr_err("intercepts:         %016llx\n", control->intercept);
3118         pr_err("pause filter count: %d\n", control->pause_filter_count);
3119         pr_err("iopm_base_pa:       %016llx\n", control->iopm_base_pa);
3120         pr_err("msrpm_base_pa:      %016llx\n", control->msrpm_base_pa);
3121         pr_err("tsc_offset:         %016llx\n", control->tsc_offset);
3122         pr_err("asid:               %d\n", control->asid);
3123         pr_err("tlb_ctl:            %d\n", control->tlb_ctl);
3124         pr_err("int_ctl:            %08x\n", control->int_ctl);
3125         pr_err("int_vector:         %08x\n", control->int_vector);
3126         pr_err("int_state:          %08x\n", control->int_state);
3127         pr_err("exit_code:          %08x\n", control->exit_code);
3128         pr_err("exit_info1:         %016llx\n", control->exit_info_1);
3129         pr_err("exit_info2:         %016llx\n", control->exit_info_2);
3130         pr_err("exit_int_info:      %08x\n", control->exit_int_info);
3131         pr_err("exit_int_info_err:  %08x\n", control->exit_int_info_err);
3132         pr_err("nested_ctl:         %lld\n", control->nested_ctl);
3133         pr_err("nested_cr3:         %016llx\n", control->nested_cr3);
3134         pr_err("event_inj:          %08x\n", control->event_inj);
3135         pr_err("event_inj_err:      %08x\n", control->event_inj_err);
3136         pr_err("lbr_ctl:            %lld\n", control->lbr_ctl);
3137         pr_err("next_rip:           %016llx\n", control->next_rip);
3138         pr_err("VMCB State Save Area:\n");
3139         pr_err("es:   s: %04x a: %04x l: %08x b: %016llx\n",
3140                 save->es.selector, save->es.attrib,
3141                 save->es.limit, save->es.base);
3142         pr_err("cs:   s: %04x a: %04x l: %08x b: %016llx\n",
3143                 save->cs.selector, save->cs.attrib,
3144                 save->cs.limit, save->cs.base);
3145         pr_err("ss:   s: %04x a: %04x l: %08x b: %016llx\n",
3146                 save->ss.selector, save->ss.attrib,
3147                 save->ss.limit, save->ss.base);
3148         pr_err("ds:   s: %04x a: %04x l: %08x b: %016llx\n",
3149                 save->ds.selector, save->ds.attrib,
3150                 save->ds.limit, save->ds.base);
3151         pr_err("fs:   s: %04x a: %04x l: %08x b: %016llx\n",
3152                 save->fs.selector, save->fs.attrib,
3153                 save->fs.limit, save->fs.base);
3154         pr_err("gs:   s: %04x a: %04x l: %08x b: %016llx\n",
3155                 save->gs.selector, save->gs.attrib,
3156                 save->gs.limit, save->gs.base);
3157         pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3158                 save->gdtr.selector, save->gdtr.attrib,
3159                 save->gdtr.limit, save->gdtr.base);
3160         pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3161                 save->ldtr.selector, save->ldtr.attrib,
3162                 save->ldtr.limit, save->ldtr.base);
3163         pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3164                 save->idtr.selector, save->idtr.attrib,
3165                 save->idtr.limit, save->idtr.base);
3166         pr_err("tr:   s: %04x a: %04x l: %08x b: %016llx\n",
3167                 save->tr.selector, save->tr.attrib,
3168                 save->tr.limit, save->tr.base);
3169         pr_err("cpl:            %d                efer:         %016llx\n",
3170                 save->cpl, save->efer);
3171         pr_err("cr0:            %016llx cr2:          %016llx\n",
3172                 save->cr0, save->cr2);
3173         pr_err("cr3:            %016llx cr4:          %016llx\n",
3174                 save->cr3, save->cr4);
3175         pr_err("dr6:            %016llx dr7:          %016llx\n",
3176                 save->dr6, save->dr7);
3177         pr_err("rip:            %016llx rflags:       %016llx\n",
3178                 save->rip, save->rflags);
3179         pr_err("rsp:            %016llx rax:          %016llx\n",
3180                 save->rsp, save->rax);
3181         pr_err("star:           %016llx lstar:        %016llx\n",
3182                 save->star, save->lstar);
3183         pr_err("cstar:          %016llx sfmask:       %016llx\n",
3184                 save->cstar, save->sfmask);
3185         pr_err("kernel_gs_base: %016llx sysenter_cs:  %016llx\n",
3186                 save->kernel_gs_base, save->sysenter_cs);
3187         pr_err("sysenter_esp:   %016llx sysenter_eip: %016llx\n",
3188                 save->sysenter_esp, save->sysenter_eip);
3189         pr_err("gpat:           %016llx dbgctl:       %016llx\n",
3190                 save->g_pat, save->dbgctl);
3191         pr_err("br_from:        %016llx br_to:        %016llx\n",
3192                 save->br_from, save->br_to);
3193         pr_err("excp_from:      %016llx excp_to:      %016llx\n",
3194                 save->last_excp_from, save->last_excp_to);
3195
3196 }
3197
3198 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3199 {
3200         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3201
3202         *info1 = control->exit_info_1;
3203         *info2 = control->exit_info_2;
3204 }
3205
3206 static int handle_exit(struct kvm_vcpu *vcpu)
3207 {
3208         struct vcpu_svm *svm = to_svm(vcpu);
3209         struct kvm_run *kvm_run = vcpu->run;
3210         u32 exit_code = svm->vmcb->control.exit_code;
3211
3212         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3213
3214         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3215                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3216         if (npt_enabled)
3217                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3218
3219         if (unlikely(svm->nested.exit_required)) {
3220                 nested_svm_vmexit(svm);
3221                 svm->nested.exit_required = false;
3222
3223                 return 1;
3224         }
3225
3226         if (is_guest_mode(vcpu)) {
3227                 int vmexit;
3228
3229                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3230                                         svm->vmcb->control.exit_info_1,
3231                                         svm->vmcb->control.exit_info_2,
3232                                         svm->vmcb->control.exit_int_info,
3233                                         svm->vmcb->control.exit_int_info_err);
3234
3235                 vmexit = nested_svm_exit_special(svm);
3236
3237                 if (vmexit == NESTED_EXIT_CONTINUE)
3238                         vmexit = nested_svm_exit_handled(svm);
3239
3240                 if (vmexit == NESTED_EXIT_DONE)
3241                         return 1;
3242         }
3243
3244         svm_complete_interrupts(svm);
3245
3246         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3247                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3248                 kvm_run->fail_entry.hardware_entry_failure_reason
3249                         = svm->vmcb->control.exit_code;
3250                 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3251                 dump_vmcb(vcpu);
3252                 return 0;
3253         }
3254
3255         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3256             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3257             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3258             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3259                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3260                        "exit_code 0x%x\n",
3261                        __func__, svm->vmcb->control.exit_int_info,
3262                        exit_code);
3263
3264         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3265             || !svm_exit_handlers[exit_code]) {
3266                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3267                 kvm_run->hw.hardware_exit_reason = exit_code;
3268                 return 0;
3269         }
3270
3271         return svm_exit_handlers[exit_code](svm);
3272 }
3273
3274 static void reload_tss(struct kvm_vcpu *vcpu)
3275 {
3276         int cpu = raw_smp_processor_id();
3277
3278         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3279         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3280         load_TR_desc();
3281 }
3282
3283 static void pre_svm_run(struct vcpu_svm *svm)
3284 {
3285         int cpu = raw_smp_processor_id();
3286
3287         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3288
3289         /* FIXME: handle wraparound of asid_generation */
3290         if (svm->asid_generation != sd->asid_generation)
3291                 new_asid(svm, sd);
3292 }
3293
3294 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3295 {
3296         struct vcpu_svm *svm = to_svm(vcpu);
3297
3298         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3299         vcpu->arch.hflags |= HF_NMI_MASK;
3300         set_intercept(svm, INTERCEPT_IRET);
3301         ++vcpu->stat.nmi_injections;
3302 }
3303
3304 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3305 {
3306         struct vmcb_control_area *control;
3307
3308         control = &svm->vmcb->control;
3309         control->int_vector = irq;
3310         control->int_ctl &= ~V_INTR_PRIO_MASK;
3311         control->int_ctl |= V_IRQ_MASK |
3312                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3313         mark_dirty(svm->vmcb, VMCB_INTR);
3314 }
3315
3316 static void svm_set_irq(struct kvm_vcpu *vcpu)
3317 {
3318         struct vcpu_svm *svm = to_svm(vcpu);
3319
3320         BUG_ON(!(gif_set(svm)));
3321
3322         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3323         ++vcpu->stat.irq_injections;
3324
3325         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3326                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3327 }
3328
3329 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3330 {
3331         struct vcpu_svm *svm = to_svm(vcpu);
3332
3333         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3334                 return;
3335
3336         if (irr == -1)
3337                 return;
3338
3339         if (tpr >= irr)
3340                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3341 }
3342
3343 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3344 {
3345         struct vcpu_svm *svm = to_svm(vcpu);
3346         struct vmcb *vmcb = svm->vmcb;
3347         int ret;
3348         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3349               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3350         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3351
3352         return ret;
3353 }
3354
3355 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3356 {
3357         struct vcpu_svm *svm = to_svm(vcpu);
3358
3359         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3360 }
3361
3362 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3363 {
3364         struct vcpu_svm *svm = to_svm(vcpu);
3365
3366         if (masked) {
3367                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3368                 set_intercept(svm, INTERCEPT_IRET);
3369         } else {
3370                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3371                 clr_intercept(svm, INTERCEPT_IRET);
3372         }
3373 }
3374
3375 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3376 {
3377         struct vcpu_svm *svm = to_svm(vcpu);
3378         struct vmcb *vmcb = svm->vmcb;
3379         int ret;
3380
3381         if (!gif_set(svm) ||
3382              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3383                 return 0;
3384
3385         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3386
3387         if (is_guest_mode(vcpu))
3388                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3389
3390         return ret;
3391 }
3392
3393 static void enable_irq_window(struct kvm_vcpu *vcpu)
3394 {
3395         struct vcpu_svm *svm = to_svm(vcpu);
3396
3397         /*
3398          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3399          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3400          * get that intercept, this function will be called again though and
3401          * we'll get the vintr intercept.
3402          */
3403         if (gif_set(svm) && nested_svm_intr(svm)) {
3404                 svm_set_vintr(svm);
3405                 svm_inject_irq(svm, 0x0);
3406         }
3407 }
3408
3409 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3410 {
3411         struct vcpu_svm *svm = to_svm(vcpu);
3412
3413         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3414             == HF_NMI_MASK)
3415                 return; /* IRET will cause a vm exit */
3416
3417         /*
3418          * Something prevents NMI from been injected. Single step over possible
3419          * problem (IRET or exception injection or interrupt shadow)
3420          */
3421         svm->nmi_singlestep = true;
3422         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3423         update_db_intercept(vcpu);
3424 }
3425
3426 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3427 {
3428         return 0;
3429 }
3430
3431 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3432 {
3433         struct vcpu_svm *svm = to_svm(vcpu);
3434
3435         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3436                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3437         else
3438                 svm->asid_generation--;
3439 }
3440
3441 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3442 {
3443 }
3444
3445 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3446 {
3447         struct vcpu_svm *svm = to_svm(vcpu);
3448
3449         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3450                 return;
3451
3452         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3453                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3454                 kvm_set_cr8(vcpu, cr8);
3455         }
3456 }
3457
3458 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3459 {
3460         struct vcpu_svm *svm = to_svm(vcpu);
3461         u64 cr8;
3462
3463         if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3464                 return;
3465
3466         cr8 = kvm_get_cr8(vcpu);
3467         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3468         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3469 }
3470
3471 static void svm_complete_interrupts(struct vcpu_svm *svm)
3472 {
3473         u8 vector;
3474         int type;
3475         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3476         unsigned int3_injected = svm->int3_injected;
3477
3478         svm->int3_injected = 0;
3479
3480         /*
3481          * If we've made progress since setting HF_IRET_MASK, we've
3482          * executed an IRET and can allow NMI injection.
3483          */
3484         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3485             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3486                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3487                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3488         }
3489
3490         svm->vcpu.arch.nmi_injected = false;
3491         kvm_clear_exception_queue(&svm->vcpu);
3492         kvm_clear_interrupt_queue(&svm->vcpu);
3493
3494         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3495                 return;
3496
3497         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3498
3499         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3500         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3501
3502         switch (type) {
3503         case SVM_EXITINTINFO_TYPE_NMI:
3504                 svm->vcpu.arch.nmi_injected = true;
3505                 break;
3506         case SVM_EXITINTINFO_TYPE_EXEPT:
3507                 /*
3508                  * In case of software exceptions, do not reinject the vector,
3509                  * but re-execute the instruction instead. Rewind RIP first
3510                  * if we emulated INT3 before.
3511                  */
3512                 if (kvm_exception_is_soft(vector)) {
3513                         if (vector == BP_VECTOR && int3_injected &&
3514                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3515                                 kvm_rip_write(&svm->vcpu,
3516                                               kvm_rip_read(&svm->vcpu) -
3517                                               int3_injected);
3518                         break;
3519                 }
3520                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3521                         u32 err = svm->vmcb->control.exit_int_info_err;
3522                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3523
3524                 } else
3525                         kvm_requeue_exception(&svm->vcpu, vector);
3526                 break;
3527         case SVM_EXITINTINFO_TYPE_INTR:
3528                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3529                 break;
3530         default:
3531                 break;
3532         }
3533 }
3534
3535 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3536 {
3537         struct vcpu_svm *svm = to_svm(vcpu);
3538         struct vmcb_control_area *control = &svm->vmcb->control;
3539
3540         control->exit_int_info = control->event_inj;
3541         control->exit_int_info_err = control->event_inj_err;
3542         control->event_inj = 0;
3543         svm_complete_interrupts(svm);
3544 }
3545
3546 #ifdef CONFIG_X86_64
3547 #define R "r"
3548 #else
3549 #define R "e"
3550 #endif
3551
3552 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3553 {
3554         struct vcpu_svm *svm = to_svm(vcpu);
3555
3556         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3557         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3558         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3559
3560         /*
3561          * A vmexit emulation is required before the vcpu can be executed
3562          * again.
3563          */
3564         if (unlikely(svm->nested.exit_required))
3565                 return;
3566
3567         pre_svm_run(svm);
3568
3569         sync_lapic_to_cr8(vcpu);
3570
3571         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3572
3573         clgi();
3574
3575         local_irq_enable();
3576
3577         asm volatile (
3578                 "push %%"R"bp; \n\t"
3579                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3580                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3581                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3582                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3583                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3584                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3585 #ifdef CONFIG_X86_64
3586                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3587                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3588                 "mov %c[r10](%[svm]), %%r10 \n\t"
3589                 "mov %c[r11](%[svm]), %%r11 \n\t"
3590                 "mov %c[r12](%[svm]), %%r12 \n\t"
3591                 "mov %c[r13](%[svm]), %%r13 \n\t"
3592                 "mov %c[r14](%[svm]), %%r14 \n\t"
3593                 "mov %c[r15](%[svm]), %%r15 \n\t"
3594 #endif
3595
3596                 /* Enter guest mode */
3597                 "push %%"R"ax \n\t"
3598                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3599                 __ex(SVM_VMLOAD) "\n\t"
3600                 __ex(SVM_VMRUN) "\n\t"
3601                 __ex(SVM_VMSAVE) "\n\t"
3602                 "pop %%"R"ax \n\t"
3603
3604                 /* Save guest registers, load host registers */
3605                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3606                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3607                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3608                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3609                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3610                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3611 #ifdef CONFIG_X86_64
3612                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3613                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3614                 "mov %%r10, %c[r10](%[svm]) \n\t"
3615                 "mov %%r11, %c[r11](%[svm]) \n\t"
3616                 "mov %%r12, %c[r12](%[svm]) \n\t"
3617                 "mov %%r13, %c[r13](%[svm]) \n\t"
3618                 "mov %%r14, %c[r14](%[svm]) \n\t"
3619                 "mov %%r15, %c[r15](%[svm]) \n\t"
3620 #endif
3621                 "pop %%"R"bp"
3622                 :
3623                 : [svm]"a"(svm),
3624                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3625                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3626                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3627                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3628                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3629                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3630                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3631 #ifdef CONFIG_X86_64
3632                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3633                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3634                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3635                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3636                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3637                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3638                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3639                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3640 #endif
3641                 : "cc", "memory"
3642                 , R"bx", R"cx", R"dx", R"si", R"di"
3643 #ifdef CONFIG_X86_64
3644                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3645 #endif
3646                 );
3647
3648 #ifdef CONFIG_X86_64
3649         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3650 #else
3651         loadsegment(fs, svm->host.fs);
3652 #endif
3653
3654         reload_tss(vcpu);
3655
3656         local_irq_disable();
3657
3658         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3659         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3660         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3661         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3662
3663         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3664                 kvm_before_handle_nmi(&svm->vcpu);
3665
3666         stgi();
3667
3668         /* Any pending NMI will happen here */
3669
3670         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3671                 kvm_after_handle_nmi(&svm->vcpu);
3672
3673         sync_cr8_to_lapic(vcpu);
3674
3675         svm->next_rip = 0;
3676
3677         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3678
3679         /* if exit due to PF check for async PF */
3680         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3681                 svm->apf_reason = kvm_read_and_reset_pf_reason();
3682
3683         if (npt_enabled) {
3684                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3685                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3686         }
3687
3688         /*
3689          * We need to handle MC intercepts here before the vcpu has a chance to
3690          * change the physical cpu
3691          */
3692         if (unlikely(svm->vmcb->control.exit_code ==
3693                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3694                 svm_handle_mce(svm);
3695
3696         mark_all_clean(svm->vmcb);
3697 }
3698
3699 #undef R
3700
3701 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3702 {
3703         struct vcpu_svm *svm = to_svm(vcpu);
3704
3705         svm->vmcb->save.cr3 = root;
3706         mark_dirty(svm->vmcb, VMCB_CR);
3707         svm_flush_tlb(vcpu);
3708 }
3709
3710 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3711 {
3712         struct vcpu_svm *svm = to_svm(vcpu);
3713
3714         svm->vmcb->control.nested_cr3 = root;
3715         mark_dirty(svm->vmcb, VMCB_NPT);
3716
3717         /* Also sync guest cr3 here in case we live migrate */
3718         svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3719         mark_dirty(svm->vmcb, VMCB_CR);
3720
3721         svm_flush_tlb(vcpu);
3722 }
3723
3724 static int is_disabled(void)
3725 {
3726         u64 vm_cr;
3727
3728         rdmsrl(MSR_VM_CR, vm_cr);
3729         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3730                 return 1;
3731
3732         return 0;
3733 }
3734
3735 static void
3736 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3737 {
3738         /*
3739          * Patch in the VMMCALL instruction:
3740          */
3741         hypercall[0] = 0x0f;
3742         hypercall[1] = 0x01;
3743         hypercall[2] = 0xd9;
3744 }
3745
3746 static void svm_check_processor_compat(void *rtn)
3747 {
3748         *(int *)rtn = 0;
3749 }
3750
3751 static bool svm_cpu_has_accelerated_tpr(void)
3752 {
3753         return false;
3754 }
3755
3756 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3757 {
3758         return 0;
3759 }
3760
3761 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3762 {
3763 }
3764
3765 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3766 {
3767         switch (func) {
3768         case 0x80000001:
3769                 if (nested)
3770                         entry->ecx |= (1 << 2); /* Set SVM bit */
3771                 break;
3772         case 0x8000000A:
3773                 entry->eax = 1; /* SVM revision 1 */
3774                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3775                                    ASID emulation to nested SVM */
3776                 entry->ecx = 0; /* Reserved */
3777                 entry->edx = 0; /* Per default do not support any
3778                                    additional features */
3779
3780                 /* Support next_rip if host supports it */
3781                 if (boot_cpu_has(X86_FEATURE_NRIPS))
3782                         entry->edx |= SVM_FEATURE_NRIP;
3783
3784                 /* Support NPT for the guest if enabled */
3785                 if (npt_enabled)
3786                         entry->edx |= SVM_FEATURE_NPT;
3787
3788                 break;
3789         }
3790 }
3791
3792 static const struct trace_print_flags svm_exit_reasons_str[] = {
3793         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3794         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3795         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3796         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3797         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3798         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3799         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3800         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3801         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3802         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3803         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3804         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3805         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3806         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3807         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3808         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3809         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3810         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3811         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3812         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3813         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3814         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3815         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3816         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3817         { SVM_EXIT_INTR,                        "interrupt" },
3818         { SVM_EXIT_NMI,                         "nmi" },
3819         { SVM_EXIT_SMI,                         "smi" },
3820         { SVM_EXIT_INIT,                        "init" },
3821         { SVM_EXIT_VINTR,                       "vintr" },
3822         { SVM_EXIT_CPUID,                       "cpuid" },
3823         { SVM_EXIT_INVD,                        "invd" },
3824         { SVM_EXIT_HLT,                         "hlt" },
3825         { SVM_EXIT_INVLPG,                      "invlpg" },
3826         { SVM_EXIT_INVLPGA,                     "invlpga" },
3827         { SVM_EXIT_IOIO,                        "io" },
3828         { SVM_EXIT_MSR,                         "msr" },
3829         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3830         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3831         { SVM_EXIT_VMRUN,                       "vmrun" },
3832         { SVM_EXIT_VMMCALL,                     "hypercall" },
3833         { SVM_EXIT_VMLOAD,                      "vmload" },
3834         { SVM_EXIT_VMSAVE,                      "vmsave" },
3835         { SVM_EXIT_STGI,                        "stgi" },
3836         { SVM_EXIT_CLGI,                        "clgi" },
3837         { SVM_EXIT_SKINIT,                      "skinit" },
3838         { SVM_EXIT_WBINVD,                      "wbinvd" },
3839         { SVM_EXIT_MONITOR,                     "monitor" },
3840         { SVM_EXIT_MWAIT,                       "mwait" },
3841         { SVM_EXIT_XSETBV,                      "xsetbv" },
3842         { SVM_EXIT_NPF,                         "npf" },
3843         { -1, NULL }
3844 };
3845
3846 static int svm_get_lpage_level(void)
3847 {
3848         return PT_PDPE_LEVEL;
3849 }
3850
3851 static bool svm_rdtscp_supported(void)
3852 {
3853         return false;
3854 }
3855
3856 static bool svm_has_wbinvd_exit(void)
3857 {
3858         return true;
3859 }
3860
3861 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3862 {
3863         struct vcpu_svm *svm = to_svm(vcpu);
3864
3865         set_exception_intercept(svm, NM_VECTOR);
3866         update_cr0_intercept(svm);
3867 }
3868
3869 static struct kvm_x86_ops svm_x86_ops = {
3870         .cpu_has_kvm_support = has_svm,
3871         .disabled_by_bios = is_disabled,
3872         .hardware_setup = svm_hardware_setup,
3873         .hardware_unsetup = svm_hardware_unsetup,
3874         .check_processor_compatibility = svm_check_processor_compat,
3875         .hardware_enable = svm_hardware_enable,
3876         .hardware_disable = svm_hardware_disable,
3877         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3878
3879         .vcpu_create = svm_create_vcpu,
3880         .vcpu_free = svm_free_vcpu,
3881         .vcpu_reset = svm_vcpu_reset,
3882
3883         .prepare_guest_switch = svm_prepare_guest_switch,
3884         .vcpu_load = svm_vcpu_load,
3885         .vcpu_put = svm_vcpu_put,
3886
3887         .set_guest_debug = svm_guest_debug,
3888         .get_msr = svm_get_msr,
3889         .set_msr = svm_set_msr,
3890         .get_segment_base = svm_get_segment_base,
3891         .get_segment = svm_get_segment,
3892         .set_segment = svm_set_segment,
3893         .get_cpl = svm_get_cpl,
3894         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3895         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3896         .decache_cr3 = svm_decache_cr3,
3897         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3898         .set_cr0 = svm_set_cr0,
3899         .set_cr3 = svm_set_cr3,
3900         .set_cr4 = svm_set_cr4,
3901         .set_efer = svm_set_efer,
3902         .get_idt = svm_get_idt,
3903         .set_idt = svm_set_idt,
3904         .get_gdt = svm_get_gdt,
3905         .set_gdt = svm_set_gdt,
3906         .set_dr7 = svm_set_dr7,
3907         .cache_reg = svm_cache_reg,
3908         .get_rflags = svm_get_rflags,
3909         .set_rflags = svm_set_rflags,
3910         .fpu_activate = svm_fpu_activate,
3911         .fpu_deactivate = svm_fpu_deactivate,
3912
3913         .tlb_flush = svm_flush_tlb,
3914
3915         .run = svm_vcpu_run,
3916         .handle_exit = handle_exit,
3917         .skip_emulated_instruction = skip_emulated_instruction,
3918         .set_interrupt_shadow = svm_set_interrupt_shadow,
3919         .get_interrupt_shadow = svm_get_interrupt_shadow,
3920         .patch_hypercall = svm_patch_hypercall,
3921         .set_irq = svm_set_irq,
3922         .set_nmi = svm_inject_nmi,
3923         .queue_exception = svm_queue_exception,
3924         .cancel_injection = svm_cancel_injection,
3925         .interrupt_allowed = svm_interrupt_allowed,
3926         .nmi_allowed = svm_nmi_allowed,
3927         .get_nmi_mask = svm_get_nmi_mask,
3928         .set_nmi_mask = svm_set_nmi_mask,
3929         .enable_nmi_window = enable_nmi_window,
3930         .enable_irq_window = enable_irq_window,
3931         .update_cr8_intercept = update_cr8_intercept,
3932
3933         .set_tss_addr = svm_set_tss_addr,
3934         .get_tdp_level = get_npt_level,
3935         .get_mt_mask = svm_get_mt_mask,
3936
3937         .get_exit_info = svm_get_exit_info,
3938         .exit_reasons_str = svm_exit_reasons_str,
3939
3940         .get_lpage_level = svm_get_lpage_level,
3941
3942         .cpuid_update = svm_cpuid_update,
3943
3944         .rdtscp_supported = svm_rdtscp_supported,
3945
3946         .set_supported_cpuid = svm_set_supported_cpuid,
3947
3948         .has_wbinvd_exit = svm_has_wbinvd_exit,
3949
3950         .write_tsc_offset = svm_write_tsc_offset,
3951         .adjust_tsc_offset = svm_adjust_tsc_offset,
3952
3953         .set_tdp_cr3 = set_tdp_cr3,
3954 };
3955
3956 static int __init svm_init(void)
3957 {
3958         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3959                         __alignof__(struct vcpu_svm), THIS_MODULE);
3960 }
3961
3962 static void __exit svm_exit(void)
3963 {
3964         kvm_exit();
3965 }
3966
3967 module_init(svm_init)
3968 module_exit(svm_exit)