2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
37 #define PT_MAX_FULL_LEVELS 4
38 #define CMPXCHG cmpxchg
40 #define CMPXCHG cmpxchg64
41 #define PT_MAX_FULL_LEVELS 2
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
53 #define PT_MAX_FULL_LEVELS 2
54 #define CMPXCHG cmpxchg
56 #error Invalid PTTYPE value
59 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
63 * The guest_walker structure emulates the behavior of the hardware page
68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
70 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
77 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
79 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
82 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
83 gfn_t table_gfn, unsigned index,
84 pt_element_t orig_pte, pt_element_t new_pte)
90 page = gfn_to_page(kvm, table_gfn);
92 table = kmap_atomic(page, KM_USER0);
93 ret = CMPXCHG(&table[index], orig_pte, new_pte);
94 kunmap_atomic(table, KM_USER0);
96 kvm_release_page_dirty(page);
98 return (ret != orig_pte);
101 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
105 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
108 access &= ~(gpte >> PT64_NX_SHIFT);
114 * Fetch a guest pte for a guest virtual address
116 static int FNAME(walk_addr)(struct guest_walker *walker,
117 struct kvm_vcpu *vcpu, gva_t addr,
118 int write_fault, int user_fault, int fetch_fault)
122 unsigned index, pt_access, uninitialized_var(pte_access);
124 bool eperm, present, rsvd_fault;
126 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
130 eperm = rsvd_fault = false;
131 walker->level = vcpu->arch.mmu.root_level;
132 pte = vcpu->arch.cr3;
134 if (!is_long_mode(vcpu)) {
135 pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
136 trace_kvm_mmu_paging_element(pte, walker->level);
137 if (!is_present_gpte(pte)) {
144 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
145 (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
150 index = PT_INDEX(addr, walker->level);
152 table_gfn = gpte_to_gfn(pte);
153 pte_gpa = gfn_to_gpa(table_gfn);
154 pte_gpa += index * sizeof(pt_element_t);
155 walker->table_gfn[walker->level - 1] = table_gfn;
156 walker->pte_gpa[walker->level - 1] = pte_gpa;
158 if (kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte))) {
163 trace_kvm_mmu_paging_element(pte, walker->level);
165 if (!is_present_gpte(pte)) {
170 if (is_rsvd_bits_set(vcpu, pte, walker->level)) {
175 if (write_fault && !is_writable_pte(pte))
176 if (user_fault || is_write_protection(vcpu))
179 if (user_fault && !(pte & PT_USER_MASK))
183 if (fetch_fault && (pte & PT64_NX_MASK))
187 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
188 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
190 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
191 index, pte, pte|PT_ACCESSED_MASK))
193 mark_page_dirty(vcpu->kvm, table_gfn);
194 pte |= PT_ACCESSED_MASK;
197 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
199 walker->ptes[walker->level - 1] = pte;
201 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
202 ((walker->level == PT_DIRECTORY_LEVEL) &&
204 (PTTYPE == 64 || is_pse(vcpu))) ||
205 ((walker->level == PT_PDPE_LEVEL) &&
207 is_long_mode(vcpu))) {
208 int lvl = walker->level;
210 walker->gfn = gpte_to_gfn_lvl(pte, lvl);
211 walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
215 walker->level == PT_DIRECTORY_LEVEL &&
217 walker->gfn += pse36_gfn_delta(pte);
222 pt_access = pte_access;
226 if (!present || eperm || rsvd_fault)
229 if (write_fault && !is_dirty_gpte(pte)) {
232 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
233 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
237 mark_page_dirty(vcpu->kvm, table_gfn);
238 pte |= PT_DIRTY_MASK;
239 walker->ptes[walker->level - 1] = pte;
242 walker->pt_access = pt_access;
243 walker->pte_access = pte_access;
244 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
245 __func__, (u64)pte, pte_access, pt_access);
249 walker->error_code = 0;
251 walker->error_code |= PFERR_PRESENT_MASK;
253 walker->error_code |= PFERR_WRITE_MASK;
255 walker->error_code |= PFERR_USER_MASK;
256 if (fetch_fault && is_nx(vcpu))
257 walker->error_code |= PFERR_FETCH_MASK;
259 walker->error_code |= PFERR_RSVD_MASK;
260 trace_kvm_mmu_walker_error(walker->error_code);
264 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
265 u64 *spte, const void *pte)
272 gpte = *(const pt_element_t *)pte;
273 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
274 if (!is_present_gpte(gpte)) {
276 new_spte = shadow_trap_nonpresent_pte;
278 new_spte = shadow_notrap_nonpresent_pte;
279 __set_spte(spte, new_spte);
283 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
284 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
285 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
287 pfn = vcpu->arch.update_pte.pfn;
288 if (is_error_pfn(pfn))
290 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
294 * we call mmu_set_spte() with reset_host_protection = true beacuse that
295 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
297 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
298 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
299 gpte_to_gfn(gpte), pfn, true, true);
303 * Fetch a shadow pte for a specific level in the paging hierarchy.
305 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
306 struct guest_walker *gw,
307 int user_fault, int write_fault, int hlevel,
308 int *ptwrite, pfn_t pfn)
310 unsigned access = gw->pt_access;
311 struct kvm_mmu_page *sp;
317 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
318 unsigned direct_access;
319 pt_element_t curr_pte;
320 struct kvm_shadow_walk_iterator iterator;
322 if (!is_present_gpte(gw->ptes[gw->level - 1]))
325 direct_access = gw->pt_access & gw->pte_access;
327 direct_access &= ~ACC_WRITE_MASK;
329 for_each_shadow_entry(vcpu, addr, iterator) {
330 level = iterator.level;
331 sptep = iterator.sptep;
332 if (iterator.level == hlevel) {
333 mmu_set_spte(vcpu, sptep, access,
334 gw->pte_access & access,
335 user_fault, write_fault,
336 dirty, ptwrite, level,
337 gw->gfn, pfn, false, true);
341 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)
342 && level == gw->level)
343 validate_direct_spte(vcpu, sptep, direct_access);
345 drop_large_spte(vcpu, sptep);
347 if (is_shadow_present_pte(*sptep))
350 if (level <= gw->level) {
352 access = direct_access;
355 * It is a large guest pages backed by small host pages,
356 * So we set @direct(@sp->role.direct)=1, and set
357 * @table_gfn(@sp->gfn)=the base page frame for linear
360 table_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
361 access &= gw->pte_access;
364 table_gfn = gw->table_gfn[level - 2];
366 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
367 direct, access, sptep);
369 r = kvm_read_guest_atomic(vcpu->kvm,
370 gw->pte_gpa[level - 2],
371 &curr_pte, sizeof(curr_pte));
372 if (r || curr_pte != gw->ptes[level - 2]) {
373 kvm_mmu_put_page(sp, sptep);
374 kvm_release_pfn_clean(pfn);
380 link_shadow_page(sptep, sp);
387 * Page fault handler. There are several causes for a page fault:
388 * - there is no shadow pte for the guest pte
389 * - write access through a shadow pte marked read only so that we can set
391 * - write access to a shadow pte marked read only so we can update the page
392 * dirty bitmap, when userspace requests it
393 * - mmio access; in this case we will never install a present shadow pte
394 * - normal guest page fault due to the guest pte marked not present, not
395 * writable, or not executable
397 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
398 * a negative value on error.
400 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
403 int write_fault = error_code & PFERR_WRITE_MASK;
404 int user_fault = error_code & PFERR_USER_MASK;
405 int fetch_fault = error_code & PFERR_FETCH_MASK;
406 struct guest_walker walker;
411 int level = PT_PAGE_TABLE_LEVEL;
412 unsigned long mmu_seq;
414 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
415 kvm_mmu_audit(vcpu, "pre page fault");
417 r = mmu_topup_memory_caches(vcpu);
422 * Look up the guest pte for the faulting address.
424 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
428 * The page is not mapped by the guest. Let the guest handle it.
431 pgprintk("%s: guest page fault\n", __func__);
432 inject_page_fault(vcpu, addr, walker.error_code);
433 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
437 if (walker.level >= PT_DIRECTORY_LEVEL) {
438 level = min(walker.level, mapping_level(vcpu, walker.gfn));
439 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
442 mmu_seq = vcpu->kvm->mmu_notifier_seq;
444 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
447 if (is_error_pfn(pfn))
448 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
450 spin_lock(&vcpu->kvm->mmu_lock);
451 if (mmu_notifier_retry(vcpu, mmu_seq))
453 kvm_mmu_free_some_pages(vcpu);
454 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
455 level, &write_pt, pfn);
457 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
458 sptep, *sptep, write_pt);
461 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
463 ++vcpu->stat.pf_fixed;
464 kvm_mmu_audit(vcpu, "post page fault (fixed)");
465 spin_unlock(&vcpu->kvm->mmu_lock);
470 spin_unlock(&vcpu->kvm->mmu_lock);
471 kvm_release_pfn_clean(pfn);
475 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
477 struct kvm_shadow_walk_iterator iterator;
478 struct kvm_mmu_page *sp;
484 spin_lock(&vcpu->kvm->mmu_lock);
486 for_each_shadow_entry(vcpu, gva, iterator) {
487 level = iterator.level;
488 sptep = iterator.sptep;
490 sp = page_header(__pa(sptep));
491 if (is_last_spte(*sptep, level)) {
498 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
499 offset = sp->role.quadrant << shift;
501 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
502 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
504 if (is_shadow_present_pte(*sptep)) {
505 if (is_large_pte(*sptep))
506 --vcpu->kvm->stat.lpages;
507 drop_spte(vcpu->kvm, sptep,
508 shadow_trap_nonpresent_pte);
511 __set_spte(sptep, shadow_trap_nonpresent_pte);
515 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
520 kvm_flush_remote_tlbs(vcpu->kvm);
522 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
524 spin_unlock(&vcpu->kvm->mmu_lock);
529 if (mmu_topup_memory_caches(vcpu))
531 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
534 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
537 struct guest_walker walker;
538 gpa_t gpa = UNMAPPED_GVA;
541 r = FNAME(walk_addr)(&walker, vcpu, vaddr,
542 !!(access & PFERR_WRITE_MASK),
543 !!(access & PFERR_USER_MASK),
544 !!(access & PFERR_FETCH_MASK));
547 gpa = gfn_to_gpa(walker.gfn);
548 gpa |= vaddr & ~PAGE_MASK;
550 *error = walker.error_code;
555 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
556 struct kvm_mmu_page *sp)
559 pt_element_t pt[256 / sizeof(pt_element_t)];
563 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
564 nonpaging_prefetch_page(vcpu, sp);
568 pte_gpa = gfn_to_gpa(sp->gfn);
570 offset = sp->role.quadrant << PT64_LEVEL_BITS;
571 pte_gpa += offset * sizeof(pt_element_t);
574 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
575 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
576 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
577 for (j = 0; j < ARRAY_SIZE(pt); ++j)
578 if (r || is_present_gpte(pt[j]))
579 sp->spt[i+j] = shadow_trap_nonpresent_pte;
581 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
586 * Using the cached information from sp->gfns is safe because:
587 * - The spte has a reference to the struct page, so the pfn for a given gfn
588 * can't change unless all sptes pointing to it are nuked first.
590 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
593 int i, offset, nr_present;
594 bool reset_host_protection;
597 offset = nr_present = 0;
599 /* direct kvm_mmu_page can not be unsync. */
600 BUG_ON(sp->role.direct);
603 offset = sp->role.quadrant << PT64_LEVEL_BITS;
605 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
607 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
613 if (!is_shadow_present_pte(sp->spt[i]))
616 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
618 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
619 sizeof(pt_element_t)))
622 gfn = gpte_to_gfn(gpte);
623 if (gfn != sp->gfns[i] ||
624 !is_present_gpte(gpte) || !(gpte & PT_ACCESSED_MASK)) {
627 if (is_present_gpte(gpte) || !clear_unsync)
628 nonpresent = shadow_trap_nonpresent_pte;
630 nonpresent = shadow_notrap_nonpresent_pte;
631 drop_spte(vcpu->kvm, &sp->spt[i], nonpresent);
636 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
637 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
638 pte_access &= ~ACC_WRITE_MASK;
639 reset_host_protection = 0;
641 reset_host_protection = 1;
643 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
644 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
645 spte_to_pfn(sp->spt[i]), true, false,
646 reset_host_protection);
655 #undef PT_BASE_ADDR_MASK
658 #undef PT_LVL_ADDR_MASK
659 #undef PT_LVL_OFFSET_MASK
661 #undef PT_MAX_FULL_LEVELS
663 #undef gpte_to_gfn_lvl