Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
[linux-2.6.git] / arch / x86 / kvm / mmu.c
1 /*
2  * Kernel-based Virtual Machine driver for Linux
3  *
4  * This module enables machines with Intel VT-x extensions to run virtual
5  * machines without emulation or binary translation.
6  *
7  * MMU support
8  *
9  * Copyright (C) 2006 Qumranet, Inc.
10  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11  *
12  * Authors:
13  *   Yaniv Kamay  <yaniv@qumranet.com>
14  *   Avi Kivity   <avi@qumranet.com>
15  *
16  * This work is licensed under the terms of the GNU GPL, version 2.  See
17  * the COPYING file in the top-level directory.
18  *
19  */
20
21 #include "irq.h"
22 #include "mmu.h"
23 #include "x86.h"
24 #include "kvm_cache_regs.h"
25
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
29 #include <linux/mm.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
38
39 #include <asm/page.h>
40 #include <asm/cmpxchg.h>
41 #include <asm/io.h>
42 #include <asm/vmx.h>
43
44 /*
45  * When setting this variable to true it enables Two-Dimensional-Paging
46  * where the hardware walks 2 page tables:
47  * 1. the guest-virtual to guest-physical
48  * 2. while doing 1. it walks guest-physical to host-physical
49  * If the hardware supports that we don't need to do shadow paging.
50  */
51 bool tdp_enabled = false;
52
53 enum {
54         AUDIT_PRE_PAGE_FAULT,
55         AUDIT_POST_PAGE_FAULT,
56         AUDIT_PRE_PTE_WRITE,
57         AUDIT_POST_PTE_WRITE,
58         AUDIT_PRE_SYNC,
59         AUDIT_POST_SYNC
60 };
61
62 char *audit_point_name[] = {
63         "pre page fault",
64         "post page fault",
65         "pre pte write",
66         "post pte write",
67         "pre sync",
68         "post sync"
69 };
70
71 #undef MMU_DEBUG
72
73 #ifdef MMU_DEBUG
74
75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
77
78 #else
79
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
82
83 #endif
84
85 #ifdef MMU_DEBUG
86 static int dbg = 0;
87 module_param(dbg, bool, 0644);
88 #endif
89
90 static int oos_shadow = 1;
91 module_param(oos_shadow, bool, 0644);
92
93 #ifndef MMU_DEBUG
94 #define ASSERT(x) do { } while (0)
95 #else
96 #define ASSERT(x)                                                       \
97         if (!(x)) {                                                     \
98                 printk(KERN_WARNING "assertion failed %s:%d: %s\n",     \
99                        __FILE__, __LINE__, #x);                         \
100         }
101 #endif
102
103 #define PTE_PREFETCH_NUM                8
104
105 #define PT_FIRST_AVAIL_BITS_SHIFT 9
106 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
107
108 #define PT64_LEVEL_BITS 9
109
110 #define PT64_LEVEL_SHIFT(level) \
111                 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
112
113 #define PT64_INDEX(address, level)\
114         (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
115
116
117 #define PT32_LEVEL_BITS 10
118
119 #define PT32_LEVEL_SHIFT(level) \
120                 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121
122 #define PT32_LVL_OFFSET_MASK(level) \
123         (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
124                                                 * PT32_LEVEL_BITS))) - 1))
125
126 #define PT32_INDEX(address, level)\
127         (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
128
129
130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
131 #define PT64_DIR_BASE_ADDR_MASK \
132         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
133 #define PT64_LVL_ADDR_MASK(level) \
134         (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
135                                                 * PT64_LEVEL_BITS))) - 1))
136 #define PT64_LVL_OFFSET_MASK(level) \
137         (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
138                                                 * PT64_LEVEL_BITS))) - 1))
139
140 #define PT32_BASE_ADDR_MASK PAGE_MASK
141 #define PT32_DIR_BASE_ADDR_MASK \
142         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
143 #define PT32_LVL_ADDR_MASK(level) \
144         (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
145                                             * PT32_LEVEL_BITS))) - 1))
146
147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
148                         | PT64_NX_MASK)
149
150 #define PTE_LIST_EXT 4
151
152 #define ACC_EXEC_MASK    1
153 #define ACC_WRITE_MASK   PT_WRITABLE_MASK
154 #define ACC_USER_MASK    PT_USER_MASK
155 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
156
157 #include <trace/events/kvm.h>
158
159 #define CREATE_TRACE_POINTS
160 #include "mmutrace.h"
161
162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
163
164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
165
166 struct pte_list_desc {
167         u64 *sptes[PTE_LIST_EXT];
168         struct pte_list_desc *more;
169 };
170
171 struct kvm_shadow_walk_iterator {
172         u64 addr;
173         hpa_t shadow_addr;
174         u64 *sptep;
175         int level;
176         unsigned index;
177 };
178
179 #define for_each_shadow_entry(_vcpu, _addr, _walker)    \
180         for (shadow_walk_init(&(_walker), _vcpu, _addr);        \
181              shadow_walk_okay(&(_walker));                      \
182              shadow_walk_next(&(_walker)))
183
184 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte)     \
185         for (shadow_walk_init(&(_walker), _vcpu, _addr);                \
186              shadow_walk_okay(&(_walker)) &&                            \
187                 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; });  \
188              __shadow_walk_next(&(_walker), spte))
189
190 static struct kmem_cache *pte_list_desc_cache;
191 static struct kmem_cache *mmu_page_header_cache;
192 static struct percpu_counter kvm_total_used_mmu_pages;
193
194 static u64 __read_mostly shadow_nx_mask;
195 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
196 static u64 __read_mostly shadow_user_mask;
197 static u64 __read_mostly shadow_accessed_mask;
198 static u64 __read_mostly shadow_dirty_mask;
199 static u64 __read_mostly shadow_mmio_mask;
200
201 static void mmu_spte_set(u64 *sptep, u64 spte);
202
203 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
204 {
205         shadow_mmio_mask = mmio_mask;
206 }
207 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
208
209 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
210 {
211         access &= ACC_WRITE_MASK | ACC_USER_MASK;
212
213         trace_mark_mmio_spte(sptep, gfn, access);
214         mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
215 }
216
217 static bool is_mmio_spte(u64 spte)
218 {
219         return (spte & shadow_mmio_mask) == shadow_mmio_mask;
220 }
221
222 static gfn_t get_mmio_spte_gfn(u64 spte)
223 {
224         return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
225 }
226
227 static unsigned get_mmio_spte_access(u64 spte)
228 {
229         return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
230 }
231
232 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
233 {
234         if (unlikely(is_noslot_pfn(pfn))) {
235                 mark_mmio_spte(sptep, gfn, access);
236                 return true;
237         }
238
239         return false;
240 }
241
242 static inline u64 rsvd_bits(int s, int e)
243 {
244         return ((1ULL << (e - s + 1)) - 1) << s;
245 }
246
247 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
248                 u64 dirty_mask, u64 nx_mask, u64 x_mask)
249 {
250         shadow_user_mask = user_mask;
251         shadow_accessed_mask = accessed_mask;
252         shadow_dirty_mask = dirty_mask;
253         shadow_nx_mask = nx_mask;
254         shadow_x_mask = x_mask;
255 }
256 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
257
258 static int is_cpuid_PSE36(void)
259 {
260         return 1;
261 }
262
263 static int is_nx(struct kvm_vcpu *vcpu)
264 {
265         return vcpu->arch.efer & EFER_NX;
266 }
267
268 static int is_shadow_present_pte(u64 pte)
269 {
270         return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
271 }
272
273 static int is_large_pte(u64 pte)
274 {
275         return pte & PT_PAGE_SIZE_MASK;
276 }
277
278 static int is_dirty_gpte(unsigned long pte)
279 {
280         return pte & PT_DIRTY_MASK;
281 }
282
283 static int is_rmap_spte(u64 pte)
284 {
285         return is_shadow_present_pte(pte);
286 }
287
288 static int is_last_spte(u64 pte, int level)
289 {
290         if (level == PT_PAGE_TABLE_LEVEL)
291                 return 1;
292         if (is_large_pte(pte))
293                 return 1;
294         return 0;
295 }
296
297 static pfn_t spte_to_pfn(u64 pte)
298 {
299         return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
300 }
301
302 static gfn_t pse36_gfn_delta(u32 gpte)
303 {
304         int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
305
306         return (gpte & PT32_DIR_PSE36_MASK) << shift;
307 }
308
309 #ifdef CONFIG_X86_64
310 static void __set_spte(u64 *sptep, u64 spte)
311 {
312         *sptep = spte;
313 }
314
315 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
316 {
317         *sptep = spte;
318 }
319
320 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
321 {
322         return xchg(sptep, spte);
323 }
324
325 static u64 __get_spte_lockless(u64 *sptep)
326 {
327         return ACCESS_ONCE(*sptep);
328 }
329
330 static bool __check_direct_spte_mmio_pf(u64 spte)
331 {
332         /* It is valid if the spte is zapped. */
333         return spte == 0ull;
334 }
335 #else
336 union split_spte {
337         struct {
338                 u32 spte_low;
339                 u32 spte_high;
340         };
341         u64 spte;
342 };
343
344 static void count_spte_clear(u64 *sptep, u64 spte)
345 {
346         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
347
348         if (is_shadow_present_pte(spte))
349                 return;
350
351         /* Ensure the spte is completely set before we increase the count */
352         smp_wmb();
353         sp->clear_spte_count++;
354 }
355
356 static void __set_spte(u64 *sptep, u64 spte)
357 {
358         union split_spte *ssptep, sspte;
359
360         ssptep = (union split_spte *)sptep;
361         sspte = (union split_spte)spte;
362
363         ssptep->spte_high = sspte.spte_high;
364
365         /*
366          * If we map the spte from nonpresent to present, We should store
367          * the high bits firstly, then set present bit, so cpu can not
368          * fetch this spte while we are setting the spte.
369          */
370         smp_wmb();
371
372         ssptep->spte_low = sspte.spte_low;
373 }
374
375 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
376 {
377         union split_spte *ssptep, sspte;
378
379         ssptep = (union split_spte *)sptep;
380         sspte = (union split_spte)spte;
381
382         ssptep->spte_low = sspte.spte_low;
383
384         /*
385          * If we map the spte from present to nonpresent, we should clear
386          * present bit firstly to avoid vcpu fetch the old high bits.
387          */
388         smp_wmb();
389
390         ssptep->spte_high = sspte.spte_high;
391         count_spte_clear(sptep, spte);
392 }
393
394 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
395 {
396         union split_spte *ssptep, sspte, orig;
397
398         ssptep = (union split_spte *)sptep;
399         sspte = (union split_spte)spte;
400
401         /* xchg acts as a barrier before the setting of the high bits */
402         orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
403         orig.spte_high = ssptep->spte_high = sspte.spte_high;
404         count_spte_clear(sptep, spte);
405
406         return orig.spte;
407 }
408
409 /*
410  * The idea using the light way get the spte on x86_32 guest is from
411  * gup_get_pte(arch/x86/mm/gup.c).
412  * The difference is we can not catch the spte tlb flush if we leave
413  * guest mode, so we emulate it by increase clear_spte_count when spte
414  * is cleared.
415  */
416 static u64 __get_spte_lockless(u64 *sptep)
417 {
418         struct kvm_mmu_page *sp =  page_header(__pa(sptep));
419         union split_spte spte, *orig = (union split_spte *)sptep;
420         int count;
421
422 retry:
423         count = sp->clear_spte_count;
424         smp_rmb();
425
426         spte.spte_low = orig->spte_low;
427         smp_rmb();
428
429         spte.spte_high = orig->spte_high;
430         smp_rmb();
431
432         if (unlikely(spte.spte_low != orig->spte_low ||
433               count != sp->clear_spte_count))
434                 goto retry;
435
436         return spte.spte;
437 }
438
439 static bool __check_direct_spte_mmio_pf(u64 spte)
440 {
441         union split_spte sspte = (union split_spte)spte;
442         u32 high_mmio_mask = shadow_mmio_mask >> 32;
443
444         /* It is valid if the spte is zapped. */
445         if (spte == 0ull)
446                 return true;
447
448         /* It is valid if the spte is being zapped. */
449         if (sspte.spte_low == 0ull &&
450             (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
451                 return true;
452
453         return false;
454 }
455 #endif
456
457 static bool spte_has_volatile_bits(u64 spte)
458 {
459         if (!shadow_accessed_mask)
460                 return false;
461
462         if (!is_shadow_present_pte(spte))
463                 return false;
464
465         if ((spte & shadow_accessed_mask) &&
466               (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
467                 return false;
468
469         return true;
470 }
471
472 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
473 {
474         return (old_spte & bit_mask) && !(new_spte & bit_mask);
475 }
476
477 /* Rules for using mmu_spte_set:
478  * Set the sptep from nonpresent to present.
479  * Note: the sptep being assigned *must* be either not present
480  * or in a state where the hardware will not attempt to update
481  * the spte.
482  */
483 static void mmu_spte_set(u64 *sptep, u64 new_spte)
484 {
485         WARN_ON(is_shadow_present_pte(*sptep));
486         __set_spte(sptep, new_spte);
487 }
488
489 /* Rules for using mmu_spte_update:
490  * Update the state bits, it means the mapped pfn is not changged.
491  */
492 static void mmu_spte_update(u64 *sptep, u64 new_spte)
493 {
494         u64 mask, old_spte = *sptep;
495
496         WARN_ON(!is_rmap_spte(new_spte));
497
498         if (!is_shadow_present_pte(old_spte))
499                 return mmu_spte_set(sptep, new_spte);
500
501         new_spte |= old_spte & shadow_dirty_mask;
502
503         mask = shadow_accessed_mask;
504         if (is_writable_pte(old_spte))
505                 mask |= shadow_dirty_mask;
506
507         if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
508                 __update_clear_spte_fast(sptep, new_spte);
509         else
510                 old_spte = __update_clear_spte_slow(sptep, new_spte);
511
512         if (!shadow_accessed_mask)
513                 return;
514
515         if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
516                 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
517         if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
518                 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
519 }
520
521 /*
522  * Rules for using mmu_spte_clear_track_bits:
523  * It sets the sptep from present to nonpresent, and track the
524  * state bits, it is used to clear the last level sptep.
525  */
526 static int mmu_spte_clear_track_bits(u64 *sptep)
527 {
528         pfn_t pfn;
529         u64 old_spte = *sptep;
530
531         if (!spte_has_volatile_bits(old_spte))
532                 __update_clear_spte_fast(sptep, 0ull);
533         else
534                 old_spte = __update_clear_spte_slow(sptep, 0ull);
535
536         if (!is_rmap_spte(old_spte))
537                 return 0;
538
539         pfn = spte_to_pfn(old_spte);
540         if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
541                 kvm_set_pfn_accessed(pfn);
542         if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
543                 kvm_set_pfn_dirty(pfn);
544         return 1;
545 }
546
547 /*
548  * Rules for using mmu_spte_clear_no_track:
549  * Directly clear spte without caring the state bits of sptep,
550  * it is used to set the upper level spte.
551  */
552 static void mmu_spte_clear_no_track(u64 *sptep)
553 {
554         __update_clear_spte_fast(sptep, 0ull);
555 }
556
557 static u64 mmu_spte_get_lockless(u64 *sptep)
558 {
559         return __get_spte_lockless(sptep);
560 }
561
562 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
563 {
564         rcu_read_lock();
565         atomic_inc(&vcpu->kvm->arch.reader_counter);
566
567         /* Increase the counter before walking shadow page table */
568         smp_mb__after_atomic_inc();
569 }
570
571 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
572 {
573         /* Decrease the counter after walking shadow page table finished */
574         smp_mb__before_atomic_dec();
575         atomic_dec(&vcpu->kvm->arch.reader_counter);
576         rcu_read_unlock();
577 }
578
579 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
580                                   struct kmem_cache *base_cache, int min)
581 {
582         void *obj;
583
584         if (cache->nobjs >= min)
585                 return 0;
586         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
587                 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
588                 if (!obj)
589                         return -ENOMEM;
590                 cache->objects[cache->nobjs++] = obj;
591         }
592         return 0;
593 }
594
595 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
596                                   struct kmem_cache *cache)
597 {
598         while (mc->nobjs)
599                 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
600 }
601
602 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
603                                        int min)
604 {
605         void *page;
606
607         if (cache->nobjs >= min)
608                 return 0;
609         while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
610                 page = (void *)__get_free_page(GFP_KERNEL);
611                 if (!page)
612                         return -ENOMEM;
613                 cache->objects[cache->nobjs++] = page;
614         }
615         return 0;
616 }
617
618 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
619 {
620         while (mc->nobjs)
621                 free_page((unsigned long)mc->objects[--mc->nobjs]);
622 }
623
624 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
625 {
626         int r;
627
628         r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
629                                    pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
630         if (r)
631                 goto out;
632         r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
633         if (r)
634                 goto out;
635         r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
636                                    mmu_page_header_cache, 4);
637 out:
638         return r;
639 }
640
641 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
642 {
643         mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
644                                 pte_list_desc_cache);
645         mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
646         mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
647                                 mmu_page_header_cache);
648 }
649
650 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
651                                     size_t size)
652 {
653         void *p;
654
655         BUG_ON(!mc->nobjs);
656         p = mc->objects[--mc->nobjs];
657         return p;
658 }
659
660 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
661 {
662         return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
663                                       sizeof(struct pte_list_desc));
664 }
665
666 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
667 {
668         kmem_cache_free(pte_list_desc_cache, pte_list_desc);
669 }
670
671 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
672 {
673         if (!sp->role.direct)
674                 return sp->gfns[index];
675
676         return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
677 }
678
679 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
680 {
681         if (sp->role.direct)
682                 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
683         else
684                 sp->gfns[index] = gfn;
685 }
686
687 /*
688  * Return the pointer to the large page information for a given gfn,
689  * handling slots that are not large page aligned.
690  */
691 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
692                                               struct kvm_memory_slot *slot,
693                                               int level)
694 {
695         unsigned long idx;
696
697         idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
698               (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
699         return &slot->lpage_info[level - 2][idx];
700 }
701
702 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
703 {
704         struct kvm_memory_slot *slot;
705         struct kvm_lpage_info *linfo;
706         int i;
707
708         slot = gfn_to_memslot(kvm, gfn);
709         for (i = PT_DIRECTORY_LEVEL;
710              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
711                 linfo = lpage_info_slot(gfn, slot, i);
712                 linfo->write_count += 1;
713         }
714         kvm->arch.indirect_shadow_pages++;
715 }
716
717 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
718 {
719         struct kvm_memory_slot *slot;
720         struct kvm_lpage_info *linfo;
721         int i;
722
723         slot = gfn_to_memslot(kvm, gfn);
724         for (i = PT_DIRECTORY_LEVEL;
725              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
726                 linfo = lpage_info_slot(gfn, slot, i);
727                 linfo->write_count -= 1;
728                 WARN_ON(linfo->write_count < 0);
729         }
730         kvm->arch.indirect_shadow_pages--;
731 }
732
733 static int has_wrprotected_page(struct kvm *kvm,
734                                 gfn_t gfn,
735                                 int level)
736 {
737         struct kvm_memory_slot *slot;
738         struct kvm_lpage_info *linfo;
739
740         slot = gfn_to_memslot(kvm, gfn);
741         if (slot) {
742                 linfo = lpage_info_slot(gfn, slot, level);
743                 return linfo->write_count;
744         }
745
746         return 1;
747 }
748
749 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
750 {
751         unsigned long page_size;
752         int i, ret = 0;
753
754         page_size = kvm_host_page_size(kvm, gfn);
755
756         for (i = PT_PAGE_TABLE_LEVEL;
757              i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
758                 if (page_size >= KVM_HPAGE_SIZE(i))
759                         ret = i;
760                 else
761                         break;
762         }
763
764         return ret;
765 }
766
767 static struct kvm_memory_slot *
768 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
769                             bool no_dirty_log)
770 {
771         struct kvm_memory_slot *slot;
772
773         slot = gfn_to_memslot(vcpu->kvm, gfn);
774         if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
775               (no_dirty_log && slot->dirty_bitmap))
776                 slot = NULL;
777
778         return slot;
779 }
780
781 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
782 {
783         return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
784 }
785
786 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
787 {
788         int host_level, level, max_level;
789
790         host_level = host_mapping_level(vcpu->kvm, large_gfn);
791
792         if (host_level == PT_PAGE_TABLE_LEVEL)
793                 return host_level;
794
795         max_level = kvm_x86_ops->get_lpage_level() < host_level ?
796                 kvm_x86_ops->get_lpage_level() : host_level;
797
798         for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
799                 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
800                         break;
801
802         return level - 1;
803 }
804
805 /*
806  * Pte mapping structures:
807  *
808  * If pte_list bit zero is zero, then pte_list point to the spte.
809  *
810  * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
811  * pte_list_desc containing more mappings.
812  *
813  * Returns the number of pte entries before the spte was added or zero if
814  * the spte was not added.
815  *
816  */
817 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
818                         unsigned long *pte_list)
819 {
820         struct pte_list_desc *desc;
821         int i, count = 0;
822
823         if (!*pte_list) {
824                 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
825                 *pte_list = (unsigned long)spte;
826         } else if (!(*pte_list & 1)) {
827                 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
828                 desc = mmu_alloc_pte_list_desc(vcpu);
829                 desc->sptes[0] = (u64 *)*pte_list;
830                 desc->sptes[1] = spte;
831                 *pte_list = (unsigned long)desc | 1;
832                 ++count;
833         } else {
834                 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
835                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
836                 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
837                         desc = desc->more;
838                         count += PTE_LIST_EXT;
839                 }
840                 if (desc->sptes[PTE_LIST_EXT-1]) {
841                         desc->more = mmu_alloc_pte_list_desc(vcpu);
842                         desc = desc->more;
843                 }
844                 for (i = 0; desc->sptes[i]; ++i)
845                         ++count;
846                 desc->sptes[i] = spte;
847         }
848         return count;
849 }
850
851 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
852 {
853         struct pte_list_desc *desc;
854         u64 *prev_spte;
855         int i;
856
857         if (!*pte_list)
858                 return NULL;
859         else if (!(*pte_list & 1)) {
860                 if (!spte)
861                         return (u64 *)*pte_list;
862                 return NULL;
863         }
864         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
865         prev_spte = NULL;
866         while (desc) {
867                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
868                         if (prev_spte == spte)
869                                 return desc->sptes[i];
870                         prev_spte = desc->sptes[i];
871                 }
872                 desc = desc->more;
873         }
874         return NULL;
875 }
876
877 static void
878 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
879                            int i, struct pte_list_desc *prev_desc)
880 {
881         int j;
882
883         for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
884                 ;
885         desc->sptes[i] = desc->sptes[j];
886         desc->sptes[j] = NULL;
887         if (j != 0)
888                 return;
889         if (!prev_desc && !desc->more)
890                 *pte_list = (unsigned long)desc->sptes[0];
891         else
892                 if (prev_desc)
893                         prev_desc->more = desc->more;
894                 else
895                         *pte_list = (unsigned long)desc->more | 1;
896         mmu_free_pte_list_desc(desc);
897 }
898
899 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
900 {
901         struct pte_list_desc *desc;
902         struct pte_list_desc *prev_desc;
903         int i;
904
905         if (!*pte_list) {
906                 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
907                 BUG();
908         } else if (!(*pte_list & 1)) {
909                 rmap_printk("pte_list_remove:  %p 1->0\n", spte);
910                 if ((u64 *)*pte_list != spte) {
911                         printk(KERN_ERR "pte_list_remove:  %p 1->BUG\n", spte);
912                         BUG();
913                 }
914                 *pte_list = 0;
915         } else {
916                 rmap_printk("pte_list_remove:  %p many->many\n", spte);
917                 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
918                 prev_desc = NULL;
919                 while (desc) {
920                         for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
921                                 if (desc->sptes[i] == spte) {
922                                         pte_list_desc_remove_entry(pte_list,
923                                                                desc, i,
924                                                                prev_desc);
925                                         return;
926                                 }
927                         prev_desc = desc;
928                         desc = desc->more;
929                 }
930                 pr_err("pte_list_remove: %p many->many\n", spte);
931                 BUG();
932         }
933 }
934
935 typedef void (*pte_list_walk_fn) (u64 *spte);
936 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
937 {
938         struct pte_list_desc *desc;
939         int i;
940
941         if (!*pte_list)
942                 return;
943
944         if (!(*pte_list & 1))
945                 return fn((u64 *)*pte_list);
946
947         desc = (struct pte_list_desc *)(*pte_list & ~1ul);
948         while (desc) {
949                 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
950                         fn(desc->sptes[i]);
951                 desc = desc->more;
952         }
953 }
954
955 /*
956  * Take gfn and return the reverse mapping to it.
957  */
958 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
959 {
960         struct kvm_memory_slot *slot;
961         struct kvm_lpage_info *linfo;
962
963         slot = gfn_to_memslot(kvm, gfn);
964         if (likely(level == PT_PAGE_TABLE_LEVEL))
965                 return &slot->rmap[gfn - slot->base_gfn];
966
967         linfo = lpage_info_slot(gfn, slot, level);
968
969         return &linfo->rmap_pde;
970 }
971
972 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
973 {
974         struct kvm_mmu_page *sp;
975         unsigned long *rmapp;
976
977         sp = page_header(__pa(spte));
978         kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
979         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
980         return pte_list_add(vcpu, spte, rmapp);
981 }
982
983 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
984 {
985         return pte_list_next(rmapp, spte);
986 }
987
988 static void rmap_remove(struct kvm *kvm, u64 *spte)
989 {
990         struct kvm_mmu_page *sp;
991         gfn_t gfn;
992         unsigned long *rmapp;
993
994         sp = page_header(__pa(spte));
995         gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
996         rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
997         pte_list_remove(spte, rmapp);
998 }
999
1000 static void drop_spte(struct kvm *kvm, u64 *sptep)
1001 {
1002         if (mmu_spte_clear_track_bits(sptep))
1003                 rmap_remove(kvm, sptep);
1004 }
1005
1006 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1007 {
1008         unsigned long *rmapp;
1009         u64 *spte;
1010         int i, write_protected = 0;
1011
1012         rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
1013
1014         spte = rmap_next(kvm, rmapp, NULL);
1015         while (spte) {
1016                 BUG_ON(!spte);
1017                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1018                 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
1019                 if (is_writable_pte(*spte)) {
1020                         mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
1021                         write_protected = 1;
1022                 }
1023                 spte = rmap_next(kvm, rmapp, spte);
1024         }
1025
1026         /* check for huge page mappings */
1027         for (i = PT_DIRECTORY_LEVEL;
1028              i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1029                 rmapp = gfn_to_rmap(kvm, gfn, i);
1030                 spte = rmap_next(kvm, rmapp, NULL);
1031                 while (spte) {
1032                         BUG_ON(!spte);
1033                         BUG_ON(!(*spte & PT_PRESENT_MASK));
1034                         BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
1035                         pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
1036                         if (is_writable_pte(*spte)) {
1037                                 drop_spte(kvm, spte);
1038                                 --kvm->stat.lpages;
1039                                 spte = NULL;
1040                                 write_protected = 1;
1041                         }
1042                         spte = rmap_next(kvm, rmapp, spte);
1043                 }
1044         }
1045
1046         return write_protected;
1047 }
1048
1049 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1050                            unsigned long data)
1051 {
1052         u64 *spte;
1053         int need_tlb_flush = 0;
1054
1055         while ((spte = rmap_next(kvm, rmapp, NULL))) {
1056                 BUG_ON(!(*spte & PT_PRESENT_MASK));
1057                 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
1058                 drop_spte(kvm, spte);
1059                 need_tlb_flush = 1;
1060         }
1061         return need_tlb_flush;
1062 }
1063
1064 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1065                              unsigned long data)
1066 {
1067         int need_flush = 0;
1068         u64 *spte, new_spte;
1069         pte_t *ptep = (pte_t *)data;
1070         pfn_t new_pfn;
1071
1072         WARN_ON(pte_huge(*ptep));
1073         new_pfn = pte_pfn(*ptep);
1074         spte = rmap_next(kvm, rmapp, NULL);
1075         while (spte) {
1076                 BUG_ON(!is_shadow_present_pte(*spte));
1077                 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1078                 need_flush = 1;
1079                 if (pte_write(*ptep)) {
1080                         drop_spte(kvm, spte);
1081                         spte = rmap_next(kvm, rmapp, NULL);
1082                 } else {
1083                         new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1084                         new_spte |= (u64)new_pfn << PAGE_SHIFT;
1085
1086                         new_spte &= ~PT_WRITABLE_MASK;
1087                         new_spte &= ~SPTE_HOST_WRITEABLE;
1088                         new_spte &= ~shadow_accessed_mask;
1089                         mmu_spte_clear_track_bits(spte);
1090                         mmu_spte_set(spte, new_spte);
1091                         spte = rmap_next(kvm, rmapp, spte);
1092                 }
1093         }
1094         if (need_flush)
1095                 kvm_flush_remote_tlbs(kvm);
1096
1097         return 0;
1098 }
1099
1100 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1101                           unsigned long data,
1102                           int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1103                                          unsigned long data))
1104 {
1105         int i, j;
1106         int ret;
1107         int retval = 0;
1108         struct kvm_memslots *slots;
1109
1110         slots = kvm_memslots(kvm);
1111
1112         for (i = 0; i < slots->nmemslots; i++) {
1113                 struct kvm_memory_slot *memslot = &slots->memslots[i];
1114                 unsigned long start = memslot->userspace_addr;
1115                 unsigned long end;
1116
1117                 end = start + (memslot->npages << PAGE_SHIFT);
1118                 if (hva >= start && hva < end) {
1119                         gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1120                         gfn_t gfn = memslot->base_gfn + gfn_offset;
1121
1122                         ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1123
1124                         for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1125                                 struct kvm_lpage_info *linfo;
1126
1127                                 linfo = lpage_info_slot(gfn, memslot,
1128                                                         PT_DIRECTORY_LEVEL + j);
1129                                 ret |= handler(kvm, &linfo->rmap_pde, data);
1130                         }
1131                         trace_kvm_age_page(hva, memslot, ret);
1132                         retval |= ret;
1133                 }
1134         }
1135
1136         return retval;
1137 }
1138
1139 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1140 {
1141         return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1142 }
1143
1144 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1145 {
1146         kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1147 }
1148
1149 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1150                          unsigned long data)
1151 {
1152         u64 *spte;
1153         int young = 0;
1154
1155         /*
1156          * Emulate the accessed bit for EPT, by checking if this page has
1157          * an EPT mapping, and clearing it if it does. On the next access,
1158          * a new EPT mapping will be established.
1159          * This has some overhead, but not as much as the cost of swapping
1160          * out actively used pages or breaking up actively used hugepages.
1161          */
1162         if (!shadow_accessed_mask)
1163                 return kvm_unmap_rmapp(kvm, rmapp, data);
1164
1165         spte = rmap_next(kvm, rmapp, NULL);
1166         while (spte) {
1167                 int _young;
1168                 u64 _spte = *spte;
1169                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1170                 _young = _spte & PT_ACCESSED_MASK;
1171                 if (_young) {
1172                         young = 1;
1173                         clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1174                 }
1175                 spte = rmap_next(kvm, rmapp, spte);
1176         }
1177         return young;
1178 }
1179
1180 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1181                               unsigned long data)
1182 {
1183         u64 *spte;
1184         int young = 0;
1185
1186         /*
1187          * If there's no access bit in the secondary pte set by the
1188          * hardware it's up to gup-fast/gup to set the access bit in
1189          * the primary pte or in the page structure.
1190          */
1191         if (!shadow_accessed_mask)
1192                 goto out;
1193
1194         spte = rmap_next(kvm, rmapp, NULL);
1195         while (spte) {
1196                 u64 _spte = *spte;
1197                 BUG_ON(!(_spte & PT_PRESENT_MASK));
1198                 young = _spte & PT_ACCESSED_MASK;
1199                 if (young) {
1200                         young = 1;
1201                         break;
1202                 }
1203                 spte = rmap_next(kvm, rmapp, spte);
1204         }
1205 out:
1206         return young;
1207 }
1208
1209 #define RMAP_RECYCLE_THRESHOLD 1000
1210
1211 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1212 {
1213         unsigned long *rmapp;
1214         struct kvm_mmu_page *sp;
1215
1216         sp = page_header(__pa(spte));
1217
1218         rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1219
1220         kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1221         kvm_flush_remote_tlbs(vcpu->kvm);
1222 }
1223
1224 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1225 {
1226         return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1227 }
1228
1229 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1230 {
1231         return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1232 }
1233
1234 #ifdef MMU_DEBUG
1235 static int is_empty_shadow_page(u64 *spt)
1236 {
1237         u64 *pos;
1238         u64 *end;
1239
1240         for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1241                 if (is_shadow_present_pte(*pos)) {
1242                         printk(KERN_ERR "%s: %p %llx\n", __func__,
1243                                pos, *pos);
1244                         return 0;
1245                 }
1246         return 1;
1247 }
1248 #endif
1249
1250 /*
1251  * This value is the sum of all of the kvm instances's
1252  * kvm->arch.n_used_mmu_pages values.  We need a global,
1253  * aggregate version in order to make the slab shrinker
1254  * faster
1255  */
1256 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1257 {
1258         kvm->arch.n_used_mmu_pages += nr;
1259         percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1260 }
1261
1262 /*
1263  * Remove the sp from shadow page cache, after call it,
1264  * we can not find this sp from the cache, and the shadow
1265  * page table is still valid.
1266  * It should be under the protection of mmu lock.
1267  */
1268 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1269 {
1270         ASSERT(is_empty_shadow_page(sp->spt));
1271         hlist_del(&sp->hash_link);
1272         if (!sp->role.direct)
1273                 free_page((unsigned long)sp->gfns);
1274 }
1275
1276 /*
1277  * Free the shadow page table and the sp, we can do it
1278  * out of the protection of mmu lock.
1279  */
1280 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1281 {
1282         list_del(&sp->link);
1283         free_page((unsigned long)sp->spt);
1284         kmem_cache_free(mmu_page_header_cache, sp);
1285 }
1286
1287 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1288 {
1289         return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1290 }
1291
1292 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1293                                     struct kvm_mmu_page *sp, u64 *parent_pte)
1294 {
1295         if (!parent_pte)
1296                 return;
1297
1298         pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1299 }
1300
1301 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1302                                        u64 *parent_pte)
1303 {
1304         pte_list_remove(parent_pte, &sp->parent_ptes);
1305 }
1306
1307 static void drop_parent_pte(struct kvm_mmu_page *sp,
1308                             u64 *parent_pte)
1309 {
1310         mmu_page_remove_parent_pte(sp, parent_pte);
1311         mmu_spte_clear_no_track(parent_pte);
1312 }
1313
1314 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1315                                                u64 *parent_pte, int direct)
1316 {
1317         struct kvm_mmu_page *sp;
1318         sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1319                                         sizeof *sp);
1320         sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1321         if (!direct)
1322                 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1323                                                   PAGE_SIZE);
1324         set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1325         list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1326         bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1327         sp->parent_ptes = 0;
1328         mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1329         kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1330         return sp;
1331 }
1332
1333 static void mark_unsync(u64 *spte);
1334 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1335 {
1336         pte_list_walk(&sp->parent_ptes, mark_unsync);
1337 }
1338
1339 static void mark_unsync(u64 *spte)
1340 {
1341         struct kvm_mmu_page *sp;
1342         unsigned int index;
1343
1344         sp = page_header(__pa(spte));
1345         index = spte - sp->spt;
1346         if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1347                 return;
1348         if (sp->unsync_children++)
1349                 return;
1350         kvm_mmu_mark_parents_unsync(sp);
1351 }
1352
1353 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1354                                struct kvm_mmu_page *sp)
1355 {
1356         return 1;
1357 }
1358
1359 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1360 {
1361 }
1362
1363 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1364                                  struct kvm_mmu_page *sp, u64 *spte,
1365                                  const void *pte)
1366 {
1367         WARN_ON(1);
1368 }
1369
1370 #define KVM_PAGE_ARRAY_NR 16
1371
1372 struct kvm_mmu_pages {
1373         struct mmu_page_and_offset {
1374                 struct kvm_mmu_page *sp;
1375                 unsigned int idx;
1376         } page[KVM_PAGE_ARRAY_NR];
1377         unsigned int nr;
1378 };
1379
1380 #define for_each_unsync_children(bitmap, idx)           \
1381         for (idx = find_first_bit(bitmap, 512);         \
1382              idx < 512;                                 \
1383              idx = find_next_bit(bitmap, 512, idx+1))
1384
1385 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1386                          int idx)
1387 {
1388         int i;
1389
1390         if (sp->unsync)
1391                 for (i=0; i < pvec->nr; i++)
1392                         if (pvec->page[i].sp == sp)
1393                                 return 0;
1394
1395         pvec->page[pvec->nr].sp = sp;
1396         pvec->page[pvec->nr].idx = idx;
1397         pvec->nr++;
1398         return (pvec->nr == KVM_PAGE_ARRAY_NR);
1399 }
1400
1401 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1402                            struct kvm_mmu_pages *pvec)
1403 {
1404         int i, ret, nr_unsync_leaf = 0;
1405
1406         for_each_unsync_children(sp->unsync_child_bitmap, i) {
1407                 struct kvm_mmu_page *child;
1408                 u64 ent = sp->spt[i];
1409
1410                 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1411                         goto clear_child_bitmap;
1412
1413                 child = page_header(ent & PT64_BASE_ADDR_MASK);
1414
1415                 if (child->unsync_children) {
1416                         if (mmu_pages_add(pvec, child, i))
1417                                 return -ENOSPC;
1418
1419                         ret = __mmu_unsync_walk(child, pvec);
1420                         if (!ret)
1421                                 goto clear_child_bitmap;
1422                         else if (ret > 0)
1423                                 nr_unsync_leaf += ret;
1424                         else
1425                                 return ret;
1426                 } else if (child->unsync) {
1427                         nr_unsync_leaf++;
1428                         if (mmu_pages_add(pvec, child, i))
1429                                 return -ENOSPC;
1430                 } else
1431                          goto clear_child_bitmap;
1432
1433                 continue;
1434
1435 clear_child_bitmap:
1436                 __clear_bit(i, sp->unsync_child_bitmap);
1437                 sp->unsync_children--;
1438                 WARN_ON((int)sp->unsync_children < 0);
1439         }
1440
1441
1442         return nr_unsync_leaf;
1443 }
1444
1445 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1446                            struct kvm_mmu_pages *pvec)
1447 {
1448         if (!sp->unsync_children)
1449                 return 0;
1450
1451         mmu_pages_add(pvec, sp, 0);
1452         return __mmu_unsync_walk(sp, pvec);
1453 }
1454
1455 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1456 {
1457         WARN_ON(!sp->unsync);
1458         trace_kvm_mmu_sync_page(sp);
1459         sp->unsync = 0;
1460         --kvm->stat.mmu_unsync;
1461 }
1462
1463 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1464                                     struct list_head *invalid_list);
1465 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1466                                     struct list_head *invalid_list);
1467
1468 #define for_each_gfn_sp(kvm, sp, gfn, pos)                              \
1469   hlist_for_each_entry(sp, pos,                                         \
1470    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1471         if ((sp)->gfn != (gfn)) {} else
1472
1473 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos)               \
1474   hlist_for_each_entry(sp, pos,                                         \
1475    &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link)   \
1476                 if ((sp)->gfn != (gfn) || (sp)->role.direct ||          \
1477                         (sp)->role.invalid) {} else
1478
1479 /* @sp->gfn should be write-protected at the call site */
1480 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1481                            struct list_head *invalid_list, bool clear_unsync)
1482 {
1483         if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1484                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1485                 return 1;
1486         }
1487
1488         if (clear_unsync)
1489                 kvm_unlink_unsync_page(vcpu->kvm, sp);
1490
1491         if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1492                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1493                 return 1;
1494         }
1495
1496         kvm_mmu_flush_tlb(vcpu);
1497         return 0;
1498 }
1499
1500 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1501                                    struct kvm_mmu_page *sp)
1502 {
1503         LIST_HEAD(invalid_list);
1504         int ret;
1505
1506         ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1507         if (ret)
1508                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1509
1510         return ret;
1511 }
1512
1513 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1514                          struct list_head *invalid_list)
1515 {
1516         return __kvm_sync_page(vcpu, sp, invalid_list, true);
1517 }
1518
1519 /* @gfn should be write-protected at the call site */
1520 static void kvm_sync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
1521 {
1522         struct kvm_mmu_page *s;
1523         struct hlist_node *node;
1524         LIST_HEAD(invalid_list);
1525         bool flush = false;
1526
1527         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1528                 if (!s->unsync)
1529                         continue;
1530
1531                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1532                 kvm_unlink_unsync_page(vcpu->kvm, s);
1533                 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1534                         (vcpu->arch.mmu.sync_page(vcpu, s))) {
1535                         kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1536                         continue;
1537                 }
1538                 flush = true;
1539         }
1540
1541         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1542         if (flush)
1543                 kvm_mmu_flush_tlb(vcpu);
1544 }
1545
1546 struct mmu_page_path {
1547         struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1548         unsigned int idx[PT64_ROOT_LEVEL-1];
1549 };
1550
1551 #define for_each_sp(pvec, sp, parents, i)                       \
1552                 for (i = mmu_pages_next(&pvec, &parents, -1),   \
1553                         sp = pvec.page[i].sp;                   \
1554                         i < pvec.nr && ({ sp = pvec.page[i].sp; 1;});   \
1555                         i = mmu_pages_next(&pvec, &parents, i))
1556
1557 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1558                           struct mmu_page_path *parents,
1559                           int i)
1560 {
1561         int n;
1562
1563         for (n = i+1; n < pvec->nr; n++) {
1564                 struct kvm_mmu_page *sp = pvec->page[n].sp;
1565
1566                 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1567                         parents->idx[0] = pvec->page[n].idx;
1568                         return n;
1569                 }
1570
1571                 parents->parent[sp->role.level-2] = sp;
1572                 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1573         }
1574
1575         return n;
1576 }
1577
1578 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1579 {
1580         struct kvm_mmu_page *sp;
1581         unsigned int level = 0;
1582
1583         do {
1584                 unsigned int idx = parents->idx[level];
1585
1586                 sp = parents->parent[level];
1587                 if (!sp)
1588                         return;
1589
1590                 --sp->unsync_children;
1591                 WARN_ON((int)sp->unsync_children < 0);
1592                 __clear_bit(idx, sp->unsync_child_bitmap);
1593                 level++;
1594         } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1595 }
1596
1597 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1598                                struct mmu_page_path *parents,
1599                                struct kvm_mmu_pages *pvec)
1600 {
1601         parents->parent[parent->role.level-1] = NULL;
1602         pvec->nr = 0;
1603 }
1604
1605 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1606                               struct kvm_mmu_page *parent)
1607 {
1608         int i;
1609         struct kvm_mmu_page *sp;
1610         struct mmu_page_path parents;
1611         struct kvm_mmu_pages pages;
1612         LIST_HEAD(invalid_list);
1613
1614         kvm_mmu_pages_init(parent, &parents, &pages);
1615         while (mmu_unsync_walk(parent, &pages)) {
1616                 int protected = 0;
1617
1618                 for_each_sp(pages, sp, parents, i)
1619                         protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1620
1621                 if (protected)
1622                         kvm_flush_remote_tlbs(vcpu->kvm);
1623
1624                 for_each_sp(pages, sp, parents, i) {
1625                         kvm_sync_page(vcpu, sp, &invalid_list);
1626                         mmu_pages_clear_parents(&parents);
1627                 }
1628                 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1629                 cond_resched_lock(&vcpu->kvm->mmu_lock);
1630                 kvm_mmu_pages_init(parent, &parents, &pages);
1631         }
1632 }
1633
1634 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1635 {
1636         int i;
1637
1638         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1639                 sp->spt[i] = 0ull;
1640 }
1641
1642 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1643                                              gfn_t gfn,
1644                                              gva_t gaddr,
1645                                              unsigned level,
1646                                              int direct,
1647                                              unsigned access,
1648                                              u64 *parent_pte)
1649 {
1650         union kvm_mmu_page_role role;
1651         unsigned quadrant;
1652         struct kvm_mmu_page *sp;
1653         struct hlist_node *node;
1654         bool need_sync = false;
1655
1656         role = vcpu->arch.mmu.base_role;
1657         role.level = level;
1658         role.direct = direct;
1659         if (role.direct)
1660                 role.cr4_pae = 0;
1661         role.access = access;
1662         if (!vcpu->arch.mmu.direct_map
1663             && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1664                 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1665                 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1666                 role.quadrant = quadrant;
1667         }
1668         for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1669                 if (!need_sync && sp->unsync)
1670                         need_sync = true;
1671
1672                 if (sp->role.word != role.word)
1673                         continue;
1674
1675                 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1676                         break;
1677
1678                 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1679                 if (sp->unsync_children) {
1680                         kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1681                         kvm_mmu_mark_parents_unsync(sp);
1682                 } else if (sp->unsync)
1683                         kvm_mmu_mark_parents_unsync(sp);
1684
1685                 trace_kvm_mmu_get_page(sp, false);
1686                 return sp;
1687         }
1688         ++vcpu->kvm->stat.mmu_cache_miss;
1689         sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1690         if (!sp)
1691                 return sp;
1692         sp->gfn = gfn;
1693         sp->role = role;
1694         hlist_add_head(&sp->hash_link,
1695                 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1696         if (!direct) {
1697                 if (rmap_write_protect(vcpu->kvm, gfn))
1698                         kvm_flush_remote_tlbs(vcpu->kvm);
1699                 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1700                         kvm_sync_pages(vcpu, gfn);
1701
1702                 account_shadowed(vcpu->kvm, gfn);
1703         }
1704         init_shadow_page_table(sp);
1705         trace_kvm_mmu_get_page(sp, true);
1706         return sp;
1707 }
1708
1709 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1710                              struct kvm_vcpu *vcpu, u64 addr)
1711 {
1712         iterator->addr = addr;
1713         iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1714         iterator->level = vcpu->arch.mmu.shadow_root_level;
1715
1716         if (iterator->level == PT64_ROOT_LEVEL &&
1717             vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1718             !vcpu->arch.mmu.direct_map)
1719                 --iterator->level;
1720
1721         if (iterator->level == PT32E_ROOT_LEVEL) {
1722                 iterator->shadow_addr
1723                         = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1724                 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1725                 --iterator->level;
1726                 if (!iterator->shadow_addr)
1727                         iterator->level = 0;
1728         }
1729 }
1730
1731 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1732 {
1733         if (iterator->level < PT_PAGE_TABLE_LEVEL)
1734                 return false;
1735
1736         iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1737         iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1738         return true;
1739 }
1740
1741 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1742                                u64 spte)
1743 {
1744         if (is_last_spte(spte, iterator->level)) {
1745                 iterator->level = 0;
1746                 return;
1747         }
1748
1749         iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1750         --iterator->level;
1751 }
1752
1753 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1754 {
1755         return __shadow_walk_next(iterator, *iterator->sptep);
1756 }
1757
1758 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1759 {
1760         u64 spte;
1761
1762         spte = __pa(sp->spt)
1763                 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1764                 | PT_WRITABLE_MASK | PT_USER_MASK;
1765         mmu_spte_set(sptep, spte);
1766 }
1767
1768 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1769 {
1770         if (is_large_pte(*sptep)) {
1771                 drop_spte(vcpu->kvm, sptep);
1772                 kvm_flush_remote_tlbs(vcpu->kvm);
1773         }
1774 }
1775
1776 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1777                                    unsigned direct_access)
1778 {
1779         if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1780                 struct kvm_mmu_page *child;
1781
1782                 /*
1783                  * For the direct sp, if the guest pte's dirty bit
1784                  * changed form clean to dirty, it will corrupt the
1785                  * sp's access: allow writable in the read-only sp,
1786                  * so we should update the spte at this point to get
1787                  * a new sp with the correct access.
1788                  */
1789                 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1790                 if (child->role.access == direct_access)
1791                         return;
1792
1793                 drop_parent_pte(child, sptep);
1794                 kvm_flush_remote_tlbs(vcpu->kvm);
1795         }
1796 }
1797
1798 static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1799                              u64 *spte)
1800 {
1801         u64 pte;
1802         struct kvm_mmu_page *child;
1803
1804         pte = *spte;
1805         if (is_shadow_present_pte(pte)) {
1806                 if (is_last_spte(pte, sp->role.level))
1807                         drop_spte(kvm, spte);
1808                 else {
1809                         child = page_header(pte & PT64_BASE_ADDR_MASK);
1810                         drop_parent_pte(child, spte);
1811                 }
1812         } else if (is_mmio_spte(pte))
1813                 mmu_spte_clear_no_track(spte);
1814
1815         if (is_large_pte(pte))
1816                 --kvm->stat.lpages;
1817 }
1818
1819 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1820                                          struct kvm_mmu_page *sp)
1821 {
1822         unsigned i;
1823
1824         for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1825                 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1826 }
1827
1828 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1829 {
1830         mmu_page_remove_parent_pte(sp, parent_pte);
1831 }
1832
1833 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1834 {
1835         int i;
1836         struct kvm_vcpu *vcpu;
1837
1838         kvm_for_each_vcpu(i, vcpu, kvm)
1839                 vcpu->arch.last_pte_updated = NULL;
1840 }
1841
1842 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1843 {
1844         u64 *parent_pte;
1845
1846         while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1847                 drop_parent_pte(sp, parent_pte);
1848 }
1849
1850 static int mmu_zap_unsync_children(struct kvm *kvm,
1851                                    struct kvm_mmu_page *parent,
1852                                    struct list_head *invalid_list)
1853 {
1854         int i, zapped = 0;
1855         struct mmu_page_path parents;
1856         struct kvm_mmu_pages pages;
1857
1858         if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1859                 return 0;
1860
1861         kvm_mmu_pages_init(parent, &parents, &pages);
1862         while (mmu_unsync_walk(parent, &pages)) {
1863                 struct kvm_mmu_page *sp;
1864
1865                 for_each_sp(pages, sp, parents, i) {
1866                         kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1867                         mmu_pages_clear_parents(&parents);
1868                         zapped++;
1869                 }
1870                 kvm_mmu_pages_init(parent, &parents, &pages);
1871         }
1872
1873         return zapped;
1874 }
1875
1876 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1877                                     struct list_head *invalid_list)
1878 {
1879         int ret;
1880
1881         trace_kvm_mmu_prepare_zap_page(sp);
1882         ++kvm->stat.mmu_shadow_zapped;
1883         ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1884         kvm_mmu_page_unlink_children(kvm, sp);
1885         kvm_mmu_unlink_parents(kvm, sp);
1886         if (!sp->role.invalid && !sp->role.direct)
1887                 unaccount_shadowed(kvm, sp->gfn);
1888         if (sp->unsync)
1889                 kvm_unlink_unsync_page(kvm, sp);
1890         if (!sp->root_count) {
1891                 /* Count self */
1892                 ret++;
1893                 list_move(&sp->link, invalid_list);
1894                 kvm_mod_used_mmu_pages(kvm, -1);
1895         } else {
1896                 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1897                 kvm_reload_remote_mmus(kvm);
1898         }
1899
1900         sp->role.invalid = 1;
1901         kvm_mmu_reset_last_pte_updated(kvm);
1902         return ret;
1903 }
1904
1905 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1906 {
1907         struct kvm_mmu_page *sp;
1908
1909         list_for_each_entry(sp, invalid_list, link)
1910                 kvm_mmu_isolate_page(sp);
1911 }
1912
1913 static void free_pages_rcu(struct rcu_head *head)
1914 {
1915         struct kvm_mmu_page *next, *sp;
1916
1917         sp = container_of(head, struct kvm_mmu_page, rcu);
1918         while (sp) {
1919                 if (!list_empty(&sp->link))
1920                         next = list_first_entry(&sp->link,
1921                                       struct kvm_mmu_page, link);
1922                 else
1923                         next = NULL;
1924                 kvm_mmu_free_page(sp);
1925                 sp = next;
1926         }
1927 }
1928
1929 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1930                                     struct list_head *invalid_list)
1931 {
1932         struct kvm_mmu_page *sp;
1933
1934         if (list_empty(invalid_list))
1935                 return;
1936
1937         kvm_flush_remote_tlbs(kvm);
1938
1939         if (atomic_read(&kvm->arch.reader_counter)) {
1940                 kvm_mmu_isolate_pages(invalid_list);
1941                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1942                 list_del_init(invalid_list);
1943
1944                 trace_kvm_mmu_delay_free_pages(sp);
1945                 call_rcu(&sp->rcu, free_pages_rcu);
1946                 return;
1947         }
1948
1949         do {
1950                 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1951                 WARN_ON(!sp->role.invalid || sp->root_count);
1952                 kvm_mmu_isolate_page(sp);
1953                 kvm_mmu_free_page(sp);
1954         } while (!list_empty(invalid_list));
1955
1956 }
1957
1958 /*
1959  * Changing the number of mmu pages allocated to the vm
1960  * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1961  */
1962 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1963 {
1964         LIST_HEAD(invalid_list);
1965         /*
1966          * If we set the number of mmu pages to be smaller be than the
1967          * number of actived pages , we must to free some mmu pages before we
1968          * change the value
1969          */
1970
1971         if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1972                 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1973                         !list_empty(&kvm->arch.active_mmu_pages)) {
1974                         struct kvm_mmu_page *page;
1975
1976                         page = container_of(kvm->arch.active_mmu_pages.prev,
1977                                             struct kvm_mmu_page, link);
1978                         kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1979                 }
1980                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1981                 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
1982         }
1983
1984         kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
1985 }
1986
1987 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1988 {
1989         struct kvm_mmu_page *sp;
1990         struct hlist_node *node;
1991         LIST_HEAD(invalid_list);
1992         int r;
1993
1994         pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
1995         r = 0;
1996
1997         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1998                 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
1999                          sp->role.word);
2000                 r = 1;
2001                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2002         }
2003         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2004         return r;
2005 }
2006
2007 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
2008 {
2009         struct kvm_mmu_page *sp;
2010         struct hlist_node *node;
2011         LIST_HEAD(invalid_list);
2012
2013         for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2014                 pgprintk("%s: zap %llx %x\n",
2015                          __func__, gfn, sp->role.word);
2016                 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2017         }
2018         kvm_mmu_commit_zap_page(kvm, &invalid_list);
2019 }
2020
2021 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2022 {
2023         int slot = memslot_id(kvm, gfn);
2024         struct kvm_mmu_page *sp = page_header(__pa(pte));
2025
2026         __set_bit(slot, sp->slot_bitmap);
2027 }
2028
2029 /*
2030  * The function is based on mtrr_type_lookup() in
2031  * arch/x86/kernel/cpu/mtrr/generic.c
2032  */
2033 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2034                          u64 start, u64 end)
2035 {
2036         int i;
2037         u64 base, mask;
2038         u8 prev_match, curr_match;
2039         int num_var_ranges = KVM_NR_VAR_MTRR;
2040
2041         if (!mtrr_state->enabled)
2042                 return 0xFF;
2043
2044         /* Make end inclusive end, instead of exclusive */
2045         end--;
2046
2047         /* Look in fixed ranges. Just return the type as per start */
2048         if (mtrr_state->have_fixed && (start < 0x100000)) {
2049                 int idx;
2050
2051                 if (start < 0x80000) {
2052                         idx = 0;
2053                         idx += (start >> 16);
2054                         return mtrr_state->fixed_ranges[idx];
2055                 } else if (start < 0xC0000) {
2056                         idx = 1 * 8;
2057                         idx += ((start - 0x80000) >> 14);
2058                         return mtrr_state->fixed_ranges[idx];
2059                 } else if (start < 0x1000000) {
2060                         idx = 3 * 8;
2061                         idx += ((start - 0xC0000) >> 12);
2062                         return mtrr_state->fixed_ranges[idx];
2063                 }
2064         }
2065
2066         /*
2067          * Look in variable ranges
2068          * Look of multiple ranges matching this address and pick type
2069          * as per MTRR precedence
2070          */
2071         if (!(mtrr_state->enabled & 2))
2072                 return mtrr_state->def_type;
2073
2074         prev_match = 0xFF;
2075         for (i = 0; i < num_var_ranges; ++i) {
2076                 unsigned short start_state, end_state;
2077
2078                 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2079                         continue;
2080
2081                 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2082                        (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2083                 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2084                        (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2085
2086                 start_state = ((start & mask) == (base & mask));
2087                 end_state = ((end & mask) == (base & mask));
2088                 if (start_state != end_state)
2089                         return 0xFE;
2090
2091                 if ((start & mask) != (base & mask))
2092                         continue;
2093
2094                 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2095                 if (prev_match == 0xFF) {
2096                         prev_match = curr_match;
2097                         continue;
2098                 }
2099
2100                 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2101                     curr_match == MTRR_TYPE_UNCACHABLE)
2102                         return MTRR_TYPE_UNCACHABLE;
2103
2104                 if ((prev_match == MTRR_TYPE_WRBACK &&
2105                      curr_match == MTRR_TYPE_WRTHROUGH) ||
2106                     (prev_match == MTRR_TYPE_WRTHROUGH &&
2107                      curr_match == MTRR_TYPE_WRBACK)) {
2108                         prev_match = MTRR_TYPE_WRTHROUGH;
2109                         curr_match = MTRR_TYPE_WRTHROUGH;
2110                 }
2111
2112                 if (prev_match != curr_match)
2113                         return MTRR_TYPE_UNCACHABLE;
2114         }
2115
2116         if (prev_match != 0xFF)
2117                 return prev_match;
2118
2119         return mtrr_state->def_type;
2120 }
2121
2122 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2123 {
2124         u8 mtrr;
2125
2126         mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2127                              (gfn << PAGE_SHIFT) + PAGE_SIZE);
2128         if (mtrr == 0xfe || mtrr == 0xff)
2129                 mtrr = MTRR_TYPE_WRBACK;
2130         return mtrr;
2131 }
2132 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2133
2134 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2135 {
2136         trace_kvm_mmu_unsync_page(sp);
2137         ++vcpu->kvm->stat.mmu_unsync;
2138         sp->unsync = 1;
2139
2140         kvm_mmu_mark_parents_unsync(sp);
2141 }
2142
2143 static void kvm_unsync_pages(struct kvm_vcpu *vcpu,  gfn_t gfn)
2144 {
2145         struct kvm_mmu_page *s;
2146         struct hlist_node *node;
2147
2148         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2149                 if (s->unsync)
2150                         continue;
2151                 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2152                 __kvm_unsync_page(vcpu, s);
2153         }
2154 }
2155
2156 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2157                                   bool can_unsync)
2158 {
2159         struct kvm_mmu_page *s;
2160         struct hlist_node *node;
2161         bool need_unsync = false;
2162
2163         for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2164                 if (!can_unsync)
2165                         return 1;
2166
2167                 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2168                         return 1;
2169
2170                 if (!need_unsync && !s->unsync) {
2171                         if (!oos_shadow)
2172                                 return 1;
2173                         need_unsync = true;
2174                 }
2175         }
2176         if (need_unsync)
2177                 kvm_unsync_pages(vcpu, gfn);
2178         return 0;
2179 }
2180
2181 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2182                     unsigned pte_access, int user_fault,
2183                     int write_fault, int level,
2184                     gfn_t gfn, pfn_t pfn, bool speculative,
2185                     bool can_unsync, bool host_writable)
2186 {
2187         u64 spte, entry = *sptep;
2188         int ret = 0;
2189
2190         if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2191                 return 0;
2192
2193         /*
2194          * We don't set the accessed bit, since we sometimes want to see
2195          * whether the guest actually used the pte (in order to detect
2196          * demand paging).
2197          */
2198         spte = PT_PRESENT_MASK;
2199         if (!speculative)
2200                 spte |= shadow_accessed_mask;
2201
2202         if (pte_access & ACC_EXEC_MASK)
2203                 spte |= shadow_x_mask;
2204         else
2205                 spte |= shadow_nx_mask;
2206         if (pte_access & ACC_USER_MASK)
2207                 spte |= shadow_user_mask;
2208         if (level > PT_PAGE_TABLE_LEVEL)
2209                 spte |= PT_PAGE_SIZE_MASK;
2210         if (tdp_enabled)
2211                 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2212                         kvm_is_mmio_pfn(pfn));
2213
2214         if (host_writable)
2215                 spte |= SPTE_HOST_WRITEABLE;
2216         else
2217                 pte_access &= ~ACC_WRITE_MASK;
2218
2219         spte |= (u64)pfn << PAGE_SHIFT;
2220
2221         if ((pte_access & ACC_WRITE_MASK)
2222             || (!vcpu->arch.mmu.direct_map && write_fault
2223                 && !is_write_protection(vcpu) && !user_fault)) {
2224
2225                 if (level > PT_PAGE_TABLE_LEVEL &&
2226                     has_wrprotected_page(vcpu->kvm, gfn, level)) {
2227                         ret = 1;
2228                         drop_spte(vcpu->kvm, sptep);
2229                         goto done;
2230                 }
2231
2232                 spte |= PT_WRITABLE_MASK;
2233
2234                 if (!vcpu->arch.mmu.direct_map
2235                     && !(pte_access & ACC_WRITE_MASK)) {
2236                         spte &= ~PT_USER_MASK;
2237                         /*
2238                          * If we converted a user page to a kernel page,
2239                          * so that the kernel can write to it when cr0.wp=0,
2240                          * then we should prevent the kernel from executing it
2241                          * if SMEP is enabled.
2242                          */
2243                         if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2244                                 spte |= PT64_NX_MASK;
2245                 }
2246
2247                 /*
2248                  * Optimization: for pte sync, if spte was writable the hash
2249                  * lookup is unnecessary (and expensive). Write protection
2250                  * is responsibility of mmu_get_page / kvm_sync_page.
2251                  * Same reasoning can be applied to dirty page accounting.
2252                  */
2253                 if (!can_unsync && is_writable_pte(*sptep))
2254                         goto set_pte;
2255
2256                 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2257                         pgprintk("%s: found shadow page for %llx, marking ro\n",
2258                                  __func__, gfn);
2259                         ret = 1;
2260                         pte_access &= ~ACC_WRITE_MASK;
2261                         if (is_writable_pte(spte))
2262                                 spte &= ~PT_WRITABLE_MASK;
2263                 }
2264         }
2265
2266         if (pte_access & ACC_WRITE_MASK)
2267                 mark_page_dirty(vcpu->kvm, gfn);
2268
2269 set_pte:
2270         mmu_spte_update(sptep, spte);
2271         /*
2272          * If we overwrite a writable spte with a read-only one we
2273          * should flush remote TLBs. Otherwise rmap_write_protect
2274          * will find a read-only spte, even though the writable spte
2275          * might be cached on a CPU's TLB.
2276          */
2277         if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2278                 kvm_flush_remote_tlbs(vcpu->kvm);
2279 done:
2280         return ret;
2281 }
2282
2283 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2284                          unsigned pt_access, unsigned pte_access,
2285                          int user_fault, int write_fault,
2286                          int *emulate, int level, gfn_t gfn,
2287                          pfn_t pfn, bool speculative,
2288                          bool host_writable)
2289 {
2290         int was_rmapped = 0;
2291         int rmap_count;
2292
2293         pgprintk("%s: spte %llx access %x write_fault %d"
2294                  " user_fault %d gfn %llx\n",
2295                  __func__, *sptep, pt_access,
2296                  write_fault, user_fault, gfn);
2297
2298         if (is_rmap_spte(*sptep)) {
2299                 /*
2300                  * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2301                  * the parent of the now unreachable PTE.
2302                  */
2303                 if (level > PT_PAGE_TABLE_LEVEL &&
2304                     !is_large_pte(*sptep)) {
2305                         struct kvm_mmu_page *child;
2306                         u64 pte = *sptep;
2307
2308                         child = page_header(pte & PT64_BASE_ADDR_MASK);
2309                         drop_parent_pte(child, sptep);
2310                         kvm_flush_remote_tlbs(vcpu->kvm);
2311                 } else if (pfn != spte_to_pfn(*sptep)) {
2312                         pgprintk("hfn old %llx new %llx\n",
2313                                  spte_to_pfn(*sptep), pfn);
2314                         drop_spte(vcpu->kvm, sptep);
2315                         kvm_flush_remote_tlbs(vcpu->kvm);
2316                 } else
2317                         was_rmapped = 1;
2318         }
2319
2320         if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2321                       level, gfn, pfn, speculative, true,
2322                       host_writable)) {
2323                 if (write_fault)
2324                         *emulate = 1;
2325                 kvm_mmu_flush_tlb(vcpu);
2326         }
2327
2328         if (unlikely(is_mmio_spte(*sptep) && emulate))
2329                 *emulate = 1;
2330
2331         pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2332         pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2333                  is_large_pte(*sptep)? "2MB" : "4kB",
2334                  *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2335                  *sptep, sptep);
2336         if (!was_rmapped && is_large_pte(*sptep))
2337                 ++vcpu->kvm->stat.lpages;
2338
2339         if (is_shadow_present_pte(*sptep)) {
2340                 page_header_update_slot(vcpu->kvm, sptep, gfn);
2341                 if (!was_rmapped) {
2342                         rmap_count = rmap_add(vcpu, sptep, gfn);
2343                         if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2344                                 rmap_recycle(vcpu, sptep, gfn);
2345                 }
2346         }
2347         kvm_release_pfn_clean(pfn);
2348         if (speculative) {
2349                 vcpu->arch.last_pte_updated = sptep;
2350                 vcpu->arch.last_pte_gfn = gfn;
2351         }
2352 }
2353
2354 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2355 {
2356 }
2357
2358 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2359                                      bool no_dirty_log)
2360 {
2361         struct kvm_memory_slot *slot;
2362         unsigned long hva;
2363
2364         slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2365         if (!slot) {
2366                 get_page(fault_page);
2367                 return page_to_pfn(fault_page);
2368         }
2369
2370         hva = gfn_to_hva_memslot(slot, gfn);
2371
2372         return hva_to_pfn_atomic(vcpu->kvm, hva);
2373 }
2374
2375 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2376                                     struct kvm_mmu_page *sp,
2377                                     u64 *start, u64 *end)
2378 {
2379         struct page *pages[PTE_PREFETCH_NUM];
2380         unsigned access = sp->role.access;
2381         int i, ret;
2382         gfn_t gfn;
2383
2384         gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2385         if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2386                 return -1;
2387
2388         ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2389         if (ret <= 0)
2390                 return -1;
2391
2392         for (i = 0; i < ret; i++, gfn++, start++)
2393                 mmu_set_spte(vcpu, start, ACC_ALL,
2394                              access, 0, 0, NULL,
2395                              sp->role.level, gfn,
2396                              page_to_pfn(pages[i]), true, true);
2397
2398         return 0;
2399 }
2400
2401 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2402                                   struct kvm_mmu_page *sp, u64 *sptep)
2403 {
2404         u64 *spte, *start = NULL;
2405         int i;
2406
2407         WARN_ON(!sp->role.direct);
2408
2409         i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2410         spte = sp->spt + i;
2411
2412         for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2413                 if (is_shadow_present_pte(*spte) || spte == sptep) {
2414                         if (!start)
2415                                 continue;
2416                         if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2417                                 break;
2418                         start = NULL;
2419                 } else if (!start)
2420                         start = spte;
2421         }
2422 }
2423
2424 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2425 {
2426         struct kvm_mmu_page *sp;
2427
2428         /*
2429          * Since it's no accessed bit on EPT, it's no way to
2430          * distinguish between actually accessed translations
2431          * and prefetched, so disable pte prefetch if EPT is
2432          * enabled.
2433          */
2434         if (!shadow_accessed_mask)
2435                 return;
2436
2437         sp = page_header(__pa(sptep));
2438         if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2439                 return;
2440
2441         __direct_pte_prefetch(vcpu, sp, sptep);
2442 }
2443
2444 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2445                         int map_writable, int level, gfn_t gfn, pfn_t pfn,
2446                         bool prefault)
2447 {
2448         struct kvm_shadow_walk_iterator iterator;
2449         struct kvm_mmu_page *sp;
2450         int emulate = 0;
2451         gfn_t pseudo_gfn;
2452
2453         for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2454                 if (iterator.level == level) {
2455                         unsigned pte_access = ACC_ALL;
2456
2457                         mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2458                                      0, write, &emulate,
2459                                      level, gfn, pfn, prefault, map_writable);
2460                         direct_pte_prefetch(vcpu, iterator.sptep);
2461                         ++vcpu->stat.pf_fixed;
2462                         break;
2463                 }
2464
2465                 if (!is_shadow_present_pte(*iterator.sptep)) {
2466                         u64 base_addr = iterator.addr;
2467
2468                         base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2469                         pseudo_gfn = base_addr >> PAGE_SHIFT;
2470                         sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2471                                               iterator.level - 1,
2472                                               1, ACC_ALL, iterator.sptep);
2473                         if (!sp) {
2474                                 pgprintk("nonpaging_map: ENOMEM\n");
2475                                 kvm_release_pfn_clean(pfn);
2476                                 return -ENOMEM;
2477                         }
2478
2479                         mmu_spte_set(iterator.sptep,
2480                                      __pa(sp->spt)
2481                                      | PT_PRESENT_MASK | PT_WRITABLE_MASK
2482                                      | shadow_user_mask | shadow_x_mask
2483                                      | shadow_accessed_mask);
2484                 }
2485         }
2486         return emulate;
2487 }
2488
2489 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2490 {
2491         siginfo_t info;
2492
2493         info.si_signo   = SIGBUS;
2494         info.si_errno   = 0;
2495         info.si_code    = BUS_MCEERR_AR;
2496         info.si_addr    = (void __user *)address;
2497         info.si_addr_lsb = PAGE_SHIFT;
2498
2499         send_sig_info(SIGBUS, &info, tsk);
2500 }
2501
2502 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2503 {
2504         kvm_release_pfn_clean(pfn);
2505         if (is_hwpoison_pfn(pfn)) {
2506                 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2507                 return 0;
2508         }
2509
2510         return -EFAULT;
2511 }
2512
2513 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2514                                         gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2515 {
2516         pfn_t pfn = *pfnp;
2517         gfn_t gfn = *gfnp;
2518         int level = *levelp;
2519
2520         /*
2521          * Check if it's a transparent hugepage. If this would be an
2522          * hugetlbfs page, level wouldn't be set to
2523          * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2524          * here.
2525          */
2526         if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2527             level == PT_PAGE_TABLE_LEVEL &&
2528             PageTransCompound(pfn_to_page(pfn)) &&
2529             !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2530                 unsigned long mask;
2531                 /*
2532                  * mmu_notifier_retry was successful and we hold the
2533                  * mmu_lock here, so the pmd can't become splitting
2534                  * from under us, and in turn
2535                  * __split_huge_page_refcount() can't run from under
2536                  * us and we can safely transfer the refcount from
2537                  * PG_tail to PG_head as we switch the pfn to tail to
2538                  * head.
2539                  */
2540                 *levelp = level = PT_DIRECTORY_LEVEL;
2541                 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2542                 VM_BUG_ON((gfn & mask) != (pfn & mask));
2543                 if (pfn & mask) {
2544                         gfn &= ~mask;
2545                         *gfnp = gfn;
2546                         kvm_release_pfn_clean(pfn);
2547                         pfn &= ~mask;
2548                         if (!get_page_unless_zero(pfn_to_page(pfn)))
2549                                 BUG();
2550                         *pfnp = pfn;
2551                 }
2552         }
2553 }
2554
2555 static bool mmu_invalid_pfn(pfn_t pfn)
2556 {
2557         return unlikely(is_invalid_pfn(pfn));
2558 }
2559
2560 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2561                                 pfn_t pfn, unsigned access, int *ret_val)
2562 {
2563         bool ret = true;
2564
2565         /* The pfn is invalid, report the error! */
2566         if (unlikely(is_invalid_pfn(pfn))) {
2567                 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2568                 goto exit;
2569         }
2570
2571         if (unlikely(is_noslot_pfn(pfn)))
2572                 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2573
2574         ret = false;
2575 exit:
2576         return ret;
2577 }
2578
2579 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2580                          gva_t gva, pfn_t *pfn, bool write, bool *writable);
2581
2582 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2583                          bool prefault)
2584 {
2585         int r;
2586         int level;
2587         int force_pt_level;
2588         pfn_t pfn;
2589         unsigned long mmu_seq;
2590         bool map_writable;
2591
2592         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2593         if (likely(!force_pt_level)) {
2594                 level = mapping_level(vcpu, gfn);
2595                 /*
2596                  * This path builds a PAE pagetable - so we can map
2597                  * 2mb pages at maximum. Therefore check if the level
2598                  * is larger than that.
2599                  */
2600                 if (level > PT_DIRECTORY_LEVEL)
2601                         level = PT_DIRECTORY_LEVEL;
2602
2603                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2604         } else
2605                 level = PT_PAGE_TABLE_LEVEL;
2606
2607         mmu_seq = vcpu->kvm->mmu_notifier_seq;
2608         smp_rmb();
2609
2610         if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2611                 return 0;
2612
2613         if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2614                 return r;
2615
2616         spin_lock(&vcpu->kvm->mmu_lock);
2617         if (mmu_notifier_retry(vcpu, mmu_seq))
2618                 goto out_unlock;
2619         kvm_mmu_free_some_pages(vcpu);
2620         if (likely(!force_pt_level))
2621                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2622         r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2623                          prefault);
2624         spin_unlock(&vcpu->kvm->mmu_lock);
2625
2626
2627         return r;
2628
2629 out_unlock:
2630         spin_unlock(&vcpu->kvm->mmu_lock);
2631         kvm_release_pfn_clean(pfn);
2632         return 0;
2633 }
2634
2635
2636 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2637 {
2638         int i;
2639         struct kvm_mmu_page *sp;
2640         LIST_HEAD(invalid_list);
2641
2642         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2643                 return;
2644         spin_lock(&vcpu->kvm->mmu_lock);
2645         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2646             (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2647              vcpu->arch.mmu.direct_map)) {
2648                 hpa_t root = vcpu->arch.mmu.root_hpa;
2649
2650                 sp = page_header(root);
2651                 --sp->root_count;
2652                 if (!sp->root_count && sp->role.invalid) {
2653                         kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2654                         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2655                 }
2656                 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2657                 spin_unlock(&vcpu->kvm->mmu_lock);
2658                 return;
2659         }
2660         for (i = 0; i < 4; ++i) {
2661                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2662
2663                 if (root) {
2664                         root &= PT64_BASE_ADDR_MASK;
2665                         sp = page_header(root);
2666                         --sp->root_count;
2667                         if (!sp->root_count && sp->role.invalid)
2668                                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2669                                                          &invalid_list);
2670                 }
2671                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2672         }
2673         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2674         spin_unlock(&vcpu->kvm->mmu_lock);
2675         vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2676 }
2677
2678 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2679 {
2680         int ret = 0;
2681
2682         if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2683                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2684                 ret = 1;
2685         }
2686
2687         return ret;
2688 }
2689
2690 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2691 {
2692         struct kvm_mmu_page *sp;
2693         unsigned i;
2694
2695         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2696                 spin_lock(&vcpu->kvm->mmu_lock);
2697                 kvm_mmu_free_some_pages(vcpu);
2698                 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2699                                       1, ACC_ALL, NULL);
2700                 ++sp->root_count;
2701                 spin_unlock(&vcpu->kvm->mmu_lock);
2702                 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2703         } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2704                 for (i = 0; i < 4; ++i) {
2705                         hpa_t root = vcpu->arch.mmu.pae_root[i];
2706
2707                         ASSERT(!VALID_PAGE(root));
2708                         spin_lock(&vcpu->kvm->mmu_lock);
2709                         kvm_mmu_free_some_pages(vcpu);
2710                         sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2711                                               i << 30,
2712                                               PT32_ROOT_LEVEL, 1, ACC_ALL,
2713                                               NULL);
2714                         root = __pa(sp->spt);
2715                         ++sp->root_count;
2716                         spin_unlock(&vcpu->kvm->mmu_lock);
2717                         vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2718                 }
2719                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2720         } else
2721                 BUG();
2722
2723         return 0;
2724 }
2725
2726 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2727 {
2728         struct kvm_mmu_page *sp;
2729         u64 pdptr, pm_mask;
2730         gfn_t root_gfn;
2731         int i;
2732
2733         root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2734
2735         if (mmu_check_root(vcpu, root_gfn))
2736                 return 1;
2737
2738         /*
2739          * Do we shadow a long mode page table? If so we need to
2740          * write-protect the guests page table root.
2741          */
2742         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2743                 hpa_t root = vcpu->arch.mmu.root_hpa;
2744
2745                 ASSERT(!VALID_PAGE(root));
2746
2747                 spin_lock(&vcpu->kvm->mmu_lock);
2748                 kvm_mmu_free_some_pages(vcpu);
2749                 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2750                                       0, ACC_ALL, NULL);
2751                 root = __pa(sp->spt);
2752                 ++sp->root_count;
2753                 spin_unlock(&vcpu->kvm->mmu_lock);
2754                 vcpu->arch.mmu.root_hpa = root;
2755                 return 0;
2756         }
2757
2758         /*
2759          * We shadow a 32 bit page table. This may be a legacy 2-level
2760          * or a PAE 3-level page table. In either case we need to be aware that
2761          * the shadow page table may be a PAE or a long mode page table.
2762          */
2763         pm_mask = PT_PRESENT_MASK;
2764         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2765                 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2766
2767         for (i = 0; i < 4; ++i) {
2768                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2769
2770                 ASSERT(!VALID_PAGE(root));
2771                 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2772                         pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
2773                         if (!is_present_gpte(pdptr)) {
2774                                 vcpu->arch.mmu.pae_root[i] = 0;
2775                                 continue;
2776                         }
2777                         root_gfn = pdptr >> PAGE_SHIFT;
2778                         if (mmu_check_root(vcpu, root_gfn))
2779                                 return 1;
2780                 }
2781                 spin_lock(&vcpu->kvm->mmu_lock);
2782                 kvm_mmu_free_some_pages(vcpu);
2783                 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2784                                       PT32_ROOT_LEVEL, 0,
2785                                       ACC_ALL, NULL);
2786                 root = __pa(sp->spt);
2787                 ++sp->root_count;
2788                 spin_unlock(&vcpu->kvm->mmu_lock);
2789
2790                 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2791         }
2792         vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2793
2794         /*
2795          * If we shadow a 32 bit page table with a long mode page
2796          * table we enter this path.
2797          */
2798         if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2799                 if (vcpu->arch.mmu.lm_root == NULL) {
2800                         /*
2801                          * The additional page necessary for this is only
2802                          * allocated on demand.
2803                          */
2804
2805                         u64 *lm_root;
2806
2807                         lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2808                         if (lm_root == NULL)
2809                                 return 1;
2810
2811                         lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2812
2813                         vcpu->arch.mmu.lm_root = lm_root;
2814                 }
2815
2816                 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2817         }
2818
2819         return 0;
2820 }
2821
2822 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2823 {
2824         if (vcpu->arch.mmu.direct_map)
2825                 return mmu_alloc_direct_roots(vcpu);
2826         else
2827                 return mmu_alloc_shadow_roots(vcpu);
2828 }
2829
2830 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2831 {
2832         int i;
2833         struct kvm_mmu_page *sp;
2834
2835         if (vcpu->arch.mmu.direct_map)
2836                 return;
2837
2838         if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2839                 return;
2840
2841         vcpu_clear_mmio_info(vcpu, ~0ul);
2842         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2843         if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2844                 hpa_t root = vcpu->arch.mmu.root_hpa;
2845                 sp = page_header(root);
2846                 mmu_sync_children(vcpu, sp);
2847                 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2848                 return;
2849         }
2850         for (i = 0; i < 4; ++i) {
2851                 hpa_t root = vcpu->arch.mmu.pae_root[i];
2852
2853                 if (root && VALID_PAGE(root)) {
2854                         root &= PT64_BASE_ADDR_MASK;
2855                         sp = page_header(root);
2856                         mmu_sync_children(vcpu, sp);
2857                 }
2858         }
2859         trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2860 }
2861
2862 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2863 {
2864         spin_lock(&vcpu->kvm->mmu_lock);
2865         mmu_sync_roots(vcpu);
2866         spin_unlock(&vcpu->kvm->mmu_lock);
2867 }
2868
2869 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2870                                   u32 access, struct x86_exception *exception)
2871 {
2872         if (exception)
2873                 exception->error_code = 0;
2874         return vaddr;
2875 }
2876
2877 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2878                                          u32 access,
2879                                          struct x86_exception *exception)
2880 {
2881         if (exception)
2882                 exception->error_code = 0;
2883         return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2884 }
2885
2886 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2887 {
2888         if (direct)
2889                 return vcpu_match_mmio_gpa(vcpu, addr);
2890
2891         return vcpu_match_mmio_gva(vcpu, addr);
2892 }
2893
2894
2895 /*
2896  * On direct hosts, the last spte is only allows two states
2897  * for mmio page fault:
2898  *   - It is the mmio spte
2899  *   - It is zapped or it is being zapped.
2900  *
2901  * This function completely checks the spte when the last spte
2902  * is not the mmio spte.
2903  */
2904 static bool check_direct_spte_mmio_pf(u64 spte)
2905 {
2906         return __check_direct_spte_mmio_pf(spte);
2907 }
2908
2909 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2910 {
2911         struct kvm_shadow_walk_iterator iterator;
2912         u64 spte = 0ull;
2913
2914         walk_shadow_page_lockless_begin(vcpu);
2915         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2916                 if (!is_shadow_present_pte(spte))
2917                         break;
2918         walk_shadow_page_lockless_end(vcpu);
2919
2920         return spte;
2921 }
2922
2923 /*
2924  * If it is a real mmio page fault, return 1 and emulat the instruction
2925  * directly, return 0 to let CPU fault again on the address, -1 is
2926  * returned if bug is detected.
2927  */
2928 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2929 {
2930         u64 spte;
2931
2932         if (quickly_check_mmio_pf(vcpu, addr, direct))
2933                 return 1;
2934
2935         spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2936
2937         if (is_mmio_spte(spte)) {
2938                 gfn_t gfn = get_mmio_spte_gfn(spte);
2939                 unsigned access = get_mmio_spte_access(spte);
2940
2941                 if (direct)
2942                         addr = 0;
2943
2944                 trace_handle_mmio_page_fault(addr, gfn, access);
2945                 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
2946                 return 1;
2947         }
2948
2949         /*
2950          * It's ok if the gva is remapped by other cpus on shadow guest,
2951          * it's a BUG if the gfn is not a mmio page.
2952          */
2953         if (direct && !check_direct_spte_mmio_pf(spte))
2954                 return -1;
2955
2956         /*
2957          * If the page table is zapped by other cpus, let CPU fault again on
2958          * the address.
2959          */
2960         return 0;
2961 }
2962 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
2963
2964 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
2965                                   u32 error_code, bool direct)
2966 {
2967         int ret;
2968
2969         ret = handle_mmio_page_fault_common(vcpu, addr, direct);
2970         WARN_ON(ret < 0);
2971         return ret;
2972 }
2973
2974 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2975                                 u32 error_code, bool prefault)
2976 {
2977         gfn_t gfn;
2978         int r;
2979
2980         pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2981
2982         if (unlikely(error_code & PFERR_RSVD_MASK))
2983                 return handle_mmio_page_fault(vcpu, gva, error_code, true);
2984
2985         r = mmu_topup_memory_caches(vcpu);
2986         if (r)
2987                 return r;
2988
2989         ASSERT(vcpu);
2990         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2991
2992         gfn = gva >> PAGE_SHIFT;
2993
2994         return nonpaging_map(vcpu, gva & PAGE_MASK,
2995                              error_code & PFERR_WRITE_MASK, gfn, prefault);
2996 }
2997
2998 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
2999 {
3000         struct kvm_arch_async_pf arch;
3001
3002         arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3003         arch.gfn = gfn;
3004         arch.direct_map = vcpu->arch.mmu.direct_map;
3005         arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3006
3007         return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3008 }
3009
3010 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3011 {
3012         if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3013                      kvm_event_needs_reinjection(vcpu)))
3014                 return false;
3015
3016         return kvm_x86_ops->interrupt_allowed(vcpu);
3017 }
3018
3019 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3020                          gva_t gva, pfn_t *pfn, bool write, bool *writable)
3021 {
3022         bool async;
3023
3024         *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3025
3026         if (!async)
3027                 return false; /* *pfn has correct page already */
3028
3029         put_page(pfn_to_page(*pfn));
3030
3031         if (!prefault && can_do_async_pf(vcpu)) {
3032                 trace_kvm_try_async_get_page(gva, gfn);
3033                 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3034                         trace_kvm_async_pf_doublefault(gva, gfn);
3035                         kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3036                         return true;
3037                 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3038                         return true;
3039         }
3040
3041         *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3042
3043         return false;
3044 }
3045
3046 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3047                           bool prefault)
3048 {
3049         pfn_t pfn;
3050         int r;
3051         int level;
3052         int force_pt_level;
3053         gfn_t gfn = gpa >> PAGE_SHIFT;
3054         unsigned long mmu_seq;
3055         int write = error_code & PFERR_WRITE_MASK;
3056         bool map_writable;
3057
3058         ASSERT(vcpu);
3059         ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3060
3061         if (unlikely(error_code & PFERR_RSVD_MASK))
3062                 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3063
3064         r = mmu_topup_memory_caches(vcpu);
3065         if (r)
3066                 return r;
3067
3068         force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3069         if (likely(!force_pt_level)) {
3070                 level = mapping_level(vcpu, gfn);
3071                 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3072         } else
3073                 level = PT_PAGE_TABLE_LEVEL;
3074
3075         mmu_seq = vcpu->kvm->mmu_notifier_seq;
3076         smp_rmb();
3077
3078         if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3079                 return 0;
3080
3081         if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3082                 return r;
3083
3084         spin_lock(&vcpu->kvm->mmu_lock);
3085         if (mmu_notifier_retry(vcpu, mmu_seq))
3086                 goto out_unlock;
3087         kvm_mmu_free_some_pages(vcpu);
3088         if (likely(!force_pt_level))
3089                 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3090         r = __direct_map(vcpu, gpa, write, map_writable,
3091                          level, gfn, pfn, prefault);
3092         spin_unlock(&vcpu->kvm->mmu_lock);
3093
3094         return r;
3095
3096 out_unlock:
3097         spin_unlock(&vcpu->kvm->mmu_lock);
3098         kvm_release_pfn_clean(pfn);
3099         return 0;
3100 }
3101
3102 static void nonpaging_free(struct kvm_vcpu *vcpu)
3103 {
3104         mmu_free_roots(vcpu);
3105 }
3106
3107 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3108                                   struct kvm_mmu *context)
3109 {
3110         context->new_cr3 = nonpaging_new_cr3;
3111         context->page_fault = nonpaging_page_fault;
3112         context->gva_to_gpa = nonpaging_gva_to_gpa;
3113         context->free = nonpaging_free;
3114         context->sync_page = nonpaging_sync_page;
3115         context->invlpg = nonpaging_invlpg;
3116         context->update_pte = nonpaging_update_pte;
3117         context->root_level = 0;
3118         context->shadow_root_level = PT32E_ROOT_LEVEL;
3119         context->root_hpa = INVALID_PAGE;
3120         context->direct_map = true;
3121         context->nx = false;
3122         return 0;
3123 }
3124
3125 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3126 {
3127         ++vcpu->stat.tlb_flush;
3128         kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3129 }
3130
3131 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3132 {
3133         pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3134         mmu_free_roots(vcpu);
3135 }
3136
3137 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3138 {
3139         return kvm_read_cr3(vcpu);
3140 }
3141
3142 static void inject_page_fault(struct kvm_vcpu *vcpu,
3143                               struct x86_exception *fault)
3144 {
3145         vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3146 }
3147
3148 static void paging_free(struct kvm_vcpu *vcpu)
3149 {
3150         nonpaging_free(vcpu);
3151 }
3152
3153 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3154 {
3155         int bit7;
3156
3157         bit7 = (gpte >> 7) & 1;
3158         return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3159 }
3160
3161 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3162                            int *nr_present)
3163 {
3164         if (unlikely(is_mmio_spte(*sptep))) {
3165                 if (gfn != get_mmio_spte_gfn(*sptep)) {
3166                         mmu_spte_clear_no_track(sptep);
3167                         return true;
3168                 }
3169
3170                 (*nr_present)++;
3171                 mark_mmio_spte(sptep, gfn, access);
3172                 return true;
3173         }
3174
3175         return false;
3176 }
3177
3178 #define PTTYPE 64
3179 #include "paging_tmpl.h"
3180 #undef PTTYPE
3181
3182 #define PTTYPE 32
3183 #include "paging_tmpl.h"
3184 #undef PTTYPE
3185
3186 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3187                                   struct kvm_mmu *context,
3188                                   int level)
3189 {
3190         int maxphyaddr = cpuid_maxphyaddr(vcpu);
3191         u64 exb_bit_rsvd = 0;
3192
3193         if (!context->nx)
3194                 exb_bit_rsvd = rsvd_bits(63, 63);
3195         switch (level) {
3196         case PT32_ROOT_LEVEL:
3197                 /* no rsvd bits for 2 level 4K page table entries */
3198                 context->rsvd_bits_mask[0][1] = 0;
3199                 context->rsvd_bits_mask[0][0] = 0;
3200                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3201
3202                 if (!is_pse(vcpu)) {
3203                         context->rsvd_bits_mask[1][1] = 0;
3204                         break;
3205                 }
3206
3207                 if (is_cpuid_PSE36())
3208                         /* 36bits PSE 4MB page */
3209                         context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3210                 else
3211                         /* 32 bits PSE 4MB page */
3212                         context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3213                 break;
3214         case PT32E_ROOT_LEVEL:
3215                 context->rsvd_bits_mask[0][2] =
3216                         rsvd_bits(maxphyaddr, 63) |
3217                         rsvd_bits(7, 8) | rsvd_bits(1, 2);      /* PDPTE */
3218                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3219                         rsvd_bits(maxphyaddr, 62);      /* PDE */
3220                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3221                         rsvd_bits(maxphyaddr, 62);      /* PTE */
3222                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3223                         rsvd_bits(maxphyaddr, 62) |
3224                         rsvd_bits(13, 20);              /* large page */
3225                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3226                 break;
3227         case PT64_ROOT_LEVEL:
3228                 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3229                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3230                 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3231                         rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3232                 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3233                         rsvd_bits(maxphyaddr, 51);
3234                 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3235                         rsvd_bits(maxphyaddr, 51);
3236                 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3237                 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3238                         rsvd_bits(maxphyaddr, 51) |
3239                         rsvd_bits(13, 29);
3240                 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3241                         rsvd_bits(maxphyaddr, 51) |
3242                         rsvd_bits(13, 20);              /* large page */
3243                 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3244                 break;
3245         }
3246 }
3247
3248 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3249                                         struct kvm_mmu *context,
3250                                         int level)
3251 {
3252         context->nx = is_nx(vcpu);
3253
3254         reset_rsvds_bits_mask(vcpu, context, level);
3255
3256         ASSERT(is_pae(vcpu));
3257         context->new_cr3 = paging_new_cr3;
3258         context->page_fault = paging64_page_fault;
3259         context->gva_to_gpa = paging64_gva_to_gpa;
3260         context->sync_page = paging64_sync_page;
3261         context->invlpg = paging64_invlpg;
3262         context->update_pte = paging64_update_pte;
3263         context->free = paging_free;
3264         context->root_level = level;
3265         context->shadow_root_level = level;
3266         context->root_hpa = INVALID_PAGE;
3267         context->direct_map = false;
3268         return 0;
3269 }
3270
3271 static int paging64_init_context(struct kvm_vcpu *vcpu,
3272                                  struct kvm_mmu *context)
3273 {
3274         return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3275 }
3276
3277 static int paging32_init_context(struct kvm_vcpu *vcpu,
3278                                  struct kvm_mmu *context)
3279 {
3280         context->nx = false;
3281
3282         reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3283
3284         context->new_cr3 = paging_new_cr3;
3285         context->page_fault = paging32_page_fault;
3286         context->gva_to_gpa = paging32_gva_to_gpa;
3287         context->free = paging_free;
3288         context->sync_page = paging32_sync_page;
3289         context->invlpg = paging32_invlpg;
3290         context->update_pte = paging32_update_pte;
3291         context->root_level = PT32_ROOT_LEVEL;
3292         context->shadow_root_level = PT32E_ROOT_LEVEL;
3293         context->root_hpa = INVALID_PAGE;
3294         context->direct_map = false;
3295         return 0;
3296 }
3297
3298 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3299                                   struct kvm_mmu *context)
3300 {
3301         return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3302 }
3303
3304 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3305 {
3306         struct kvm_mmu *context = vcpu->arch.walk_mmu;
3307
3308         context->base_role.word = 0;
3309         context->new_cr3 = nonpaging_new_cr3;
3310         context->page_fault = tdp_page_fault;
3311         context->free = nonpaging_free;
3312         context->sync_page = nonpaging_sync_page;
3313         context->invlpg = nonpaging_invlpg;
3314         context->update_pte = nonpaging_update_pte;
3315         context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3316         context->root_hpa = INVALID_PAGE;
3317         context->direct_map = true;
3318         context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3319         context->get_cr3 = get_cr3;
3320         context->inject_page_fault = kvm_inject_page_fault;
3321         context->nx = is_nx(vcpu);
3322
3323         if (!is_paging(vcpu)) {
3324                 context->nx = false;
3325                 context->gva_to_gpa = nonpaging_gva_to_gpa;
3326                 context->root_level = 0;
3327         } else if (is_long_mode(vcpu)) {
3328                 context->nx = is_nx(vcpu);
3329                 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3330                 context->gva_to_gpa = paging64_gva_to_gpa;
3331                 context->root_level = PT64_ROOT_LEVEL;
3332         } else if (is_pae(vcpu)) {
3333                 context->nx = is_nx(vcpu);
3334                 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3335                 context->gva_to_gpa = paging64_gva_to_gpa;
3336                 context->root_level = PT32E_ROOT_LEVEL;
3337         } else {
3338                 context->nx = false;
3339                 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3340                 context->gva_to_gpa = paging32_gva_to_gpa;
3341                 context->root_level = PT32_ROOT_LEVEL;
3342         }
3343
3344         return 0;
3345 }
3346
3347 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3348 {
3349         int r;
3350         bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3351         ASSERT(vcpu);
3352         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3353
3354         if (!is_paging(vcpu))
3355                 r = nonpaging_init_context(vcpu, context);
3356         else if (is_long_mode(vcpu))
3357                 r = paging64_init_context(vcpu, context);
3358         else if (is_pae(vcpu))
3359                 r = paging32E_init_context(vcpu, context);
3360         else
3361                 r = paging32_init_context(vcpu, context);
3362
3363         vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3364         vcpu->arch.mmu.base_role.cr0_wp  = is_write_protection(vcpu);
3365         vcpu->arch.mmu.base_role.smep_andnot_wp
3366                 = smep && !is_write_protection(vcpu);
3367
3368         return r;
3369 }
3370 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3371
3372 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3373 {
3374         int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3375
3376         vcpu->arch.walk_mmu->set_cr3           = kvm_x86_ops->set_cr3;
3377         vcpu->arch.walk_mmu->get_cr3           = get_cr3;
3378         vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3379
3380         return r;
3381 }
3382
3383 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3384 {
3385         struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3386
3387         g_context->get_cr3           = get_cr3;
3388         g_context->inject_page_fault = kvm_inject_page_fault;
3389
3390         /*
3391          * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3392          * translation of l2_gpa to l1_gpa addresses is done using the
3393          * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3394          * functions between mmu and nested_mmu are swapped.
3395          */
3396         if (!is_paging(vcpu)) {
3397                 g_context->nx = false;
3398                 g_context->root_level = 0;
3399                 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3400         } else if (is_long_mode(vcpu)) {
3401                 g_context->nx = is_nx(vcpu);
3402                 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3403                 g_context->root_level = PT64_ROOT_LEVEL;
3404                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3405         } else if (is_pae(vcpu)) {
3406                 g_context->nx = is_nx(vcpu);
3407                 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3408                 g_context->root_level = PT32E_ROOT_LEVEL;
3409                 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3410         } else {
3411                 g_context->nx = false;
3412                 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3413                 g_context->root_level = PT32_ROOT_LEVEL;
3414                 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3415         }
3416
3417         return 0;
3418 }
3419
3420 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3421 {
3422         if (mmu_is_nested(vcpu))
3423                 return init_kvm_nested_mmu(vcpu);
3424         else if (tdp_enabled)
3425                 return init_kvm_tdp_mmu(vcpu);
3426         else
3427                 return init_kvm_softmmu(vcpu);
3428 }
3429
3430 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3431 {
3432         ASSERT(vcpu);
3433         if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3434                 /* mmu.free() should set root_hpa = INVALID_PAGE */
3435                 vcpu->arch.mmu.free(vcpu);
3436 }
3437
3438 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3439 {
3440         destroy_kvm_mmu(vcpu);
3441         return init_kvm_mmu(vcpu);
3442 }
3443 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3444
3445 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3446 {
3447         int r;
3448
3449         r = mmu_topup_memory_caches(vcpu);
3450         if (r)
3451                 goto out;
3452         r = mmu_alloc_roots(vcpu);
3453         spin_lock(&vcpu->kvm->mmu_lock);
3454         mmu_sync_roots(vcpu);
3455         spin_unlock(&vcpu->kvm->mmu_lock);
3456         if (r)
3457                 goto out;
3458         /* set_cr3() should ensure TLB has been flushed */
3459         vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3460 out:
3461         return r;
3462 }
3463 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3464
3465 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3466 {
3467         mmu_free_roots(vcpu);
3468 }
3469 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3470
3471 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3472                                   struct kvm_mmu_page *sp, u64 *spte,
3473                                   const void *new)
3474 {
3475         if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3476                 ++vcpu->kvm->stat.mmu_pde_zapped;
3477                 return;
3478         }
3479
3480         ++vcpu->kvm->stat.mmu_pte_updated;
3481         vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3482 }
3483
3484 static bool need_remote_flush(u64 old, u64 new)
3485 {
3486         if (!is_shadow_present_pte(old))
3487                 return false;
3488         if (!is_shadow_present_pte(new))
3489                 return true;
3490         if ((old ^ new) & PT64_BASE_ADDR_MASK)
3491                 return true;
3492         old ^= PT64_NX_MASK;
3493         new ^= PT64_NX_MASK;
3494         return (old & ~new & PT64_PERM_MASK) != 0;
3495 }
3496
3497 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3498                                     bool remote_flush, bool local_flush)
3499 {
3500         if (zap_page)
3501                 return;
3502
3503         if (remote_flush)
3504                 kvm_flush_remote_tlbs(vcpu->kvm);
3505         else if (local_flush)
3506                 kvm_mmu_flush_tlb(vcpu);
3507 }
3508
3509 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3510 {
3511         u64 *spte = vcpu->arch.last_pte_updated;
3512
3513         return !!(spte && (*spte & shadow_accessed_mask));
3514 }
3515
3516 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3517 {
3518         u64 *spte = vcpu->arch.last_pte_updated;
3519
3520         if (spte
3521             && vcpu->arch.last_pte_gfn == gfn
3522             && shadow_accessed_mask
3523             && !(*spte & shadow_accessed_mask)
3524             && is_shadow_present_pte(*spte))
3525                 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3526 }
3527
3528 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3529                        const u8 *new, int bytes,
3530                        bool guest_initiated)
3531 {
3532         gfn_t gfn = gpa >> PAGE_SHIFT;
3533         union kvm_mmu_page_role mask = { .word = 0 };
3534         struct kvm_mmu_page *sp;
3535         struct hlist_node *node;
3536         LIST_HEAD(invalid_list);
3537         u64 entry, gentry, *spte;
3538         unsigned pte_size, page_offset, misaligned, quadrant, offset;
3539         int level, npte, invlpg_counter, r, flooded = 0;
3540         bool remote_flush, local_flush, zap_page;
3541
3542         /*
3543          * If we don't have indirect shadow pages, it means no page is
3544          * write-protected, so we can exit simply.
3545          */
3546         if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3547                 return;
3548
3549         zap_page = remote_flush = local_flush = false;
3550         offset = offset_in_page(gpa);
3551
3552         pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3553
3554         invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
3555
3556         /*
3557          * Assume that the pte write on a page table of the same type
3558          * as the current vcpu paging mode since we update the sptes only
3559          * when they have the same mode.
3560          */
3561         if ((is_pae(vcpu) && bytes == 4) || !new) {
3562                 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3563                 if (is_pae(vcpu)) {
3564                         gpa &= ~(gpa_t)7;
3565                         bytes = 8;
3566                 }
3567                 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
3568                 if (r)
3569                         gentry = 0;
3570                 new = (const u8 *)&gentry;
3571         }
3572
3573         switch (bytes) {
3574         case 4:
3575                 gentry = *(const u32 *)new;
3576                 break;
3577         case 8:
3578                 gentry = *(const u64 *)new;
3579                 break;
3580         default:
3581                 gentry = 0;
3582                 break;
3583         }
3584
3585         spin_lock(&vcpu->kvm->mmu_lock);
3586         if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3587                 gentry = 0;
3588         kvm_mmu_free_some_pages(vcpu);
3589         ++vcpu->kvm->stat.mmu_pte_write;
3590         trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3591         if (guest_initiated) {
3592                 kvm_mmu_access_page(vcpu, gfn);
3593                 if (gfn == vcpu->arch.last_pt_write_gfn
3594                     && !last_updated_pte_accessed(vcpu)) {
3595                         ++vcpu->arch.last_pt_write_count;
3596                         if (vcpu->arch.last_pt_write_count >= 3)
3597                                 flooded = 1;
3598                 } else {
3599                         vcpu->arch.last_pt_write_gfn = gfn;
3600                         vcpu->arch.last_pt_write_count = 1;
3601                         vcpu->arch.last_pte_updated = NULL;
3602                 }
3603         }
3604
3605         mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3606         for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3607                 pte_size = sp->role.cr4_pae ? 8 : 4;
3608                 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3609                 misaligned |= bytes < 4;
3610                 if (misaligned || flooded) {
3611                         /*
3612                          * Misaligned accesses are too much trouble to fix
3613                          * up; also, they usually indicate a page is not used
3614                          * as a page table.
3615                          *
3616                          * If we're seeing too many writes to a page,
3617                          * it may no longer be a page table, or we may be
3618                          * forking, in which case it is better to unmap the
3619                          * page.
3620                          */
3621                         pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3622                                  gpa, bytes, sp->role.word);
3623                         zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3624                                                      &invalid_list);
3625                         ++vcpu->kvm->stat.mmu_flooded;
3626                         continue;
3627                 }
3628                 page_offset = offset;
3629                 level = sp->role.level;
3630                 npte = 1;
3631                 if (!sp->role.cr4_pae) {
3632                         page_offset <<= 1;      /* 32->64 */
3633                         /*
3634                          * A 32-bit pde maps 4MB while the shadow pdes map
3635                          * only 2MB.  So we need to double the offset again
3636                          * and zap two pdes instead of one.
3637                          */
3638                         if (level == PT32_ROOT_LEVEL) {
3639                                 page_offset &= ~7; /* kill rounding error */
3640                                 page_offset <<= 1;
3641                                 npte = 2;
3642                         }
3643                         quadrant = page_offset >> PAGE_SHIFT;
3644                         page_offset &= ~PAGE_MASK;
3645                         if (quadrant != sp->role.quadrant)
3646                                 continue;
3647                 }
3648                 local_flush = true;
3649                 spte = &sp->spt[page_offset / sizeof(*spte)];
3650                 while (npte--) {
3651                         entry = *spte;
3652                         mmu_page_zap_pte(vcpu->kvm, sp, spte);
3653                         if (gentry &&
3654                               !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3655                               & mask.word))
3656                                 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3657                         if (!remote_flush && need_remote_flush(entry, *spte))
3658                                 remote_flush = true;
3659                         ++spte;
3660                 }
3661         }
3662         mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3663         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3664         trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3665         spin_unlock(&vcpu->kvm->mmu_lock);
3666 }
3667
3668 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3669 {
3670         gpa_t gpa;
3671         int r;
3672
3673         if (vcpu->arch.mmu.direct_map)
3674                 return 0;
3675
3676         gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3677
3678         spin_lock(&vcpu->kvm->mmu_lock);
3679         r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3680         spin_unlock(&vcpu->kvm->mmu_lock);
3681         return r;
3682 }
3683 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3684
3685 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3686 {
3687         LIST_HEAD(invalid_list);
3688
3689         while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3690                !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3691                 struct kvm_mmu_page *sp;
3692
3693                 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3694                                   struct kvm_mmu_page, link);
3695                 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3696                 ++vcpu->kvm->stat.mmu_recycled;
3697         }
3698         kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3699 }
3700
3701 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3702                        void *insn, int insn_len)
3703 {
3704         int r;
3705         enum emulation_result er;
3706
3707         r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3708         if (r < 0)
3709                 goto out;
3710
3711         if (!r) {
3712                 r = 1;
3713                 goto out;
3714         }
3715
3716         r = mmu_topup_memory_caches(vcpu);
3717         if (r)
3718                 goto out;
3719
3720         er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
3721
3722         switch (er) {
3723         case EMULATE_DONE:
3724                 return 1;
3725         case EMULATE_DO_MMIO:
3726                 ++vcpu->stat.mmio_exits;
3727                 /* fall through */
3728         case EMULATE_FAIL:
3729                 return 0;
3730         default:
3731                 BUG();
3732         }
3733 out:
3734         return r;
3735 }
3736 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3737
3738 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3739 {
3740         vcpu->arch.mmu.invlpg(vcpu, gva);
3741         kvm_mmu_flush_tlb(vcpu);
3742         ++vcpu->stat.invlpg;
3743 }
3744 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3745
3746 void kvm_enable_tdp(void)
3747 {
3748         tdp_enabled = true;
3749 }
3750 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3751
3752 void kvm_disable_tdp(void)
3753 {
3754         tdp_enabled = false;
3755 }
3756 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3757
3758 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3759 {
3760         free_page((unsigned long)vcpu->arch.mmu.pae_root);
3761         if (vcpu->arch.mmu.lm_root != NULL)
3762                 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3763 }
3764
3765 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3766 {
3767         struct page *page;
3768         int i;
3769
3770         ASSERT(vcpu);
3771
3772         /*
3773          * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3774          * Therefore we need to allocate shadow page tables in the first
3775          * 4GB of memory, which happens to fit the DMA32 zone.
3776          */
3777         page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3778         if (!page)
3779                 return -ENOMEM;
3780
3781         vcpu->arch.mmu.pae_root = page_address(page);
3782         for (i = 0; i < 4; ++i)
3783                 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3784
3785         return 0;
3786 }
3787
3788 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3789 {
3790         ASSERT(vcpu);
3791         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3792
3793         return alloc_mmu_pages(vcpu);
3794 }
3795
3796 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3797 {
3798         ASSERT(vcpu);
3799         ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3800
3801         return init_kvm_mmu(vcpu);
3802 }
3803
3804 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3805 {
3806         struct kvm_mmu_page *sp;
3807
3808         list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3809                 int i;
3810                 u64 *pt;
3811
3812                 if (!test_bit(slot, sp->slot_bitmap))
3813                         continue;
3814
3815                 pt = sp->spt;
3816                 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3817                         if (!is_shadow_present_pte(pt[i]) ||
3818                               !is_last_spte(pt[i], sp->role.level))
3819                                 continue;
3820
3821                         if (is_large_pte(pt[i])) {
3822                                 drop_spte(kvm, &pt[i]);
3823                                 --kvm->stat.lpages;
3824                                 continue;
3825                         }
3826
3827                         /* avoid RMW */
3828                         if (is_writable_pte(pt[i]))
3829                                 mmu_spte_update(&pt[i],
3830                                                 pt[i] & ~PT_WRITABLE_MASK);
3831                 }
3832         }
3833         kvm_flush_remote_tlbs(kvm);
3834 }
3835
3836 void kvm_mmu_zap_all(struct kvm *kvm)
3837 {
3838         struct kvm_mmu_page *sp, *node;
3839         LIST_HEAD(invalid_list);
3840
3841         spin_lock(&kvm->mmu_lock);
3842 restart:
3843         list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3844                 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3845                         goto restart;
3846
3847         kvm_mmu_commit_zap_page(kvm, &invalid_list);
3848         spin_unlock(&kvm->mmu_lock);
3849 }
3850
3851 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3852                                                struct list_head *invalid_list)
3853 {
3854         struct kvm_mmu_page *page;
3855
3856         page = container_of(kvm->arch.active_mmu_pages.prev,
3857                             struct kvm_mmu_page, link);
3858         return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3859 }
3860
3861 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3862 {
3863         struct kvm *kvm;
3864         struct kvm *kvm_freed = NULL;
3865         int nr_to_scan = sc->nr_to_scan;
3866
3867         if (nr_to_scan == 0)
3868                 goto out;
3869
3870         raw_spin_lock(&kvm_lock);
3871
3872         list_for_each_entry(kvm, &vm_list, vm_list) {
3873                 int idx, freed_pages;
3874                 LIST_HEAD(invalid_list);
3875
3876                 idx = srcu_read_lock(&kvm->srcu);
3877                 spin_lock(&kvm->mmu_lock);
3878                 if (!kvm_freed && nr_to_scan > 0 &&
3879                     kvm->arch.n_used_mmu_pages > 0) {
3880                         freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3881                                                           &invalid_list);
3882                         kvm_freed = kvm;
3883                 }
3884                 nr_to_scan--;
3885
3886                 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3887                 spin_unlock(&kvm->mmu_lock);
3888                 srcu_read_unlock(&kvm->srcu, idx);
3889         }
3890         if (kvm_freed)
3891                 list_move_tail(&kvm_freed->vm_list, &vm_list);
3892
3893         raw_spin_unlock(&kvm_lock);
3894
3895 out:
3896         return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3897 }
3898
3899 static struct shrinker mmu_shrinker = {
3900         .shrink = mmu_shrink,
3901         .seeks = DEFAULT_SEEKS * 10,
3902 };
3903
3904 static void mmu_destroy_caches(void)
3905 {
3906         if (pte_list_desc_cache)
3907                 kmem_cache_destroy(pte_list_desc_cache);
3908         if (mmu_page_header_cache)
3909                 kmem_cache_destroy(mmu_page_header_cache);
3910 }
3911
3912 int kvm_mmu_module_init(void)
3913 {
3914         pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3915                                             sizeof(struct pte_list_desc),
3916                                             0, 0, NULL);
3917         if (!pte_list_desc_cache)
3918                 goto nomem;
3919
3920         mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3921                                                   sizeof(struct kvm_mmu_page),
3922                                                   0, 0, NULL);
3923         if (!mmu_page_header_cache)
3924                 goto nomem;
3925
3926         if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3927                 goto nomem;
3928
3929         register_shrinker(&mmu_shrinker);
3930
3931         return 0;
3932
3933 nomem:
3934         mmu_destroy_caches();
3935         return -ENOMEM;
3936 }
3937
3938 /*
3939  * Caculate mmu pages needed for kvm.
3940  */
3941 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3942 {
3943         int i;
3944         unsigned int nr_mmu_pages;
3945         unsigned int  nr_pages = 0;
3946         struct kvm_memslots *slots;
3947
3948         slots = kvm_memslots(kvm);
3949
3950         for (i = 0; i < slots->nmemslots; i++)
3951                 nr_pages += slots->memslots[i].npages;
3952
3953         nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3954         nr_mmu_pages = max(nr_mmu_pages,
3955                         (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3956
3957         return nr_mmu_pages;
3958 }
3959
3960 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3961                                 unsigned len)
3962 {
3963         if (len > buffer->len)
3964                 return NULL;
3965         return buffer->ptr;
3966 }
3967
3968 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3969                                 unsigned len)
3970 {
3971         void *ret;
3972
3973         ret = pv_mmu_peek_buffer(buffer, len);
3974         if (!ret)
3975                 return ret;
3976         buffer->ptr += len;
3977         buffer->len -= len;
3978         buffer->processed += len;
3979         return ret;
3980 }
3981
3982 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3983                              gpa_t addr, gpa_t value)
3984 {
3985         int bytes = 8;
3986         int r;
3987
3988         if (!is_long_mode(vcpu) && !is_pae(vcpu))
3989                 bytes = 4;
3990
3991         r = mmu_topup_memory_caches(vcpu);
3992         if (r)
3993                 return r;
3994
3995         if (!emulator_write_phys(vcpu, addr, &value, bytes))
3996                 return -EFAULT;
3997
3998         return 1;
3999 }
4000
4001 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
4002 {
4003         (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
4004         return 1;
4005 }
4006
4007 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
4008 {
4009         spin_lock(&vcpu->kvm->mmu_lock);
4010         mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
4011         spin_unlock(&vcpu->kvm->mmu_lock);
4012         return 1;
4013 }
4014
4015 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
4016                              struct kvm_pv_mmu_op_buffer *buffer)
4017 {
4018         struct kvm_mmu_op_header *header;
4019
4020         header = pv_mmu_peek_buffer(buffer, sizeof *header);
4021         if (!header)
4022                 return 0;
4023         switch (header->op) {
4024         case KVM_MMU_OP_WRITE_PTE: {
4025                 struct kvm_mmu_op_write_pte *wpte;
4026
4027                 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
4028                 if (!wpte)
4029                         return 0;
4030                 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
4031                                         wpte->pte_val);
4032         }
4033         case KVM_MMU_OP_FLUSH_TLB: {
4034                 struct kvm_mmu_op_flush_tlb *ftlb;
4035
4036                 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
4037                 if (!ftlb)
4038                         return 0;
4039                 return kvm_pv_mmu_flush_tlb(vcpu);
4040         }
4041         case KVM_MMU_OP_RELEASE_PT: {
4042                 struct kvm_mmu_op_release_pt *rpt;
4043
4044                 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
4045                 if (!rpt)
4046                         return 0;
4047                 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
4048         }
4049         default: return 0;
4050         }
4051 }
4052
4053 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
4054                   gpa_t addr, unsigned long *ret)
4055 {
4056         int r;
4057         struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
4058
4059         buffer->ptr = buffer->buf;
4060         buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
4061         buffer->processed = 0;
4062
4063         r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
4064         if (r)
4065                 goto out;
4066
4067         while (buffer->len) {
4068                 r = kvm_pv_mmu_op_one(vcpu, buffer);
4069                 if (r < 0)
4070                         goto out;
4071                 if (r == 0)
4072                         break;
4073         }
4074
4075         r = 1;
4076 out:
4077         *ret = buffer->processed;
4078         return r;
4079 }
4080
4081 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4082 {
4083         struct kvm_shadow_walk_iterator iterator;
4084         u64 spte;
4085         int nr_sptes = 0;
4086
4087         walk_shadow_page_lockless_begin(vcpu);
4088         for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4089                 sptes[iterator.level-1] = spte;
4090                 nr_sptes++;
4091                 if (!is_shadow_present_pte(spte))
4092                         break;
4093         }
4094         walk_shadow_page_lockless_end(vcpu);
4095
4096         return nr_sptes;
4097 }
4098 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4099
4100 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4101 {
4102         ASSERT(vcpu);
4103
4104         destroy_kvm_mmu(vcpu);
4105         free_mmu_pages(vcpu);
4106         mmu_free_memory_caches(vcpu);
4107 }
4108
4109 #ifdef CONFIG_KVM_MMU_AUDIT
4110 #include "mmu_audit.c"
4111 #else
4112 static void mmu_audit_disable(void) { }
4113 #endif
4114
4115 void kvm_mmu_module_exit(void)
4116 {
4117         mmu_destroy_caches();
4118         percpu_counter_destroy(&kvm_total_used_mmu_pages);
4119         unregister_shrinker(&mmu_shrinker);
4120         mmu_audit_disable();
4121 }