KVM: Add irq ack notifier list
[linux-2.6.git] / arch / x86 / kvm / i8259.c
1 /*
2  * 8259 interrupt controller emulation
3  *
4  * Copyright (c) 2003-2004 Fabrice Bellard
5  * Copyright (c) 2007 Intel Corporation
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a copy
8  * of this software and associated documentation files (the "Software"), to deal
9  * in the Software without restriction, including without limitation the rights
10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11  * copies of the Software, and to permit persons to whom the Software is
12  * furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice shall be included in
15  * all copies or substantial portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23  * THE SOFTWARE.
24  * Authors:
25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
26  *   Port from Qemu.
27  */
28 #include <linux/mm.h>
29 #include "irq.h"
30
31 #include <linux/kvm_host.h>
32
33 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
34 {
35         s->isr &= ~(1 << irq);
36 }
37
38 /*
39  * set irq level. If an edge is detected, then the IRR is set to 1
40  */
41 static inline void pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
42 {
43         int mask;
44         mask = 1 << irq;
45         if (s->elcr & mask)     /* level triggered */
46                 if (level) {
47                         s->irr |= mask;
48                         s->last_irr |= mask;
49                 } else {
50                         s->irr &= ~mask;
51                         s->last_irr &= ~mask;
52                 }
53         else    /* edge triggered */
54                 if (level) {
55                         if ((s->last_irr & mask) == 0)
56                                 s->irr |= mask;
57                         s->last_irr |= mask;
58                 } else
59                         s->last_irr &= ~mask;
60 }
61
62 /*
63  * return the highest priority found in mask (highest = smallest
64  * number). Return 8 if no irq
65  */
66 static inline int get_priority(struct kvm_kpic_state *s, int mask)
67 {
68         int priority;
69         if (mask == 0)
70                 return 8;
71         priority = 0;
72         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
73                 priority++;
74         return priority;
75 }
76
77 /*
78  * return the pic wanted interrupt. return -1 if none
79  */
80 static int pic_get_irq(struct kvm_kpic_state *s)
81 {
82         int mask, cur_priority, priority;
83
84         mask = s->irr & ~s->imr;
85         priority = get_priority(s, mask);
86         if (priority == 8)
87                 return -1;
88         /*
89          * compute current priority. If special fully nested mode on the
90          * master, the IRQ coming from the slave is not taken into account
91          * for the priority computation.
92          */
93         mask = s->isr;
94         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
95                 mask &= ~(1 << 2);
96         cur_priority = get_priority(s, mask);
97         if (priority < cur_priority)
98                 /*
99                  * higher priority found: an irq should be generated
100                  */
101                 return (priority + s->priority_add) & 7;
102         else
103                 return -1;
104 }
105
106 /*
107  * raise irq to CPU if necessary. must be called every time the active
108  * irq may change
109  */
110 static void pic_update_irq(struct kvm_pic *s)
111 {
112         int irq2, irq;
113
114         irq2 = pic_get_irq(&s->pics[1]);
115         if (irq2 >= 0) {
116                 /*
117                  * if irq request by slave pic, signal master PIC
118                  */
119                 pic_set_irq1(&s->pics[0], 2, 1);
120                 pic_set_irq1(&s->pics[0], 2, 0);
121         }
122         irq = pic_get_irq(&s->pics[0]);
123         if (irq >= 0)
124                 s->irq_request(s->irq_request_opaque, 1);
125         else
126                 s->irq_request(s->irq_request_opaque, 0);
127 }
128
129 void kvm_pic_update_irq(struct kvm_pic *s)
130 {
131         pic_update_irq(s);
132 }
133
134 void kvm_pic_set_irq(void *opaque, int irq, int level)
135 {
136         struct kvm_pic *s = opaque;
137
138         if (irq >= 0 && irq < PIC_NUM_PINS) {
139                 pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
140                 pic_update_irq(s);
141         }
142 }
143
144 /*
145  * acknowledge interrupt 'irq'
146  */
147 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
148 {
149         s->isr |= 1 << irq;
150         if (s->auto_eoi) {
151                 if (s->rotate_on_auto_eoi)
152                         s->priority_add = (irq + 1) & 7;
153                 pic_clear_isr(s, irq);
154         }
155         /*
156          * We don't clear a level sensitive interrupt here
157          */
158         if (!(s->elcr & (1 << irq)))
159                 s->irr &= ~(1 << irq);
160 }
161
162 int kvm_pic_read_irq(struct kvm_pic *s)
163 {
164         int irq, irq2, intno;
165
166         irq = pic_get_irq(&s->pics[0]);
167         if (irq >= 0) {
168                 pic_intack(&s->pics[0], irq);
169                 if (irq == 2) {
170                         irq2 = pic_get_irq(&s->pics[1]);
171                         if (irq2 >= 0)
172                                 pic_intack(&s->pics[1], irq2);
173                         else
174                                 /*
175                                  * spurious IRQ on slave controller
176                                  */
177                                 irq2 = 7;
178                         intno = s->pics[1].irq_base + irq2;
179                         irq = irq2 + 8;
180                 } else
181                         intno = s->pics[0].irq_base + irq;
182         } else {
183                 /*
184                  * spurious IRQ on host controller
185                  */
186                 irq = 7;
187                 intno = s->pics[0].irq_base + irq;
188         }
189         pic_update_irq(s);
190
191         return intno;
192 }
193
194 void kvm_pic_reset(struct kvm_kpic_state *s)
195 {
196         s->last_irr = 0;
197         s->irr = 0;
198         s->imr = 0;
199         s->isr = 0;
200         s->priority_add = 0;
201         s->irq_base = 0;
202         s->read_reg_select = 0;
203         s->poll = 0;
204         s->special_mask = 0;
205         s->init_state = 0;
206         s->auto_eoi = 0;
207         s->rotate_on_auto_eoi = 0;
208         s->special_fully_nested_mode = 0;
209         s->init4 = 0;
210 }
211
212 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
213 {
214         struct kvm_kpic_state *s = opaque;
215         int priority, cmd, irq;
216
217         addr &= 1;
218         if (addr == 0) {
219                 if (val & 0x10) {
220                         kvm_pic_reset(s);       /* init */
221                         /*
222                          * deassert a pending interrupt
223                          */
224                         s->pics_state->irq_request(s->pics_state->
225                                                    irq_request_opaque, 0);
226                         s->init_state = 1;
227                         s->init4 = val & 1;
228                         if (val & 0x02)
229                                 printk(KERN_ERR "single mode not supported");
230                         if (val & 0x08)
231                                 printk(KERN_ERR
232                                        "level sensitive irq not supported");
233                 } else if (val & 0x08) {
234                         if (val & 0x04)
235                                 s->poll = 1;
236                         if (val & 0x02)
237                                 s->read_reg_select = val & 1;
238                         if (val & 0x40)
239                                 s->special_mask = (val >> 5) & 1;
240                 } else {
241                         cmd = val >> 5;
242                         switch (cmd) {
243                         case 0:
244                         case 4:
245                                 s->rotate_on_auto_eoi = cmd >> 2;
246                                 break;
247                         case 1: /* end of interrupt */
248                         case 5:
249                                 priority = get_priority(s, s->isr);
250                                 if (priority != 8) {
251                                         irq = (priority + s->priority_add) & 7;
252                                         pic_clear_isr(s, irq);
253                                         if (cmd == 5)
254                                                 s->priority_add = (irq + 1) & 7;
255                                         pic_update_irq(s->pics_state);
256                                 }
257                                 break;
258                         case 3:
259                                 irq = val & 7;
260                                 pic_clear_isr(s, irq);
261                                 pic_update_irq(s->pics_state);
262                                 break;
263                         case 6:
264                                 s->priority_add = (val + 1) & 7;
265                                 pic_update_irq(s->pics_state);
266                                 break;
267                         case 7:
268                                 irq = val & 7;
269                                 s->priority_add = (irq + 1) & 7;
270                                 pic_clear_isr(s, irq);
271                                 pic_update_irq(s->pics_state);
272                                 break;
273                         default:
274                                 break;  /* no operation */
275                         }
276                 }
277         } else
278                 switch (s->init_state) {
279                 case 0:         /* normal mode */
280                         s->imr = val;
281                         pic_update_irq(s->pics_state);
282                         break;
283                 case 1:
284                         s->irq_base = val & 0xf8;
285                         s->init_state = 2;
286                         break;
287                 case 2:
288                         if (s->init4)
289                                 s->init_state = 3;
290                         else
291                                 s->init_state = 0;
292                         break;
293                 case 3:
294                         s->special_fully_nested_mode = (val >> 4) & 1;
295                         s->auto_eoi = (val >> 1) & 1;
296                         s->init_state = 0;
297                         break;
298                 }
299 }
300
301 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
302 {
303         int ret;
304
305         ret = pic_get_irq(s);
306         if (ret >= 0) {
307                 if (addr1 >> 7) {
308                         s->pics_state->pics[0].isr &= ~(1 << 2);
309                         s->pics_state->pics[0].irr &= ~(1 << 2);
310                 }
311                 s->irr &= ~(1 << ret);
312                 pic_clear_isr(s, ret);
313                 if (addr1 >> 7 || ret != 2)
314                         pic_update_irq(s->pics_state);
315         } else {
316                 ret = 0x07;
317                 pic_update_irq(s->pics_state);
318         }
319
320         return ret;
321 }
322
323 static u32 pic_ioport_read(void *opaque, u32 addr1)
324 {
325         struct kvm_kpic_state *s = opaque;
326         unsigned int addr;
327         int ret;
328
329         addr = addr1;
330         addr &= 1;
331         if (s->poll) {
332                 ret = pic_poll_read(s, addr1);
333                 s->poll = 0;
334         } else
335                 if (addr == 0)
336                         if (s->read_reg_select)
337                                 ret = s->isr;
338                         else
339                                 ret = s->irr;
340                 else
341                         ret = s->imr;
342         return ret;
343 }
344
345 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
346 {
347         struct kvm_kpic_state *s = opaque;
348         s->elcr = val & s->elcr_mask;
349 }
350
351 static u32 elcr_ioport_read(void *opaque, u32 addr1)
352 {
353         struct kvm_kpic_state *s = opaque;
354         return s->elcr;
355 }
356
357 static int picdev_in_range(struct kvm_io_device *this, gpa_t addr,
358                            int len, int is_write)
359 {
360         switch (addr) {
361         case 0x20:
362         case 0x21:
363         case 0xa0:
364         case 0xa1:
365         case 0x4d0:
366         case 0x4d1:
367                 return 1;
368         default:
369                 return 0;
370         }
371 }
372
373 static void picdev_write(struct kvm_io_device *this,
374                          gpa_t addr, int len, const void *val)
375 {
376         struct kvm_pic *s = this->private;
377         unsigned char data = *(unsigned char *)val;
378
379         if (len != 1) {
380                 if (printk_ratelimit())
381                         printk(KERN_ERR "PIC: non byte write\n");
382                 return;
383         }
384         switch (addr) {
385         case 0x20:
386         case 0x21:
387         case 0xa0:
388         case 0xa1:
389                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
390                 break;
391         case 0x4d0:
392         case 0x4d1:
393                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
394                 break;
395         }
396 }
397
398 static void picdev_read(struct kvm_io_device *this,
399                         gpa_t addr, int len, void *val)
400 {
401         struct kvm_pic *s = this->private;
402         unsigned char data = 0;
403
404         if (len != 1) {
405                 if (printk_ratelimit())
406                         printk(KERN_ERR "PIC: non byte read\n");
407                 return;
408         }
409         switch (addr) {
410         case 0x20:
411         case 0x21:
412         case 0xa0:
413         case 0xa1:
414                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
415                 break;
416         case 0x4d0:
417         case 0x4d1:
418                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
419                 break;
420         }
421         *(unsigned char *)val = data;
422 }
423
424 /*
425  * callback when PIC0 irq status changed
426  */
427 static void pic_irq_request(void *opaque, int level)
428 {
429         struct kvm *kvm = opaque;
430         struct kvm_vcpu *vcpu = kvm->vcpus[0];
431
432         pic_irqchip(kvm)->output = level;
433         if (vcpu)
434                 kvm_vcpu_kick(vcpu);
435 }
436
437 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
438 {
439         struct kvm_pic *s;
440         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
441         if (!s)
442                 return NULL;
443         s->pics[0].elcr_mask = 0xf8;
444         s->pics[1].elcr_mask = 0xde;
445         s->irq_request = pic_irq_request;
446         s->irq_request_opaque = kvm;
447         s->pics[0].pics_state = s;
448         s->pics[1].pics_state = s;
449
450         /*
451          * Initialize PIO device
452          */
453         s->dev.read = picdev_read;
454         s->dev.write = picdev_write;
455         s->dev.in_range = picdev_in_range;
456         s->dev.private = s;
457         kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
458         return s;
459 }