Merge branch 'linus' into tracing/hw-breakpoints
[linux-2.6.git] / arch / x86 / kernel / uv_time.c
1 /*
2  * SGI RTC clock/timer routines.
3  *
4  *  This program is free software; you can redistribute it and/or modify
5  *  it under the terms of the GNU General Public License as published by
6  *  the Free Software Foundation; either version 2 of the License, or
7  *  (at your option) any later version.
8  *
9  *  This program is distributed in the hope that it will be useful,
10  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
11  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  *  GNU General Public License for more details.
13  *
14  *  You should have received a copy of the GNU General Public License
15  *  along with this program; if not, write to the Free Software
16  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
17  *
18  *  Copyright (c) 2009 Silicon Graphics, Inc.  All Rights Reserved.
19  *  Copyright (c) Dimitri Sivanich
20  */
21 #include <linux/clockchips.h>
22
23 #include <asm/uv/uv_mmrs.h>
24 #include <asm/uv/uv_hub.h>
25 #include <asm/uv/bios.h>
26 #include <asm/uv/uv.h>
27 #include <asm/apic.h>
28 #include <asm/cpu.h>
29
30 #define RTC_NAME                "sgi_rtc"
31
32 static cycle_t uv_read_rtc(struct clocksource *cs);
33 static int uv_rtc_next_event(unsigned long, struct clock_event_device *);
34 static void uv_rtc_timer_setup(enum clock_event_mode,
35                                 struct clock_event_device *);
36
37 static struct clocksource clocksource_uv = {
38         .name           = RTC_NAME,
39         .rating         = 400,
40         .read           = uv_read_rtc,
41         .mask           = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK,
42         .shift          = 10,
43         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
44 };
45
46 static struct clock_event_device clock_event_device_uv = {
47         .name           = RTC_NAME,
48         .features       = CLOCK_EVT_FEAT_ONESHOT,
49         .shift          = 20,
50         .rating         = 400,
51         .irq            = -1,
52         .set_next_event = uv_rtc_next_event,
53         .set_mode       = uv_rtc_timer_setup,
54         .event_handler  = NULL,
55 };
56
57 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced);
58
59 /* There is one of these allocated per node */
60 struct uv_rtc_timer_head {
61         spinlock_t      lock;
62         /* next cpu waiting for timer, local node relative: */
63         int             next_cpu;
64         /* number of cpus on this node: */
65         int             ncpus;
66         struct {
67                 int     lcpu;           /* systemwide logical cpu number */
68                 u64     expires;        /* next timer expiration for this cpu */
69         } cpu[1];
70 };
71
72 /*
73  * Access to uv_rtc_timer_head via blade id.
74  */
75 static struct uv_rtc_timer_head         **blade_info __read_mostly;
76
77 static int                              uv_rtc_enable;
78
79 /*
80  * Hardware interface routines
81  */
82
83 /* Send IPIs to another node */
84 static void uv_rtc_send_IPI(int cpu)
85 {
86         unsigned long apicid, val;
87         int pnode;
88
89         apicid = cpu_physical_id(cpu);
90         pnode = uv_apicid_to_pnode(apicid);
91         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
92               (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
93               (GENERIC_INTERRUPT_VECTOR << UVH_IPI_INT_VECTOR_SHFT);
94
95         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
96 }
97
98 /* Check for an RTC interrupt pending */
99 static int uv_intr_pending(int pnode)
100 {
101         return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) &
102                 UVH_EVENT_OCCURRED0_RTC1_MASK;
103 }
104
105 /* Setup interrupt and return non-zero if early expiration occurred. */
106 static int uv_setup_intr(int cpu, u64 expires)
107 {
108         u64 val;
109         int pnode = uv_cpu_to_pnode(cpu);
110
111         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
112                 UVH_RTC1_INT_CONFIG_M_MASK);
113         uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L);
114
115         uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS,
116                 UVH_EVENT_OCCURRED0_RTC1_MASK);
117
118         val = (GENERIC_INTERRUPT_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) |
119                 ((u64)cpu_physical_id(cpu) << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT);
120
121         /* Set configuration */
122         uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val);
123         /* Initialize comparator value */
124         uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires);
125
126         return (expires < uv_read_rtc(NULL) && !uv_intr_pending(pnode));
127 }
128
129 /*
130  * Per-cpu timer tracking routines
131  */
132
133 static __init void uv_rtc_deallocate_timers(void)
134 {
135         int bid;
136
137         for_each_possible_blade(bid) {
138                 kfree(blade_info[bid]);
139         }
140         kfree(blade_info);
141 }
142
143 /* Allocate per-node list of cpu timer expiration times. */
144 static __init int uv_rtc_allocate_timers(void)
145 {
146         int cpu;
147
148         blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL);
149         if (!blade_info)
150                 return -ENOMEM;
151         memset(blade_info, 0, uv_possible_blades * sizeof(void *));
152
153         for_each_present_cpu(cpu) {
154                 int nid = cpu_to_node(cpu);
155                 int bid = uv_cpu_to_blade_id(cpu);
156                 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
157                 struct uv_rtc_timer_head *head = blade_info[bid];
158
159                 if (!head) {
160                         head = kmalloc_node(sizeof(struct uv_rtc_timer_head) +
161                                 (uv_blade_nr_possible_cpus(bid) *
162                                         2 * sizeof(u64)),
163                                 GFP_KERNEL, nid);
164                         if (!head) {
165                                 uv_rtc_deallocate_timers();
166                                 return -ENOMEM;
167                         }
168                         spin_lock_init(&head->lock);
169                         head->ncpus = uv_blade_nr_possible_cpus(bid);
170                         head->next_cpu = -1;
171                         blade_info[bid] = head;
172                 }
173
174                 head->cpu[bcpu].lcpu = cpu;
175                 head->cpu[bcpu].expires = ULLONG_MAX;
176         }
177
178         return 0;
179 }
180
181 /* Find and set the next expiring timer.  */
182 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode)
183 {
184         u64 lowest = ULLONG_MAX;
185         int c, bcpu = -1;
186
187         head->next_cpu = -1;
188         for (c = 0; c < head->ncpus; c++) {
189                 u64 exp = head->cpu[c].expires;
190                 if (exp < lowest) {
191                         bcpu = c;
192                         lowest = exp;
193                 }
194         }
195         if (bcpu >= 0) {
196                 head->next_cpu = bcpu;
197                 c = head->cpu[bcpu].lcpu;
198                 if (uv_setup_intr(c, lowest))
199                         /* If we didn't set it up in time, trigger */
200                         uv_rtc_send_IPI(c);
201         } else {
202                 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG,
203                         UVH_RTC1_INT_CONFIG_M_MASK);
204         }
205 }
206
207 /*
208  * Set expiration time for current cpu.
209  *
210  * Returns 1 if we missed the expiration time.
211  */
212 static int uv_rtc_set_timer(int cpu, u64 expires)
213 {
214         int pnode = uv_cpu_to_pnode(cpu);
215         int bid = uv_cpu_to_blade_id(cpu);
216         struct uv_rtc_timer_head *head = blade_info[bid];
217         int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
218         u64 *t = &head->cpu[bcpu].expires;
219         unsigned long flags;
220         int next_cpu;
221
222         spin_lock_irqsave(&head->lock, flags);
223
224         next_cpu = head->next_cpu;
225         *t = expires;
226         /* Will this one be next to go off? */
227         if (next_cpu < 0 || bcpu == next_cpu ||
228                         expires < head->cpu[next_cpu].expires) {
229                 head->next_cpu = bcpu;
230                 if (uv_setup_intr(cpu, expires)) {
231                         *t = ULLONG_MAX;
232                         uv_rtc_find_next_timer(head, pnode);
233                         spin_unlock_irqrestore(&head->lock, flags);
234                         return 1;
235                 }
236         }
237
238         spin_unlock_irqrestore(&head->lock, flags);
239         return 0;
240 }
241
242 /*
243  * Unset expiration time for current cpu.
244  *
245  * Returns 1 if this timer was pending.
246  */
247 static int uv_rtc_unset_timer(int cpu)
248 {
249         int pnode = uv_cpu_to_pnode(cpu);
250         int bid = uv_cpu_to_blade_id(cpu);
251         struct uv_rtc_timer_head *head = blade_info[bid];
252         int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id;
253         u64 *t = &head->cpu[bcpu].expires;
254         unsigned long flags;
255         int rc = 0;
256
257         spin_lock_irqsave(&head->lock, flags);
258
259         if (head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t)
260                 rc = 1;
261
262         *t = ULLONG_MAX;
263
264         /* Was the hardware setup for this timer? */
265         if (head->next_cpu == bcpu)
266                 uv_rtc_find_next_timer(head, pnode);
267
268         spin_unlock_irqrestore(&head->lock, flags);
269
270         return rc;
271 }
272
273
274 /*
275  * Kernel interface routines.
276  */
277
278 /*
279  * Read the RTC.
280  */
281 static cycle_t uv_read_rtc(struct clocksource *cs)
282 {
283         return (cycle_t)uv_read_local_mmr(UVH_RTC);
284 }
285
286 /*
287  * Program the next event, relative to now
288  */
289 static int uv_rtc_next_event(unsigned long delta,
290                              struct clock_event_device *ced)
291 {
292         int ced_cpu = cpumask_first(ced->cpumask);
293
294         return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL));
295 }
296
297 /*
298  * Setup the RTC timer in oneshot mode
299  */
300 static void uv_rtc_timer_setup(enum clock_event_mode mode,
301                                struct clock_event_device *evt)
302 {
303         int ced_cpu = cpumask_first(evt->cpumask);
304
305         switch (mode) {
306         case CLOCK_EVT_MODE_PERIODIC:
307         case CLOCK_EVT_MODE_ONESHOT:
308         case CLOCK_EVT_MODE_RESUME:
309                 /* Nothing to do here yet */
310                 break;
311         case CLOCK_EVT_MODE_UNUSED:
312         case CLOCK_EVT_MODE_SHUTDOWN:
313                 uv_rtc_unset_timer(ced_cpu);
314                 break;
315         }
316 }
317
318 static void uv_rtc_interrupt(void)
319 {
320         struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
321         int cpu = smp_processor_id();
322
323         if (!ced || !ced->event_handler)
324                 return;
325
326         if (uv_rtc_unset_timer(cpu) != 1)
327                 return;
328
329         ced->event_handler(ced);
330 }
331
332 static int __init uv_enable_rtc(char *str)
333 {
334         uv_rtc_enable = 1;
335
336         return 1;
337 }
338 __setup("uvrtc", uv_enable_rtc);
339
340 static __init void uv_rtc_register_clockevents(struct work_struct *dummy)
341 {
342         struct clock_event_device *ced = &__get_cpu_var(cpu_ced);
343
344         *ced = clock_event_device_uv;
345         ced->cpumask = cpumask_of(smp_processor_id());
346         clockevents_register_device(ced);
347 }
348
349 static __init int uv_rtc_setup_clock(void)
350 {
351         int rc;
352
353         if (!uv_rtc_enable || !is_uv_system() || generic_interrupt_extension)
354                 return -ENODEV;
355
356         generic_interrupt_extension = uv_rtc_interrupt;
357
358         clocksource_uv.mult = clocksource_hz2mult(sn_rtc_cycles_per_second,
359                                 clocksource_uv.shift);
360
361         rc = clocksource_register(&clocksource_uv);
362         if (rc) {
363                 generic_interrupt_extension = NULL;
364                 return rc;
365         }
366
367         /* Setup and register clockevents */
368         rc = uv_rtc_allocate_timers();
369         if (rc) {
370                 clocksource_unregister(&clocksource_uv);
371                 generic_interrupt_extension = NULL;
372                 return rc;
373         }
374
375         clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second,
376                                 NSEC_PER_SEC, clock_event_device_uv.shift);
377
378         clock_event_device_uv.min_delta_ns = NSEC_PER_SEC /
379                                                 sn_rtc_cycles_per_second;
380
381         clock_event_device_uv.max_delta_ns = clocksource_uv.mask *
382                                 (NSEC_PER_SEC / sn_rtc_cycles_per_second);
383
384         rc = schedule_on_each_cpu(uv_rtc_register_clockevents);
385         if (rc) {
386                 clocksource_unregister(&clocksource_uv);
387                 generic_interrupt_extension = NULL;
388                 uv_rtc_deallocate_timers();
389         }
390
391         return rc;
392 }
393 arch_initcall(uv_rtc_setup_clock);