Merge branch 'timers/for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / arch / x86 / kernel / quirks.c
1 /*
2  * This file contains work-arounds for x86 and x86_64 platform bugs.
3  */
4 #include <linux/pci.h>
5 #include <linux/irq.h>
6
7 #include <asm/hpet.h>
8
9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
10
11 static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
12 {
13         u8 config, rev;
14         u16 word;
15
16         /* BIOS may enable hardware IRQ balancing for
17          * E7520/E7320/E7525(revision ID 0x9 and below)
18          * based platforms.
19          * Disable SW irqbalance/affinity on those platforms.
20          */
21         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
22         if (rev > 0x9)
23                 return;
24
25         /* enable access to config space*/
26         pci_read_config_byte(dev, 0xf4, &config);
27         pci_write_config_byte(dev, 0xf4, config|0x2);
28
29         /*
30          * read xTPR register.  We may not have a pci_dev for device 8
31          * because it might be hidden until the above write.
32          */
33         pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word);
34
35         if (!(word & (1 << 13))) {
36                 dev_info(&dev->dev, "Intel E7520/7320/7525 detected; "
37                         "disabling irq balancing and affinity\n");
38 #ifdef CONFIG_IRQBALANCE
39                 irqbalance_disable("");
40 #endif
41                 noirqdebug_setup("");
42 #ifdef CONFIG_PROC_FS
43                 no_irq_affinity = 1;
44 #endif
45         }
46
47         /* put back the original value for config space*/
48         if (!(config & 0x2))
49                 pci_write_config_byte(dev, 0xf4, config);
50 }
51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
52                         quirk_intel_irqbalance);
53 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
54                         quirk_intel_irqbalance);
55 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
56                         quirk_intel_irqbalance);
57 #endif
58
59 #if defined(CONFIG_HPET_TIMER)
60 unsigned long force_hpet_address;
61
62 static enum {
63         NONE_FORCE_HPET_RESUME,
64         OLD_ICH_FORCE_HPET_RESUME,
65         ICH_FORCE_HPET_RESUME,
66         VT8237_FORCE_HPET_RESUME,
67         NVIDIA_FORCE_HPET_RESUME,
68         ATI_FORCE_HPET_RESUME,
69 } force_hpet_resume_type;
70
71 static void __iomem *rcba_base;
72
73 static void ich_force_hpet_resume(void)
74 {
75         u32 val;
76
77         if (!force_hpet_address)
78                 return;
79
80         if (rcba_base == NULL)
81                 BUG();
82
83         /* read the Function Disable register, dword mode only */
84         val = readl(rcba_base + 0x3404);
85         if (!(val & 0x80)) {
86                 /* HPET disabled in HPTC. Trying to enable */
87                 writel(val | 0x80, rcba_base + 0x3404);
88         }
89
90         val = readl(rcba_base + 0x3404);
91         if (!(val & 0x80))
92                 BUG();
93         else
94                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
95
96         return;
97 }
98
99 static void ich_force_enable_hpet(struct pci_dev *dev)
100 {
101         u32 val;
102         u32 uninitialized_var(rcba);
103         int err = 0;
104
105         if (hpet_address || force_hpet_address)
106                 return;
107
108         pci_read_config_dword(dev, 0xF0, &rcba);
109         rcba &= 0xFFFFC000;
110         if (rcba == 0) {
111                 dev_printk(KERN_DEBUG, &dev->dev, "RCBA disabled; "
112                         "cannot force enable HPET\n");
113                 return;
114         }
115
116         /* use bits 31:14, 16 kB aligned */
117         rcba_base = ioremap_nocache(rcba, 0x4000);
118         if (rcba_base == NULL) {
119                 dev_printk(KERN_DEBUG, &dev->dev, "ioremap failed; "
120                         "cannot force enable HPET\n");
121                 return;
122         }
123
124         /* read the Function Disable register, dword mode only */
125         val = readl(rcba_base + 0x3404);
126
127         if (val & 0x80) {
128                 /* HPET is enabled in HPTC. Just not reported by BIOS */
129                 val = val & 0x3;
130                 force_hpet_address = 0xFED00000 | (val << 12);
131                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
132                         "0x%lx\n", force_hpet_address);
133                 iounmap(rcba_base);
134                 return;
135         }
136
137         /* HPET disabled in HPTC. Trying to enable */
138         writel(val | 0x80, rcba_base + 0x3404);
139
140         val = readl(rcba_base + 0x3404);
141         if (!(val & 0x80)) {
142                 err = 1;
143         } else {
144                 val = val & 0x3;
145                 force_hpet_address = 0xFED00000 | (val << 12);
146         }
147
148         if (err) {
149                 force_hpet_address = 0;
150                 iounmap(rcba_base);
151                 dev_printk(KERN_DEBUG, &dev->dev,
152                         "Failed to force enable HPET\n");
153         } else {
154                 force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
155                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
156                         "0x%lx\n", force_hpet_address);
157         }
158 }
159
160 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
161                          ich_force_enable_hpet);
162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0,
163                          ich_force_enable_hpet);
164 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
165                          ich_force_enable_hpet);
166 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
167                          ich_force_enable_hpet);
168 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
169                          ich_force_enable_hpet);
170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
171                          ich_force_enable_hpet);
172 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
173                          ich_force_enable_hpet);
174 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7,
175                          ich_force_enable_hpet);
176
177
178 static struct pci_dev *cached_dev;
179
180 static void hpet_print_force_info(void)
181 {
182         printk(KERN_INFO "HPET not enabled in BIOS. "
183                "You might try hpet=force boot option\n");
184 }
185
186 static void old_ich_force_hpet_resume(void)
187 {
188         u32 val;
189         u32 uninitialized_var(gen_cntl);
190
191         if (!force_hpet_address || !cached_dev)
192                 return;
193
194         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
195         gen_cntl &= (~(0x7 << 15));
196         gen_cntl |= (0x4 << 15);
197
198         pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
199         pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
200         val = gen_cntl >> 15;
201         val &= 0x7;
202         if (val == 0x4)
203                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
204         else
205                 BUG();
206 }
207
208 static void old_ich_force_enable_hpet(struct pci_dev *dev)
209 {
210         u32 val;
211         u32 uninitialized_var(gen_cntl);
212
213         if (hpet_address || force_hpet_address)
214                 return;
215
216         pci_read_config_dword(dev, 0xD0, &gen_cntl);
217         /*
218          * Bit 17 is HPET enable bit.
219          * Bit 16:15 control the HPET base address.
220          */
221         val = gen_cntl >> 15;
222         val &= 0x7;
223         if (val & 0x4) {
224                 val &= 0x3;
225                 force_hpet_address = 0xFED00000 | (val << 12);
226                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
227                         force_hpet_address);
228                 return;
229         }
230
231         /*
232          * HPET is disabled. Trying enabling at FED00000 and check
233          * whether it sticks
234          */
235         gen_cntl &= (~(0x7 << 15));
236         gen_cntl |= (0x4 << 15);
237         pci_write_config_dword(dev, 0xD0, gen_cntl);
238
239         pci_read_config_dword(dev, 0xD0, &gen_cntl);
240
241         val = gen_cntl >> 15;
242         val &= 0x7;
243         if (val & 0x4) {
244                 /* HPET is enabled in HPTC. Just not reported by BIOS */
245                 val &= 0x3;
246                 force_hpet_address = 0xFED00000 | (val << 12);
247                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
248                         "0x%lx\n", force_hpet_address);
249                 cached_dev = dev;
250                 force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
251                 return;
252         }
253
254         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
255 }
256
257 /*
258  * Undocumented chipset features. Make sure that the user enforced
259  * this.
260  */
261 static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
262 {
263         if (hpet_force_user)
264                 old_ich_force_enable_hpet(dev);
265         else
266                 hpet_print_force_info();
267 }
268
269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1,
270                          old_ich_force_enable_hpet_user);
271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
272                          old_ich_force_enable_hpet_user);
273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
274                          old_ich_force_enable_hpet_user);
275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
276                          old_ich_force_enable_hpet_user);
277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
278                          old_ich_force_enable_hpet_user);
279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
280                          old_ich_force_enable_hpet);
281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
282                          old_ich_force_enable_hpet);
283
284
285 static void vt8237_force_hpet_resume(void)
286 {
287         u32 val;
288
289         if (!force_hpet_address || !cached_dev)
290                 return;
291
292         val = 0xfed00000 | 0x80;
293         pci_write_config_dword(cached_dev, 0x68, val);
294
295         pci_read_config_dword(cached_dev, 0x68, &val);
296         if (val & 0x80)
297                 printk(KERN_DEBUG "Force enabled HPET at resume\n");
298         else
299                 BUG();
300 }
301
302 static void vt8237_force_enable_hpet(struct pci_dev *dev)
303 {
304         u32 uninitialized_var(val);
305
306         if (hpet_address || force_hpet_address)
307                 return;
308
309         if (!hpet_force_user) {
310                 hpet_print_force_info();
311                 return;
312         }
313
314         pci_read_config_dword(dev, 0x68, &val);
315         /*
316          * Bit 7 is HPET enable bit.
317          * Bit 31:10 is HPET base address (contrary to what datasheet claims)
318          */
319         if (val & 0x80) {
320                 force_hpet_address = (val & ~0x3ff);
321                 dev_printk(KERN_DEBUG, &dev->dev, "HPET at 0x%lx\n",
322                         force_hpet_address);
323                 return;
324         }
325
326         /*
327          * HPET is disabled. Trying enabling at FED00000 and check
328          * whether it sticks
329          */
330         val = 0xfed00000 | 0x80;
331         pci_write_config_dword(dev, 0x68, val);
332
333         pci_read_config_dword(dev, 0x68, &val);
334         if (val & 0x80) {
335                 force_hpet_address = (val & ~0x3ff);
336                 dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at "
337                         "0x%lx\n", force_hpet_address);
338                 cached_dev = dev;
339                 force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
340                 return;
341         }
342
343         dev_printk(KERN_DEBUG, &dev->dev, "Failed to force enable HPET\n");
344 }
345
346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
347                          vt8237_force_enable_hpet);
348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
349                          vt8237_force_enable_hpet);
350
351 static void ati_force_hpet_resume(void)
352 {
353         pci_write_config_dword(cached_dev, 0x14, 0xfed00000);
354         printk(KERN_DEBUG "Force enabled HPET at resume\n");
355 }
356
357 static void ati_force_enable_hpet(struct pci_dev *dev)
358 {
359         u32 uninitialized_var(val);
360
361         if (hpet_address || force_hpet_address)
362                 return;
363
364         if (!hpet_force_user) {
365                 hpet_print_force_info();
366                 return;
367         }
368
369         pci_write_config_dword(dev, 0x14, 0xfed00000);
370         pci_read_config_dword(dev, 0x14, &val);
371         force_hpet_address = val;
372         force_hpet_resume_type = ATI_FORCE_HPET_RESUME;
373         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
374                    force_hpet_address);
375         cached_dev = dev;
376         return;
377 }
378 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
379                          ati_force_enable_hpet);
380
381 /*
382  * Undocumented chipset feature taken from LinuxBIOS.
383  */
384 static void nvidia_force_hpet_resume(void)
385 {
386         pci_write_config_dword(cached_dev, 0x44, 0xfed00001);
387         printk(KERN_DEBUG "Force enabled HPET at resume\n");
388 }
389
390 static void nvidia_force_enable_hpet(struct pci_dev *dev)
391 {
392         u32 uninitialized_var(val);
393
394         if (hpet_address || force_hpet_address)
395                 return;
396
397         if (!hpet_force_user) {
398                 hpet_print_force_info();
399                 return;
400         }
401
402         pci_write_config_dword(dev, 0x44, 0xfed00001);
403         pci_read_config_dword(dev, 0x44, &val);
404         force_hpet_address = val & 0xfffffffe;
405         force_hpet_resume_type = NVIDIA_FORCE_HPET_RESUME;
406         dev_printk(KERN_DEBUG, &dev->dev, "Force enabled HPET at 0x%lx\n",
407                 force_hpet_address);
408         cached_dev = dev;
409         return;
410 }
411
412 /* ISA Bridges */
413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0050,
414                         nvidia_force_enable_hpet);
415 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0051,
416                         nvidia_force_enable_hpet);
417
418 /* LPC bridges */
419 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0260,
420                         nvidia_force_enable_hpet);
421 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0360,
422                         nvidia_force_enable_hpet);
423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0361,
424                         nvidia_force_enable_hpet);
425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0362,
426                         nvidia_force_enable_hpet);
427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0363,
428                         nvidia_force_enable_hpet);
429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0364,
430                         nvidia_force_enable_hpet);
431 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0365,
432                         nvidia_force_enable_hpet);
433 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0366,
434                         nvidia_force_enable_hpet);
435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x0367,
436                         nvidia_force_enable_hpet);
437
438 void force_hpet_resume(void)
439 {
440         switch (force_hpet_resume_type) {
441         case ICH_FORCE_HPET_RESUME:
442                 ich_force_hpet_resume();
443                 return;
444         case OLD_ICH_FORCE_HPET_RESUME:
445                 old_ich_force_hpet_resume();
446                 return;
447         case VT8237_FORCE_HPET_RESUME:
448                 vt8237_force_hpet_resume();
449                 return;
450         case NVIDIA_FORCE_HPET_RESUME:
451                 nvidia_force_hpet_resume();
452                 return;
453         case ATI_FORCE_HPET_RESUME:
454                 ati_force_hpet_resume();
455                 return;
456         default:
457                 break;
458         }
459 }
460
461 #endif