Merge branch 'linus' into tracing/hw-breakpoints
[linux-2.6.git] / arch / x86 / kernel / process.c
1 #include <linux/errno.h>
2 #include <linux/kernel.h>
3 #include <linux/mm.h>
4 #include <linux/smp.h>
5 #include <linux/prctl.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
9 #include <linux/pm.h>
10 #include <linux/clockchips.h>
11 #include <linux/random.h>
12 #include <trace/power.h>
13 #include <asm/system.h>
14 #include <asm/apic.h>
15 #include <asm/syscalls.h>
16 #include <asm/idle.h>
17 #include <asm/uaccess.h>
18 #include <asm/i387.h>
19 #include <asm/ds.h>
20 #include <asm/debugreg.h>
21 #include <asm/hw_breakpoint.h>
22
23 unsigned long idle_halt;
24 EXPORT_SYMBOL(idle_halt);
25 unsigned long idle_nomwait;
26 EXPORT_SYMBOL(idle_nomwait);
27
28 struct kmem_cache *task_xstate_cachep;
29
30 DEFINE_TRACE(power_start);
31 DEFINE_TRACE(power_end);
32
33 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
34 {
35         *dst = *src;
36         if (src->thread.xstate) {
37                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
38                                                       GFP_KERNEL);
39                 if (!dst->thread.xstate)
40                         return -ENOMEM;
41                 WARN_ON((unsigned long)dst->thread.xstate & 15);
42                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
43         }
44         return 0;
45 }
46
47 void free_thread_xstate(struct task_struct *tsk)
48 {
49         if (tsk->thread.xstate) {
50                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
51                 tsk->thread.xstate = NULL;
52         }
53         if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
54                 flush_thread_hw_breakpoint(tsk);
55
56         WARN(tsk->thread.ds_ctx, "leaking DS context\n");
57 }
58
59 void free_thread_info(struct thread_info *ti)
60 {
61         free_thread_xstate(ti->task);
62         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
63 }
64
65 void arch_task_cache_init(void)
66 {
67         task_xstate_cachep =
68                 kmem_cache_create("task_xstate", xstate_size,
69                                   __alignof__(union thread_xstate),
70                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
71 }
72
73 /*
74  * Free current thread data structures etc..
75  */
76 void exit_thread(void)
77 {
78         struct task_struct *me = current;
79         struct thread_struct *t = &me->thread;
80         unsigned long *bp = t->io_bitmap_ptr;
81
82         if (bp) {
83                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
84
85                 t->io_bitmap_ptr = NULL;
86                 clear_thread_flag(TIF_IO_BITMAP);
87                 /*
88                  * Careful, clear this in the TSS too:
89                  */
90                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
91                 t->io_bitmap_max = 0;
92                 put_cpu();
93                 kfree(bp);
94         }
95 }
96
97 void flush_thread(void)
98 {
99         struct task_struct *tsk = current;
100
101 #ifdef CONFIG_X86_64
102         if (test_tsk_thread_flag(tsk, TIF_ABI_PENDING)) {
103                 clear_tsk_thread_flag(tsk, TIF_ABI_PENDING);
104                 if (test_tsk_thread_flag(tsk, TIF_IA32)) {
105                         clear_tsk_thread_flag(tsk, TIF_IA32);
106                 } else {
107                         set_tsk_thread_flag(tsk, TIF_IA32);
108                         current_thread_info()->status |= TS_COMPAT;
109                 }
110         }
111 #endif
112
113         clear_tsk_thread_flag(tsk, TIF_DEBUG);
114
115         if (unlikely(test_tsk_thread_flag(tsk, TIF_DEBUG)))
116                 flush_thread_hw_breakpoint(tsk);
117         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
118         /*
119          * Forget coprocessor state..
120          */
121         tsk->fpu_counter = 0;
122         clear_fpu(tsk);
123         clear_used_math();
124 }
125
126 static void hard_disable_TSC(void)
127 {
128         write_cr4(read_cr4() | X86_CR4_TSD);
129 }
130
131 void disable_TSC(void)
132 {
133         preempt_disable();
134         if (!test_and_set_thread_flag(TIF_NOTSC))
135                 /*
136                  * Must flip the CPU state synchronously with
137                  * TIF_NOTSC in the current running context.
138                  */
139                 hard_disable_TSC();
140         preempt_enable();
141 }
142
143 static void hard_enable_TSC(void)
144 {
145         write_cr4(read_cr4() & ~X86_CR4_TSD);
146 }
147
148 static void enable_TSC(void)
149 {
150         preempt_disable();
151         if (test_and_clear_thread_flag(TIF_NOTSC))
152                 /*
153                  * Must flip the CPU state synchronously with
154                  * TIF_NOTSC in the current running context.
155                  */
156                 hard_enable_TSC();
157         preempt_enable();
158 }
159
160 int get_tsc_mode(unsigned long adr)
161 {
162         unsigned int val;
163
164         if (test_thread_flag(TIF_NOTSC))
165                 val = PR_TSC_SIGSEGV;
166         else
167                 val = PR_TSC_ENABLE;
168
169         return put_user(val, (unsigned int __user *)adr);
170 }
171
172 int set_tsc_mode(unsigned int val)
173 {
174         if (val == PR_TSC_SIGSEGV)
175                 disable_TSC();
176         else if (val == PR_TSC_ENABLE)
177                 enable_TSC();
178         else
179                 return -EINVAL;
180
181         return 0;
182 }
183
184 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
185                       struct tss_struct *tss)
186 {
187         struct thread_struct *prev, *next;
188
189         prev = &prev_p->thread;
190         next = &next_p->thread;
191
192         if (test_tsk_thread_flag(next_p, TIF_DS_AREA_MSR) ||
193             test_tsk_thread_flag(prev_p, TIF_DS_AREA_MSR))
194                 ds_switch_to(prev_p, next_p);
195         else if (next->debugctlmsr != prev->debugctlmsr)
196                 update_debugctlmsr(next->debugctlmsr);
197
198         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
199             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
200                 /* prev and next are different */
201                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
202                         hard_disable_TSC();
203                 else
204                         hard_enable_TSC();
205         }
206
207         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
208                 /*
209                  * Copy the relevant range of the IO bitmap.
210                  * Normally this is 128 bytes or less:
211                  */
212                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
213                        max(prev->io_bitmap_max, next->io_bitmap_max));
214         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
215                 /*
216                  * Clear any possible leftover bits:
217                  */
218                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
219         }
220 }
221
222 int sys_fork(struct pt_regs *regs)
223 {
224         return do_fork(SIGCHLD, regs->sp, regs, 0, NULL, NULL);
225 }
226
227 /*
228  * This is trivial, and on the face of it looks like it
229  * could equally well be done in user mode.
230  *
231  * Not so, for quite unobvious reasons - register pressure.
232  * In user mode vfork() cannot have a stack frame, and if
233  * done by calling the "clone()" system call directly, you
234  * do not have enough call-clobbered registers to hold all
235  * the information you need.
236  */
237 int sys_vfork(struct pt_regs *regs)
238 {
239         return do_fork(CLONE_VFORK | CLONE_VM | SIGCHLD, regs->sp, regs, 0,
240                        NULL, NULL);
241 }
242
243
244 /*
245  * Idle related variables and functions
246  */
247 unsigned long boot_option_idle_override = 0;
248 EXPORT_SYMBOL(boot_option_idle_override);
249
250 /*
251  * Powermanagement idle function, if any..
252  */
253 void (*pm_idle)(void);
254 EXPORT_SYMBOL(pm_idle);
255
256 #ifdef CONFIG_X86_32
257 /*
258  * This halt magic was a workaround for ancient floppy DMA
259  * wreckage. It should be safe to remove.
260  */
261 static int hlt_counter;
262 void disable_hlt(void)
263 {
264         hlt_counter++;
265 }
266 EXPORT_SYMBOL(disable_hlt);
267
268 void enable_hlt(void)
269 {
270         hlt_counter--;
271 }
272 EXPORT_SYMBOL(enable_hlt);
273
274 static inline int hlt_use_halt(void)
275 {
276         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
277 }
278 #else
279 static inline int hlt_use_halt(void)
280 {
281         return 1;
282 }
283 #endif
284
285 /*
286  * We use this if we don't have any better
287  * idle routine..
288  */
289 void default_idle(void)
290 {
291         if (hlt_use_halt()) {
292                 struct power_trace it;
293
294                 trace_power_start(&it, POWER_CSTATE, 1);
295                 current_thread_info()->status &= ~TS_POLLING;
296                 /*
297                  * TS_POLLING-cleared state must be visible before we
298                  * test NEED_RESCHED:
299                  */
300                 smp_mb();
301
302                 if (!need_resched())
303                         safe_halt();    /* enables interrupts racelessly */
304                 else
305                         local_irq_enable();
306                 current_thread_info()->status |= TS_POLLING;
307                 trace_power_end(&it);
308         } else {
309                 local_irq_enable();
310                 /* loop is done by the caller */
311                 cpu_relax();
312         }
313 }
314 #ifdef CONFIG_APM_MODULE
315 EXPORT_SYMBOL(default_idle);
316 #endif
317
318 void stop_this_cpu(void *dummy)
319 {
320         local_irq_disable();
321         /*
322          * Remove this CPU:
323          */
324         set_cpu_online(smp_processor_id(), false);
325         disable_local_APIC();
326
327         for (;;) {
328                 if (hlt_works(smp_processor_id()))
329                         halt();
330         }
331 }
332
333 static void do_nothing(void *unused)
334 {
335 }
336
337 /*
338  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
339  * pm_idle and update to new pm_idle value. Required while changing pm_idle
340  * handler on SMP systems.
341  *
342  * Caller must have changed pm_idle to the new value before the call. Old
343  * pm_idle value will not be used by any CPU after the return of this function.
344  */
345 void cpu_idle_wait(void)
346 {
347         smp_mb();
348         /* kick all the CPUs so that they exit out of pm_idle */
349         smp_call_function(do_nothing, NULL, 1);
350 }
351 EXPORT_SYMBOL_GPL(cpu_idle_wait);
352
353 /*
354  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
355  * which can obviate IPI to trigger checking of need_resched.
356  * We execute MONITOR against need_resched and enter optimized wait state
357  * through MWAIT. Whenever someone changes need_resched, we would be woken
358  * up from MWAIT (without an IPI).
359  *
360  * New with Core Duo processors, MWAIT can take some hints based on CPU
361  * capability.
362  */
363 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
364 {
365         struct power_trace it;
366
367         trace_power_start(&it, POWER_CSTATE, (ax>>4)+1);
368         if (!need_resched()) {
369                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
370                         clflush((void *)&current_thread_info()->flags);
371
372                 __monitor((void *)&current_thread_info()->flags, 0, 0);
373                 smp_mb();
374                 if (!need_resched())
375                         __mwait(ax, cx);
376         }
377         trace_power_end(&it);
378 }
379
380 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
381 static void mwait_idle(void)
382 {
383         struct power_trace it;
384         if (!need_resched()) {
385                 trace_power_start(&it, POWER_CSTATE, 1);
386                 if (cpu_has(&current_cpu_data, X86_FEATURE_CLFLUSH_MONITOR))
387                         clflush((void *)&current_thread_info()->flags);
388
389                 __monitor((void *)&current_thread_info()->flags, 0, 0);
390                 smp_mb();
391                 if (!need_resched())
392                         __sti_mwait(0, 0);
393                 else
394                         local_irq_enable();
395                 trace_power_end(&it);
396         } else
397                 local_irq_enable();
398 }
399
400 /*
401  * On SMP it's slightly faster (but much more power-consuming!)
402  * to poll the ->work.need_resched flag instead of waiting for the
403  * cross-CPU IPI to arrive. Use this option with caution.
404  */
405 static void poll_idle(void)
406 {
407         struct power_trace it;
408
409         trace_power_start(&it, POWER_CSTATE, 0);
410         local_irq_enable();
411         while (!need_resched())
412                 cpu_relax();
413         trace_power_end(&it);
414 }
415
416 /*
417  * mwait selection logic:
418  *
419  * It depends on the CPU. For AMD CPUs that support MWAIT this is
420  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
421  * then depend on a clock divisor and current Pstate of the core. If
422  * all cores of a processor are in halt state (C1) the processor can
423  * enter the C1E (C1 enhanced) state. If mwait is used this will never
424  * happen.
425  *
426  * idle=mwait overrides this decision and forces the usage of mwait.
427  */
428 static int __cpuinitdata force_mwait;
429
430 #define MWAIT_INFO                      0x05
431 #define MWAIT_ECX_EXTENDED_INFO         0x01
432 #define MWAIT_EDX_C1                    0xf0
433
434 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
435 {
436         u32 eax, ebx, ecx, edx;
437
438         if (force_mwait)
439                 return 1;
440
441         if (c->cpuid_level < MWAIT_INFO)
442                 return 0;
443
444         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
445         /* Check, whether EDX has extended info about MWAIT */
446         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
447                 return 1;
448
449         /*
450          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
451          * C1  supports MWAIT
452          */
453         return (edx & MWAIT_EDX_C1);
454 }
455
456 /*
457  * Check for AMD CPUs, which have potentially C1E support
458  */
459 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
460 {
461         if (c->x86_vendor != X86_VENDOR_AMD)
462                 return 0;
463
464         if (c->x86 < 0x0F)
465                 return 0;
466
467         /* Family 0x0f models < rev F do not have C1E */
468         if (c->x86 == 0x0f && c->x86_model < 0x40)
469                 return 0;
470
471         return 1;
472 }
473
474 static cpumask_var_t c1e_mask;
475 static int c1e_detected;
476
477 void c1e_remove_cpu(int cpu)
478 {
479         if (c1e_mask != NULL)
480                 cpumask_clear_cpu(cpu, c1e_mask);
481 }
482
483 /*
484  * C1E aware idle routine. We check for C1E active in the interrupt
485  * pending message MSR. If we detect C1E, then we handle it the same
486  * way as C3 power states (local apic timer and TSC stop)
487  */
488 static void c1e_idle(void)
489 {
490         if (need_resched())
491                 return;
492
493         if (!c1e_detected) {
494                 u32 lo, hi;
495
496                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
497                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
498                         c1e_detected = 1;
499                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
500                                 mark_tsc_unstable("TSC halt in AMD C1E");
501                         printk(KERN_INFO "System has AMD C1E enabled\n");
502                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
503                 }
504         }
505
506         if (c1e_detected) {
507                 int cpu = smp_processor_id();
508
509                 if (!cpumask_test_cpu(cpu, c1e_mask)) {
510                         cpumask_set_cpu(cpu, c1e_mask);
511                         /*
512                          * Force broadcast so ACPI can not interfere. Needs
513                          * to run with interrupts enabled as it uses
514                          * smp_function_call.
515                          */
516                         local_irq_enable();
517                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
518                                            &cpu);
519                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
520                                cpu);
521                         local_irq_disable();
522                 }
523                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
524
525                 default_idle();
526
527                 /*
528                  * The switch back from broadcast mode needs to be
529                  * called with interrupts disabled.
530                  */
531                  local_irq_disable();
532                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
533                  local_irq_enable();
534         } else
535                 default_idle();
536 }
537
538 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
539 {
540 #ifdef CONFIG_SMP
541         if (pm_idle == poll_idle && smp_num_siblings > 1) {
542                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
543                         " performance may degrade.\n");
544         }
545 #endif
546         if (pm_idle)
547                 return;
548
549         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
550                 /*
551                  * One CPU supports mwait => All CPUs supports mwait
552                  */
553                 printk(KERN_INFO "using mwait in idle threads.\n");
554                 pm_idle = mwait_idle;
555         } else if (check_c1e_idle(c)) {
556                 printk(KERN_INFO "using C1E aware idle routine\n");
557                 pm_idle = c1e_idle;
558         } else
559                 pm_idle = default_idle;
560 }
561
562 void __init init_c1e_mask(void)
563 {
564         /* If we're using c1e_idle, we need to allocate c1e_mask. */
565         if (pm_idle == c1e_idle) {
566                 alloc_cpumask_var(&c1e_mask, GFP_KERNEL);
567                 cpumask_clear(c1e_mask);
568         }
569 }
570
571 static int __init idle_setup(char *str)
572 {
573         if (!str)
574                 return -EINVAL;
575
576         if (!strcmp(str, "poll")) {
577                 printk("using polling idle threads.\n");
578                 pm_idle = poll_idle;
579         } else if (!strcmp(str, "mwait"))
580                 force_mwait = 1;
581         else if (!strcmp(str, "halt")) {
582                 /*
583                  * When the boot option of idle=halt is added, halt is
584                  * forced to be used for CPU idle. In such case CPU C2/C3
585                  * won't be used again.
586                  * To continue to load the CPU idle driver, don't touch
587                  * the boot_option_idle_override.
588                  */
589                 pm_idle = default_idle;
590                 idle_halt = 1;
591                 return 0;
592         } else if (!strcmp(str, "nomwait")) {
593                 /*
594                  * If the boot option of "idle=nomwait" is added,
595                  * it means that mwait will be disabled for CPU C2/C3
596                  * states. In such case it won't touch the variable
597                  * of boot_option_idle_override.
598                  */
599                 idle_nomwait = 1;
600                 return 0;
601         } else
602                 return -1;
603
604         boot_option_idle_override = 1;
605         return 0;
606 }
607 early_param("idle", idle_setup);
608
609 unsigned long arch_align_stack(unsigned long sp)
610 {
611         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
612                 sp -= get_random_int() % 8192;
613         return sp & ~0xf;
614 }
615
616 unsigned long arch_randomize_brk(struct mm_struct *mm)
617 {
618         unsigned long range_end = mm->brk + 0x02000000;
619         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
620 }
621