Merge branches 'x86/apic', 'x86/cleanups', 'x86/cpufeature', 'x86/crashdump', 'x86...
[linux-2.6.git] / arch / x86 / kernel / process.c
1 #include <linux/errno.h>
2 #include <linux/kernel.h>
3 #include <linux/mm.h>
4 #include <asm/idle.h>
5 #include <linux/smp.h>
6 #include <linux/slab.h>
7 #include <linux/sched.h>
8 #include <linux/module.h>
9 #include <linux/pm.h>
10 #include <linux/clockchips.h>
11 #include <asm/system.h>
12 #include <asm/apic.h>
13
14 unsigned long idle_halt;
15 EXPORT_SYMBOL(idle_halt);
16 unsigned long idle_nomwait;
17 EXPORT_SYMBOL(idle_nomwait);
18
19 struct kmem_cache *task_xstate_cachep;
20
21 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
22 {
23         *dst = *src;
24         if (src->thread.xstate) {
25                 dst->thread.xstate = kmem_cache_alloc(task_xstate_cachep,
26                                                       GFP_KERNEL);
27                 if (!dst->thread.xstate)
28                         return -ENOMEM;
29                 WARN_ON((unsigned long)dst->thread.xstate & 15);
30                 memcpy(dst->thread.xstate, src->thread.xstate, xstate_size);
31         }
32         return 0;
33 }
34
35 void free_thread_xstate(struct task_struct *tsk)
36 {
37         if (tsk->thread.xstate) {
38                 kmem_cache_free(task_xstate_cachep, tsk->thread.xstate);
39                 tsk->thread.xstate = NULL;
40         }
41 }
42
43 void free_thread_info(struct thread_info *ti)
44 {
45         free_thread_xstate(ti->task);
46         free_pages((unsigned long)ti, get_order(THREAD_SIZE));
47 }
48
49 void arch_task_cache_init(void)
50 {
51         task_xstate_cachep =
52                 kmem_cache_create("task_xstate", xstate_size,
53                                   __alignof__(union thread_xstate),
54                                   SLAB_PANIC, NULL);
55 }
56
57 /*
58  * Idle related variables and functions
59  */
60 unsigned long boot_option_idle_override = 0;
61 EXPORT_SYMBOL(boot_option_idle_override);
62
63 /*
64  * Powermanagement idle function, if any..
65  */
66 void (*pm_idle)(void);
67 EXPORT_SYMBOL(pm_idle);
68
69 #ifdef CONFIG_X86_32
70 /*
71  * This halt magic was a workaround for ancient floppy DMA
72  * wreckage. It should be safe to remove.
73  */
74 static int hlt_counter;
75 void disable_hlt(void)
76 {
77         hlt_counter++;
78 }
79 EXPORT_SYMBOL(disable_hlt);
80
81 void enable_hlt(void)
82 {
83         hlt_counter--;
84 }
85 EXPORT_SYMBOL(enable_hlt);
86
87 static inline int hlt_use_halt(void)
88 {
89         return (!hlt_counter && boot_cpu_data.hlt_works_ok);
90 }
91 #else
92 static inline int hlt_use_halt(void)
93 {
94         return 1;
95 }
96 #endif
97
98 /*
99  * We use this if we don't have any better
100  * idle routine..
101  */
102 void default_idle(void)
103 {
104         if (hlt_use_halt()) {
105                 current_thread_info()->status &= ~TS_POLLING;
106                 /*
107                  * TS_POLLING-cleared state must be visible before we
108                  * test NEED_RESCHED:
109                  */
110                 smp_mb();
111
112                 if (!need_resched())
113                         safe_halt();    /* enables interrupts racelessly */
114                 else
115                         local_irq_enable();
116                 current_thread_info()->status |= TS_POLLING;
117         } else {
118                 local_irq_enable();
119                 /* loop is done by the caller */
120                 cpu_relax();
121         }
122 }
123 #ifdef CONFIG_APM_MODULE
124 EXPORT_SYMBOL(default_idle);
125 #endif
126
127 void stop_this_cpu(void *dummy)
128 {
129         local_irq_disable();
130         /*
131          * Remove this CPU:
132          */
133         cpu_clear(smp_processor_id(), cpu_online_map);
134         disable_local_APIC();
135
136         for (;;) {
137                 if (hlt_works(smp_processor_id()))
138                         halt();
139         }
140 }
141
142 static void do_nothing(void *unused)
143 {
144 }
145
146 /*
147  * cpu_idle_wait - Used to ensure that all the CPUs discard old value of
148  * pm_idle and update to new pm_idle value. Required while changing pm_idle
149  * handler on SMP systems.
150  *
151  * Caller must have changed pm_idle to the new value before the call. Old
152  * pm_idle value will not be used by any CPU after the return of this function.
153  */
154 void cpu_idle_wait(void)
155 {
156         smp_mb();
157         /* kick all the CPUs so that they exit out of pm_idle */
158         smp_call_function(do_nothing, NULL, 1);
159 }
160 EXPORT_SYMBOL_GPL(cpu_idle_wait);
161
162 /*
163  * This uses new MONITOR/MWAIT instructions on P4 processors with PNI,
164  * which can obviate IPI to trigger checking of need_resched.
165  * We execute MONITOR against need_resched and enter optimized wait state
166  * through MWAIT. Whenever someone changes need_resched, we would be woken
167  * up from MWAIT (without an IPI).
168  *
169  * New with Core Duo processors, MWAIT can take some hints based on CPU
170  * capability.
171  */
172 void mwait_idle_with_hints(unsigned long ax, unsigned long cx)
173 {
174         if (!need_resched()) {
175                 __monitor((void *)&current_thread_info()->flags, 0, 0);
176                 smp_mb();
177                 if (!need_resched())
178                         __mwait(ax, cx);
179         }
180 }
181
182 /* Default MONITOR/MWAIT with no hints, used for default C1 state */
183 static void mwait_idle(void)
184 {
185         if (!need_resched()) {
186                 __monitor((void *)&current_thread_info()->flags, 0, 0);
187                 smp_mb();
188                 if (!need_resched())
189                         __sti_mwait(0, 0);
190                 else
191                         local_irq_enable();
192         } else
193                 local_irq_enable();
194 }
195
196 /*
197  * On SMP it's slightly faster (but much more power-consuming!)
198  * to poll the ->work.need_resched flag instead of waiting for the
199  * cross-CPU IPI to arrive. Use this option with caution.
200  */
201 static void poll_idle(void)
202 {
203         local_irq_enable();
204         while (!need_resched())
205                 cpu_relax();
206 }
207
208 /*
209  * mwait selection logic:
210  *
211  * It depends on the CPU. For AMD CPUs that support MWAIT this is
212  * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings
213  * then depend on a clock divisor and current Pstate of the core. If
214  * all cores of a processor are in halt state (C1) the processor can
215  * enter the C1E (C1 enhanced) state. If mwait is used this will never
216  * happen.
217  *
218  * idle=mwait overrides this decision and forces the usage of mwait.
219  */
220 static int __cpuinitdata force_mwait;
221
222 #define MWAIT_INFO                      0x05
223 #define MWAIT_ECX_EXTENDED_INFO         0x01
224 #define MWAIT_EDX_C1                    0xf0
225
226 static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
227 {
228         u32 eax, ebx, ecx, edx;
229
230         if (force_mwait)
231                 return 1;
232
233         if (c->cpuid_level < MWAIT_INFO)
234                 return 0;
235
236         cpuid(MWAIT_INFO, &eax, &ebx, &ecx, &edx);
237         /* Check, whether EDX has extended info about MWAIT */
238         if (!(ecx & MWAIT_ECX_EXTENDED_INFO))
239                 return 1;
240
241         /*
242          * edx enumeratios MONITOR/MWAIT extensions. Check, whether
243          * C1  supports MWAIT
244          */
245         return (edx & MWAIT_EDX_C1);
246 }
247
248 /*
249  * Check for AMD CPUs, which have potentially C1E support
250  */
251 static int __cpuinit check_c1e_idle(const struct cpuinfo_x86 *c)
252 {
253         if (c->x86_vendor != X86_VENDOR_AMD)
254                 return 0;
255
256         if (c->x86 < 0x0F)
257                 return 0;
258
259         /* Family 0x0f models < rev F do not have C1E */
260         if (c->x86 == 0x0f && c->x86_model < 0x40)
261                 return 0;
262
263         return 1;
264 }
265
266 static cpumask_t c1e_mask = CPU_MASK_NONE;
267 static int c1e_detected;
268
269 void c1e_remove_cpu(int cpu)
270 {
271         cpu_clear(cpu, c1e_mask);
272 }
273
274 /*
275  * C1E aware idle routine. We check for C1E active in the interrupt
276  * pending message MSR. If we detect C1E, then we handle it the same
277  * way as C3 power states (local apic timer and TSC stop)
278  */
279 static void c1e_idle(void)
280 {
281         if (need_resched())
282                 return;
283
284         if (!c1e_detected) {
285                 u32 lo, hi;
286
287                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
288                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
289                         c1e_detected = 1;
290                         if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
291                                 mark_tsc_unstable("TSC halt in AMD C1E");
292                         printk(KERN_INFO "System has AMD C1E enabled\n");
293                         set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
294                 }
295         }
296
297         if (c1e_detected) {
298                 int cpu = smp_processor_id();
299
300                 if (!cpu_isset(cpu, c1e_mask)) {
301                         cpu_set(cpu, c1e_mask);
302                         /*
303                          * Force broadcast so ACPI can not interfere. Needs
304                          * to run with interrupts enabled as it uses
305                          * smp_function_call.
306                          */
307                         local_irq_enable();
308                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
309                                            &cpu);
310                         printk(KERN_INFO "Switch to broadcast mode on CPU%d\n",
311                                cpu);
312                         local_irq_disable();
313                 }
314                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
315
316                 default_idle();
317
318                 /*
319                  * The switch back from broadcast mode needs to be
320                  * called with interrupts disabled.
321                  */
322                  local_irq_disable();
323                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
324                  local_irq_enable();
325         } else
326                 default_idle();
327 }
328
329 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
330 {
331 #ifdef CONFIG_X86_SMP
332         if (pm_idle == poll_idle && smp_num_siblings > 1) {
333                 printk(KERN_WARNING "WARNING: polling idle and HT enabled,"
334                         " performance may degrade.\n");
335         }
336 #endif
337         if (pm_idle)
338                 return;
339
340         if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) {
341                 /*
342                  * One CPU supports mwait => All CPUs supports mwait
343                  */
344                 printk(KERN_INFO "using mwait in idle threads.\n");
345                 pm_idle = mwait_idle;
346         } else if (check_c1e_idle(c)) {
347                 printk(KERN_INFO "using C1E aware idle routine\n");
348                 pm_idle = c1e_idle;
349         } else
350                 pm_idle = default_idle;
351 }
352
353 static int __init idle_setup(char *str)
354 {
355         if (!str)
356                 return -EINVAL;
357
358         if (!strcmp(str, "poll")) {
359                 printk("using polling idle threads.\n");
360                 pm_idle = poll_idle;
361         } else if (!strcmp(str, "mwait"))
362                 force_mwait = 1;
363         else if (!strcmp(str, "halt")) {
364                 /*
365                  * When the boot option of idle=halt is added, halt is
366                  * forced to be used for CPU idle. In such case CPU C2/C3
367                  * won't be used again.
368                  * To continue to load the CPU idle driver, don't touch
369                  * the boot_option_idle_override.
370                  */
371                 pm_idle = default_idle;
372                 idle_halt = 1;
373                 return 0;
374         } else if (!strcmp(str, "nomwait")) {
375                 /*
376                  * If the boot option of "idle=nomwait" is added,
377                  * it means that mwait will be disabled for CPU C2/C3
378                  * states. In such case it won't touch the variable
379                  * of boot_option_idle_override.
380                  */
381                 idle_nomwait = 1;
382                 return 0;
383         } else
384                 return -1;
385
386         boot_option_idle_override = 1;
387         return 0;
388 }
389 early_param("idle", idle_setup);
390