4ee1e5ee9b5732f3bd0dca4f771df97287ba86bd
[linux-2.6.git] / arch / x86 / kernel / io_apic_32.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38
39 #include <asm/io.h>
40 #include <asm/smp.h>
41 #include <asm/desc.h>
42 #include <asm/timer.h>
43 #include <asm/i8259.h>
44 #include <asm/nmi.h>
45 #include <asm/msidef.h>
46 #include <asm/hypertransport.h>
47
48 #include <mach_apic.h>
49 #include <mach_apicdef.h>
50
51 #include "io_ports.h"
52
53 int (*ioapic_renumber_irq)(int ioapic, int irq);
54 atomic_t irq_mis_count;
55
56 /* Where if anywhere is the i8259 connect in external int mode */
57 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
58
59 static DEFINE_SPINLOCK(ioapic_lock);
60 static DEFINE_SPINLOCK(vector_lock);
61
62 int timer_over_8254 __initdata = 1;
63
64 /*
65  *      Is the SiS APIC rmw bug present ?
66  *      -1 = don't know, 0 = no, 1 = yes
67  */
68 int sis_apic_bug = -1;
69
70 /*
71  * # of IRQ routing registers
72  */
73 int nr_ioapic_registers[MAX_IO_APICS];
74
75 static int disable_timer_pin_1 __initdata;
76
77 /*
78  * Rough estimation of how many shared IRQs there are, can
79  * be changed anytime.
80  */
81 #define MAX_PLUS_SHARED_IRQS NR_IRQS
82 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
83
84 /*
85  * This is performance-critical, we want to do it O(1)
86  *
87  * the indexing order of this array favors 1:1 mappings
88  * between pins and IRQs.
89  */
90
91 static struct irq_pin_list {
92         int apic, pin, next;
93 } irq_2_pin[PIN_MAP_SIZE];
94
95 struct io_apic {
96         unsigned int index;
97         unsigned int unused[3];
98         unsigned int data;
99 };
100
101 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
102 {
103         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
104                 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
105 }
106
107 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
108 {
109         struct io_apic __iomem *io_apic = io_apic_base(apic);
110         writel(reg, &io_apic->index);
111         return readl(&io_apic->data);
112 }
113
114 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
115 {
116         struct io_apic __iomem *io_apic = io_apic_base(apic);
117         writel(reg, &io_apic->index);
118         writel(value, &io_apic->data);
119 }
120
121 /*
122  * Re-write a value: to be used for read-modify-write
123  * cycles where the read already set up the index register.
124  *
125  * Older SiS APIC requires we rewrite the index register
126  */
127 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
128 {
129         volatile struct io_apic __iomem *io_apic = io_apic_base(apic);
130         if (sis_apic_bug)
131                 writel(reg, &io_apic->index);
132         writel(value, &io_apic->data);
133 }
134
135 union entry_union {
136         struct { u32 w1, w2; };
137         struct IO_APIC_route_entry entry;
138 };
139
140 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
141 {
142         union entry_union eu;
143         unsigned long flags;
144         spin_lock_irqsave(&ioapic_lock, flags);
145         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
146         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
147         spin_unlock_irqrestore(&ioapic_lock, flags);
148         return eu.entry;
149 }
150
151 /*
152  * When we write a new IO APIC routing entry, we need to write the high
153  * word first! If the mask bit in the low word is clear, we will enable
154  * the interrupt, and we need to make sure the entry is fully populated
155  * before that happens.
156  */
157 static void
158 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
159 {
160         union entry_union eu;
161         eu.entry = e;
162         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
163         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
164 }
165
166 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
167 {
168         unsigned long flags;
169         spin_lock_irqsave(&ioapic_lock, flags);
170         __ioapic_write_entry(apic, pin, e);
171         spin_unlock_irqrestore(&ioapic_lock, flags);
172 }
173
174 /*
175  * When we mask an IO APIC routing entry, we need to write the low
176  * word first, in order to set the mask bit before we change the
177  * high bits!
178  */
179 static void ioapic_mask_entry(int apic, int pin)
180 {
181         unsigned long flags;
182         union entry_union eu = { .entry.mask = 1 };
183
184         spin_lock_irqsave(&ioapic_lock, flags);
185         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
186         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
187         spin_unlock_irqrestore(&ioapic_lock, flags);
188 }
189
190 /*
191  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
192  * shared ISA-space IRQs, so we have to support them. We are super
193  * fast in the common case, and fast for shared ISA-space IRQs.
194  */
195 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
196 {
197         static int first_free_entry = NR_IRQS;
198         struct irq_pin_list *entry = irq_2_pin + irq;
199
200         while (entry->next)
201                 entry = irq_2_pin + entry->next;
202
203         if (entry->pin != -1) {
204                 entry->next = first_free_entry;
205                 entry = irq_2_pin + entry->next;
206                 if (++first_free_entry >= PIN_MAP_SIZE)
207                         panic("io_apic.c: whoops");
208         }
209         entry->apic = apic;
210         entry->pin = pin;
211 }
212
213 /*
214  * Reroute an IRQ to a different pin.
215  */
216 static void __init replace_pin_at_irq(unsigned int irq,
217                                       int oldapic, int oldpin,
218                                       int newapic, int newpin)
219 {
220         struct irq_pin_list *entry = irq_2_pin + irq;
221
222         while (1) {
223                 if (entry->apic == oldapic && entry->pin == oldpin) {
224                         entry->apic = newapic;
225                         entry->pin = newpin;
226                 }
227                 if (!entry->next)
228                         break;
229                 entry = irq_2_pin + entry->next;
230         }
231 }
232
233 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
234 {
235         struct irq_pin_list *entry = irq_2_pin + irq;
236         unsigned int pin, reg;
237
238         for (;;) {
239                 pin = entry->pin;
240                 if (pin == -1)
241                         break;
242                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
243                 reg &= ~disable;
244                 reg |= enable;
245                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
246                 if (!entry->next)
247                         break;
248                 entry = irq_2_pin + entry->next;
249         }
250 }
251
252 /* mask = 1 */
253 static void __mask_IO_APIC_irq (unsigned int irq)
254 {
255         __modify_IO_APIC_irq(irq, 0x00010000, 0);
256 }
257
258 /* mask = 0 */
259 static void __unmask_IO_APIC_irq (unsigned int irq)
260 {
261         __modify_IO_APIC_irq(irq, 0, 0x00010000);
262 }
263
264 /* mask = 1, trigger = 0 */
265 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
266 {
267         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
268 }
269
270 /* mask = 0, trigger = 1 */
271 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
272 {
273         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
274 }
275
276 static void mask_IO_APIC_irq (unsigned int irq)
277 {
278         unsigned long flags;
279
280         spin_lock_irqsave(&ioapic_lock, flags);
281         __mask_IO_APIC_irq(irq);
282         spin_unlock_irqrestore(&ioapic_lock, flags);
283 }
284
285 static void unmask_IO_APIC_irq (unsigned int irq)
286 {
287         unsigned long flags;
288
289         spin_lock_irqsave(&ioapic_lock, flags);
290         __unmask_IO_APIC_irq(irq);
291         spin_unlock_irqrestore(&ioapic_lock, flags);
292 }
293
294 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
295 {
296         struct IO_APIC_route_entry entry;
297         
298         /* Check delivery_mode to be sure we're not clearing an SMI pin */
299         entry = ioapic_read_entry(apic, pin);
300         if (entry.delivery_mode == dest_SMI)
301                 return;
302
303         /*
304          * Disable it in the IO-APIC irq-routing table:
305          */
306         ioapic_mask_entry(apic, pin);
307 }
308
309 static void clear_IO_APIC (void)
310 {
311         int apic, pin;
312
313         for (apic = 0; apic < nr_ioapics; apic++)
314                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
315                         clear_IO_APIC_pin(apic, pin);
316 }
317
318 #ifdef CONFIG_SMP
319 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
320 {
321         unsigned long flags;
322         int pin;
323         struct irq_pin_list *entry = irq_2_pin + irq;
324         unsigned int apicid_value;
325         cpumask_t tmp;
326         
327         cpus_and(tmp, cpumask, cpu_online_map);
328         if (cpus_empty(tmp))
329                 tmp = TARGET_CPUS;
330
331         cpus_and(cpumask, tmp, CPU_MASK_ALL);
332
333         apicid_value = cpu_mask_to_apicid(cpumask);
334         /* Prepare to do the io_apic_write */
335         apicid_value = apicid_value << 24;
336         spin_lock_irqsave(&ioapic_lock, flags);
337         for (;;) {
338                 pin = entry->pin;
339                 if (pin == -1)
340                         break;
341                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
342                 if (!entry->next)
343                         break;
344                 entry = irq_2_pin + entry->next;
345         }
346         irq_desc[irq].affinity = cpumask;
347         spin_unlock_irqrestore(&ioapic_lock, flags);
348 }
349
350 #if defined(CONFIG_IRQBALANCE)
351 # include <asm/processor.h>     /* kernel_thread() */
352 # include <linux/kernel_stat.h> /* kstat */
353 # include <linux/slab.h>                /* kmalloc() */
354 # include <linux/timer.h>       /* time_after() */
355  
356 #define IRQBALANCE_CHECK_ARCH -999
357 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
358 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
359 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
360 #define BALANCED_IRQ_LESS_DELTA         (HZ)
361
362 static int irqbalance_disabled __read_mostly = IRQBALANCE_CHECK_ARCH;
363 static int physical_balance __read_mostly;
364 static long balanced_irq_interval __read_mostly = MAX_BALANCED_IRQ_INTERVAL;
365
366 static struct irq_cpu_info {
367         unsigned long * last_irq;
368         unsigned long * irq_delta;
369         unsigned long irq;
370 } irq_cpu_data[NR_CPUS];
371
372 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
373 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
374 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
375
376 #define IDLE_ENOUGH(cpu,now) \
377         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
378
379 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
380
381 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
382
383 static cpumask_t balance_irq_affinity[NR_IRQS] = {
384         [0 ... NR_IRQS-1] = CPU_MASK_ALL
385 };
386
387 void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
388 {
389         balance_irq_affinity[irq] = mask;
390 }
391
392 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
393                         unsigned long now, int direction)
394 {
395         int search_idle = 1;
396         int cpu = curr_cpu;
397
398         goto inside;
399
400         do {
401                 if (unlikely(cpu == curr_cpu))
402                         search_idle = 0;
403 inside:
404                 if (direction == 1) {
405                         cpu++;
406                         if (cpu >= NR_CPUS)
407                                 cpu = 0;
408                 } else {
409                         cpu--;
410                         if (cpu == -1)
411                                 cpu = NR_CPUS-1;
412                 }
413         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
414                         (search_idle && !IDLE_ENOUGH(cpu,now)));
415
416         return cpu;
417 }
418
419 static inline void balance_irq(int cpu, int irq)
420 {
421         unsigned long now = jiffies;
422         cpumask_t allowed_mask;
423         unsigned int new_cpu;
424                 
425         if (irqbalance_disabled)
426                 return; 
427
428         cpus_and(allowed_mask, cpu_online_map, balance_irq_affinity[irq]);
429         new_cpu = move(cpu, allowed_mask, now, 1);
430         if (cpu != new_cpu) {
431                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
432         }
433 }
434
435 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
436 {
437         int i, j;
438
439         for_each_online_cpu(i) {
440                 for (j = 0; j < NR_IRQS; j++) {
441                         if (!irq_desc[j].action)
442                                 continue;
443                         /* Is it a significant load ?  */
444                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
445                                                 useful_load_threshold)
446                                 continue;
447                         balance_irq(i, j);
448                 }
449         }
450         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
451                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
452         return;
453 }
454
455 static void do_irq_balance(void)
456 {
457         int i, j;
458         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
459         unsigned long move_this_load = 0;
460         int max_loaded = 0, min_loaded = 0;
461         int load;
462         unsigned long useful_load_threshold = balanced_irq_interval + 10;
463         int selected_irq;
464         int tmp_loaded, first_attempt = 1;
465         unsigned long tmp_cpu_irq;
466         unsigned long imbalance = 0;
467         cpumask_t allowed_mask, target_cpu_mask, tmp;
468
469         for_each_possible_cpu(i) {
470                 int package_index;
471                 CPU_IRQ(i) = 0;
472                 if (!cpu_online(i))
473                         continue;
474                 package_index = CPU_TO_PACKAGEINDEX(i);
475                 for (j = 0; j < NR_IRQS; j++) {
476                         unsigned long value_now, delta;
477                         /* Is this an active IRQ or balancing disabled ? */
478                         if (!irq_desc[j].action || irq_balancing_disabled(j))
479                                 continue;
480                         if ( package_index == i )
481                                 IRQ_DELTA(package_index,j) = 0;
482                         /* Determine the total count per processor per IRQ */
483                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
484
485                         /* Determine the activity per processor per IRQ */
486                         delta = value_now - LAST_CPU_IRQ(i,j);
487
488                         /* Update last_cpu_irq[][] for the next time */
489                         LAST_CPU_IRQ(i,j) = value_now;
490
491                         /* Ignore IRQs whose rate is less than the clock */
492                         if (delta < useful_load_threshold)
493                                 continue;
494                         /* update the load for the processor or package total */
495                         IRQ_DELTA(package_index,j) += delta;
496
497                         /* Keep track of the higher numbered sibling as well */
498                         if (i != package_index)
499                                 CPU_IRQ(i) += delta;
500                         /*
501                          * We have sibling A and sibling B in the package
502                          *
503                          * cpu_irq[A] = load for cpu A + load for cpu B
504                          * cpu_irq[B] = load for cpu B
505                          */
506                         CPU_IRQ(package_index) += delta;
507                 }
508         }
509         /* Find the least loaded processor package */
510         for_each_online_cpu(i) {
511                 if (i != CPU_TO_PACKAGEINDEX(i))
512                         continue;
513                 if (min_cpu_irq > CPU_IRQ(i)) {
514                         min_cpu_irq = CPU_IRQ(i);
515                         min_loaded = i;
516                 }
517         }
518         max_cpu_irq = ULONG_MAX;
519
520 tryanothercpu:
521         /* Look for heaviest loaded processor.
522          * We may come back to get the next heaviest loaded processor.
523          * Skip processors with trivial loads.
524          */
525         tmp_cpu_irq = 0;
526         tmp_loaded = -1;
527         for_each_online_cpu(i) {
528                 if (i != CPU_TO_PACKAGEINDEX(i))
529                         continue;
530                 if (max_cpu_irq <= CPU_IRQ(i)) 
531                         continue;
532                 if (tmp_cpu_irq < CPU_IRQ(i)) {
533                         tmp_cpu_irq = CPU_IRQ(i);
534                         tmp_loaded = i;
535                 }
536         }
537
538         if (tmp_loaded == -1) {
539          /* In the case of small number of heavy interrupt sources, 
540           * loading some of the cpus too much. We use Ingo's original 
541           * approach to rotate them around.
542           */
543                 if (!first_attempt && imbalance >= useful_load_threshold) {
544                         rotate_irqs_among_cpus(useful_load_threshold);
545                         return;
546                 }
547                 goto not_worth_the_effort;
548         }
549         
550         first_attempt = 0;              /* heaviest search */
551         max_cpu_irq = tmp_cpu_irq;      /* load */
552         max_loaded = tmp_loaded;        /* processor */
553         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
554         
555         /* if imbalance is less than approx 10% of max load, then
556          * observe diminishing returns action. - quit
557          */
558         if (imbalance < (max_cpu_irq >> 3))
559                 goto not_worth_the_effort;
560
561 tryanotherirq:
562         /* if we select an IRQ to move that can't go where we want, then
563          * see if there is another one to try.
564          */
565         move_this_load = 0;
566         selected_irq = -1;
567         for (j = 0; j < NR_IRQS; j++) {
568                 /* Is this an active IRQ? */
569                 if (!irq_desc[j].action)
570                         continue;
571                 if (imbalance <= IRQ_DELTA(max_loaded,j))
572                         continue;
573                 /* Try to find the IRQ that is closest to the imbalance
574                  * without going over.
575                  */
576                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
577                         move_this_load = IRQ_DELTA(max_loaded,j);
578                         selected_irq = j;
579                 }
580         }
581         if (selected_irq == -1) {
582                 goto tryanothercpu;
583         }
584
585         imbalance = move_this_load;
586         
587         /* For physical_balance case, we accumlated both load
588          * values in the one of the siblings cpu_irq[],
589          * to use the same code for physical and logical processors
590          * as much as possible. 
591          *
592          * NOTE: the cpu_irq[] array holds the sum of the load for
593          * sibling A and sibling B in the slot for the lowest numbered
594          * sibling (A), _AND_ the load for sibling B in the slot for
595          * the higher numbered sibling.
596          *
597          * We seek the least loaded sibling by making the comparison
598          * (A+B)/2 vs B
599          */
600         load = CPU_IRQ(min_loaded) >> 1;
601         for_each_cpu_mask(j, per_cpu(cpu_sibling_map, min_loaded)) {
602                 if (load > CPU_IRQ(j)) {
603                         /* This won't change cpu_sibling_map[min_loaded] */
604                         load = CPU_IRQ(j);
605                         min_loaded = j;
606                 }
607         }
608
609         cpus_and(allowed_mask,
610                 cpu_online_map,
611                 balance_irq_affinity[selected_irq]);
612         target_cpu_mask = cpumask_of_cpu(min_loaded);
613         cpus_and(tmp, target_cpu_mask, allowed_mask);
614
615         if (!cpus_empty(tmp)) {
616                 /* mark for change destination */
617                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
618
619                 /* Since we made a change, come back sooner to 
620                  * check for more variation.
621                  */
622                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
623                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);       
624                 return;
625         }
626         goto tryanotherirq;
627
628 not_worth_the_effort:
629         /*
630          * if we did not find an IRQ to move, then adjust the time interval
631          * upward
632          */
633         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
634                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);       
635         return;
636 }
637
638 static int balanced_irq(void *unused)
639 {
640         int i;
641         unsigned long prev_balance_time = jiffies;
642         long time_remaining = balanced_irq_interval;
643
644         /* push everything to CPU 0 to give us a starting point.  */
645         for (i = 0 ; i < NR_IRQS ; i++) {
646                 irq_desc[i].pending_mask = cpumask_of_cpu(0);
647                 set_pending_irq(i, cpumask_of_cpu(0));
648         }
649
650         set_freezable();
651         for ( ; ; ) {
652                 time_remaining = schedule_timeout_interruptible(time_remaining);
653                 try_to_freeze();
654                 if (time_after(jiffies,
655                                 prev_balance_time+balanced_irq_interval)) {
656                         preempt_disable();
657                         do_irq_balance();
658                         prev_balance_time = jiffies;
659                         time_remaining = balanced_irq_interval;
660                         preempt_enable();
661                 }
662         }
663         return 0;
664 }
665
666 static int __init balanced_irq_init(void)
667 {
668         int i;
669         struct cpuinfo_x86 *c;
670         cpumask_t tmp;
671
672         cpus_shift_right(tmp, cpu_online_map, 2);
673         c = &boot_cpu_data;
674         /* When not overwritten by the command line ask subarchitecture. */
675         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
676                 irqbalance_disabled = NO_BALANCE_IRQ;
677         if (irqbalance_disabled)
678                 return 0;
679         
680          /* disable irqbalance completely if there is only one processor online */
681         if (num_online_cpus() < 2) {
682                 irqbalance_disabled = 1;
683                 return 0;
684         }
685         /*
686          * Enable physical balance only if more than 1 physical processor
687          * is present
688          */
689         if (smp_num_siblings > 1 && !cpus_empty(tmp))
690                 physical_balance = 1;
691
692         for_each_online_cpu(i) {
693                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
694                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
695                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
696                         printk(KERN_ERR "balanced_irq_init: out of memory");
697                         goto failed;
698                 }
699                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
700                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
701         }
702         
703         printk(KERN_INFO "Starting balanced_irq\n");
704         if (!IS_ERR(kthread_run(balanced_irq, NULL, "kirqd")))
705                 return 0;
706         printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
707 failed:
708         for_each_possible_cpu(i) {
709                 kfree(irq_cpu_data[i].irq_delta);
710                 irq_cpu_data[i].irq_delta = NULL;
711                 kfree(irq_cpu_data[i].last_irq);
712                 irq_cpu_data[i].last_irq = NULL;
713         }
714         return 0;
715 }
716
717 int __devinit irqbalance_disable(char *str)
718 {
719         irqbalance_disabled = 1;
720         return 1;
721 }
722
723 __setup("noirqbalance", irqbalance_disable);
724
725 late_initcall(balanced_irq_init);
726 #endif /* CONFIG_IRQBALANCE */
727 #endif /* CONFIG_SMP */
728
729 #ifndef CONFIG_SMP
730 void fastcall send_IPI_self(int vector)
731 {
732         unsigned int cfg;
733
734         /*
735          * Wait for idle.
736          */
737         apic_wait_icr_idle();
738         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
739         /*
740          * Send the IPI. The write to APIC_ICR fires this off.
741          */
742         apic_write_around(APIC_ICR, cfg);
743 }
744 #endif /* !CONFIG_SMP */
745
746
747 /*
748  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
749  * specific CPU-side IRQs.
750  */
751
752 #define MAX_PIRQS 8
753 static int pirq_entries [MAX_PIRQS];
754 static int pirqs_enabled;
755 int skip_ioapic_setup;
756
757 static int __init ioapic_pirq_setup(char *str)
758 {
759         int i, max;
760         int ints[MAX_PIRQS+1];
761
762         get_options(str, ARRAY_SIZE(ints), ints);
763
764         for (i = 0; i < MAX_PIRQS; i++)
765                 pirq_entries[i] = -1;
766
767         pirqs_enabled = 1;
768         apic_printk(APIC_VERBOSE, KERN_INFO
769                         "PIRQ redirection, working around broken MP-BIOS.\n");
770         max = MAX_PIRQS;
771         if (ints[0] < MAX_PIRQS)
772                 max = ints[0];
773
774         for (i = 0; i < max; i++) {
775                 apic_printk(APIC_VERBOSE, KERN_DEBUG
776                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
777                 /*
778                  * PIRQs are mapped upside down, usually.
779                  */
780                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
781         }
782         return 1;
783 }
784
785 __setup("pirq=", ioapic_pirq_setup);
786
787 /*
788  * Find the IRQ entry number of a certain pin.
789  */
790 static int find_irq_entry(int apic, int pin, int type)
791 {
792         int i;
793
794         for (i = 0; i < mp_irq_entries; i++)
795                 if (mp_irqs[i].mpc_irqtype == type &&
796                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
797                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
798                     mp_irqs[i].mpc_dstirq == pin)
799                         return i;
800
801         return -1;
802 }
803
804 /*
805  * Find the pin to which IRQ[irq] (ISA) is connected
806  */
807 static int __init find_isa_irq_pin(int irq, int type)
808 {
809         int i;
810
811         for (i = 0; i < mp_irq_entries; i++) {
812                 int lbus = mp_irqs[i].mpc_srcbus;
813
814                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
815                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
816                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
817                     ) &&
818                     (mp_irqs[i].mpc_irqtype == type) &&
819                     (mp_irqs[i].mpc_srcbusirq == irq))
820
821                         return mp_irqs[i].mpc_dstirq;
822         }
823         return -1;
824 }
825
826 static int __init find_isa_irq_apic(int irq, int type)
827 {
828         int i;
829
830         for (i = 0; i < mp_irq_entries; i++) {
831                 int lbus = mp_irqs[i].mpc_srcbus;
832
833                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
834                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
835                      mp_bus_id_to_type[lbus] == MP_BUS_MCA
836                     ) &&
837                     (mp_irqs[i].mpc_irqtype == type) &&
838                     (mp_irqs[i].mpc_srcbusirq == irq))
839                         break;
840         }
841         if (i < mp_irq_entries) {
842                 int apic;
843                 for(apic = 0; apic < nr_ioapics; apic++) {
844                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
845                                 return apic;
846                 }
847         }
848
849         return -1;
850 }
851
852 /*
853  * Find a specific PCI IRQ entry.
854  * Not an __init, possibly needed by modules
855  */
856 static int pin_2_irq(int idx, int apic, int pin);
857
858 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
859 {
860         int apic, i, best_guess = -1;
861
862         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
863                 "slot:%d, pin:%d.\n", bus, slot, pin);
864         if (mp_bus_id_to_pci_bus[bus] == -1) {
865                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
866                 return -1;
867         }
868         for (i = 0; i < mp_irq_entries; i++) {
869                 int lbus = mp_irqs[i].mpc_srcbus;
870
871                 for (apic = 0; apic < nr_ioapics; apic++)
872                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
873                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
874                                 break;
875
876                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
877                     !mp_irqs[i].mpc_irqtype &&
878                     (bus == lbus) &&
879                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
880                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
881
882                         if (!(apic || IO_APIC_IRQ(irq)))
883                                 continue;
884
885                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
886                                 return irq;
887                         /*
888                          * Use the first all-but-pin matching entry as a
889                          * best-guess fuzzy result for broken mptables.
890                          */
891                         if (best_guess < 0)
892                                 best_guess = irq;
893                 }
894         }
895         return best_guess;
896 }
897 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
898
899 /*
900  * This function currently is only a helper for the i386 smp boot process where 
901  * we need to reprogram the ioredtbls to cater for the cpus which have come online
902  * so mask in all cases should simply be TARGET_CPUS
903  */
904 #ifdef CONFIG_SMP
905 void __init setup_ioapic_dest(void)
906 {
907         int pin, ioapic, irq, irq_entry;
908
909         if (skip_ioapic_setup == 1)
910                 return;
911
912         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
913                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
914                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
915                         if (irq_entry == -1)
916                                 continue;
917                         irq = pin_2_irq(irq_entry, ioapic, pin);
918                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
919                 }
920
921         }
922 }
923 #endif
924
925 /*
926  * EISA Edge/Level control register, ELCR
927  */
928 static int EISA_ELCR(unsigned int irq)
929 {
930         if (irq < 16) {
931                 unsigned int port = 0x4d0 + (irq >> 3);
932                 return (inb(port) >> (irq & 7)) & 1;
933         }
934         apic_printk(APIC_VERBOSE, KERN_INFO
935                         "Broken MPtable reports ISA irq %d\n", irq);
936         return 0;
937 }
938
939 /* EISA interrupts are always polarity zero and can be edge or level
940  * trigger depending on the ELCR value.  If an interrupt is listed as
941  * EISA conforming in the MP table, that means its trigger type must
942  * be read in from the ELCR */
943
944 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
945 #define default_EISA_polarity(idx)      (0)
946
947 /* ISA interrupts are always polarity zero edge triggered,
948  * when listed as conforming in the MP table. */
949
950 #define default_ISA_trigger(idx)        (0)
951 #define default_ISA_polarity(idx)       (0)
952
953 /* PCI interrupts are always polarity one level triggered,
954  * when listed as conforming in the MP table. */
955
956 #define default_PCI_trigger(idx)        (1)
957 #define default_PCI_polarity(idx)       (1)
958
959 /* MCA interrupts are always polarity zero level triggered,
960  * when listed as conforming in the MP table. */
961
962 #define default_MCA_trigger(idx)        (1)
963 #define default_MCA_polarity(idx)       (0)
964
965 static int __init MPBIOS_polarity(int idx)
966 {
967         int bus = mp_irqs[idx].mpc_srcbus;
968         int polarity;
969
970         /*
971          * Determine IRQ line polarity (high active or low active):
972          */
973         switch (mp_irqs[idx].mpc_irqflag & 3)
974         {
975                 case 0: /* conforms, ie. bus-type dependent polarity */
976                 {
977                         switch (mp_bus_id_to_type[bus])
978                         {
979                                 case MP_BUS_ISA: /* ISA pin */
980                                 {
981                                         polarity = default_ISA_polarity(idx);
982                                         break;
983                                 }
984                                 case MP_BUS_EISA: /* EISA pin */
985                                 {
986                                         polarity = default_EISA_polarity(idx);
987                                         break;
988                                 }
989                                 case MP_BUS_PCI: /* PCI pin */
990                                 {
991                                         polarity = default_PCI_polarity(idx);
992                                         break;
993                                 }
994                                 case MP_BUS_MCA: /* MCA pin */
995                                 {
996                                         polarity = default_MCA_polarity(idx);
997                                         break;
998                                 }
999                                 default:
1000                                 {
1001                                         printk(KERN_WARNING "broken BIOS!!\n");
1002                                         polarity = 1;
1003                                         break;
1004                                 }
1005                         }
1006                         break;
1007                 }
1008                 case 1: /* high active */
1009                 {
1010                         polarity = 0;
1011                         break;
1012                 }
1013                 case 2: /* reserved */
1014                 {
1015                         printk(KERN_WARNING "broken BIOS!!\n");
1016                         polarity = 1;
1017                         break;
1018                 }
1019                 case 3: /* low active */
1020                 {
1021                         polarity = 1;
1022                         break;
1023                 }
1024                 default: /* invalid */
1025                 {
1026                         printk(KERN_WARNING "broken BIOS!!\n");
1027                         polarity = 1;
1028                         break;
1029                 }
1030         }
1031         return polarity;
1032 }
1033
1034 static int MPBIOS_trigger(int idx)
1035 {
1036         int bus = mp_irqs[idx].mpc_srcbus;
1037         int trigger;
1038
1039         /*
1040          * Determine IRQ trigger mode (edge or level sensitive):
1041          */
1042         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
1043         {
1044                 case 0: /* conforms, ie. bus-type dependent */
1045                 {
1046                         switch (mp_bus_id_to_type[bus])
1047                         {
1048                                 case MP_BUS_ISA: /* ISA pin */
1049                                 {
1050                                         trigger = default_ISA_trigger(idx);
1051                                         break;
1052                                 }
1053                                 case MP_BUS_EISA: /* EISA pin */
1054                                 {
1055                                         trigger = default_EISA_trigger(idx);
1056                                         break;
1057                                 }
1058                                 case MP_BUS_PCI: /* PCI pin */
1059                                 {
1060                                         trigger = default_PCI_trigger(idx);
1061                                         break;
1062                                 }
1063                                 case MP_BUS_MCA: /* MCA pin */
1064                                 {
1065                                         trigger = default_MCA_trigger(idx);
1066                                         break;
1067                                 }
1068                                 default:
1069                                 {
1070                                         printk(KERN_WARNING "broken BIOS!!\n");
1071                                         trigger = 1;
1072                                         break;
1073                                 }
1074                         }
1075                         break;
1076                 }
1077                 case 1: /* edge */
1078                 {
1079                         trigger = 0;
1080                         break;
1081                 }
1082                 case 2: /* reserved */
1083                 {
1084                         printk(KERN_WARNING "broken BIOS!!\n");
1085                         trigger = 1;
1086                         break;
1087                 }
1088                 case 3: /* level */
1089                 {
1090                         trigger = 1;
1091                         break;
1092                 }
1093                 default: /* invalid */
1094                 {
1095                         printk(KERN_WARNING "broken BIOS!!\n");
1096                         trigger = 0;
1097                         break;
1098                 }
1099         }
1100         return trigger;
1101 }
1102
1103 static inline int irq_polarity(int idx)
1104 {
1105         return MPBIOS_polarity(idx);
1106 }
1107
1108 static inline int irq_trigger(int idx)
1109 {
1110         return MPBIOS_trigger(idx);
1111 }
1112
1113 static int pin_2_irq(int idx, int apic, int pin)
1114 {
1115         int irq, i;
1116         int bus = mp_irqs[idx].mpc_srcbus;
1117
1118         /*
1119          * Debugging check, we are in big trouble if this message pops up!
1120          */
1121         if (mp_irqs[idx].mpc_dstirq != pin)
1122                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1123
1124         switch (mp_bus_id_to_type[bus])
1125         {
1126                 case MP_BUS_ISA: /* ISA pin */
1127                 case MP_BUS_EISA:
1128                 case MP_BUS_MCA:
1129                 {
1130                         irq = mp_irqs[idx].mpc_srcbusirq;
1131                         break;
1132                 }
1133                 case MP_BUS_PCI: /* PCI pin */
1134                 {
1135                         /*
1136                          * PCI IRQs are mapped in order
1137                          */
1138                         i = irq = 0;
1139                         while (i < apic)
1140                                 irq += nr_ioapic_registers[i++];
1141                         irq += pin;
1142
1143                         /*
1144                          * For MPS mode, so far only needed by ES7000 platform
1145                          */
1146                         if (ioapic_renumber_irq)
1147                                 irq = ioapic_renumber_irq(apic, irq);
1148
1149                         break;
1150                 }
1151                 default:
1152                 {
1153                         printk(KERN_ERR "unknown bus type %d.\n",bus); 
1154                         irq = 0;
1155                         break;
1156                 }
1157         }
1158
1159         /*
1160          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1161          */
1162         if ((pin >= 16) && (pin <= 23)) {
1163                 if (pirq_entries[pin-16] != -1) {
1164                         if (!pirq_entries[pin-16]) {
1165                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1166                                                 "disabling PIRQ%d\n", pin-16);
1167                         } else {
1168                                 irq = pirq_entries[pin-16];
1169                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1170                                                 "using PIRQ%d -> IRQ %d\n",
1171                                                 pin-16, irq);
1172                         }
1173                 }
1174         }
1175         return irq;
1176 }
1177
1178 static inline int IO_APIC_irq_trigger(int irq)
1179 {
1180         int apic, idx, pin;
1181
1182         for (apic = 0; apic < nr_ioapics; apic++) {
1183                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1184                         idx = find_irq_entry(apic,pin,mp_INT);
1185                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1186                                 return irq_trigger(idx);
1187                 }
1188         }
1189         /*
1190          * nonexistent IRQs are edge default
1191          */
1192         return 0;
1193 }
1194
1195 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1196 static u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1197
1198 static int __assign_irq_vector(int irq)
1199 {
1200         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1201         int vector, offset, i;
1202
1203         BUG_ON((unsigned)irq >= NR_IRQ_VECTORS);
1204
1205         if (irq_vector[irq] > 0)
1206                 return irq_vector[irq];
1207
1208         vector = current_vector;
1209         offset = current_offset;
1210 next:
1211         vector += 8;
1212         if (vector >= FIRST_SYSTEM_VECTOR) {
1213                 offset = (offset + 1) % 8;
1214                 vector = FIRST_DEVICE_VECTOR + offset;
1215         }
1216         if (vector == current_vector)
1217                 return -ENOSPC;
1218         if (vector == SYSCALL_VECTOR)
1219                 goto next;
1220         for (i = 0; i < NR_IRQ_VECTORS; i++)
1221                 if (irq_vector[i] == vector)
1222                         goto next;
1223
1224         current_vector = vector;
1225         current_offset = offset;
1226         irq_vector[irq] = vector;
1227
1228         return vector;
1229 }
1230
1231 static int assign_irq_vector(int irq)
1232 {
1233         unsigned long flags;
1234         int vector;
1235
1236         spin_lock_irqsave(&vector_lock, flags);
1237         vector = __assign_irq_vector(irq);
1238         spin_unlock_irqrestore(&vector_lock, flags);
1239
1240         return vector;
1241 }
1242 static struct irq_chip ioapic_chip;
1243
1244 #define IOAPIC_AUTO     -1
1245 #define IOAPIC_EDGE     0
1246 #define IOAPIC_LEVEL    1
1247
1248 static void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1249 {
1250         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1251             trigger == IOAPIC_LEVEL) {
1252                 irq_desc[irq].status |= IRQ_LEVEL;
1253                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1254                                          handle_fasteoi_irq, "fasteoi");
1255         } else {
1256                 irq_desc[irq].status &= ~IRQ_LEVEL;
1257                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1258                                          handle_edge_irq, "edge");
1259         }
1260         set_intr_gate(vector, interrupt[irq]);
1261 }
1262
1263 static void __init setup_IO_APIC_irqs(void)
1264 {
1265         struct IO_APIC_route_entry entry;
1266         int apic, pin, idx, irq, first_notcon = 1, vector;
1267         unsigned long flags;
1268
1269         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1270
1271         for (apic = 0; apic < nr_ioapics; apic++) {
1272         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1273
1274                 /*
1275                  * add it to the IO-APIC irq-routing table:
1276                  */
1277                 memset(&entry,0,sizeof(entry));
1278
1279                 entry.delivery_mode = INT_DELIVERY_MODE;
1280                 entry.dest_mode = INT_DEST_MODE;
1281                 entry.mask = 0;                         /* enable IRQ */
1282                 entry.dest.logical.logical_dest = 
1283                                         cpu_mask_to_apicid(TARGET_CPUS);
1284
1285                 idx = find_irq_entry(apic,pin,mp_INT);
1286                 if (idx == -1) {
1287                         if (first_notcon) {
1288                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1289                                                 " IO-APIC (apicid-pin) %d-%d",
1290                                                 mp_ioapics[apic].mpc_apicid,
1291                                                 pin);
1292                                 first_notcon = 0;
1293                         } else
1294                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1295                                         mp_ioapics[apic].mpc_apicid, pin);
1296                         continue;
1297                 }
1298
1299                 entry.trigger = irq_trigger(idx);
1300                 entry.polarity = irq_polarity(idx);
1301
1302                 if (irq_trigger(idx)) {
1303                         entry.trigger = 1;
1304                         entry.mask = 1;
1305                 }
1306
1307                 irq = pin_2_irq(idx, apic, pin);
1308                 /*
1309                  * skip adding the timer int on secondary nodes, which causes
1310                  * a small but painful rift in the time-space continuum
1311                  */
1312                 if (multi_timer_check(apic, irq))
1313                         continue;
1314                 else
1315                         add_pin_to_irq(irq, apic, pin);
1316
1317                 if (!apic && !IO_APIC_IRQ(irq))
1318                         continue;
1319
1320                 if (IO_APIC_IRQ(irq)) {
1321                         vector = assign_irq_vector(irq);
1322                         entry.vector = vector;
1323                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1324                 
1325                         if (!apic && (irq < 16))
1326                                 disable_8259A_irq(irq);
1327                 }
1328                 spin_lock_irqsave(&ioapic_lock, flags);
1329                 __ioapic_write_entry(apic, pin, entry);
1330                 spin_unlock_irqrestore(&ioapic_lock, flags);
1331         }
1332         }
1333
1334         if (!first_notcon)
1335                 apic_printk(APIC_VERBOSE, " not connected.\n");
1336 }
1337
1338 /*
1339  * Set up the 8259A-master output pin:
1340  */
1341 static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
1342 {
1343         struct IO_APIC_route_entry entry;
1344
1345         memset(&entry,0,sizeof(entry));
1346
1347         disable_8259A_irq(0);
1348
1349         /* mask LVT0 */
1350         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1351
1352         /*
1353          * We use logical delivery to get the timer IRQ
1354          * to the first CPU.
1355          */
1356         entry.dest_mode = INT_DEST_MODE;
1357         entry.mask = 0;                                 /* unmask IRQ now */
1358         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1359         entry.delivery_mode = INT_DELIVERY_MODE;
1360         entry.polarity = 0;
1361         entry.trigger = 0;
1362         entry.vector = vector;
1363
1364         /*
1365          * The timer IRQ doesn't have to know that behind the
1366          * scene we have a 8259A-master in AEOI mode ...
1367          */
1368         irq_desc[0].chip = &ioapic_chip;
1369         set_irq_handler(0, handle_edge_irq);
1370
1371         /*
1372          * Add it to the IO-APIC irq-routing table:
1373          */
1374         ioapic_write_entry(apic, pin, entry);
1375
1376         enable_8259A_irq(0);
1377 }
1378
1379 void __init print_IO_APIC(void)
1380 {
1381         int apic, i;
1382         union IO_APIC_reg_00 reg_00;
1383         union IO_APIC_reg_01 reg_01;
1384         union IO_APIC_reg_02 reg_02;
1385         union IO_APIC_reg_03 reg_03;
1386         unsigned long flags;
1387
1388         if (apic_verbosity == APIC_QUIET)
1389                 return;
1390
1391         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1392         for (i = 0; i < nr_ioapics; i++)
1393                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1394                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1395
1396         /*
1397          * We are a bit conservative about what we expect.  We have to
1398          * know about every hardware change ASAP.
1399          */
1400         printk(KERN_INFO "testing the IO APIC.......................\n");
1401
1402         for (apic = 0; apic < nr_ioapics; apic++) {
1403
1404         spin_lock_irqsave(&ioapic_lock, flags);
1405         reg_00.raw = io_apic_read(apic, 0);
1406         reg_01.raw = io_apic_read(apic, 1);
1407         if (reg_01.bits.version >= 0x10)
1408                 reg_02.raw = io_apic_read(apic, 2);
1409         if (reg_01.bits.version >= 0x20)
1410                 reg_03.raw = io_apic_read(apic, 3);
1411         spin_unlock_irqrestore(&ioapic_lock, flags);
1412
1413         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1414         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1415         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1416         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1417         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1418
1419         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1420         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1421
1422         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1423         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1424
1425         /*
1426          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1427          * but the value of reg_02 is read as the previous read register
1428          * value, so ignore it if reg_02 == reg_01.
1429          */
1430         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1431                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1432                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1433         }
1434
1435         /*
1436          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1437          * or reg_03, but the value of reg_0[23] is read as the previous read
1438          * register value, so ignore it if reg_03 == reg_0[12].
1439          */
1440         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1441             reg_03.raw != reg_01.raw) {
1442                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1443                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1444         }
1445
1446         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1447
1448         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1449                           " Stat Dest Deli Vect:   \n");
1450
1451         for (i = 0; i <= reg_01.bits.entries; i++) {
1452                 struct IO_APIC_route_entry entry;
1453
1454                 entry = ioapic_read_entry(apic, i);
1455
1456                 printk(KERN_DEBUG " %02x %03X %02X  ",
1457                         i,
1458                         entry.dest.logical.logical_dest,
1459                         entry.dest.physical.physical_dest
1460                 );
1461
1462                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1463                         entry.mask,
1464                         entry.trigger,
1465                         entry.irr,
1466                         entry.polarity,
1467                         entry.delivery_status,
1468                         entry.dest_mode,
1469                         entry.delivery_mode,
1470                         entry.vector
1471                 );
1472         }
1473         }
1474         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1475         for (i = 0; i < NR_IRQS; i++) {
1476                 struct irq_pin_list *entry = irq_2_pin + i;
1477                 if (entry->pin < 0)
1478                         continue;
1479                 printk(KERN_DEBUG "IRQ%d ", i);
1480                 for (;;) {
1481                         printk("-> %d:%d", entry->apic, entry->pin);
1482                         if (!entry->next)
1483                                 break;
1484                         entry = irq_2_pin + entry->next;
1485                 }
1486                 printk("\n");
1487         }
1488
1489         printk(KERN_INFO ".................................... done.\n");
1490
1491         return;
1492 }
1493
1494 #if 0
1495
1496 static void print_APIC_bitfield (int base)
1497 {
1498         unsigned int v;
1499         int i, j;
1500
1501         if (apic_verbosity == APIC_QUIET)
1502                 return;
1503
1504         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1505         for (i = 0; i < 8; i++) {
1506                 v = apic_read(base + i*0x10);
1507                 for (j = 0; j < 32; j++) {
1508                         if (v & (1<<j))
1509                                 printk("1");
1510                         else
1511                                 printk("0");
1512                 }
1513                 printk("\n");
1514         }
1515 }
1516
1517 void /*__init*/ print_local_APIC(void * dummy)
1518 {
1519         unsigned int v, ver, maxlvt;
1520
1521         if (apic_verbosity == APIC_QUIET)
1522                 return;
1523
1524         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1525                 smp_processor_id(), hard_smp_processor_id());
1526         v = apic_read(APIC_ID);
1527         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1528         v = apic_read(APIC_LVR);
1529         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1530         ver = GET_APIC_VERSION(v);
1531         maxlvt = lapic_get_maxlvt();
1532
1533         v = apic_read(APIC_TASKPRI);
1534         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1535
1536         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1537                 v = apic_read(APIC_ARBPRI);
1538                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1539                         v & APIC_ARBPRI_MASK);
1540                 v = apic_read(APIC_PROCPRI);
1541                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1542         }
1543
1544         v = apic_read(APIC_EOI);
1545         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1546         v = apic_read(APIC_RRR);
1547         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1548         v = apic_read(APIC_LDR);
1549         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1550         v = apic_read(APIC_DFR);
1551         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1552         v = apic_read(APIC_SPIV);
1553         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1554
1555         printk(KERN_DEBUG "... APIC ISR field:\n");
1556         print_APIC_bitfield(APIC_ISR);
1557         printk(KERN_DEBUG "... APIC TMR field:\n");
1558         print_APIC_bitfield(APIC_TMR);
1559         printk(KERN_DEBUG "... APIC IRR field:\n");
1560         print_APIC_bitfield(APIC_IRR);
1561
1562         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1563                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1564                         apic_write(APIC_ESR, 0);
1565                 v = apic_read(APIC_ESR);
1566                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1567         }
1568
1569         v = apic_read(APIC_ICR);
1570         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1571         v = apic_read(APIC_ICR2);
1572         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1573
1574         v = apic_read(APIC_LVTT);
1575         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1576
1577         if (maxlvt > 3) {                       /* PC is LVT#4. */
1578                 v = apic_read(APIC_LVTPC);
1579                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1580         }
1581         v = apic_read(APIC_LVT0);
1582         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1583         v = apic_read(APIC_LVT1);
1584         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1585
1586         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1587                 v = apic_read(APIC_LVTERR);
1588                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1589         }
1590
1591         v = apic_read(APIC_TMICT);
1592         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1593         v = apic_read(APIC_TMCCT);
1594         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1595         v = apic_read(APIC_TDCR);
1596         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1597         printk("\n");
1598 }
1599
1600 void print_all_local_APICs (void)
1601 {
1602         on_each_cpu(print_local_APIC, NULL, 1, 1);
1603 }
1604
1605 void /*__init*/ print_PIC(void)
1606 {
1607         unsigned int v;
1608         unsigned long flags;
1609
1610         if (apic_verbosity == APIC_QUIET)
1611                 return;
1612
1613         printk(KERN_DEBUG "\nprinting PIC contents\n");
1614
1615         spin_lock_irqsave(&i8259A_lock, flags);
1616
1617         v = inb(0xa1) << 8 | inb(0x21);
1618         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1619
1620         v = inb(0xa0) << 8 | inb(0x20);
1621         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1622
1623         outb(0x0b,0xa0);
1624         outb(0x0b,0x20);
1625         v = inb(0xa0) << 8 | inb(0x20);
1626         outb(0x0a,0xa0);
1627         outb(0x0a,0x20);
1628
1629         spin_unlock_irqrestore(&i8259A_lock, flags);
1630
1631         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1632
1633         v = inb(0x4d1) << 8 | inb(0x4d0);
1634         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1635 }
1636
1637 #endif  /*  0  */
1638
1639 static void __init enable_IO_APIC(void)
1640 {
1641         union IO_APIC_reg_01 reg_01;
1642         int i8259_apic, i8259_pin;
1643         int i, apic;
1644         unsigned long flags;
1645
1646         for (i = 0; i < PIN_MAP_SIZE; i++) {
1647                 irq_2_pin[i].pin = -1;
1648                 irq_2_pin[i].next = 0;
1649         }
1650         if (!pirqs_enabled)
1651                 for (i = 0; i < MAX_PIRQS; i++)
1652                         pirq_entries[i] = -1;
1653
1654         /*
1655          * The number of IO-APIC IRQ registers (== #pins):
1656          */
1657         for (apic = 0; apic < nr_ioapics; apic++) {
1658                 spin_lock_irqsave(&ioapic_lock, flags);
1659                 reg_01.raw = io_apic_read(apic, 1);
1660                 spin_unlock_irqrestore(&ioapic_lock, flags);
1661                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1662         }
1663         for(apic = 0; apic < nr_ioapics; apic++) {
1664                 int pin;
1665                 /* See if any of the pins is in ExtINT mode */
1666                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1667                         struct IO_APIC_route_entry entry;
1668                         entry = ioapic_read_entry(apic, pin);
1669
1670
1671                         /* If the interrupt line is enabled and in ExtInt mode
1672                          * I have found the pin where the i8259 is connected.
1673                          */
1674                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1675                                 ioapic_i8259.apic = apic;
1676                                 ioapic_i8259.pin  = pin;
1677                                 goto found_i8259;
1678                         }
1679                 }
1680         }
1681  found_i8259:
1682         /* Look to see what if the MP table has reported the ExtINT */
1683         /* If we could not find the appropriate pin by looking at the ioapic
1684          * the i8259 probably is not connected the ioapic but give the
1685          * mptable a chance anyway.
1686          */
1687         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1688         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1689         /* Trust the MP table if nothing is setup in the hardware */
1690         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1691                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1692                 ioapic_i8259.pin  = i8259_pin;
1693                 ioapic_i8259.apic = i8259_apic;
1694         }
1695         /* Complain if the MP table and the hardware disagree */
1696         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1697                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1698         {
1699                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1700         }
1701
1702         /*
1703          * Do not trust the IO-APIC being empty at bootup
1704          */
1705         clear_IO_APIC();
1706 }
1707
1708 /*
1709  * Not an __init, needed by the reboot code
1710  */
1711 void disable_IO_APIC(void)
1712 {
1713         /*
1714          * Clear the IO-APIC before rebooting:
1715          */
1716         clear_IO_APIC();
1717
1718         /*
1719          * If the i8259 is routed through an IOAPIC
1720          * Put that IOAPIC in virtual wire mode
1721          * so legacy interrupts can be delivered.
1722          */
1723         if (ioapic_i8259.pin != -1) {
1724                 struct IO_APIC_route_entry entry;
1725
1726                 memset(&entry, 0, sizeof(entry));
1727                 entry.mask            = 0; /* Enabled */
1728                 entry.trigger         = 0; /* Edge */
1729                 entry.irr             = 0;
1730                 entry.polarity        = 0; /* High */
1731                 entry.delivery_status = 0;
1732                 entry.dest_mode       = 0; /* Physical */
1733                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1734                 entry.vector          = 0;
1735                 entry.dest.physical.physical_dest =
1736                                         GET_APIC_ID(apic_read(APIC_ID));
1737
1738                 /*
1739                  * Add it to the IO-APIC irq-routing table:
1740                  */
1741                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1742         }
1743         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1744 }
1745
1746 /*
1747  * function to set the IO-APIC physical IDs based on the
1748  * values stored in the MPC table.
1749  *
1750  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1751  */
1752
1753 #ifndef CONFIG_X86_NUMAQ
1754 static void __init setup_ioapic_ids_from_mpc(void)
1755 {
1756         union IO_APIC_reg_00 reg_00;
1757         physid_mask_t phys_id_present_map;
1758         int apic;
1759         int i;
1760         unsigned char old_id;
1761         unsigned long flags;
1762
1763         /*
1764          * Don't check I/O APIC IDs for xAPIC systems.  They have
1765          * no meaning without the serial APIC bus.
1766          */
1767         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1768                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1769                 return;
1770         /*
1771          * This is broken; anything with a real cpu count has to
1772          * circumvent this idiocy regardless.
1773          */
1774         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1775
1776         /*
1777          * Set the IOAPIC ID to the value stored in the MPC table.
1778          */
1779         for (apic = 0; apic < nr_ioapics; apic++) {
1780
1781                 /* Read the register 0 value */
1782                 spin_lock_irqsave(&ioapic_lock, flags);
1783                 reg_00.raw = io_apic_read(apic, 0);
1784                 spin_unlock_irqrestore(&ioapic_lock, flags);
1785                 
1786                 old_id = mp_ioapics[apic].mpc_apicid;
1787
1788                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1789                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1790                                 apic, mp_ioapics[apic].mpc_apicid);
1791                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1792                                 reg_00.bits.ID);
1793                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1794                 }
1795
1796                 /*
1797                  * Sanity check, is the ID really free? Every APIC in a
1798                  * system must have a unique ID or we get lots of nice
1799                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1800                  */
1801                 if (check_apicid_used(phys_id_present_map,
1802                                         mp_ioapics[apic].mpc_apicid)) {
1803                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1804                                 apic, mp_ioapics[apic].mpc_apicid);
1805                         for (i = 0; i < get_physical_broadcast(); i++)
1806                                 if (!physid_isset(i, phys_id_present_map))
1807                                         break;
1808                         if (i >= get_physical_broadcast())
1809                                 panic("Max APIC ID exceeded!\n");
1810                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1811                                 i);
1812                         physid_set(i, phys_id_present_map);
1813                         mp_ioapics[apic].mpc_apicid = i;
1814                 } else {
1815                         physid_mask_t tmp;
1816                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1817                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1818                                         "phys_id_present_map\n",
1819                                         mp_ioapics[apic].mpc_apicid);
1820                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1821                 }
1822
1823
1824                 /*
1825                  * We need to adjust the IRQ routing table
1826                  * if the ID changed.
1827                  */
1828                 if (old_id != mp_ioapics[apic].mpc_apicid)
1829                         for (i = 0; i < mp_irq_entries; i++)
1830                                 if (mp_irqs[i].mpc_dstapic == old_id)
1831                                         mp_irqs[i].mpc_dstapic
1832                                                 = mp_ioapics[apic].mpc_apicid;
1833
1834                 /*
1835                  * Read the right value from the MPC table and
1836                  * write it into the ID register.
1837                  */
1838                 apic_printk(APIC_VERBOSE, KERN_INFO
1839                         "...changing IO-APIC physical APIC ID to %d ...",
1840                         mp_ioapics[apic].mpc_apicid);
1841
1842                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1843                 spin_lock_irqsave(&ioapic_lock, flags);
1844                 io_apic_write(apic, 0, reg_00.raw);
1845                 spin_unlock_irqrestore(&ioapic_lock, flags);
1846
1847                 /*
1848                  * Sanity check
1849                  */
1850                 spin_lock_irqsave(&ioapic_lock, flags);
1851                 reg_00.raw = io_apic_read(apic, 0);
1852                 spin_unlock_irqrestore(&ioapic_lock, flags);
1853                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1854                         printk("could not set ID!\n");
1855                 else
1856                         apic_printk(APIC_VERBOSE, " ok.\n");
1857         }
1858 }
1859 #else
1860 static void __init setup_ioapic_ids_from_mpc(void) { }
1861 #endif
1862
1863 int no_timer_check __initdata;
1864
1865 static int __init notimercheck(char *s)
1866 {
1867         no_timer_check = 1;
1868         return 1;
1869 }
1870 __setup("no_timer_check", notimercheck);
1871
1872 /*
1873  * There is a nasty bug in some older SMP boards, their mptable lies
1874  * about the timer IRQ. We do the following to work around the situation:
1875  *
1876  *      - timer IRQ defaults to IO-APIC IRQ
1877  *      - if this function detects that timer IRQs are defunct, then we fall
1878  *        back to ISA timer IRQs
1879  */
1880 static int __init timer_irq_works(void)
1881 {
1882         unsigned long t1 = jiffies;
1883
1884         if (no_timer_check)
1885                 return 1;
1886
1887         local_irq_enable();
1888         /* Let ten ticks pass... */
1889         mdelay((10 * 1000) / HZ);
1890
1891         /*
1892          * Expect a few ticks at least, to be sure some possible
1893          * glue logic does not lock up after one or two first
1894          * ticks in a non-ExtINT mode.  Also the local APIC
1895          * might have cached one ExtINT interrupt.  Finally, at
1896          * least one tick may be lost due to delays.
1897          */
1898         if (jiffies - t1 > 4)
1899                 return 1;
1900
1901         return 0;
1902 }
1903
1904 /*
1905  * In the SMP+IOAPIC case it might happen that there are an unspecified
1906  * number of pending IRQ events unhandled. These cases are very rare,
1907  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1908  * better to do it this way as thus we do not have to be aware of
1909  * 'pending' interrupts in the IRQ path, except at this point.
1910  */
1911 /*
1912  * Edge triggered needs to resend any interrupt
1913  * that was delayed but this is now handled in the device
1914  * independent code.
1915  */
1916
1917 /*
1918  * Startup quirk:
1919  *
1920  * Starting up a edge-triggered IO-APIC interrupt is
1921  * nasty - we need to make sure that we get the edge.
1922  * If it is already asserted for some reason, we need
1923  * return 1 to indicate that is was pending.
1924  *
1925  * This is not complete - we should be able to fake
1926  * an edge even if it isn't on the 8259A...
1927  *
1928  * (We do this for level-triggered IRQs too - it cannot hurt.)
1929  */
1930 static unsigned int startup_ioapic_irq(unsigned int irq)
1931 {
1932         int was_pending = 0;
1933         unsigned long flags;
1934
1935         spin_lock_irqsave(&ioapic_lock, flags);
1936         if (irq < 16) {
1937                 disable_8259A_irq(irq);
1938                 if (i8259A_irq_pending(irq))
1939                         was_pending = 1;
1940         }
1941         __unmask_IO_APIC_irq(irq);
1942         spin_unlock_irqrestore(&ioapic_lock, flags);
1943
1944         return was_pending;
1945 }
1946
1947 static void ack_ioapic_irq(unsigned int irq)
1948 {
1949         move_native_irq(irq);
1950         ack_APIC_irq();
1951 }
1952
1953 static void ack_ioapic_quirk_irq(unsigned int irq)
1954 {
1955         unsigned long v;
1956         int i;
1957
1958         move_native_irq(irq);
1959 /*
1960  * It appears there is an erratum which affects at least version 0x11
1961  * of I/O APIC (that's the 82093AA and cores integrated into various
1962  * chipsets).  Under certain conditions a level-triggered interrupt is
1963  * erroneously delivered as edge-triggered one but the respective IRR
1964  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1965  * message but it will never arrive and further interrupts are blocked
1966  * from the source.  The exact reason is so far unknown, but the
1967  * phenomenon was observed when two consecutive interrupt requests
1968  * from a given source get delivered to the same CPU and the source is
1969  * temporarily disabled in between.
1970  *
1971  * A workaround is to simulate an EOI message manually.  We achieve it
1972  * by setting the trigger mode to edge and then to level when the edge
1973  * trigger mode gets detected in the TMR of a local APIC for a
1974  * level-triggered interrupt.  We mask the source for the time of the
1975  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1976  * The idea is from Manfred Spraul.  --macro
1977  */
1978         i = irq_vector[irq];
1979
1980         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1981
1982         ack_APIC_irq();
1983
1984         if (!(v & (1 << (i & 0x1f)))) {
1985                 atomic_inc(&irq_mis_count);
1986                 spin_lock(&ioapic_lock);
1987                 __mask_and_edge_IO_APIC_irq(irq);
1988                 __unmask_and_level_IO_APIC_irq(irq);
1989                 spin_unlock(&ioapic_lock);
1990         }
1991 }
1992
1993 static int ioapic_retrigger_irq(unsigned int irq)
1994 {
1995         send_IPI_self(irq_vector[irq]);
1996
1997         return 1;
1998 }
1999
2000 static struct irq_chip ioapic_chip __read_mostly = {
2001         .name           = "IO-APIC",
2002         .startup        = startup_ioapic_irq,
2003         .mask           = mask_IO_APIC_irq,
2004         .unmask         = unmask_IO_APIC_irq,
2005         .ack            = ack_ioapic_irq,
2006         .eoi            = ack_ioapic_quirk_irq,
2007 #ifdef CONFIG_SMP
2008         .set_affinity   = set_ioapic_affinity_irq,
2009 #endif
2010         .retrigger      = ioapic_retrigger_irq,
2011 };
2012
2013
2014 static inline void init_IO_APIC_traps(void)
2015 {
2016         int irq;
2017
2018         /*
2019          * NOTE! The local APIC isn't very good at handling
2020          * multiple interrupts at the same interrupt level.
2021          * As the interrupt level is determined by taking the
2022          * vector number and shifting that right by 4, we
2023          * want to spread these out a bit so that they don't
2024          * all fall in the same interrupt level.
2025          *
2026          * Also, we've got to be careful not to trash gate
2027          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2028          */
2029         for (irq = 0; irq < NR_IRQS ; irq++) {
2030                 int tmp = irq;
2031                 if (IO_APIC_IRQ(tmp) && !irq_vector[tmp]) {
2032                         /*
2033                          * Hmm.. We don't have an entry for this,
2034                          * so default to an old-fashioned 8259
2035                          * interrupt if we can..
2036                          */
2037                         if (irq < 16)
2038                                 make_8259A_irq(irq);
2039                         else
2040                                 /* Strange. Oh, well.. */
2041                                 irq_desc[irq].chip = &no_irq_chip;
2042                 }
2043         }
2044 }
2045
2046 /*
2047  * The local APIC irq-chip implementation:
2048  */
2049
2050 static void ack_apic(unsigned int irq)
2051 {
2052         ack_APIC_irq();
2053 }
2054
2055 static void mask_lapic_irq (unsigned int irq)
2056 {
2057         unsigned long v;
2058
2059         v = apic_read(APIC_LVT0);
2060         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2061 }
2062
2063 static void unmask_lapic_irq (unsigned int irq)
2064 {
2065         unsigned long v;
2066
2067         v = apic_read(APIC_LVT0);
2068         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2069 }
2070
2071 static struct irq_chip lapic_chip __read_mostly = {
2072         .name           = "local-APIC-edge",
2073         .mask           = mask_lapic_irq,
2074         .unmask         = unmask_lapic_irq,
2075         .eoi            = ack_apic,
2076 };
2077
2078 static void setup_nmi (void)
2079 {
2080         /*
2081          * Dirty trick to enable the NMI watchdog ...
2082          * We put the 8259A master into AEOI mode and
2083          * unmask on all local APICs LVT0 as NMI.
2084          *
2085          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2086          * is from Maciej W. Rozycki - so we do not have to EOI from
2087          * the NMI handler or the timer interrupt.
2088          */ 
2089         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2090
2091         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2092
2093         apic_printk(APIC_VERBOSE, " done.\n");
2094 }
2095
2096 /*
2097  * This looks a bit hackish but it's about the only one way of sending
2098  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2099  * not support the ExtINT mode, unfortunately.  We need to send these
2100  * cycles as some i82489DX-based boards have glue logic that keeps the
2101  * 8259A interrupt line asserted until INTA.  --macro
2102  */
2103 static inline void unlock_ExtINT_logic(void)
2104 {
2105         int apic, pin, i;
2106         struct IO_APIC_route_entry entry0, entry1;
2107         unsigned char save_control, save_freq_select;
2108
2109         pin  = find_isa_irq_pin(8, mp_INT);
2110         if (pin == -1) {
2111                 WARN_ON_ONCE(1);
2112                 return;
2113         }
2114         apic = find_isa_irq_apic(8, mp_INT);
2115         if (apic == -1) {
2116                 WARN_ON_ONCE(1);
2117                 return;
2118         }
2119
2120         entry0 = ioapic_read_entry(apic, pin);
2121         clear_IO_APIC_pin(apic, pin);
2122
2123         memset(&entry1, 0, sizeof(entry1));
2124
2125         entry1.dest_mode = 0;                   /* physical delivery */
2126         entry1.mask = 0;                        /* unmask IRQ now */
2127         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2128         entry1.delivery_mode = dest_ExtINT;
2129         entry1.polarity = entry0.polarity;
2130         entry1.trigger = 0;
2131         entry1.vector = 0;
2132
2133         ioapic_write_entry(apic, pin, entry1);
2134
2135         save_control = CMOS_READ(RTC_CONTROL);
2136         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2137         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2138                    RTC_FREQ_SELECT);
2139         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2140
2141         i = 100;
2142         while (i-- > 0) {
2143                 mdelay(10);
2144                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2145                         i -= 10;
2146         }
2147
2148         CMOS_WRITE(save_control, RTC_CONTROL);
2149         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2150         clear_IO_APIC_pin(apic, pin);
2151
2152         ioapic_write_entry(apic, pin, entry0);
2153 }
2154
2155 int timer_uses_ioapic_pin_0;
2156
2157 /*
2158  * This code may look a bit paranoid, but it's supposed to cooperate with
2159  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2160  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2161  * fanatically on his truly buggy board.
2162  */
2163 static inline void __init check_timer(void)
2164 {
2165         int apic1, pin1, apic2, pin2;
2166         int vector;
2167
2168         /*
2169          * get/set the timer IRQ vector:
2170          */
2171         disable_8259A_irq(0);
2172         vector = assign_irq_vector(0);
2173         set_intr_gate(vector, interrupt[0]);
2174
2175         /*
2176          * Subtle, code in do_timer_interrupt() expects an AEOI
2177          * mode for the 8259A whenever interrupts are routed
2178          * through I/O APICs.  Also IRQ0 has to be enabled in
2179          * the 8259A which implies the virtual wire has to be
2180          * disabled in the local APIC.
2181          */
2182         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2183         init_8259A(1);
2184         timer_ack = 1;
2185         if (timer_over_8254 > 0)
2186                 enable_8259A_irq(0);
2187
2188         pin1  = find_isa_irq_pin(0, mp_INT);
2189         apic1 = find_isa_irq_apic(0, mp_INT);
2190         pin2  = ioapic_i8259.pin;
2191         apic2 = ioapic_i8259.apic;
2192
2193         if (pin1 == 0)
2194                 timer_uses_ioapic_pin_0 = 1;
2195
2196         printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2197                 vector, apic1, pin1, apic2, pin2);
2198
2199         if (pin1 != -1) {
2200                 /*
2201                  * Ok, does IRQ0 through the IOAPIC work?
2202                  */
2203                 unmask_IO_APIC_irq(0);
2204                 if (timer_irq_works()) {
2205                         if (nmi_watchdog == NMI_IO_APIC) {
2206                                 disable_8259A_irq(0);
2207                                 setup_nmi();
2208                                 enable_8259A_irq(0);
2209                         }
2210                         if (disable_timer_pin_1 > 0)
2211                                 clear_IO_APIC_pin(0, pin1);
2212                         return;
2213                 }
2214                 clear_IO_APIC_pin(apic1, pin1);
2215                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
2216                                 "IO-APIC\n");
2217         }
2218
2219         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2220         if (pin2 != -1) {
2221                 printk("\n..... (found pin %d) ...", pin2);
2222                 /*
2223                  * legacy devices should be connected to IO APIC #0
2224                  */
2225                 setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
2226                 if (timer_irq_works()) {
2227                         printk("works.\n");
2228                         if (pin1 != -1)
2229                                 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
2230                         else
2231                                 add_pin_to_irq(0, apic2, pin2);
2232                         if (nmi_watchdog == NMI_IO_APIC) {
2233                                 setup_nmi();
2234                         }
2235                         return;
2236                 }
2237                 /*
2238                  * Cleanup, just in case ...
2239                  */
2240                 clear_IO_APIC_pin(apic2, pin2);
2241         }
2242         printk(" failed.\n");
2243
2244         if (nmi_watchdog == NMI_IO_APIC) {
2245                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2246                 nmi_watchdog = 0;
2247         }
2248
2249         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2250
2251         disable_8259A_irq(0);
2252         set_irq_chip_and_handler_name(0, &lapic_chip, handle_fasteoi_irq,
2253                                       "fasteoi");
2254         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2255         enable_8259A_irq(0);
2256
2257         if (timer_irq_works()) {
2258                 printk(" works.\n");
2259                 return;
2260         }
2261         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2262         printk(" failed.\n");
2263
2264         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2265
2266         timer_ack = 0;
2267         init_8259A(0);
2268         make_8259A_irq(0);
2269         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2270
2271         unlock_ExtINT_logic();
2272
2273         if (timer_irq_works()) {
2274                 printk(" works.\n");
2275                 return;
2276         }
2277         printk(" failed :(.\n");
2278         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2279                 "report.  Then try booting with the 'noapic' option");
2280 }
2281
2282 /*
2283  *
2284  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2285  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2286  *   Linux doesn't really care, as it's not actually used
2287  *   for any interrupt handling anyway.
2288  */
2289 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2290
2291 void __init setup_IO_APIC(void)
2292 {
2293         enable_IO_APIC();
2294
2295         if (acpi_ioapic)
2296                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2297         else
2298                 io_apic_irqs = ~PIC_IRQS;
2299
2300         printk("ENABLING IO-APIC IRQs\n");
2301
2302         /*
2303          * Set up IO-APIC IRQ routing.
2304          */
2305         if (!acpi_ioapic)
2306                 setup_ioapic_ids_from_mpc();
2307         sync_Arb_IDs();
2308         setup_IO_APIC_irqs();
2309         init_IO_APIC_traps();
2310         check_timer();
2311         if (!acpi_ioapic)
2312                 print_IO_APIC();
2313 }
2314
2315 static int __init setup_disable_8254_timer(char *s)
2316 {
2317         timer_over_8254 = -1;
2318         return 1;
2319 }
2320 static int __init setup_enable_8254_timer(char *s)
2321 {
2322         timer_over_8254 = 2;
2323         return 1;
2324 }
2325
2326 __setup("disable_8254_timer", setup_disable_8254_timer);
2327 __setup("enable_8254_timer", setup_enable_8254_timer);
2328
2329 /*
2330  *      Called after all the initialization is done. If we didnt find any
2331  *      APIC bugs then we can allow the modify fast path
2332  */
2333  
2334 static int __init io_apic_bug_finalize(void)
2335 {
2336         if(sis_apic_bug == -1)
2337                 sis_apic_bug = 0;
2338         return 0;
2339 }
2340
2341 late_initcall(io_apic_bug_finalize);
2342
2343 struct sysfs_ioapic_data {
2344         struct sys_device dev;
2345         struct IO_APIC_route_entry entry[0];
2346 };
2347 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2348
2349 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2350 {
2351         struct IO_APIC_route_entry *entry;
2352         struct sysfs_ioapic_data *data;
2353         int i;
2354         
2355         data = container_of(dev, struct sysfs_ioapic_data, dev);
2356         entry = data->entry;
2357         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2358                 entry[i] = ioapic_read_entry(dev->id, i);
2359
2360         return 0;
2361 }
2362
2363 static int ioapic_resume(struct sys_device *dev)
2364 {
2365         struct IO_APIC_route_entry *entry;
2366         struct sysfs_ioapic_data *data;
2367         unsigned long flags;
2368         union IO_APIC_reg_00 reg_00;
2369         int i;
2370         
2371         data = container_of(dev, struct sysfs_ioapic_data, dev);
2372         entry = data->entry;
2373
2374         spin_lock_irqsave(&ioapic_lock, flags);
2375         reg_00.raw = io_apic_read(dev->id, 0);
2376         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2377                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2378                 io_apic_write(dev->id, 0, reg_00.raw);
2379         }
2380         spin_unlock_irqrestore(&ioapic_lock, flags);
2381         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++)
2382                 ioapic_write_entry(dev->id, i, entry[i]);
2383
2384         return 0;
2385 }
2386
2387 static struct sysdev_class ioapic_sysdev_class = {
2388         set_kset_name("ioapic"),
2389         .suspend = ioapic_suspend,
2390         .resume = ioapic_resume,
2391 };
2392
2393 static int __init ioapic_init_sysfs(void)
2394 {
2395         struct sys_device * dev;
2396         int i, size, error = 0;
2397
2398         error = sysdev_class_register(&ioapic_sysdev_class);
2399         if (error)
2400                 return error;
2401
2402         for (i = 0; i < nr_ioapics; i++ ) {
2403                 size = sizeof(struct sys_device) + nr_ioapic_registers[i] 
2404                         * sizeof(struct IO_APIC_route_entry);
2405                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2406                 if (!mp_ioapic_data[i]) {
2407                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2408                         continue;
2409                 }
2410                 memset(mp_ioapic_data[i], 0, size);
2411                 dev = &mp_ioapic_data[i]->dev;
2412                 dev->id = i; 
2413                 dev->cls = &ioapic_sysdev_class;
2414                 error = sysdev_register(dev);
2415                 if (error) {
2416                         kfree(mp_ioapic_data[i]);
2417                         mp_ioapic_data[i] = NULL;
2418                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2419                         continue;
2420                 }
2421         }
2422
2423         return 0;
2424 }
2425
2426 device_initcall(ioapic_init_sysfs);
2427
2428 /*
2429  * Dynamic irq allocate and deallocation
2430  */
2431 int create_irq(void)
2432 {
2433         /* Allocate an unused irq */
2434         int irq, new, vector = 0;
2435         unsigned long flags;
2436
2437         irq = -ENOSPC;
2438         spin_lock_irqsave(&vector_lock, flags);
2439         for (new = (NR_IRQS - 1); new >= 0; new--) {
2440                 if (platform_legacy_irq(new))
2441                         continue;
2442                 if (irq_vector[new] != 0)
2443                         continue;
2444                 vector = __assign_irq_vector(new);
2445                 if (likely(vector > 0))
2446                         irq = new;
2447                 break;
2448         }
2449         spin_unlock_irqrestore(&vector_lock, flags);
2450
2451         if (irq >= 0) {
2452                 set_intr_gate(vector, interrupt[irq]);
2453                 dynamic_irq_init(irq);
2454         }
2455         return irq;
2456 }
2457
2458 void destroy_irq(unsigned int irq)
2459 {
2460         unsigned long flags;
2461
2462         dynamic_irq_cleanup(irq);
2463
2464         spin_lock_irqsave(&vector_lock, flags);
2465         irq_vector[irq] = 0;
2466         spin_unlock_irqrestore(&vector_lock, flags);
2467 }
2468
2469 /*
2470  * MSI mesage composition
2471  */
2472 #ifdef CONFIG_PCI_MSI
2473 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
2474 {
2475         int vector;
2476         unsigned dest;
2477
2478         vector = assign_irq_vector(irq);
2479         if (vector >= 0) {
2480                 dest = cpu_mask_to_apicid(TARGET_CPUS);
2481
2482                 msg->address_hi = MSI_ADDR_BASE_HI;
2483                 msg->address_lo =
2484                         MSI_ADDR_BASE_LO |
2485                         ((INT_DEST_MODE == 0) ?
2486                                 MSI_ADDR_DEST_MODE_PHYSICAL:
2487                                 MSI_ADDR_DEST_MODE_LOGICAL) |
2488                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2489                                 MSI_ADDR_REDIRECTION_CPU:
2490                                 MSI_ADDR_REDIRECTION_LOWPRI) |
2491                         MSI_ADDR_DEST_ID(dest);
2492
2493                 msg->data =
2494                         MSI_DATA_TRIGGER_EDGE |
2495                         MSI_DATA_LEVEL_ASSERT |
2496                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2497                                 MSI_DATA_DELIVERY_FIXED:
2498                                 MSI_DATA_DELIVERY_LOWPRI) |
2499                         MSI_DATA_VECTOR(vector);
2500         }
2501         return vector;
2502 }
2503
2504 #ifdef CONFIG_SMP
2505 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2506 {
2507         struct msi_msg msg;
2508         unsigned int dest;
2509         cpumask_t tmp;
2510         int vector;
2511
2512         cpus_and(tmp, mask, cpu_online_map);
2513         if (cpus_empty(tmp))
2514                 tmp = TARGET_CPUS;
2515
2516         vector = assign_irq_vector(irq);
2517         if (vector < 0)
2518                 return;
2519
2520         dest = cpu_mask_to_apicid(mask);
2521
2522         read_msi_msg(irq, &msg);
2523
2524         msg.data &= ~MSI_DATA_VECTOR_MASK;
2525         msg.data |= MSI_DATA_VECTOR(vector);
2526         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2527         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2528
2529         write_msi_msg(irq, &msg);
2530         irq_desc[irq].affinity = mask;
2531 }
2532 #endif /* CONFIG_SMP */
2533
2534 /*
2535  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2536  * which implement the MSI or MSI-X Capability Structure.
2537  */
2538 static struct irq_chip msi_chip = {
2539         .name           = "PCI-MSI",
2540         .unmask         = unmask_msi_irq,
2541         .mask           = mask_msi_irq,
2542         .ack            = ack_ioapic_irq,
2543 #ifdef CONFIG_SMP
2544         .set_affinity   = set_msi_irq_affinity,
2545 #endif
2546         .retrigger      = ioapic_retrigger_irq,
2547 };
2548
2549 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2550 {
2551         struct msi_msg msg;
2552         int irq, ret;
2553         irq = create_irq();
2554         if (irq < 0)
2555                 return irq;
2556
2557         ret = msi_compose_msg(dev, irq, &msg);
2558         if (ret < 0) {
2559                 destroy_irq(irq);
2560                 return ret;
2561         }
2562
2563         set_irq_msi(irq, desc);
2564         write_msi_msg(irq, &msg);
2565
2566         set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq,
2567                                       "edge");
2568
2569         return 0;
2570 }
2571
2572 void arch_teardown_msi_irq(unsigned int irq)
2573 {
2574         destroy_irq(irq);
2575 }
2576
2577 #endif /* CONFIG_PCI_MSI */
2578
2579 /*
2580  * Hypertransport interrupt support
2581  */
2582 #ifdef CONFIG_HT_IRQ
2583
2584 #ifdef CONFIG_SMP
2585
2586 static void target_ht_irq(unsigned int irq, unsigned int dest)
2587 {
2588         struct ht_irq_msg msg;
2589         fetch_ht_irq_msg(irq, &msg);
2590
2591         msg.address_lo &= ~(HT_IRQ_LOW_DEST_ID_MASK);
2592         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2593
2594         msg.address_lo |= HT_IRQ_LOW_DEST_ID(dest);
2595         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2596
2597         write_ht_irq_msg(irq, &msg);
2598 }
2599
2600 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2601 {
2602         unsigned int dest;
2603         cpumask_t tmp;
2604
2605         cpus_and(tmp, mask, cpu_online_map);
2606         if (cpus_empty(tmp))
2607                 tmp = TARGET_CPUS;
2608
2609         cpus_and(mask, tmp, CPU_MASK_ALL);
2610
2611         dest = cpu_mask_to_apicid(mask);
2612
2613         target_ht_irq(irq, dest);
2614         irq_desc[irq].affinity = mask;
2615 }
2616 #endif
2617
2618 static struct irq_chip ht_irq_chip = {
2619         .name           = "PCI-HT",
2620         .mask           = mask_ht_irq,
2621         .unmask         = unmask_ht_irq,
2622         .ack            = ack_ioapic_irq,
2623 #ifdef CONFIG_SMP
2624         .set_affinity   = set_ht_irq_affinity,
2625 #endif
2626         .retrigger      = ioapic_retrigger_irq,
2627 };
2628
2629 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2630 {
2631         int vector;
2632
2633         vector = assign_irq_vector(irq);
2634         if (vector >= 0) {
2635                 struct ht_irq_msg msg;
2636                 unsigned dest;
2637                 cpumask_t tmp;
2638
2639                 cpus_clear(tmp);
2640                 cpu_set(vector >> 8, tmp);
2641                 dest = cpu_mask_to_apicid(tmp);
2642
2643                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2644
2645                 msg.address_lo =
2646                         HT_IRQ_LOW_BASE |
2647                         HT_IRQ_LOW_DEST_ID(dest) |
2648                         HT_IRQ_LOW_VECTOR(vector) |
2649                         ((INT_DEST_MODE == 0) ?
2650                                 HT_IRQ_LOW_DM_PHYSICAL :
2651                                 HT_IRQ_LOW_DM_LOGICAL) |
2652                         HT_IRQ_LOW_RQEOI_EDGE |
2653                         ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2654                                 HT_IRQ_LOW_MT_FIXED :
2655                                 HT_IRQ_LOW_MT_ARBITRATED) |
2656                         HT_IRQ_LOW_IRQ_MASKED;
2657
2658                 write_ht_irq_msg(irq, &msg);
2659
2660                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2661                                               handle_edge_irq, "edge");
2662         }
2663         return vector;
2664 }
2665 #endif /* CONFIG_HT_IRQ */
2666
2667 /* --------------------------------------------------------------------------
2668                           ACPI-based IOAPIC Configuration
2669    -------------------------------------------------------------------------- */
2670
2671 #ifdef CONFIG_ACPI
2672
2673 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2674 {
2675         union IO_APIC_reg_00 reg_00;
2676         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2677         physid_mask_t tmp;
2678         unsigned long flags;
2679         int i = 0;
2680
2681         /*
2682          * The P4 platform supports up to 256 APIC IDs on two separate APIC 
2683          * buses (one for LAPICs, one for IOAPICs), where predecessors only 
2684          * supports up to 16 on one shared APIC bus.
2685          * 
2686          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2687          *      advantage of new APIC bus architecture.
2688          */
2689
2690         if (physids_empty(apic_id_map))
2691                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2692
2693         spin_lock_irqsave(&ioapic_lock, flags);
2694         reg_00.raw = io_apic_read(ioapic, 0);
2695         spin_unlock_irqrestore(&ioapic_lock, flags);
2696
2697         if (apic_id >= get_physical_broadcast()) {
2698                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2699                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2700                 apic_id = reg_00.bits.ID;
2701         }
2702
2703         /*
2704          * Every APIC in a system must have a unique ID or we get lots of nice 
2705          * 'stuck on smp_invalidate_needed IPI wait' messages.
2706          */
2707         if (check_apicid_used(apic_id_map, apic_id)) {
2708
2709                 for (i = 0; i < get_physical_broadcast(); i++) {
2710                         if (!check_apicid_used(apic_id_map, i))
2711                                 break;
2712                 }
2713
2714                 if (i == get_physical_broadcast())
2715                         panic("Max apic_id exceeded!\n");
2716
2717                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2718                         "trying %d\n", ioapic, apic_id, i);
2719
2720                 apic_id = i;
2721         } 
2722
2723         tmp = apicid_to_cpu_present(apic_id);
2724         physids_or(apic_id_map, apic_id_map, tmp);
2725
2726         if (reg_00.bits.ID != apic_id) {
2727                 reg_00.bits.ID = apic_id;
2728
2729                 spin_lock_irqsave(&ioapic_lock, flags);
2730                 io_apic_write(ioapic, 0, reg_00.raw);
2731                 reg_00.raw = io_apic_read(ioapic, 0);
2732                 spin_unlock_irqrestore(&ioapic_lock, flags);
2733
2734                 /* Sanity check */
2735                 if (reg_00.bits.ID != apic_id) {
2736                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
2737                         return -1;
2738                 }
2739         }
2740
2741         apic_printk(APIC_VERBOSE, KERN_INFO
2742                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2743
2744         return apic_id;
2745 }
2746
2747
2748 int __init io_apic_get_version (int ioapic)
2749 {
2750         union IO_APIC_reg_01    reg_01;
2751         unsigned long flags;
2752
2753         spin_lock_irqsave(&ioapic_lock, flags);
2754         reg_01.raw = io_apic_read(ioapic, 1);
2755         spin_unlock_irqrestore(&ioapic_lock, flags);
2756
2757         return reg_01.bits.version;
2758 }
2759
2760
2761 int __init io_apic_get_redir_entries (int ioapic)
2762 {
2763         union IO_APIC_reg_01    reg_01;
2764         unsigned long flags;
2765
2766         spin_lock_irqsave(&ioapic_lock, flags);
2767         reg_01.raw = io_apic_read(ioapic, 1);
2768         spin_unlock_irqrestore(&ioapic_lock, flags);
2769
2770         return reg_01.bits.entries;
2771 }
2772
2773
2774 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2775 {
2776         struct IO_APIC_route_entry entry;
2777         unsigned long flags;
2778
2779         if (!IO_APIC_IRQ(irq)) {
2780                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2781                         ioapic);
2782                 return -EINVAL;
2783         }
2784
2785         /*
2786          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2787          * Note that we mask (disable) IRQs now -- these get enabled when the
2788          * corresponding device driver registers for this IRQ.
2789          */
2790
2791         memset(&entry,0,sizeof(entry));
2792
2793         entry.delivery_mode = INT_DELIVERY_MODE;
2794         entry.dest_mode = INT_DEST_MODE;
2795         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2796         entry.trigger = edge_level;
2797         entry.polarity = active_high_low;
2798         entry.mask  = 1;
2799
2800         /*
2801          * IRQs < 16 are already in the irq_2_pin[] map
2802          */
2803         if (irq >= 16)
2804                 add_pin_to_irq(irq, ioapic, pin);
2805
2806         entry.vector = assign_irq_vector(irq);
2807
2808         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2809                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2810                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2811                 edge_level, active_high_low);
2812
2813         ioapic_register_intr(irq, entry.vector, edge_level);
2814
2815         if (!ioapic && (irq < 16))
2816                 disable_8259A_irq(irq);
2817
2818         spin_lock_irqsave(&ioapic_lock, flags);
2819         __ioapic_write_entry(ioapic, pin, entry);
2820         spin_unlock_irqrestore(&ioapic_lock, flags);
2821
2822         return 0;
2823 }
2824
2825 #endif /* CONFIG_ACPI */
2826
2827 static int __init parse_disable_timer_pin_1(char *arg)
2828 {
2829         disable_timer_pin_1 = 1;
2830         return 0;
2831 }
2832 early_param("disable_timer_pin_1", parse_disable_timer_pin_1);
2833
2834 static int __init parse_enable_timer_pin_1(char *arg)
2835 {
2836         disable_timer_pin_1 = -1;
2837         return 0;
2838 }
2839 early_param("enable_timer_pin_1", parse_enable_timer_pin_1);
2840
2841 static int __init parse_noapic(char *arg)
2842 {
2843         /* disable IO-APIC */
2844         disable_ioapic_setup();
2845         return 0;
2846 }
2847 early_param("noapic", parse_noapic);