smp, generic: introduce arch_disable_smp_support() instead of disable_ioapic_setup()
[linux-2.6.git] / arch / x86 / kernel / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h>      /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
64
65 #include <asm/genapic.h>
66
67 #define __apicdebuginit(type) static type __init
68
69 /*
70  *      Is the SiS APIC rmw bug present ?
71  *      -1 = don't know, 0 = no, 1 = yes
72  */
73 int sis_apic_bug = -1;
74
75 static DEFINE_SPINLOCK(ioapic_lock);
76 static DEFINE_SPINLOCK(vector_lock);
77
78 /*
79  * # of IRQ routing registers
80  */
81 int nr_ioapic_registers[MAX_IO_APICS];
82
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
85 int nr_ioapics;
86
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
89
90 /* # of MP IRQ source entries */
91 int mp_irq_entries;
92
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type[MAX_MP_BUSSES];
95 #endif
96
97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
98
99 int skip_ioapic_setup;
100
101 void arch_disable_smp_support(void)
102 {
103 #ifdef CONFIG_PCI
104         noioapicquirk = 1;
105         noioapicreroute = -1;
106 #endif
107         skip_ioapic_setup = 1;
108 }
109
110 static int __init parse_noapic(char *str)
111 {
112         /* disable IO-APIC */
113         arch_disable_smp_support();
114         return 0;
115 }
116 early_param("noapic", parse_noapic);
117
118 struct irq_pin_list;
119
120 /*
121  * This is performance-critical, we want to do it O(1)
122  *
123  * the indexing order of this array favors 1:1 mappings
124  * between pins and IRQs.
125  */
126
127 struct irq_pin_list {
128         int apic, pin;
129         struct irq_pin_list *next;
130 };
131
132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
133 {
134         struct irq_pin_list *pin;
135         int node;
136
137         node = cpu_to_node(cpu);
138
139         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
140
141         return pin;
142 }
143
144 struct irq_cfg {
145         struct irq_pin_list *irq_2_pin;
146         cpumask_var_t domain;
147         cpumask_var_t old_domain;
148         unsigned move_cleanup_count;
149         u8 vector;
150         u8 move_in_progress : 1;
151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
152         u8 move_desc_pending : 1;
153 #endif
154 };
155
156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
157 #ifdef CONFIG_SPARSE_IRQ
158 static struct irq_cfg irq_cfgx[] = {
159 #else
160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
161 #endif
162         [0]  = { .vector = IRQ0_VECTOR,  },
163         [1]  = { .vector = IRQ1_VECTOR,  },
164         [2]  = { .vector = IRQ2_VECTOR,  },
165         [3]  = { .vector = IRQ3_VECTOR,  },
166         [4]  = { .vector = IRQ4_VECTOR,  },
167         [5]  = { .vector = IRQ5_VECTOR,  },
168         [6]  = { .vector = IRQ6_VECTOR,  },
169         [7]  = { .vector = IRQ7_VECTOR,  },
170         [8]  = { .vector = IRQ8_VECTOR,  },
171         [9]  = { .vector = IRQ9_VECTOR,  },
172         [10] = { .vector = IRQ10_VECTOR, },
173         [11] = { .vector = IRQ11_VECTOR, },
174         [12] = { .vector = IRQ12_VECTOR, },
175         [13] = { .vector = IRQ13_VECTOR, },
176         [14] = { .vector = IRQ14_VECTOR, },
177         [15] = { .vector = IRQ15_VECTOR, },
178 };
179
180 int __init arch_early_irq_init(void)
181 {
182         struct irq_cfg *cfg;
183         struct irq_desc *desc;
184         int count;
185         int i;
186
187         cfg = irq_cfgx;
188         count = ARRAY_SIZE(irq_cfgx);
189
190         for (i = 0; i < count; i++) {
191                 desc = irq_to_desc(i);
192                 desc->chip_data = &cfg[i];
193                 alloc_bootmem_cpumask_var(&cfg[i].domain);
194                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
195                 if (i < NR_IRQS_LEGACY)
196                         cpumask_setall(cfg[i].domain);
197         }
198
199         return 0;
200 }
201
202 #ifdef CONFIG_SPARSE_IRQ
203 static struct irq_cfg *irq_cfg(unsigned int irq)
204 {
205         struct irq_cfg *cfg = NULL;
206         struct irq_desc *desc;
207
208         desc = irq_to_desc(irq);
209         if (desc)
210                 cfg = desc->chip_data;
211
212         return cfg;
213 }
214
215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
216 {
217         struct irq_cfg *cfg;
218         int node;
219
220         node = cpu_to_node(cpu);
221
222         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
223         if (cfg) {
224                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
225                         kfree(cfg);
226                         cfg = NULL;
227                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
228                                                           GFP_ATOMIC, node)) {
229                         free_cpumask_var(cfg->domain);
230                         kfree(cfg);
231                         cfg = NULL;
232                 } else {
233                         cpumask_clear(cfg->domain);
234                         cpumask_clear(cfg->old_domain);
235                 }
236         }
237
238         return cfg;
239 }
240
241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
242 {
243         struct irq_cfg *cfg;
244
245         cfg = desc->chip_data;
246         if (!cfg) {
247                 desc->chip_data = get_one_free_irq_cfg(cpu);
248                 if (!desc->chip_data) {
249                         printk(KERN_ERR "can not alloc irq_cfg\n");
250                         BUG_ON(1);
251                 }
252         }
253
254         return 0;
255 }
256
257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
258
259 static void
260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
261 {
262         struct irq_pin_list *old_entry, *head, *tail, *entry;
263
264         cfg->irq_2_pin = NULL;
265         old_entry = old_cfg->irq_2_pin;
266         if (!old_entry)
267                 return;
268
269         entry = get_one_free_irq_2_pin(cpu);
270         if (!entry)
271                 return;
272
273         entry->apic     = old_entry->apic;
274         entry->pin      = old_entry->pin;
275         head            = entry;
276         tail            = entry;
277         old_entry       = old_entry->next;
278         while (old_entry) {
279                 entry = get_one_free_irq_2_pin(cpu);
280                 if (!entry) {
281                         entry = head;
282                         while (entry) {
283                                 head = entry->next;
284                                 kfree(entry);
285                                 entry = head;
286                         }
287                         /* still use the old one */
288                         return;
289                 }
290                 entry->apic     = old_entry->apic;
291                 entry->pin      = old_entry->pin;
292                 tail->next      = entry;
293                 tail            = entry;
294                 old_entry       = old_entry->next;
295         }
296
297         tail->next = NULL;
298         cfg->irq_2_pin = head;
299 }
300
301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
302 {
303         struct irq_pin_list *entry, *next;
304
305         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
306                 return;
307
308         entry = old_cfg->irq_2_pin;
309
310         while (entry) {
311                 next = entry->next;
312                 kfree(entry);
313                 entry = next;
314         }
315         old_cfg->irq_2_pin = NULL;
316 }
317
318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
319                                  struct irq_desc *desc, int cpu)
320 {
321         struct irq_cfg *cfg;
322         struct irq_cfg *old_cfg;
323
324         cfg = get_one_free_irq_cfg(cpu);
325
326         if (!cfg)
327                 return;
328
329         desc->chip_data = cfg;
330
331         old_cfg = old_desc->chip_data;
332
333         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
334
335         init_copy_irq_2_pin(old_cfg, cfg, cpu);
336 }
337
338 static void free_irq_cfg(struct irq_cfg *old_cfg)
339 {
340         kfree(old_cfg);
341 }
342
343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
344 {
345         struct irq_cfg *old_cfg, *cfg;
346
347         old_cfg = old_desc->chip_data;
348         cfg = desc->chip_data;
349
350         if (old_cfg == cfg)
351                 return;
352
353         if (old_cfg) {
354                 free_irq_2_pin(old_cfg, cfg);
355                 free_irq_cfg(old_cfg);
356                 old_desc->chip_data = NULL;
357         }
358 }
359
360 static void
361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
362 {
363         struct irq_cfg *cfg = desc->chip_data;
364
365         if (!cfg->move_in_progress) {
366                 /* it means that domain is not changed */
367                 if (!cpumask_intersects(desc->affinity, mask))
368                         cfg->move_desc_pending = 1;
369         }
370 }
371 #endif
372
373 #else
374 static struct irq_cfg *irq_cfg(unsigned int irq)
375 {
376         return irq < nr_irqs ? irq_cfgx + irq : NULL;
377 }
378
379 #endif
380
381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
382 static inline void
383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
384 {
385 }
386 #endif
387
388 struct io_apic {
389         unsigned int index;
390         unsigned int unused[3];
391         unsigned int data;
392 };
393
394 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
395 {
396         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
397                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
398 }
399
400 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
401 {
402         struct io_apic __iomem *io_apic = io_apic_base(apic);
403         writel(reg, &io_apic->index);
404         return readl(&io_apic->data);
405 }
406
407 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
408 {
409         struct io_apic __iomem *io_apic = io_apic_base(apic);
410         writel(reg, &io_apic->index);
411         writel(value, &io_apic->data);
412 }
413
414 /*
415  * Re-write a value: to be used for read-modify-write
416  * cycles where the read already set up the index register.
417  *
418  * Older SiS APIC requires we rewrite the index register
419  */
420 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
421 {
422         struct io_apic __iomem *io_apic = io_apic_base(apic);
423
424         if (sis_apic_bug)
425                 writel(reg, &io_apic->index);
426         writel(value, &io_apic->data);
427 }
428
429 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
430 {
431         struct irq_pin_list *entry;
432         unsigned long flags;
433
434         spin_lock_irqsave(&ioapic_lock, flags);
435         entry = cfg->irq_2_pin;
436         for (;;) {
437                 unsigned int reg;
438                 int pin;
439
440                 if (!entry)
441                         break;
442                 pin = entry->pin;
443                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
444                 /* Is the remote IRR bit set? */
445                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
446                         spin_unlock_irqrestore(&ioapic_lock, flags);
447                         return true;
448                 }
449                 if (!entry->next)
450                         break;
451                 entry = entry->next;
452         }
453         spin_unlock_irqrestore(&ioapic_lock, flags);
454
455         return false;
456 }
457
458 union entry_union {
459         struct { u32 w1, w2; };
460         struct IO_APIC_route_entry entry;
461 };
462
463 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
464 {
465         union entry_union eu;
466         unsigned long flags;
467         spin_lock_irqsave(&ioapic_lock, flags);
468         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
469         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
470         spin_unlock_irqrestore(&ioapic_lock, flags);
471         return eu.entry;
472 }
473
474 /*
475  * When we write a new IO APIC routing entry, we need to write the high
476  * word first! If the mask bit in the low word is clear, we will enable
477  * the interrupt, and we need to make sure the entry is fully populated
478  * before that happens.
479  */
480 static void
481 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
482 {
483         union entry_union eu;
484         eu.entry = e;
485         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
486         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
487 }
488
489 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
490 {
491         unsigned long flags;
492         spin_lock_irqsave(&ioapic_lock, flags);
493         __ioapic_write_entry(apic, pin, e);
494         spin_unlock_irqrestore(&ioapic_lock, flags);
495 }
496
497 /*
498  * When we mask an IO APIC routing entry, we need to write the low
499  * word first, in order to set the mask bit before we change the
500  * high bits!
501  */
502 static void ioapic_mask_entry(int apic, int pin)
503 {
504         unsigned long flags;
505         union entry_union eu = { .entry.mask = 1 };
506
507         spin_lock_irqsave(&ioapic_lock, flags);
508         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
509         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
510         spin_unlock_irqrestore(&ioapic_lock, flags);
511 }
512
513 #ifdef CONFIG_SMP
514 static void send_cleanup_vector(struct irq_cfg *cfg)
515 {
516         cpumask_var_t cleanup_mask;
517
518         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
519                 unsigned int i;
520                 cfg->move_cleanup_count = 0;
521                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
522                         cfg->move_cleanup_count++;
523                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
524                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
525         } else {
526                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
527                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
528                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
529                 free_cpumask_var(cleanup_mask);
530         }
531         cfg->move_in_progress = 0;
532 }
533
534 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
535 {
536         int apic, pin;
537         struct irq_pin_list *entry;
538         u8 vector = cfg->vector;
539
540         entry = cfg->irq_2_pin;
541         for (;;) {
542                 unsigned int reg;
543
544                 if (!entry)
545                         break;
546
547                 apic = entry->apic;
548                 pin = entry->pin;
549 #ifdef CONFIG_INTR_REMAP
550                 /*
551                  * With interrupt-remapping, destination information comes
552                  * from interrupt-remapping table entry.
553                  */
554                 if (!irq_remapped(irq))
555                         io_apic_write(apic, 0x11 + pin*2, dest);
556 #else
557                 io_apic_write(apic, 0x11 + pin*2, dest);
558 #endif
559                 reg = io_apic_read(apic, 0x10 + pin*2);
560                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
561                 reg |= vector;
562                 io_apic_modify(apic, 0x10 + pin*2, reg);
563                 if (!entry->next)
564                         break;
565                 entry = entry->next;
566         }
567 }
568
569 static int
570 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
571
572 /*
573  * Either sets desc->affinity to a valid value, and returns
574  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
575  * leaves desc->affinity untouched.
576  */
577 static unsigned int
578 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
579 {
580         struct irq_cfg *cfg;
581         unsigned int irq;
582
583         if (!cpumask_intersects(mask, cpu_online_mask))
584                 return BAD_APICID;
585
586         irq = desc->irq;
587         cfg = desc->chip_data;
588         if (assign_irq_vector(irq, cfg, mask))
589                 return BAD_APICID;
590
591         cpumask_and(desc->affinity, cfg->domain, mask);
592         set_extra_move_desc(desc, mask);
593
594         return apic->cpu_mask_to_apicid_and(desc->affinity, cpu_online_mask);
595 }
596
597 static void
598 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
599 {
600         struct irq_cfg *cfg;
601         unsigned long flags;
602         unsigned int dest;
603         unsigned int irq;
604
605         irq = desc->irq;
606         cfg = desc->chip_data;
607
608         spin_lock_irqsave(&ioapic_lock, flags);
609         dest = set_desc_affinity(desc, mask);
610         if (dest != BAD_APICID) {
611                 /* Only the high 8 bits are valid. */
612                 dest = SET_APIC_LOGICAL_ID(dest);
613                 __target_IO_APIC_irq(irq, dest, cfg);
614         }
615         spin_unlock_irqrestore(&ioapic_lock, flags);
616 }
617
618 static void
619 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
620 {
621         struct irq_desc *desc;
622
623         desc = irq_to_desc(irq);
624
625         set_ioapic_affinity_irq_desc(desc, mask);
626 }
627 #endif /* CONFIG_SMP */
628
629 /*
630  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
631  * shared ISA-space IRQs, so we have to support them. We are super
632  * fast in the common case, and fast for shared ISA-space IRQs.
633  */
634 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
635 {
636         struct irq_pin_list *entry;
637
638         entry = cfg->irq_2_pin;
639         if (!entry) {
640                 entry = get_one_free_irq_2_pin(cpu);
641                 if (!entry) {
642                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
643                                         apic, pin);
644                         return;
645                 }
646                 cfg->irq_2_pin = entry;
647                 entry->apic = apic;
648                 entry->pin = pin;
649                 return;
650         }
651
652         while (entry->next) {
653                 /* not again, please */
654                 if (entry->apic == apic && entry->pin == pin)
655                         return;
656
657                 entry = entry->next;
658         }
659
660         entry->next = get_one_free_irq_2_pin(cpu);
661         entry = entry->next;
662         entry->apic = apic;
663         entry->pin = pin;
664 }
665
666 /*
667  * Reroute an IRQ to a different pin.
668  */
669 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
670                                       int oldapic, int oldpin,
671                                       int newapic, int newpin)
672 {
673         struct irq_pin_list *entry = cfg->irq_2_pin;
674         int replaced = 0;
675
676         while (entry) {
677                 if (entry->apic == oldapic && entry->pin == oldpin) {
678                         entry->apic = newapic;
679                         entry->pin = newpin;
680                         replaced = 1;
681                         /* every one is different, right? */
682                         break;
683                 }
684                 entry = entry->next;
685         }
686
687         /* why? call replace before add? */
688         if (!replaced)
689                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
690 }
691
692 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
693                                 int mask_and, int mask_or,
694                                 void (*final)(struct irq_pin_list *entry))
695 {
696         int pin;
697         struct irq_pin_list *entry;
698
699         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
700                 unsigned int reg;
701                 pin = entry->pin;
702                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
703                 reg &= mask_and;
704                 reg |= mask_or;
705                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
706                 if (final)
707                         final(entry);
708         }
709 }
710
711 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
712 {
713         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
714 }
715
716 #ifdef CONFIG_X86_64
717 static void io_apic_sync(struct irq_pin_list *entry)
718 {
719         /*
720          * Synchronize the IO-APIC and the CPU by doing
721          * a dummy read from the IO-APIC
722          */
723         struct io_apic __iomem *io_apic;
724         io_apic = io_apic_base(entry->apic);
725         readl(&io_apic->data);
726 }
727
728 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
729 {
730         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
731 }
732 #else /* CONFIG_X86_32 */
733 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
734 {
735         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
736 }
737
738 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
739 {
740         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
741                         IO_APIC_REDIR_MASKED, NULL);
742 }
743
744 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
745 {
746         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
747                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
748 }
749 #endif /* CONFIG_X86_32 */
750
751 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
752 {
753         struct irq_cfg *cfg = desc->chip_data;
754         unsigned long flags;
755
756         BUG_ON(!cfg);
757
758         spin_lock_irqsave(&ioapic_lock, flags);
759         __mask_IO_APIC_irq(cfg);
760         spin_unlock_irqrestore(&ioapic_lock, flags);
761 }
762
763 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
764 {
765         struct irq_cfg *cfg = desc->chip_data;
766         unsigned long flags;
767
768         spin_lock_irqsave(&ioapic_lock, flags);
769         __unmask_IO_APIC_irq(cfg);
770         spin_unlock_irqrestore(&ioapic_lock, flags);
771 }
772
773 static void mask_IO_APIC_irq(unsigned int irq)
774 {
775         struct irq_desc *desc = irq_to_desc(irq);
776
777         mask_IO_APIC_irq_desc(desc);
778 }
779 static void unmask_IO_APIC_irq(unsigned int irq)
780 {
781         struct irq_desc *desc = irq_to_desc(irq);
782
783         unmask_IO_APIC_irq_desc(desc);
784 }
785
786 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
787 {
788         struct IO_APIC_route_entry entry;
789
790         /* Check delivery_mode to be sure we're not clearing an SMI pin */
791         entry = ioapic_read_entry(apic, pin);
792         if (entry.delivery_mode == dest_SMI)
793                 return;
794         /*
795          * Disable it in the IO-APIC irq-routing table:
796          */
797         ioapic_mask_entry(apic, pin);
798 }
799
800 static void clear_IO_APIC (void)
801 {
802         int apic, pin;
803
804         for (apic = 0; apic < nr_ioapics; apic++)
805                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
806                         clear_IO_APIC_pin(apic, pin);
807 }
808
809 #ifdef CONFIG_X86_32
810 /*
811  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
812  * specific CPU-side IRQs.
813  */
814
815 #define MAX_PIRQS 8
816 static int pirq_entries [MAX_PIRQS];
817 static int pirqs_enabled;
818
819 static int __init ioapic_pirq_setup(char *str)
820 {
821         int i, max;
822         int ints[MAX_PIRQS+1];
823
824         get_options(str, ARRAY_SIZE(ints), ints);
825
826         for (i = 0; i < MAX_PIRQS; i++)
827                 pirq_entries[i] = -1;
828
829         pirqs_enabled = 1;
830         apic_printk(APIC_VERBOSE, KERN_INFO
831                         "PIRQ redirection, working around broken MP-BIOS.\n");
832         max = MAX_PIRQS;
833         if (ints[0] < MAX_PIRQS)
834                 max = ints[0];
835
836         for (i = 0; i < max; i++) {
837                 apic_printk(APIC_VERBOSE, KERN_DEBUG
838                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
839                 /*
840                  * PIRQs are mapped upside down, usually.
841                  */
842                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
843         }
844         return 1;
845 }
846
847 __setup("pirq=", ioapic_pirq_setup);
848 #endif /* CONFIG_X86_32 */
849
850 #ifdef CONFIG_INTR_REMAP
851 /* I/O APIC RTE contents at the OS boot up */
852 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
853
854 /*
855  * Saves and masks all the unmasked IO-APIC RTE's
856  */
857 int save_mask_IO_APIC_setup(void)
858 {
859         union IO_APIC_reg_01 reg_01;
860         unsigned long flags;
861         int apic, pin;
862
863         /*
864          * The number of IO-APIC IRQ registers (== #pins):
865          */
866         for (apic = 0; apic < nr_ioapics; apic++) {
867                 spin_lock_irqsave(&ioapic_lock, flags);
868                 reg_01.raw = io_apic_read(apic, 1);
869                 spin_unlock_irqrestore(&ioapic_lock, flags);
870                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
871         }
872
873         for (apic = 0; apic < nr_ioapics; apic++) {
874                 early_ioapic_entries[apic] =
875                         kzalloc(sizeof(struct IO_APIC_route_entry) *
876                                 nr_ioapic_registers[apic], GFP_KERNEL);
877                 if (!early_ioapic_entries[apic])
878                         goto nomem;
879         }
880
881         for (apic = 0; apic < nr_ioapics; apic++)
882                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
883                         struct IO_APIC_route_entry entry;
884
885                         entry = early_ioapic_entries[apic][pin] =
886                                 ioapic_read_entry(apic, pin);
887                         if (!entry.mask) {
888                                 entry.mask = 1;
889                                 ioapic_write_entry(apic, pin, entry);
890                         }
891                 }
892
893         return 0;
894
895 nomem:
896         while (apic >= 0)
897                 kfree(early_ioapic_entries[apic--]);
898         memset(early_ioapic_entries, 0,
899                 ARRAY_SIZE(early_ioapic_entries));
900
901         return -ENOMEM;
902 }
903
904 void restore_IO_APIC_setup(void)
905 {
906         int apic, pin;
907
908         for (apic = 0; apic < nr_ioapics; apic++) {
909                 if (!early_ioapic_entries[apic])
910                         break;
911                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
912                         ioapic_write_entry(apic, pin,
913                                            early_ioapic_entries[apic][pin]);
914                 kfree(early_ioapic_entries[apic]);
915                 early_ioapic_entries[apic] = NULL;
916         }
917 }
918
919 void reinit_intr_remapped_IO_APIC(int intr_remapping)
920 {
921         /*
922          * for now plain restore of previous settings.
923          * TBD: In the case of OS enabling interrupt-remapping,
924          * IO-APIC RTE's need to be setup to point to interrupt-remapping
925          * table entries. for now, do a plain restore, and wait for
926          * the setup_IO_APIC_irqs() to do proper initialization.
927          */
928         restore_IO_APIC_setup();
929 }
930 #endif
931
932 /*
933  * Find the IRQ entry number of a certain pin.
934  */
935 static int find_irq_entry(int apic, int pin, int type)
936 {
937         int i;
938
939         for (i = 0; i < mp_irq_entries; i++)
940                 if (mp_irqs[i].irqtype == type &&
941                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
942                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
943                     mp_irqs[i].dstirq == pin)
944                         return i;
945
946         return -1;
947 }
948
949 /*
950  * Find the pin to which IRQ[irq] (ISA) is connected
951  */
952 static int __init find_isa_irq_pin(int irq, int type)
953 {
954         int i;
955
956         for (i = 0; i < mp_irq_entries; i++) {
957                 int lbus = mp_irqs[i].srcbus;
958
959                 if (test_bit(lbus, mp_bus_not_pci) &&
960                     (mp_irqs[i].irqtype == type) &&
961                     (mp_irqs[i].srcbusirq == irq))
962
963                         return mp_irqs[i].dstirq;
964         }
965         return -1;
966 }
967
968 static int __init find_isa_irq_apic(int irq, int type)
969 {
970         int i;
971
972         for (i = 0; i < mp_irq_entries; i++) {
973                 int lbus = mp_irqs[i].srcbus;
974
975                 if (test_bit(lbus, mp_bus_not_pci) &&
976                     (mp_irqs[i].irqtype == type) &&
977                     (mp_irqs[i].srcbusirq == irq))
978                         break;
979         }
980         if (i < mp_irq_entries) {
981                 int apic;
982                 for(apic = 0; apic < nr_ioapics; apic++) {
983                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
984                                 return apic;
985                 }
986         }
987
988         return -1;
989 }
990
991 /*
992  * Find a specific PCI IRQ entry.
993  * Not an __init, possibly needed by modules
994  */
995 static int pin_2_irq(int idx, int apic, int pin);
996
997 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
998 {
999         int apic, i, best_guess = -1;
1000
1001         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1002                 bus, slot, pin);
1003         if (test_bit(bus, mp_bus_not_pci)) {
1004                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1005                 return -1;
1006         }
1007         for (i = 0; i < mp_irq_entries; i++) {
1008                 int lbus = mp_irqs[i].srcbus;
1009
1010                 for (apic = 0; apic < nr_ioapics; apic++)
1011                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1012                             mp_irqs[i].dstapic == MP_APIC_ALL)
1013                                 break;
1014
1015                 if (!test_bit(lbus, mp_bus_not_pci) &&
1016                     !mp_irqs[i].irqtype &&
1017                     (bus == lbus) &&
1018                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1019                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1020
1021                         if (!(apic || IO_APIC_IRQ(irq)))
1022                                 continue;
1023
1024                         if (pin == (mp_irqs[i].srcbusirq & 3))
1025                                 return irq;
1026                         /*
1027                          * Use the first all-but-pin matching entry as a
1028                          * best-guess fuzzy result for broken mptables.
1029                          */
1030                         if (best_guess < 0)
1031                                 best_guess = irq;
1032                 }
1033         }
1034         return best_guess;
1035 }
1036
1037 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1038
1039 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1040 /*
1041  * EISA Edge/Level control register, ELCR
1042  */
1043 static int EISA_ELCR(unsigned int irq)
1044 {
1045         if (irq < NR_IRQS_LEGACY) {
1046                 unsigned int port = 0x4d0 + (irq >> 3);
1047                 return (inb(port) >> (irq & 7)) & 1;
1048         }
1049         apic_printk(APIC_VERBOSE, KERN_INFO
1050                         "Broken MPtable reports ISA irq %d\n", irq);
1051         return 0;
1052 }
1053
1054 #endif
1055
1056 /* ISA interrupts are always polarity zero edge triggered,
1057  * when listed as conforming in the MP table. */
1058
1059 #define default_ISA_trigger(idx)        (0)
1060 #define default_ISA_polarity(idx)       (0)
1061
1062 /* EISA interrupts are always polarity zero and can be edge or level
1063  * trigger depending on the ELCR value.  If an interrupt is listed as
1064  * EISA conforming in the MP table, that means its trigger type must
1065  * be read in from the ELCR */
1066
1067 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1068 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1069
1070 /* PCI interrupts are always polarity one level triggered,
1071  * when listed as conforming in the MP table. */
1072
1073 #define default_PCI_trigger(idx)        (1)
1074 #define default_PCI_polarity(idx)       (1)
1075
1076 /* MCA interrupts are always polarity zero level triggered,
1077  * when listed as conforming in the MP table. */
1078
1079 #define default_MCA_trigger(idx)        (1)
1080 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1081
1082 static int MPBIOS_polarity(int idx)
1083 {
1084         int bus = mp_irqs[idx].srcbus;
1085         int polarity;
1086
1087         /*
1088          * Determine IRQ line polarity (high active or low active):
1089          */
1090         switch (mp_irqs[idx].irqflag & 3)
1091         {
1092                 case 0: /* conforms, ie. bus-type dependent polarity */
1093                         if (test_bit(bus, mp_bus_not_pci))
1094                                 polarity = default_ISA_polarity(idx);
1095                         else
1096                                 polarity = default_PCI_polarity(idx);
1097                         break;
1098                 case 1: /* high active */
1099                 {
1100                         polarity = 0;
1101                         break;
1102                 }
1103                 case 2: /* reserved */
1104                 {
1105                         printk(KERN_WARNING "broken BIOS!!\n");
1106                         polarity = 1;
1107                         break;
1108                 }
1109                 case 3: /* low active */
1110                 {
1111                         polarity = 1;
1112                         break;
1113                 }
1114                 default: /* invalid */
1115                 {
1116                         printk(KERN_WARNING "broken BIOS!!\n");
1117                         polarity = 1;
1118                         break;
1119                 }
1120         }
1121         return polarity;
1122 }
1123
1124 static int MPBIOS_trigger(int idx)
1125 {
1126         int bus = mp_irqs[idx].srcbus;
1127         int trigger;
1128
1129         /*
1130          * Determine IRQ trigger mode (edge or level sensitive):
1131          */
1132         switch ((mp_irqs[idx].irqflag>>2) & 3)
1133         {
1134                 case 0: /* conforms, ie. bus-type dependent */
1135                         if (test_bit(bus, mp_bus_not_pci))
1136                                 trigger = default_ISA_trigger(idx);
1137                         else
1138                                 trigger = default_PCI_trigger(idx);
1139 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1140                         switch (mp_bus_id_to_type[bus]) {
1141                                 case MP_BUS_ISA: /* ISA pin */
1142                                 {
1143                                         /* set before the switch */
1144                                         break;
1145                                 }
1146                                 case MP_BUS_EISA: /* EISA pin */
1147                                 {
1148                                         trigger = default_EISA_trigger(idx);
1149                                         break;
1150                                 }
1151                                 case MP_BUS_PCI: /* PCI pin */
1152                                 {
1153                                         /* set before the switch */
1154                                         break;
1155                                 }
1156                                 case MP_BUS_MCA: /* MCA pin */
1157                                 {
1158                                         trigger = default_MCA_trigger(idx);
1159                                         break;
1160                                 }
1161                                 default:
1162                                 {
1163                                         printk(KERN_WARNING "broken BIOS!!\n");
1164                                         trigger = 1;
1165                                         break;
1166                                 }
1167                         }
1168 #endif
1169                         break;
1170                 case 1: /* edge */
1171                 {
1172                         trigger = 0;
1173                         break;
1174                 }
1175                 case 2: /* reserved */
1176                 {
1177                         printk(KERN_WARNING "broken BIOS!!\n");
1178                         trigger = 1;
1179                         break;
1180                 }
1181                 case 3: /* level */
1182                 {
1183                         trigger = 1;
1184                         break;
1185                 }
1186                 default: /* invalid */
1187                 {
1188                         printk(KERN_WARNING "broken BIOS!!\n");
1189                         trigger = 0;
1190                         break;
1191                 }
1192         }
1193         return trigger;
1194 }
1195
1196 static inline int irq_polarity(int idx)
1197 {
1198         return MPBIOS_polarity(idx);
1199 }
1200
1201 static inline int irq_trigger(int idx)
1202 {
1203         return MPBIOS_trigger(idx);
1204 }
1205
1206 int (*ioapic_renumber_irq)(int ioapic, int irq);
1207 static int pin_2_irq(int idx, int apic, int pin)
1208 {
1209         int irq, i;
1210         int bus = mp_irqs[idx].srcbus;
1211
1212         /*
1213          * Debugging check, we are in big trouble if this message pops up!
1214          */
1215         if (mp_irqs[idx].dstirq != pin)
1216                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1217
1218         if (test_bit(bus, mp_bus_not_pci)) {
1219                 irq = mp_irqs[idx].srcbusirq;
1220         } else {
1221                 /*
1222                  * PCI IRQs are mapped in order
1223                  */
1224                 i = irq = 0;
1225                 while (i < apic)
1226                         irq += nr_ioapic_registers[i++];
1227                 irq += pin;
1228                 /*
1229                  * For MPS mode, so far only needed by ES7000 platform
1230                  */
1231                 if (ioapic_renumber_irq)
1232                         irq = ioapic_renumber_irq(apic, irq);
1233         }
1234
1235 #ifdef CONFIG_X86_32
1236         /*
1237          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1238          */
1239         if ((pin >= 16) && (pin <= 23)) {
1240                 if (pirq_entries[pin-16] != -1) {
1241                         if (!pirq_entries[pin-16]) {
1242                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1243                                                 "disabling PIRQ%d\n", pin-16);
1244                         } else {
1245                                 irq = pirq_entries[pin-16];
1246                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1247                                                 "using PIRQ%d -> IRQ %d\n",
1248                                                 pin-16, irq);
1249                         }
1250                 }
1251         }
1252 #endif
1253
1254         return irq;
1255 }
1256
1257 void lock_vector_lock(void)
1258 {
1259         /* Used to the online set of cpus does not change
1260          * during assign_irq_vector.
1261          */
1262         spin_lock(&vector_lock);
1263 }
1264
1265 void unlock_vector_lock(void)
1266 {
1267         spin_unlock(&vector_lock);
1268 }
1269
1270 static int
1271 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1272 {
1273         /*
1274          * NOTE! The local APIC isn't very good at handling
1275          * multiple interrupts at the same interrupt level.
1276          * As the interrupt level is determined by taking the
1277          * vector number and shifting that right by 4, we
1278          * want to spread these out a bit so that they don't
1279          * all fall in the same interrupt level.
1280          *
1281          * Also, we've got to be careful not to trash gate
1282          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1283          */
1284         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1285         unsigned int old_vector;
1286         int cpu, err;
1287         cpumask_var_t tmp_mask;
1288
1289         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1290                 return -EBUSY;
1291
1292         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1293                 return -ENOMEM;
1294
1295         old_vector = cfg->vector;
1296         if (old_vector) {
1297                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1298                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1299                 if (!cpumask_empty(tmp_mask)) {
1300                         free_cpumask_var(tmp_mask);
1301                         return 0;
1302                 }
1303         }
1304
1305         /* Only try and allocate irqs on cpus that are present */
1306         err = -ENOSPC;
1307         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1308                 int new_cpu;
1309                 int vector, offset;
1310
1311                 apic->vector_allocation_domain(cpu, tmp_mask);
1312
1313                 vector = current_vector;
1314                 offset = current_offset;
1315 next:
1316                 vector += 8;
1317                 if (vector >= first_system_vector) {
1318                         /* If out of vectors on large boxen, must share them. */
1319                         offset = (offset + 1) % 8;
1320                         vector = FIRST_DEVICE_VECTOR + offset;
1321                 }
1322                 if (unlikely(current_vector == vector))
1323                         continue;
1324
1325                 if (test_bit(vector, used_vectors))
1326                         goto next;
1327
1328                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1329                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1330                                 goto next;
1331                 /* Found one! */
1332                 current_vector = vector;
1333                 current_offset = offset;
1334                 if (old_vector) {
1335                         cfg->move_in_progress = 1;
1336                         cpumask_copy(cfg->old_domain, cfg->domain);
1337                 }
1338                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1339                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1340                 cfg->vector = vector;
1341                 cpumask_copy(cfg->domain, tmp_mask);
1342                 err = 0;
1343                 break;
1344         }
1345         free_cpumask_var(tmp_mask);
1346         return err;
1347 }
1348
1349 static int
1350 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1351 {
1352         int err;
1353         unsigned long flags;
1354
1355         spin_lock_irqsave(&vector_lock, flags);
1356         err = __assign_irq_vector(irq, cfg, mask);
1357         spin_unlock_irqrestore(&vector_lock, flags);
1358         return err;
1359 }
1360
1361 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1362 {
1363         int cpu, vector;
1364
1365         BUG_ON(!cfg->vector);
1366
1367         vector = cfg->vector;
1368         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1369                 per_cpu(vector_irq, cpu)[vector] = -1;
1370
1371         cfg->vector = 0;
1372         cpumask_clear(cfg->domain);
1373
1374         if (likely(!cfg->move_in_progress))
1375                 return;
1376         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1377                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1378                                                                 vector++) {
1379                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1380                                 continue;
1381                         per_cpu(vector_irq, cpu)[vector] = -1;
1382                         break;
1383                 }
1384         }
1385         cfg->move_in_progress = 0;
1386 }
1387
1388 void __setup_vector_irq(int cpu)
1389 {
1390         /* Initialize vector_irq on a new cpu */
1391         /* This function must be called with vector_lock held */
1392         int irq, vector;
1393         struct irq_cfg *cfg;
1394         struct irq_desc *desc;
1395
1396         /* Mark the inuse vectors */
1397         for_each_irq_desc(irq, desc) {
1398                 cfg = desc->chip_data;
1399                 if (!cpumask_test_cpu(cpu, cfg->domain))
1400                         continue;
1401                 vector = cfg->vector;
1402                 per_cpu(vector_irq, cpu)[vector] = irq;
1403         }
1404         /* Mark the free vectors */
1405         for (vector = 0; vector < NR_VECTORS; ++vector) {
1406                 irq = per_cpu(vector_irq, cpu)[vector];
1407                 if (irq < 0)
1408                         continue;
1409
1410                 cfg = irq_cfg(irq);
1411                 if (!cpumask_test_cpu(cpu, cfg->domain))
1412                         per_cpu(vector_irq, cpu)[vector] = -1;
1413         }
1414 }
1415
1416 static struct irq_chip ioapic_chip;
1417 #ifdef CONFIG_INTR_REMAP
1418 static struct irq_chip ir_ioapic_chip;
1419 #endif
1420
1421 #define IOAPIC_AUTO     -1
1422 #define IOAPIC_EDGE     0
1423 #define IOAPIC_LEVEL    1
1424
1425 #ifdef CONFIG_X86_32
1426 static inline int IO_APIC_irq_trigger(int irq)
1427 {
1428         int apic, idx, pin;
1429
1430         for (apic = 0; apic < nr_ioapics; apic++) {
1431                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1432                         idx = find_irq_entry(apic, pin, mp_INT);
1433                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1434                                 return irq_trigger(idx);
1435                 }
1436         }
1437         /*
1438          * nonexistent IRQs are edge default
1439          */
1440         return 0;
1441 }
1442 #else
1443 static inline int IO_APIC_irq_trigger(int irq)
1444 {
1445         return 1;
1446 }
1447 #endif
1448
1449 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1450 {
1451
1452         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1453             trigger == IOAPIC_LEVEL)
1454                 desc->status |= IRQ_LEVEL;
1455         else
1456                 desc->status &= ~IRQ_LEVEL;
1457
1458 #ifdef CONFIG_INTR_REMAP
1459         if (irq_remapped(irq)) {
1460                 desc->status |= IRQ_MOVE_PCNTXT;
1461                 if (trigger)
1462                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1463                                                       handle_fasteoi_irq,
1464                                                      "fasteoi");
1465                 else
1466                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1467                                                       handle_edge_irq, "edge");
1468                 return;
1469         }
1470 #endif
1471         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1472             trigger == IOAPIC_LEVEL)
1473                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1474                                               handle_fasteoi_irq,
1475                                               "fasteoi");
1476         else
1477                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1478                                               handle_edge_irq, "edge");
1479 }
1480
1481 static int setup_ioapic_entry(int apic_id, int irq,
1482                               struct IO_APIC_route_entry *entry,
1483                               unsigned int destination, int trigger,
1484                               int polarity, int vector)
1485 {
1486         /*
1487          * add it to the IO-APIC irq-routing table:
1488          */
1489         memset(entry,0,sizeof(*entry));
1490
1491 #ifdef CONFIG_INTR_REMAP
1492         if (intr_remapping_enabled) {
1493                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1494                 struct irte irte;
1495                 struct IR_IO_APIC_route_entry *ir_entry =
1496                         (struct IR_IO_APIC_route_entry *) entry;
1497                 int index;
1498
1499                 if (!iommu)
1500                         panic("No mapping iommu for ioapic %d\n", apic_id);
1501
1502                 index = alloc_irte(iommu, irq, 1);
1503                 if (index < 0)
1504                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1505
1506                 memset(&irte, 0, sizeof(irte));
1507
1508                 irte.present = 1;
1509                 irte.dst_mode = apic->irq_dest_mode;
1510                 irte.trigger_mode = trigger;
1511                 irte.dlvry_mode = apic->irq_delivery_mode;
1512                 irte.vector = vector;
1513                 irte.dest_id = IRTE_DEST(destination);
1514
1515                 modify_irte(irq, &irte);
1516
1517                 ir_entry->index2 = (index >> 15) & 0x1;
1518                 ir_entry->zero = 0;
1519                 ir_entry->format = 1;
1520                 ir_entry->index = (index & 0x7fff);
1521         } else
1522 #endif
1523         {
1524                 entry->delivery_mode = apic->irq_delivery_mode;
1525                 entry->dest_mode = apic->irq_dest_mode;
1526                 entry->dest = destination;
1527         }
1528
1529         entry->mask = 0;                                /* enable IRQ */
1530         entry->trigger = trigger;
1531         entry->polarity = polarity;
1532         entry->vector = vector;
1533
1534         /* Mask level triggered irqs.
1535          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1536          */
1537         if (trigger)
1538                 entry->mask = 1;
1539         return 0;
1540 }
1541
1542 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1543                               int trigger, int polarity)
1544 {
1545         struct irq_cfg *cfg;
1546         struct IO_APIC_route_entry entry;
1547         unsigned int dest;
1548
1549         if (!IO_APIC_IRQ(irq))
1550                 return;
1551
1552         cfg = desc->chip_data;
1553
1554         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1555                 return;
1556
1557         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1558
1559         apic_printk(APIC_VERBOSE,KERN_DEBUG
1560                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1561                     "IRQ %d Mode:%i Active:%i)\n",
1562                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1563                     irq, trigger, polarity);
1564
1565
1566         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1567                                dest, trigger, polarity, cfg->vector)) {
1568                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1569                        mp_ioapics[apic_id].apicid, pin);
1570                 __clear_irq_vector(irq, cfg);
1571                 return;
1572         }
1573
1574         ioapic_register_intr(irq, desc, trigger);
1575         if (irq < NR_IRQS_LEGACY)
1576                 disable_8259A_irq(irq);
1577
1578         ioapic_write_entry(apic_id, pin, entry);
1579 }
1580
1581 static void __init setup_IO_APIC_irqs(void)
1582 {
1583         int apic_id, pin, idx, irq;
1584         int notcon = 0;
1585         struct irq_desc *desc;
1586         struct irq_cfg *cfg;
1587         int cpu = boot_cpu_id;
1588
1589         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1590
1591         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1592                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1593
1594                         idx = find_irq_entry(apic_id, pin, mp_INT);
1595                         if (idx == -1) {
1596                                 if (!notcon) {
1597                                         notcon = 1;
1598                                         apic_printk(APIC_VERBOSE,
1599                                                 KERN_DEBUG " %d-%d",
1600                                                 mp_ioapics[apic_id].apicid, pin);
1601                                 } else
1602                                         apic_printk(APIC_VERBOSE, " %d-%d",
1603                                                 mp_ioapics[apic_id].apicid, pin);
1604                                 continue;
1605                         }
1606                         if (notcon) {
1607                                 apic_printk(APIC_VERBOSE,
1608                                         " (apicid-pin) not connected\n");
1609                                 notcon = 0;
1610                         }
1611
1612                         irq = pin_2_irq(idx, apic_id, pin);
1613
1614                         /*
1615                          * Skip the timer IRQ if there's a quirk handler
1616                          * installed and if it returns 1:
1617                          */
1618                         if (apic->multi_timer_check &&
1619                                         apic->multi_timer_check(apic_id, irq))
1620                                 continue;
1621
1622                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1623                         if (!desc) {
1624                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1625                                 continue;
1626                         }
1627                         cfg = desc->chip_data;
1628                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1629
1630                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1631                                         irq_trigger(idx), irq_polarity(idx));
1632                 }
1633         }
1634
1635         if (notcon)
1636                 apic_printk(APIC_VERBOSE,
1637                         " (apicid-pin) not connected\n");
1638 }
1639
1640 /*
1641  * Set up the timer pin, possibly with the 8259A-master behind.
1642  */
1643 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1644                                         int vector)
1645 {
1646         struct IO_APIC_route_entry entry;
1647
1648 #ifdef CONFIG_INTR_REMAP
1649         if (intr_remapping_enabled)
1650                 return;
1651 #endif
1652
1653         memset(&entry, 0, sizeof(entry));
1654
1655         /*
1656          * We use logical delivery to get the timer IRQ
1657          * to the first CPU.
1658          */
1659         entry.dest_mode = apic->irq_dest_mode;
1660         entry.mask = 1;                                 /* mask IRQ now */
1661         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1662         entry.delivery_mode = apic->irq_delivery_mode;
1663         entry.polarity = 0;
1664         entry.trigger = 0;
1665         entry.vector = vector;
1666
1667         /*
1668          * The timer IRQ doesn't have to know that behind the
1669          * scene we may have a 8259A-master in AEOI mode ...
1670          */
1671         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1672
1673         /*
1674          * Add it to the IO-APIC irq-routing table:
1675          */
1676         ioapic_write_entry(apic_id, pin, entry);
1677 }
1678
1679
1680 __apicdebuginit(void) print_IO_APIC(void)
1681 {
1682         int apic, i;
1683         union IO_APIC_reg_00 reg_00;
1684         union IO_APIC_reg_01 reg_01;
1685         union IO_APIC_reg_02 reg_02;
1686         union IO_APIC_reg_03 reg_03;
1687         unsigned long flags;
1688         struct irq_cfg *cfg;
1689         struct irq_desc *desc;
1690         unsigned int irq;
1691
1692         if (apic_verbosity == APIC_QUIET)
1693                 return;
1694
1695         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1696         for (i = 0; i < nr_ioapics; i++)
1697                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1698                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1699
1700         /*
1701          * We are a bit conservative about what we expect.  We have to
1702          * know about every hardware change ASAP.
1703          */
1704         printk(KERN_INFO "testing the IO APIC.......................\n");
1705
1706         for (apic = 0; apic < nr_ioapics; apic++) {
1707
1708         spin_lock_irqsave(&ioapic_lock, flags);
1709         reg_00.raw = io_apic_read(apic, 0);
1710         reg_01.raw = io_apic_read(apic, 1);
1711         if (reg_01.bits.version >= 0x10)
1712                 reg_02.raw = io_apic_read(apic, 2);
1713         if (reg_01.bits.version >= 0x20)
1714                 reg_03.raw = io_apic_read(apic, 3);
1715         spin_unlock_irqrestore(&ioapic_lock, flags);
1716
1717         printk("\n");
1718         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1719         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1720         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1721         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1722         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1723
1724         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1725         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1726
1727         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1728         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1729
1730         /*
1731          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1732          * but the value of reg_02 is read as the previous read register
1733          * value, so ignore it if reg_02 == reg_01.
1734          */
1735         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1736                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1737                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1738         }
1739
1740         /*
1741          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1742          * or reg_03, but the value of reg_0[23] is read as the previous read
1743          * register value, so ignore it if reg_03 == reg_0[12].
1744          */
1745         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1746             reg_03.raw != reg_01.raw) {
1747                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1748                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1749         }
1750
1751         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1752
1753         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1754                           " Stat Dmod Deli Vect:   \n");
1755
1756         for (i = 0; i <= reg_01.bits.entries; i++) {
1757                 struct IO_APIC_route_entry entry;
1758
1759                 entry = ioapic_read_entry(apic, i);
1760
1761                 printk(KERN_DEBUG " %02x %03X ",
1762                         i,
1763                         entry.dest
1764                 );
1765
1766                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1767                         entry.mask,
1768                         entry.trigger,
1769                         entry.irr,
1770                         entry.polarity,
1771                         entry.delivery_status,
1772                         entry.dest_mode,
1773                         entry.delivery_mode,
1774                         entry.vector
1775                 );
1776         }
1777         }
1778         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1779         for_each_irq_desc(irq, desc) {
1780                 struct irq_pin_list *entry;
1781
1782                 cfg = desc->chip_data;
1783                 entry = cfg->irq_2_pin;
1784                 if (!entry)
1785                         continue;
1786                 printk(KERN_DEBUG "IRQ%d ", irq);
1787                 for (;;) {
1788                         printk("-> %d:%d", entry->apic, entry->pin);
1789                         if (!entry->next)
1790                                 break;
1791                         entry = entry->next;
1792                 }
1793                 printk("\n");
1794         }
1795
1796         printk(KERN_INFO ".................................... done.\n");
1797
1798         return;
1799 }
1800
1801 __apicdebuginit(void) print_APIC_bitfield(int base)
1802 {
1803         unsigned int v;
1804         int i, j;
1805
1806         if (apic_verbosity == APIC_QUIET)
1807                 return;
1808
1809         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1810         for (i = 0; i < 8; i++) {
1811                 v = apic_read(base + i*0x10);
1812                 for (j = 0; j < 32; j++) {
1813                         if (v & (1<<j))
1814                                 printk("1");
1815                         else
1816                                 printk("0");
1817                 }
1818                 printk("\n");
1819         }
1820 }
1821
1822 __apicdebuginit(void) print_local_APIC(void *dummy)
1823 {
1824         unsigned int v, ver, maxlvt;
1825         u64 icr;
1826
1827         if (apic_verbosity == APIC_QUIET)
1828                 return;
1829
1830         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1831                 smp_processor_id(), hard_smp_processor_id());
1832         v = apic_read(APIC_ID);
1833         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1834         v = apic_read(APIC_LVR);
1835         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1836         ver = GET_APIC_VERSION(v);
1837         maxlvt = lapic_get_maxlvt();
1838
1839         v = apic_read(APIC_TASKPRI);
1840         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1841
1842         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1843                 if (!APIC_XAPIC(ver)) {
1844                         v = apic_read(APIC_ARBPRI);
1845                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1846                                v & APIC_ARBPRI_MASK);
1847                 }
1848                 v = apic_read(APIC_PROCPRI);
1849                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1850         }
1851
1852         /*
1853          * Remote read supported only in the 82489DX and local APIC for
1854          * Pentium processors.
1855          */
1856         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1857                 v = apic_read(APIC_RRR);
1858                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1859         }
1860
1861         v = apic_read(APIC_LDR);
1862         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1863         if (!x2apic_enabled()) {
1864                 v = apic_read(APIC_DFR);
1865                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1866         }
1867         v = apic_read(APIC_SPIV);
1868         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1869
1870         printk(KERN_DEBUG "... APIC ISR field:\n");
1871         print_APIC_bitfield(APIC_ISR);
1872         printk(KERN_DEBUG "... APIC TMR field:\n");
1873         print_APIC_bitfield(APIC_TMR);
1874         printk(KERN_DEBUG "... APIC IRR field:\n");
1875         print_APIC_bitfield(APIC_IRR);
1876
1877         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1878                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1879                         apic_write(APIC_ESR, 0);
1880
1881                 v = apic_read(APIC_ESR);
1882                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1883         }
1884
1885         icr = apic_icr_read();
1886         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1887         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1888
1889         v = apic_read(APIC_LVTT);
1890         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1891
1892         if (maxlvt > 3) {                       /* PC is LVT#4. */
1893                 v = apic_read(APIC_LVTPC);
1894                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1895         }
1896         v = apic_read(APIC_LVT0);
1897         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1898         v = apic_read(APIC_LVT1);
1899         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1900
1901         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1902                 v = apic_read(APIC_LVTERR);
1903                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1904         }
1905
1906         v = apic_read(APIC_TMICT);
1907         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1908         v = apic_read(APIC_TMCCT);
1909         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1910         v = apic_read(APIC_TDCR);
1911         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1912         printk("\n");
1913 }
1914
1915 __apicdebuginit(void) print_all_local_APICs(void)
1916 {
1917         int cpu;
1918
1919         preempt_disable();
1920         for_each_online_cpu(cpu)
1921                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1922         preempt_enable();
1923 }
1924
1925 __apicdebuginit(void) print_PIC(void)
1926 {
1927         unsigned int v;
1928         unsigned long flags;
1929
1930         if (apic_verbosity == APIC_QUIET)
1931                 return;
1932
1933         printk(KERN_DEBUG "\nprinting PIC contents\n");
1934
1935         spin_lock_irqsave(&i8259A_lock, flags);
1936
1937         v = inb(0xa1) << 8 | inb(0x21);
1938         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1939
1940         v = inb(0xa0) << 8 | inb(0x20);
1941         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1942
1943         outb(0x0b,0xa0);
1944         outb(0x0b,0x20);
1945         v = inb(0xa0) << 8 | inb(0x20);
1946         outb(0x0a,0xa0);
1947         outb(0x0a,0x20);
1948
1949         spin_unlock_irqrestore(&i8259A_lock, flags);
1950
1951         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1952
1953         v = inb(0x4d1) << 8 | inb(0x4d0);
1954         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1955 }
1956
1957 __apicdebuginit(int) print_all_ICs(void)
1958 {
1959         print_PIC();
1960         print_all_local_APICs();
1961         print_IO_APIC();
1962
1963         return 0;
1964 }
1965
1966 fs_initcall(print_all_ICs);
1967
1968
1969 /* Where if anywhere is the i8259 connect in external int mode */
1970 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1971
1972 void __init enable_IO_APIC(void)
1973 {
1974         union IO_APIC_reg_01 reg_01;
1975         int i8259_apic, i8259_pin;
1976         int apic;
1977         unsigned long flags;
1978
1979 #ifdef CONFIG_X86_32
1980         int i;
1981         if (!pirqs_enabled)
1982                 for (i = 0; i < MAX_PIRQS; i++)
1983                         pirq_entries[i] = -1;
1984 #endif
1985
1986         /*
1987          * The number of IO-APIC IRQ registers (== #pins):
1988          */
1989         for (apic = 0; apic < nr_ioapics; apic++) {
1990                 spin_lock_irqsave(&ioapic_lock, flags);
1991                 reg_01.raw = io_apic_read(apic, 1);
1992                 spin_unlock_irqrestore(&ioapic_lock, flags);
1993                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1994         }
1995         for(apic = 0; apic < nr_ioapics; apic++) {
1996                 int pin;
1997                 /* See if any of the pins is in ExtINT mode */
1998                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1999                         struct IO_APIC_route_entry entry;
2000                         entry = ioapic_read_entry(apic, pin);
2001
2002                         /* If the interrupt line is enabled and in ExtInt mode
2003                          * I have found the pin where the i8259 is connected.
2004                          */
2005                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2006                                 ioapic_i8259.apic = apic;
2007                                 ioapic_i8259.pin  = pin;
2008                                 goto found_i8259;
2009                         }
2010                 }
2011         }
2012  found_i8259:
2013         /* Look to see what if the MP table has reported the ExtINT */
2014         /* If we could not find the appropriate pin by looking at the ioapic
2015          * the i8259 probably is not connected the ioapic but give the
2016          * mptable a chance anyway.
2017          */
2018         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2019         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2020         /* Trust the MP table if nothing is setup in the hardware */
2021         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2022                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2023                 ioapic_i8259.pin  = i8259_pin;
2024                 ioapic_i8259.apic = i8259_apic;
2025         }
2026         /* Complain if the MP table and the hardware disagree */
2027         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2028                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2029         {
2030                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2031         }
2032
2033         /*
2034          * Do not trust the IO-APIC being empty at bootup
2035          */
2036         clear_IO_APIC();
2037 }
2038
2039 /*
2040  * Not an __init, needed by the reboot code
2041  */
2042 void disable_IO_APIC(void)
2043 {
2044         /*
2045          * Clear the IO-APIC before rebooting:
2046          */
2047         clear_IO_APIC();
2048
2049         /*
2050          * If the i8259 is routed through an IOAPIC
2051          * Put that IOAPIC in virtual wire mode
2052          * so legacy interrupts can be delivered.
2053          */
2054         if (ioapic_i8259.pin != -1) {
2055                 struct IO_APIC_route_entry entry;
2056
2057                 memset(&entry, 0, sizeof(entry));
2058                 entry.mask            = 0; /* Enabled */
2059                 entry.trigger         = 0; /* Edge */
2060                 entry.irr             = 0;
2061                 entry.polarity        = 0; /* High */
2062                 entry.delivery_status = 0;
2063                 entry.dest_mode       = 0; /* Physical */
2064                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2065                 entry.vector          = 0;
2066                 entry.dest            = read_apic_id();
2067
2068                 /*
2069                  * Add it to the IO-APIC irq-routing table:
2070                  */
2071                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2072         }
2073
2074         disconnect_bsp_APIC(ioapic_i8259.pin != -1);
2075 }
2076
2077 #ifdef CONFIG_X86_32
2078 /*
2079  * function to set the IO-APIC physical IDs based on the
2080  * values stored in the MPC table.
2081  *
2082  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2083  */
2084
2085 static void __init setup_ioapic_ids_from_mpc(void)
2086 {
2087         union IO_APIC_reg_00 reg_00;
2088         physid_mask_t phys_id_present_map;
2089         int apic_id;
2090         int i;
2091         unsigned char old_id;
2092         unsigned long flags;
2093
2094         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2095                 return;
2096
2097         /*
2098          * Don't check I/O APIC IDs for xAPIC systems.  They have
2099          * no meaning without the serial APIC bus.
2100          */
2101         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2102                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2103                 return;
2104         /*
2105          * This is broken; anything with a real cpu count has to
2106          * circumvent this idiocy regardless.
2107          */
2108         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2109
2110         /*
2111          * Set the IOAPIC ID to the value stored in the MPC table.
2112          */
2113         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2114
2115                 /* Read the register 0 value */
2116                 spin_lock_irqsave(&ioapic_lock, flags);
2117                 reg_00.raw = io_apic_read(apic_id, 0);
2118                 spin_unlock_irqrestore(&ioapic_lock, flags);
2119
2120                 old_id = mp_ioapics[apic_id].apicid;
2121
2122                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2123                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2124                                 apic_id, mp_ioapics[apic_id].apicid);
2125                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2126                                 reg_00.bits.ID);
2127                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2128                 }
2129
2130                 /*
2131                  * Sanity check, is the ID really free? Every APIC in a
2132                  * system must have a unique ID or we get lots of nice
2133                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2134                  */
2135                 if (apic->check_apicid_used(phys_id_present_map,
2136                                         mp_ioapics[apic_id].apicid)) {
2137                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2138                                 apic_id, mp_ioapics[apic_id].apicid);
2139                         for (i = 0; i < get_physical_broadcast(); i++)
2140                                 if (!physid_isset(i, phys_id_present_map))
2141                                         break;
2142                         if (i >= get_physical_broadcast())
2143                                 panic("Max APIC ID exceeded!\n");
2144                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2145                                 i);
2146                         physid_set(i, phys_id_present_map);
2147                         mp_ioapics[apic_id].apicid = i;
2148                 } else {
2149                         physid_mask_t tmp;
2150                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2151                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2152                                         "phys_id_present_map\n",
2153                                         mp_ioapics[apic_id].apicid);
2154                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2155                 }
2156
2157
2158                 /*
2159                  * We need to adjust the IRQ routing table
2160                  * if the ID changed.
2161                  */
2162                 if (old_id != mp_ioapics[apic_id].apicid)
2163                         for (i = 0; i < mp_irq_entries; i++)
2164                                 if (mp_irqs[i].dstapic == old_id)
2165                                         mp_irqs[i].dstapic
2166                                                 = mp_ioapics[apic_id].apicid;
2167
2168                 /*
2169                  * Read the right value from the MPC table and
2170                  * write it into the ID register.
2171                  */
2172                 apic_printk(APIC_VERBOSE, KERN_INFO
2173                         "...changing IO-APIC physical APIC ID to %d ...",
2174                         mp_ioapics[apic_id].apicid);
2175
2176                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2177                 spin_lock_irqsave(&ioapic_lock, flags);
2178                 io_apic_write(apic_id, 0, reg_00.raw);
2179                 spin_unlock_irqrestore(&ioapic_lock, flags);
2180
2181                 /*
2182                  * Sanity check
2183                  */
2184                 spin_lock_irqsave(&ioapic_lock, flags);
2185                 reg_00.raw = io_apic_read(apic_id, 0);
2186                 spin_unlock_irqrestore(&ioapic_lock, flags);
2187                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2188                         printk("could not set ID!\n");
2189                 else
2190                         apic_printk(APIC_VERBOSE, " ok.\n");
2191         }
2192 }
2193 #endif
2194
2195 int no_timer_check __initdata;
2196
2197 static int __init notimercheck(char *s)
2198 {
2199         no_timer_check = 1;
2200         return 1;
2201 }
2202 __setup("no_timer_check", notimercheck);
2203
2204 /*
2205  * There is a nasty bug in some older SMP boards, their mptable lies
2206  * about the timer IRQ. We do the following to work around the situation:
2207  *
2208  *      - timer IRQ defaults to IO-APIC IRQ
2209  *      - if this function detects that timer IRQs are defunct, then we fall
2210  *        back to ISA timer IRQs
2211  */
2212 static int __init timer_irq_works(void)
2213 {
2214         unsigned long t1 = jiffies;
2215         unsigned long flags;
2216
2217         if (no_timer_check)
2218                 return 1;
2219
2220         local_save_flags(flags);
2221         local_irq_enable();
2222         /* Let ten ticks pass... */
2223         mdelay((10 * 1000) / HZ);
2224         local_irq_restore(flags);
2225
2226         /*
2227          * Expect a few ticks at least, to be sure some possible
2228          * glue logic does not lock up after one or two first
2229          * ticks in a non-ExtINT mode.  Also the local APIC
2230          * might have cached one ExtINT interrupt.  Finally, at
2231          * least one tick may be lost due to delays.
2232          */
2233
2234         /* jiffies wrap? */
2235         if (time_after(jiffies, t1 + 4))
2236                 return 1;
2237         return 0;
2238 }
2239
2240 /*
2241  * In the SMP+IOAPIC case it might happen that there are an unspecified
2242  * number of pending IRQ events unhandled. These cases are very rare,
2243  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2244  * better to do it this way as thus we do not have to be aware of
2245  * 'pending' interrupts in the IRQ path, except at this point.
2246  */
2247 /*
2248  * Edge triggered needs to resend any interrupt
2249  * that was delayed but this is now handled in the device
2250  * independent code.
2251  */
2252
2253 /*
2254  * Starting up a edge-triggered IO-APIC interrupt is
2255  * nasty - we need to make sure that we get the edge.
2256  * If it is already asserted for some reason, we need
2257  * return 1 to indicate that is was pending.
2258  *
2259  * This is not complete - we should be able to fake
2260  * an edge even if it isn't on the 8259A...
2261  */
2262
2263 static unsigned int startup_ioapic_irq(unsigned int irq)
2264 {
2265         int was_pending = 0;
2266         unsigned long flags;
2267         struct irq_cfg *cfg;
2268
2269         spin_lock_irqsave(&ioapic_lock, flags);
2270         if (irq < NR_IRQS_LEGACY) {
2271                 disable_8259A_irq(irq);
2272                 if (i8259A_irq_pending(irq))
2273                         was_pending = 1;
2274         }
2275         cfg = irq_cfg(irq);
2276         __unmask_IO_APIC_irq(cfg);
2277         spin_unlock_irqrestore(&ioapic_lock, flags);
2278
2279         return was_pending;
2280 }
2281
2282 #ifdef CONFIG_X86_64
2283 static int ioapic_retrigger_irq(unsigned int irq)
2284 {
2285
2286         struct irq_cfg *cfg = irq_cfg(irq);
2287         unsigned long flags;
2288
2289         spin_lock_irqsave(&vector_lock, flags);
2290         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2291         spin_unlock_irqrestore(&vector_lock, flags);
2292
2293         return 1;
2294 }
2295 #else
2296 static int ioapic_retrigger_irq(unsigned int irq)
2297 {
2298         apic->send_IPI_self(irq_cfg(irq)->vector);
2299
2300         return 1;
2301 }
2302 #endif
2303
2304 /*
2305  * Level and edge triggered IO-APIC interrupts need different handling,
2306  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2307  * handled with the level-triggered descriptor, but that one has slightly
2308  * more overhead. Level-triggered interrupts cannot be handled with the
2309  * edge-triggered handler, without risking IRQ storms and other ugly
2310  * races.
2311  */
2312
2313 #ifdef CONFIG_SMP
2314
2315 #ifdef CONFIG_INTR_REMAP
2316 static void ir_irq_migration(struct work_struct *work);
2317
2318 static DECLARE_DELAYED_WORK(ir_migration_work, ir_irq_migration);
2319
2320 /*
2321  * Migrate the IO-APIC irq in the presence of intr-remapping.
2322  *
2323  * For edge triggered, irq migration is a simple atomic update(of vector
2324  * and cpu destination) of IRTE and flush the hardware cache.
2325  *
2326  * For level triggered, we need to modify the io-apic RTE aswell with the update
2327  * vector information, along with modifying IRTE with vector and destination.
2328  * So irq migration for level triggered is little  bit more complex compared to
2329  * edge triggered migration. But the good news is, we use the same algorithm
2330  * for level triggered migration as we have today, only difference being,
2331  * we now initiate the irq migration from process context instead of the
2332  * interrupt context.
2333  *
2334  * In future, when we do a directed EOI (combined with cpu EOI broadcast
2335  * suppression) to the IO-APIC, level triggered irq migration will also be
2336  * as simple as edge triggered migration and we can do the irq migration
2337  * with a simple atomic update to IO-APIC RTE.
2338  */
2339 static void
2340 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2341 {
2342         struct irq_cfg *cfg;
2343         struct irte irte;
2344         int modify_ioapic_rte;
2345         unsigned int dest;
2346         unsigned long flags;
2347         unsigned int irq;
2348
2349         if (!cpumask_intersects(mask, cpu_online_mask))
2350                 return;
2351
2352         irq = desc->irq;
2353         if (get_irte(irq, &irte))
2354                 return;
2355
2356         cfg = desc->chip_data;
2357         if (assign_irq_vector(irq, cfg, mask))
2358                 return;
2359
2360         set_extra_move_desc(desc, mask);
2361
2362         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2363
2364         modify_ioapic_rte = desc->status & IRQ_LEVEL;
2365         if (modify_ioapic_rte) {
2366                 spin_lock_irqsave(&ioapic_lock, flags);
2367                 __target_IO_APIC_irq(irq, dest, cfg);
2368                 spin_unlock_irqrestore(&ioapic_lock, flags);
2369         }
2370
2371         irte.vector = cfg->vector;
2372         irte.dest_id = IRTE_DEST(dest);
2373
2374         /*
2375          * Modified the IRTE and flushes the Interrupt entry cache.
2376          */
2377         modify_irte(irq, &irte);
2378
2379         if (cfg->move_in_progress)
2380                 send_cleanup_vector(cfg);
2381
2382         cpumask_copy(desc->affinity, mask);
2383 }
2384
2385 static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
2386 {
2387         int ret = -1;
2388         struct irq_cfg *cfg = desc->chip_data;
2389
2390         mask_IO_APIC_irq_desc(desc);
2391
2392         if (io_apic_level_ack_pending(cfg)) {
2393                 /*
2394                  * Interrupt in progress. Migrating irq now will change the
2395                  * vector information in the IO-APIC RTE and that will confuse
2396                  * the EOI broadcast performed by cpu.
2397                  * So, delay the irq migration to the next instance.
2398                  */
2399                 schedule_delayed_work(&ir_migration_work, 1);
2400                 goto unmask;
2401         }
2402
2403         /* everthing is clear. we have right of way */
2404         migrate_ioapic_irq_desc(desc, desc->pending_mask);
2405
2406         ret = 0;
2407         desc->status &= ~IRQ_MOVE_PENDING;
2408         cpumask_clear(desc->pending_mask);
2409
2410 unmask:
2411         unmask_IO_APIC_irq_desc(desc);
2412
2413         return ret;
2414 }
2415
2416 static void ir_irq_migration(struct work_struct *work)
2417 {
2418         unsigned int irq;
2419         struct irq_desc *desc;
2420
2421         for_each_irq_desc(irq, desc) {
2422                 if (desc->status & IRQ_MOVE_PENDING) {
2423                         unsigned long flags;
2424
2425                         spin_lock_irqsave(&desc->lock, flags);
2426                         if (!desc->chip->set_affinity ||
2427                             !(desc->status & IRQ_MOVE_PENDING)) {
2428                                 desc->status &= ~IRQ_MOVE_PENDING;
2429                                 spin_unlock_irqrestore(&desc->lock, flags);
2430                                 continue;
2431                         }
2432
2433                         desc->chip->set_affinity(irq, desc->pending_mask);
2434                         spin_unlock_irqrestore(&desc->lock, flags);
2435                 }
2436         }
2437 }
2438
2439 /*
2440  * Migrates the IRQ destination in the process context.
2441  */
2442 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2443                                             const struct cpumask *mask)
2444 {
2445         if (desc->status & IRQ_LEVEL) {
2446                 desc->status |= IRQ_MOVE_PENDING;
2447                 cpumask_copy(desc->pending_mask, mask);
2448                 migrate_irq_remapped_level_desc(desc);
2449                 return;
2450         }
2451
2452         migrate_ioapic_irq_desc(desc, mask);
2453 }
2454 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2455                                        const struct cpumask *mask)
2456 {
2457         struct irq_desc *desc = irq_to_desc(irq);
2458
2459         set_ir_ioapic_affinity_irq_desc(desc, mask);
2460 }
2461 #endif
2462
2463 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2464 {
2465         unsigned vector, me;
2466
2467         ack_APIC_irq();
2468         exit_idle();
2469         irq_enter();
2470
2471         me = smp_processor_id();
2472         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2473                 unsigned int irq;
2474                 struct irq_desc *desc;
2475                 struct irq_cfg *cfg;
2476                 irq = __get_cpu_var(vector_irq)[vector];
2477
2478                 if (irq == -1)
2479                         continue;
2480
2481                 desc = irq_to_desc(irq);
2482                 if (!desc)
2483                         continue;
2484
2485                 cfg = irq_cfg(irq);
2486                 spin_lock(&desc->lock);
2487                 if (!cfg->move_cleanup_count)
2488                         goto unlock;
2489
2490                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2491                         goto unlock;
2492
2493                 __get_cpu_var(vector_irq)[vector] = -1;
2494                 cfg->move_cleanup_count--;
2495 unlock:
2496                 spin_unlock(&desc->lock);
2497         }
2498
2499         irq_exit();
2500 }
2501
2502 static void irq_complete_move(struct irq_desc **descp)
2503 {
2504         struct irq_desc *desc = *descp;
2505         struct irq_cfg *cfg = desc->chip_data;
2506         unsigned vector, me;
2507
2508         if (likely(!cfg->move_in_progress)) {
2509 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2510                 if (likely(!cfg->move_desc_pending))
2511                         return;
2512
2513                 /* domain has not changed, but affinity did */
2514                 me = smp_processor_id();
2515                 if (cpumask_test_cpu(me, desc->affinity)) {
2516                         *descp = desc = move_irq_desc(desc, me);
2517                         /* get the new one */
2518                         cfg = desc->chip_data;
2519                         cfg->move_desc_pending = 0;
2520                 }
2521 #endif
2522                 return;
2523         }
2524
2525         vector = ~get_irq_regs()->orig_ax;
2526         me = smp_processor_id();
2527 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2528                 *descp = desc = move_irq_desc(desc, me);
2529                 /* get the new one */
2530                 cfg = desc->chip_data;
2531 #endif
2532
2533         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2534                 send_cleanup_vector(cfg);
2535 }
2536 #else
2537 static inline void irq_complete_move(struct irq_desc **descp) {}
2538 #endif
2539
2540 #ifdef CONFIG_INTR_REMAP
2541 static void ack_x2apic_level(unsigned int irq)
2542 {
2543         ack_x2APIC_irq();
2544 }
2545
2546 static void ack_x2apic_edge(unsigned int irq)
2547 {
2548         ack_x2APIC_irq();
2549 }
2550
2551 #endif
2552
2553 static void ack_apic_edge(unsigned int irq)
2554 {
2555         struct irq_desc *desc = irq_to_desc(irq);
2556
2557         irq_complete_move(&desc);
2558         move_native_irq(irq);
2559         ack_APIC_irq();
2560 }
2561
2562 atomic_t irq_mis_count;
2563
2564 static void ack_apic_level(unsigned int irq)
2565 {
2566         struct irq_desc *desc = irq_to_desc(irq);
2567
2568 #ifdef CONFIG_X86_32
2569         unsigned long v;
2570         int i;
2571 #endif
2572         struct irq_cfg *cfg;
2573         int do_unmask_irq = 0;
2574
2575         irq_complete_move(&desc);
2576 #ifdef CONFIG_GENERIC_PENDING_IRQ
2577         /* If we are moving the irq we need to mask it */
2578         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2579                 do_unmask_irq = 1;
2580                 mask_IO_APIC_irq_desc(desc);
2581         }
2582 #endif
2583
2584 #ifdef CONFIG_X86_32
2585         /*
2586         * It appears there is an erratum which affects at least version 0x11
2587         * of I/O APIC (that's the 82093AA and cores integrated into various
2588         * chipsets).  Under certain conditions a level-triggered interrupt is
2589         * erroneously delivered as edge-triggered one but the respective IRR
2590         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2591         * message but it will never arrive and further interrupts are blocked
2592         * from the source.  The exact reason is so far unknown, but the
2593         * phenomenon was observed when two consecutive interrupt requests
2594         * from a given source get delivered to the same CPU and the source is
2595         * temporarily disabled in between.
2596         *
2597         * A workaround is to simulate an EOI message manually.  We achieve it
2598         * by setting the trigger mode to edge and then to level when the edge
2599         * trigger mode gets detected in the TMR of a local APIC for a
2600         * level-triggered interrupt.  We mask the source for the time of the
2601         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2602         * The idea is from Manfred Spraul.  --macro
2603         */
2604         cfg = desc->chip_data;
2605         i = cfg->vector;
2606
2607         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2608 #endif
2609
2610         /*
2611          * We must acknowledge the irq before we move it or the acknowledge will
2612          * not propagate properly.
2613          */
2614         ack_APIC_irq();
2615
2616         /* Now we can move and renable the irq */
2617         if (unlikely(do_unmask_irq)) {
2618                 /* Only migrate the irq if the ack has been received.
2619                  *
2620                  * On rare occasions the broadcast level triggered ack gets
2621                  * delayed going to ioapics, and if we reprogram the
2622                  * vector while Remote IRR is still set the irq will never
2623                  * fire again.
2624                  *
2625                  * To prevent this scenario we read the Remote IRR bit
2626                  * of the ioapic.  This has two effects.
2627                  * - On any sane system the read of the ioapic will
2628                  *   flush writes (and acks) going to the ioapic from
2629                  *   this cpu.
2630                  * - We get to see if the ACK has actually been delivered.
2631                  *
2632                  * Based on failed experiments of reprogramming the
2633                  * ioapic entry from outside of irq context starting
2634                  * with masking the ioapic entry and then polling until
2635                  * Remote IRR was clear before reprogramming the
2636                  * ioapic I don't trust the Remote IRR bit to be
2637                  * completey accurate.
2638                  *
2639                  * However there appears to be no other way to plug
2640                  * this race, so if the Remote IRR bit is not
2641                  * accurate and is causing problems then it is a hardware bug
2642                  * and you can go talk to the chipset vendor about it.
2643                  */
2644                 cfg = desc->chip_data;
2645                 if (!io_apic_level_ack_pending(cfg))
2646                         move_masked_irq(irq);
2647                 unmask_IO_APIC_irq_desc(desc);
2648         }
2649
2650 #ifdef CONFIG_X86_32
2651         if (!(v & (1 << (i & 0x1f)))) {
2652                 atomic_inc(&irq_mis_count);
2653                 spin_lock(&ioapic_lock);
2654                 __mask_and_edge_IO_APIC_irq(cfg);
2655                 __unmask_and_level_IO_APIC_irq(cfg);
2656                 spin_unlock(&ioapic_lock);
2657         }
2658 #endif
2659 }
2660
2661 static struct irq_chip ioapic_chip __read_mostly = {
2662         .name           = "IO-APIC",
2663         .startup        = startup_ioapic_irq,
2664         .mask           = mask_IO_APIC_irq,
2665         .unmask         = unmask_IO_APIC_irq,
2666         .ack            = ack_apic_edge,
2667         .eoi            = ack_apic_level,
2668 #ifdef CONFIG_SMP
2669         .set_affinity   = set_ioapic_affinity_irq,
2670 #endif
2671         .retrigger      = ioapic_retrigger_irq,
2672 };
2673
2674 #ifdef CONFIG_INTR_REMAP
2675 static struct irq_chip ir_ioapic_chip __read_mostly = {
2676         .name           = "IR-IO-APIC",
2677         .startup        = startup_ioapic_irq,
2678         .mask           = mask_IO_APIC_irq,
2679         .unmask         = unmask_IO_APIC_irq,
2680         .ack            = ack_x2apic_edge,
2681         .eoi            = ack_x2apic_level,
2682 #ifdef CONFIG_SMP
2683         .set_affinity   = set_ir_ioapic_affinity_irq,
2684 #endif
2685         .retrigger      = ioapic_retrigger_irq,
2686 };
2687 #endif
2688
2689 static inline void init_IO_APIC_traps(void)
2690 {
2691         int irq;
2692         struct irq_desc *desc;
2693         struct irq_cfg *cfg;
2694
2695         /*
2696          * NOTE! The local APIC isn't very good at handling
2697          * multiple interrupts at the same interrupt level.
2698          * As the interrupt level is determined by taking the
2699          * vector number and shifting that right by 4, we
2700          * want to spread these out a bit so that they don't
2701          * all fall in the same interrupt level.
2702          *
2703          * Also, we've got to be careful not to trash gate
2704          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2705          */
2706         for_each_irq_desc(irq, desc) {
2707                 cfg = desc->chip_data;
2708                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2709                         /*
2710                          * Hmm.. We don't have an entry for this,
2711                          * so default to an old-fashioned 8259
2712                          * interrupt if we can..
2713                          */
2714                         if (irq < NR_IRQS_LEGACY)
2715                                 make_8259A_irq(irq);
2716                         else
2717                                 /* Strange. Oh, well.. */
2718                                 desc->chip = &no_irq_chip;
2719                 }
2720         }
2721 }
2722
2723 /*
2724  * The local APIC irq-chip implementation:
2725  */
2726
2727 static void mask_lapic_irq(unsigned int irq)
2728 {
2729         unsigned long v;
2730
2731         v = apic_read(APIC_LVT0);
2732         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2733 }
2734
2735 static void unmask_lapic_irq(unsigned int irq)
2736 {
2737         unsigned long v;
2738
2739         v = apic_read(APIC_LVT0);
2740         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2741 }
2742
2743 static void ack_lapic_irq(unsigned int irq)
2744 {
2745         ack_APIC_irq();
2746 }
2747
2748 static struct irq_chip lapic_chip __read_mostly = {
2749         .name           = "local-APIC",
2750         .mask           = mask_lapic_irq,
2751         .unmask         = unmask_lapic_irq,
2752         .ack            = ack_lapic_irq,
2753 };
2754
2755 static void lapic_register_intr(int irq, struct irq_desc *desc)
2756 {
2757         desc->status &= ~IRQ_LEVEL;
2758         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2759                                       "edge");
2760 }
2761
2762 static void __init setup_nmi(void)
2763 {
2764         /*
2765          * Dirty trick to enable the NMI watchdog ...
2766          * We put the 8259A master into AEOI mode and
2767          * unmask on all local APICs LVT0 as NMI.
2768          *
2769          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2770          * is from Maciej W. Rozycki - so we do not have to EOI from
2771          * the NMI handler or the timer interrupt.
2772          */
2773         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2774
2775         enable_NMI_through_LVT0();
2776
2777         apic_printk(APIC_VERBOSE, " done.\n");
2778 }
2779
2780 /*
2781  * This looks a bit hackish but it's about the only one way of sending
2782  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2783  * not support the ExtINT mode, unfortunately.  We need to send these
2784  * cycles as some i82489DX-based boards have glue logic that keeps the
2785  * 8259A interrupt line asserted until INTA.  --macro
2786  */
2787 static inline void __init unlock_ExtINT_logic(void)
2788 {
2789         int apic, pin, i;
2790         struct IO_APIC_route_entry entry0, entry1;
2791         unsigned char save_control, save_freq_select;
2792
2793         pin  = find_isa_irq_pin(8, mp_INT);
2794         if (pin == -1) {
2795                 WARN_ON_ONCE(1);
2796                 return;
2797         }
2798         apic = find_isa_irq_apic(8, mp_INT);
2799         if (apic == -1) {
2800                 WARN_ON_ONCE(1);
2801                 return;
2802         }
2803
2804         entry0 = ioapic_read_entry(apic, pin);
2805         clear_IO_APIC_pin(apic, pin);
2806
2807         memset(&entry1, 0, sizeof(entry1));
2808
2809         entry1.dest_mode = 0;                   /* physical delivery */
2810         entry1.mask = 0;                        /* unmask IRQ now */
2811         entry1.dest = hard_smp_processor_id();
2812         entry1.delivery_mode = dest_ExtINT;
2813         entry1.polarity = entry0.polarity;
2814         entry1.trigger = 0;
2815         entry1.vector = 0;
2816
2817         ioapic_write_entry(apic, pin, entry1);
2818
2819         save_control = CMOS_READ(RTC_CONTROL);
2820         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2821         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2822                    RTC_FREQ_SELECT);
2823         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2824
2825         i = 100;
2826         while (i-- > 0) {
2827                 mdelay(10);
2828                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2829                         i -= 10;
2830         }
2831
2832         CMOS_WRITE(save_control, RTC_CONTROL);
2833         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2834         clear_IO_APIC_pin(apic, pin);
2835
2836         ioapic_write_entry(apic, pin, entry0);
2837 }
2838
2839 static int disable_timer_pin_1 __initdata;
2840 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2841 static int __init disable_timer_pin_setup(char *arg)
2842 {
2843         disable_timer_pin_1 = 1;
2844         return 0;
2845 }
2846 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2847
2848 int timer_through_8259 __initdata;
2849
2850 /*
2851  * This code may look a bit paranoid, but it's supposed to cooperate with
2852  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2853  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2854  * fanatically on his truly buggy board.
2855  *
2856  * FIXME: really need to revamp this for all platforms.
2857  */
2858 static inline void __init check_timer(void)
2859 {
2860         struct irq_desc *desc = irq_to_desc(0);
2861         struct irq_cfg *cfg = desc->chip_data;
2862         int cpu = boot_cpu_id;
2863         int apic1, pin1, apic2, pin2;
2864         unsigned long flags;
2865         unsigned int ver;
2866         int no_pin1 = 0;
2867
2868         local_irq_save(flags);
2869
2870         ver = apic_read(APIC_LVR);
2871         ver = GET_APIC_VERSION(ver);
2872
2873         /*
2874          * get/set the timer IRQ vector:
2875          */
2876         disable_8259A_irq(0);
2877         assign_irq_vector(0, cfg, apic->target_cpus());
2878
2879         /*
2880          * As IRQ0 is to be enabled in the 8259A, the virtual
2881          * wire has to be disabled in the local APIC.  Also
2882          * timer interrupts need to be acknowledged manually in
2883          * the 8259A for the i82489DX when using the NMI
2884          * watchdog as that APIC treats NMIs as level-triggered.
2885          * The AEOI mode will finish them in the 8259A
2886          * automatically.
2887          */
2888         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2889         init_8259A(1);
2890 #ifdef CONFIG_X86_32
2891         timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2892 #endif
2893
2894         pin1  = find_isa_irq_pin(0, mp_INT);
2895         apic1 = find_isa_irq_apic(0, mp_INT);
2896         pin2  = ioapic_i8259.pin;
2897         apic2 = ioapic_i8259.apic;
2898
2899         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2900                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2901                     cfg->vector, apic1, pin1, apic2, pin2);
2902
2903         /*
2904          * Some BIOS writers are clueless and report the ExtINTA
2905          * I/O APIC input from the cascaded 8259A as the timer
2906          * interrupt input.  So just in case, if only one pin
2907          * was found above, try it both directly and through the
2908          * 8259A.
2909          */
2910         if (pin1 == -1) {
2911 #ifdef CONFIG_INTR_REMAP
2912                 if (intr_remapping_enabled)
2913                         panic("BIOS bug: timer not connected to IO-APIC");
2914 #endif
2915                 pin1 = pin2;
2916                 apic1 = apic2;
2917                 no_pin1 = 1;
2918         } else if (pin2 == -1) {
2919                 pin2 = pin1;
2920                 apic2 = apic1;
2921         }
2922
2923         if (pin1 != -1) {
2924                 /*
2925                  * Ok, does IRQ0 through the IOAPIC work?
2926                  */
2927                 if (no_pin1) {
2928                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2929                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2930                 }
2931                 unmask_IO_APIC_irq_desc(desc);
2932                 if (timer_irq_works()) {
2933                         if (nmi_watchdog == NMI_IO_APIC) {
2934                                 setup_nmi();
2935                                 enable_8259A_irq(0);
2936                         }
2937                         if (disable_timer_pin_1 > 0)
2938                                 clear_IO_APIC_pin(0, pin1);
2939                         goto out;
2940                 }
2941 #ifdef CONFIG_INTR_REMAP
2942                 if (intr_remapping_enabled)
2943                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2944 #endif
2945                 clear_IO_APIC_pin(apic1, pin1);
2946                 if (!no_pin1)
2947                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2948                                     "8254 timer not connected to IO-APIC\n");
2949
2950                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2951                             "(IRQ0) through the 8259A ...\n");
2952                 apic_printk(APIC_QUIET, KERN_INFO
2953                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2954                 /*
2955                  * legacy devices should be connected to IO APIC #0
2956                  */
2957                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2958                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2959                 unmask_IO_APIC_irq_desc(desc);
2960                 enable_8259A_irq(0);
2961                 if (timer_irq_works()) {
2962                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2963                         timer_through_8259 = 1;
2964                         if (nmi_watchdog == NMI_IO_APIC) {
2965                                 disable_8259A_irq(0);
2966                                 setup_nmi();
2967                                 enable_8259A_irq(0);
2968                         }
2969                         goto out;
2970                 }
2971                 /*
2972                  * Cleanup, just in case ...
2973                  */
2974                 disable_8259A_irq(0);
2975                 clear_IO_APIC_pin(apic2, pin2);
2976                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2977         }
2978
2979         if (nmi_watchdog == NMI_IO_APIC) {
2980                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2981                             "through the IO-APIC - disabling NMI Watchdog!\n");
2982                 nmi_watchdog = NMI_NONE;
2983         }
2984 #ifdef CONFIG_X86_32
2985         timer_ack = 0;
2986 #endif
2987
2988         apic_printk(APIC_QUIET, KERN_INFO
2989                     "...trying to set up timer as Virtual Wire IRQ...\n");
2990
2991         lapic_register_intr(0, desc);
2992         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2993         enable_8259A_irq(0);
2994
2995         if (timer_irq_works()) {
2996                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2997                 goto out;
2998         }
2999         disable_8259A_irq(0);
3000         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3001         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3002
3003         apic_printk(APIC_QUIET, KERN_INFO
3004                     "...trying to set up timer as ExtINT IRQ...\n");
3005
3006         init_8259A(0);
3007         make_8259A_irq(0);
3008         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3009
3010         unlock_ExtINT_logic();
3011
3012         if (timer_irq_works()) {
3013                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3014                 goto out;
3015         }
3016         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3017         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3018                 "report.  Then try booting with the 'noapic' option.\n");
3019 out:
3020         local_irq_restore(flags);
3021 }
3022
3023 /*
3024  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3025  * to devices.  However there may be an I/O APIC pin available for
3026  * this interrupt regardless.  The pin may be left unconnected, but
3027  * typically it will be reused as an ExtINT cascade interrupt for
3028  * the master 8259A.  In the MPS case such a pin will normally be
3029  * reported as an ExtINT interrupt in the MP table.  With ACPI
3030  * there is no provision for ExtINT interrupts, and in the absence
3031  * of an override it would be treated as an ordinary ISA I/O APIC
3032  * interrupt, that is edge-triggered and unmasked by default.  We
3033  * used to do this, but it caused problems on some systems because
3034  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3035  * the same ExtINT cascade interrupt to drive the local APIC of the
3036  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3037  * the I/O APIC in all cases now.  No actual device should request
3038  * it anyway.  --macro
3039  */
3040 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3041
3042 void __init setup_IO_APIC(void)
3043 {
3044
3045 #ifdef CONFIG_X86_32
3046         enable_IO_APIC();
3047 #else
3048         /*
3049          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3050          */
3051 #endif
3052
3053         io_apic_irqs = ~PIC_IRQS;
3054
3055         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3056         /*
3057          * Set up IO-APIC IRQ routing.
3058          */
3059 #ifdef CONFIG_X86_32
3060         if (!acpi_ioapic)
3061                 setup_ioapic_ids_from_mpc();
3062 #endif
3063         sync_Arb_IDs();
3064         setup_IO_APIC_irqs();
3065         init_IO_APIC_traps();
3066         check_timer();
3067 }
3068
3069 /*
3070  *      Called after all the initialization is done. If we didnt find any
3071  *      APIC bugs then we can allow the modify fast path
3072  */
3073
3074 static int __init io_apic_bug_finalize(void)
3075 {
3076         if (sis_apic_bug == -1)
3077                 sis_apic_bug = 0;
3078         return 0;
3079 }
3080
3081 late_initcall(io_apic_bug_finalize);
3082
3083 struct sysfs_ioapic_data {
3084         struct sys_device dev;
3085         struct IO_APIC_route_entry entry[0];
3086 };
3087 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3088
3089 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3090 {
3091         struct IO_APIC_route_entry *entry;
3092         struct sysfs_ioapic_data *data;
3093         int i;
3094
3095         data = container_of(dev, struct sysfs_ioapic_data, dev);
3096         entry = data->entry;
3097         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3098                 *entry = ioapic_read_entry(dev->id, i);
3099
3100         return 0;
3101 }
3102
3103 static int ioapic_resume(struct sys_device *dev)
3104 {
3105         struct IO_APIC_route_entry *entry;
3106         struct sysfs_ioapic_data *data;
3107         unsigned long flags;
3108         union IO_APIC_reg_00 reg_00;
3109         int i;
3110
3111         data = container_of(dev, struct sysfs_ioapic_data, dev);
3112         entry = data->entry;
3113
3114         spin_lock_irqsave(&ioapic_lock, flags);
3115         reg_00.raw = io_apic_read(dev->id, 0);
3116         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3117                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3118                 io_apic_write(dev->id, 0, reg_00.raw);
3119         }
3120         spin_unlock_irqrestore(&ioapic_lock, flags);
3121         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3122                 ioapic_write_entry(dev->id, i, entry[i]);
3123
3124         return 0;
3125 }
3126
3127 static struct sysdev_class ioapic_sysdev_class = {
3128         .name = "ioapic",
3129         .suspend = ioapic_suspend,
3130         .resume = ioapic_resume,
3131 };
3132
3133 static int __init ioapic_init_sysfs(void)
3134 {
3135         struct sys_device * dev;
3136         int i, size, error;
3137
3138         error = sysdev_class_register(&ioapic_sysdev_class);
3139         if (error)
3140                 return error;
3141
3142         for (i = 0; i < nr_ioapics; i++ ) {
3143                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3144                         * sizeof(struct IO_APIC_route_entry);
3145                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3146                 if (!mp_ioapic_data[i]) {
3147                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3148                         continue;
3149                 }
3150                 dev = &mp_ioapic_data[i]->dev;
3151                 dev->id = i;
3152                 dev->cls = &ioapic_sysdev_class;
3153                 error = sysdev_register(dev);
3154                 if (error) {
3155                         kfree(mp_ioapic_data[i]);
3156                         mp_ioapic_data[i] = NULL;
3157                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3158                         continue;
3159                 }
3160         }
3161
3162         return 0;
3163 }
3164
3165 device_initcall(ioapic_init_sysfs);
3166
3167 /*
3168  * Dynamic irq allocate and deallocation
3169  */
3170 unsigned int create_irq_nr(unsigned int irq_want)
3171 {
3172         /* Allocate an unused irq */
3173         unsigned int irq;
3174         unsigned int new;
3175         unsigned long flags;
3176         struct irq_cfg *cfg_new = NULL;
3177         int cpu = boot_cpu_id;
3178         struct irq_desc *desc_new = NULL;
3179
3180         irq = 0;
3181         spin_lock_irqsave(&vector_lock, flags);
3182         for (new = irq_want; new < nr_irqs; new++) {
3183                 if (platform_legacy_irq(new))
3184                         continue;
3185
3186                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3187                 if (!desc_new) {
3188                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3189                         continue;
3190                 }
3191                 cfg_new = desc_new->chip_data;
3192
3193                 if (cfg_new->vector != 0)
3194                         continue;
3195                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3196                         irq = new;
3197                 break;
3198         }
3199         spin_unlock_irqrestore(&vector_lock, flags);
3200
3201         if (irq > 0) {
3202                 dynamic_irq_init(irq);
3203                 /* restore it, in case dynamic_irq_init clear it */
3204                 if (desc_new)
3205                         desc_new->chip_data = cfg_new;
3206         }
3207         return irq;
3208 }
3209
3210 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3211 int create_irq(void)
3212 {
3213         unsigned int irq_want;
3214         int irq;
3215
3216         irq_want = nr_irqs_gsi;
3217         irq = create_irq_nr(irq_want);
3218
3219         if (irq == 0)
3220                 irq = -1;
3221
3222         return irq;
3223 }
3224
3225 void destroy_irq(unsigned int irq)
3226 {
3227         unsigned long flags;
3228         struct irq_cfg *cfg;
3229         struct irq_desc *desc;
3230
3231         /* store it, in case dynamic_irq_cleanup clear it */
3232         desc = irq_to_desc(irq);
3233         cfg = desc->chip_data;
3234         dynamic_irq_cleanup(irq);
3235         /* connect back irq_cfg */
3236         if (desc)
3237                 desc->chip_data = cfg;
3238
3239 #ifdef CONFIG_INTR_REMAP
3240         free_irte(irq);
3241 #endif
3242         spin_lock_irqsave(&vector_lock, flags);
3243         __clear_irq_vector(irq, cfg);
3244         spin_unlock_irqrestore(&vector_lock, flags);
3245 }
3246
3247 /*
3248  * MSI message composition
3249  */
3250 #ifdef CONFIG_PCI_MSI
3251 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3252 {
3253         struct irq_cfg *cfg;
3254         int err;
3255         unsigned dest;
3256
3257         if (disable_apic)
3258                 return -ENXIO;
3259
3260         cfg = irq_cfg(irq);
3261         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3262         if (err)
3263                 return err;
3264
3265         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3266
3267 #ifdef CONFIG_INTR_REMAP
3268         if (irq_remapped(irq)) {
3269                 struct irte irte;
3270                 int ir_index;
3271                 u16 sub_handle;
3272
3273                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3274                 BUG_ON(ir_index == -1);
3275
3276                 memset (&irte, 0, sizeof(irte));
3277
3278                 irte.present = 1;
3279                 irte.dst_mode = apic->irq_dest_mode;
3280                 irte.trigger_mode = 0; /* edge */
3281                 irte.dlvry_mode = apic->irq_delivery_mode;
3282                 irte.vector = cfg->vector;
3283                 irte.dest_id = IRTE_DEST(dest);
3284
3285                 modify_irte(irq, &irte);
3286
3287                 msg->address_hi = MSI_ADDR_BASE_HI;
3288                 msg->data = sub_handle;
3289                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3290                                   MSI_ADDR_IR_SHV |
3291                                   MSI_ADDR_IR_INDEX1(ir_index) |
3292                                   MSI_ADDR_IR_INDEX2(ir_index);
3293         } else
3294 #endif
3295         {
3296                 msg->address_hi = MSI_ADDR_BASE_HI;
3297                 msg->address_lo =
3298                         MSI_ADDR_BASE_LO |
3299                         ((apic->irq_dest_mode == 0) ?
3300                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3301                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3302                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3303                                 MSI_ADDR_REDIRECTION_CPU:
3304                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3305                         MSI_ADDR_DEST_ID(dest);
3306
3307                 msg->data =
3308                         MSI_DATA_TRIGGER_EDGE |
3309                         MSI_DATA_LEVEL_ASSERT |
3310                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3311                                 MSI_DATA_DELIVERY_FIXED:
3312                                 MSI_DATA_DELIVERY_LOWPRI) |
3313                         MSI_DATA_VECTOR(cfg->vector);
3314         }
3315         return err;
3316 }
3317
3318 #ifdef CONFIG_SMP
3319 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3320 {
3321         struct irq_desc *desc = irq_to_desc(irq);
3322         struct irq_cfg *cfg;
3323         struct msi_msg msg;
3324         unsigned int dest;
3325
3326         dest = set_desc_affinity(desc, mask);
3327         if (dest == BAD_APICID)
3328                 return;
3329
3330         cfg = desc->chip_data;
3331
3332         read_msi_msg_desc(desc, &msg);
3333
3334         msg.data &= ~MSI_DATA_VECTOR_MASK;
3335         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3336         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3337         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3338
3339         write_msi_msg_desc(desc, &msg);
3340 }
3341 #ifdef CONFIG_INTR_REMAP
3342 /*
3343  * Migrate the MSI irq to another cpumask. This migration is
3344  * done in the process context using interrupt-remapping hardware.
3345  */
3346 static void
3347 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3348 {
3349         struct irq_desc *desc = irq_to_desc(irq);
3350         struct irq_cfg *cfg = desc->chip_data;
3351         unsigned int dest;
3352         struct irte irte;
3353
3354         if (get_irte(irq, &irte))
3355                 return;
3356
3357         dest = set_desc_affinity(desc, mask);
3358         if (dest == BAD_APICID)
3359                 return;
3360
3361         irte.vector = cfg->vector;
3362         irte.dest_id = IRTE_DEST(dest);
3363
3364         /*
3365          * atomically update the IRTE with the new destination and vector.
3366          */
3367         modify_irte(irq, &irte);
3368
3369         /*
3370          * After this point, all the interrupts will start arriving
3371          * at the new destination. So, time to cleanup the previous
3372          * vector allocation.
3373          */
3374         if (cfg->move_in_progress)
3375                 send_cleanup_vector(cfg);
3376 }
3377
3378 #endif
3379 #endif /* CONFIG_SMP */
3380
3381 /*
3382  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3383  * which implement the MSI or MSI-X Capability Structure.
3384  */
3385 static struct irq_chip msi_chip = {
3386         .name           = "PCI-MSI",
3387         .unmask         = unmask_msi_irq,
3388         .mask           = mask_msi_irq,
3389         .ack            = ack_apic_edge,
3390 #ifdef CONFIG_SMP
3391         .set_affinity   = set_msi_irq_affinity,
3392 #endif
3393         .retrigger      = ioapic_retrigger_irq,
3394 };
3395
3396 #ifdef CONFIG_INTR_REMAP
3397 static struct irq_chip msi_ir_chip = {
3398         .name           = "IR-PCI-MSI",
3399         .unmask         = unmask_msi_irq,
3400         .mask           = mask_msi_irq,
3401         .ack            = ack_x2apic_edge,
3402 #ifdef CONFIG_SMP
3403         .set_affinity   = ir_set_msi_irq_affinity,
3404 #endif
3405         .retrigger      = ioapic_retrigger_irq,
3406 };
3407
3408 /*
3409  * Map the PCI dev to the corresponding remapping hardware unit
3410  * and allocate 'nvec' consecutive interrupt-remapping table entries
3411  * in it.
3412  */
3413 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3414 {
3415         struct intel_iommu *iommu;
3416         int index;
3417
3418         iommu = map_dev_to_ir(dev);
3419         if (!iommu) {
3420                 printk(KERN_ERR
3421                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3422                 return -ENOENT;
3423         }
3424
3425         index = alloc_irte(iommu, irq, nvec);
3426         if (index < 0) {
3427                 printk(KERN_ERR
3428                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3429                        pci_name(dev));
3430                 return -ENOSPC;
3431         }
3432         return index;
3433 }
3434 #endif
3435
3436 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3437 {
3438         int ret;
3439         struct msi_msg msg;
3440
3441         ret = msi_compose_msg(dev, irq, &msg);
3442         if (ret < 0)
3443                 return ret;
3444
3445         set_irq_msi(irq, msidesc);
3446         write_msi_msg(irq, &msg);
3447
3448 #ifdef CONFIG_INTR_REMAP
3449         if (irq_remapped(irq)) {
3450                 struct irq_desc *desc = irq_to_desc(irq);
3451                 /*
3452                  * irq migration in process context
3453                  */
3454                 desc->status |= IRQ_MOVE_PCNTXT;
3455                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3456         } else
3457 #endif
3458                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3459
3460         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3461
3462         return 0;
3463 }
3464
3465 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3466 {
3467         unsigned int irq;
3468         int ret, sub_handle;
3469         struct msi_desc *msidesc;
3470         unsigned int irq_want;
3471
3472 #ifdef CONFIG_INTR_REMAP
3473         struct intel_iommu *iommu = 0;
3474         int index = 0;
3475 #endif
3476
3477         irq_want = nr_irqs_gsi;
3478         sub_handle = 0;
3479         list_for_each_entry(msidesc, &dev->msi_list, list) {
3480                 irq = create_irq_nr(irq_want);
3481                 irq_want++;
3482                 if (irq == 0)
3483                         return -1;
3484 #ifdef CONFIG_INTR_REMAP
3485                 if (!intr_remapping_enabled)
3486                         goto no_ir;
3487
3488                 if (!sub_handle) {
3489                         /*
3490                          * allocate the consecutive block of IRTE's
3491                          * for 'nvec'
3492                          */
3493                         index = msi_alloc_irte(dev, irq, nvec);
3494                         if (index < 0) {
3495                                 ret = index;
3496                                 goto error;
3497                         }
3498                 } else {
3499                         iommu = map_dev_to_ir(dev);
3500                         if (!iommu) {
3501                                 ret = -ENOENT;
3502                                 goto error;
3503                         }
3504                         /*
3505                          * setup the mapping between the irq and the IRTE
3506                          * base index, the sub_handle pointing to the
3507                          * appropriate interrupt remap table entry.
3508                          */
3509                         set_irte_irq(irq, iommu, index, sub_handle);
3510                 }
3511 no_ir:
3512 #endif
3513                 ret = setup_msi_irq(dev, msidesc, irq);
3514                 if (ret < 0)
3515                         goto error;
3516                 sub_handle++;
3517         }
3518         return 0;
3519
3520 error:
3521         destroy_irq(irq);
3522         return ret;
3523 }
3524
3525 void arch_teardown_msi_irq(unsigned int irq)
3526 {
3527         destroy_irq(irq);
3528 }
3529
3530 #ifdef CONFIG_DMAR
3531 #ifdef CONFIG_SMP
3532 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3533 {
3534         struct irq_desc *desc = irq_to_desc(irq);
3535         struct irq_cfg *cfg;
3536         struct msi_msg msg;
3537         unsigned int dest;
3538
3539         dest = set_desc_affinity(desc, mask);
3540         if (dest == BAD_APICID)
3541                 return;
3542
3543         cfg = desc->chip_data;
3544
3545         dmar_msi_read(irq, &msg);
3546
3547         msg.data &= ~MSI_DATA_VECTOR_MASK;
3548         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3549         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3550         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3551
3552         dmar_msi_write(irq, &msg);
3553 }
3554
3555 #endif /* CONFIG_SMP */
3556
3557 struct irq_chip dmar_msi_type = {
3558         .name = "DMAR_MSI",
3559         .unmask = dmar_msi_unmask,
3560         .mask = dmar_msi_mask,
3561         .ack = ack_apic_edge,
3562 #ifdef CONFIG_SMP
3563         .set_affinity = dmar_msi_set_affinity,
3564 #endif
3565         .retrigger = ioapic_retrigger_irq,
3566 };
3567
3568 int arch_setup_dmar_msi(unsigned int irq)
3569 {
3570         int ret;
3571         struct msi_msg msg;
3572
3573         ret = msi_compose_msg(NULL, irq, &msg);
3574         if (ret < 0)
3575                 return ret;
3576         dmar_msi_write(irq, &msg);
3577         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3578                 "edge");
3579         return 0;
3580 }
3581 #endif
3582
3583 #ifdef CONFIG_HPET_TIMER
3584
3585 #ifdef CONFIG_SMP
3586 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3587 {
3588         struct irq_desc *desc = irq_to_desc(irq);
3589         struct irq_cfg *cfg;
3590         struct msi_msg msg;
3591         unsigned int dest;
3592
3593         dest = set_desc_affinity(desc, mask);
3594         if (dest == BAD_APICID)
3595                 return;
3596
3597         cfg = desc->chip_data;
3598
3599         hpet_msi_read(irq, &msg);
3600
3601         msg.data &= ~MSI_DATA_VECTOR_MASK;
3602         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3603         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3604         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3605
3606         hpet_msi_write(irq, &msg);
3607 }
3608
3609 #endif /* CONFIG_SMP */
3610
3611 struct irq_chip hpet_msi_type = {
3612         .name = "HPET_MSI",
3613         .unmask = hpet_msi_unmask,
3614         .mask = hpet_msi_mask,
3615         .ack = ack_apic_edge,
3616 #ifdef CONFIG_SMP
3617         .set_affinity = hpet_msi_set_affinity,
3618 #endif
3619         .retrigger = ioapic_retrigger_irq,
3620 };
3621
3622 int arch_setup_hpet_msi(unsigned int irq)
3623 {
3624         int ret;
3625         struct msi_msg msg;
3626
3627         ret = msi_compose_msg(NULL, irq, &msg);
3628         if (ret < 0)
3629                 return ret;
3630
3631         hpet_msi_write(irq, &msg);
3632         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3633                 "edge");
3634
3635         return 0;
3636 }
3637 #endif
3638
3639 #endif /* CONFIG_PCI_MSI */
3640 /*
3641  * Hypertransport interrupt support
3642  */
3643 #ifdef CONFIG_HT_IRQ
3644
3645 #ifdef CONFIG_SMP
3646
3647 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3648 {
3649         struct ht_irq_msg msg;
3650         fetch_ht_irq_msg(irq, &msg);
3651
3652         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3653         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3654
3655         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3656         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3657
3658         write_ht_irq_msg(irq, &msg);
3659 }
3660
3661 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3662 {
3663         struct irq_desc *desc = irq_to_desc(irq);
3664         struct irq_cfg *cfg;
3665         unsigned int dest;
3666
3667         dest = set_desc_affinity(desc, mask);
3668         if (dest == BAD_APICID)
3669                 return;
3670
3671         cfg = desc->chip_data;
3672
3673         target_ht_irq(irq, dest, cfg->vector);
3674 }
3675
3676 #endif
3677
3678 static struct irq_chip ht_irq_chip = {
3679         .name           = "PCI-HT",
3680         .mask           = mask_ht_irq,
3681         .unmask         = unmask_ht_irq,
3682         .ack            = ack_apic_edge,
3683 #ifdef CONFIG_SMP
3684         .set_affinity   = set_ht_irq_affinity,
3685 #endif
3686         .retrigger      = ioapic_retrigger_irq,
3687 };
3688
3689 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3690 {
3691         struct irq_cfg *cfg;
3692         int err;
3693
3694         if (disable_apic)
3695                 return -ENXIO;
3696
3697         cfg = irq_cfg(irq);
3698         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3699         if (!err) {
3700                 struct ht_irq_msg msg;
3701                 unsigned dest;
3702
3703                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3704                                                     apic->target_cpus());
3705
3706                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3707
3708                 msg.address_lo =
3709                         HT_IRQ_LOW_BASE |
3710                         HT_IRQ_LOW_DEST_ID(dest) |
3711                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3712                         ((apic->irq_dest_mode == 0) ?
3713                                 HT_IRQ_LOW_DM_PHYSICAL :
3714                                 HT_IRQ_LOW_DM_LOGICAL) |
3715                         HT_IRQ_LOW_RQEOI_EDGE |
3716                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3717                                 HT_IRQ_LOW_MT_FIXED :
3718                                 HT_IRQ_LOW_MT_ARBITRATED) |
3719                         HT_IRQ_LOW_IRQ_MASKED;
3720
3721                 write_ht_irq_msg(irq, &msg);
3722
3723                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3724                                               handle_edge_irq, "edge");
3725
3726                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3727         }
3728         return err;
3729 }
3730 #endif /* CONFIG_HT_IRQ */
3731
3732 #ifdef CONFIG_X86_UV
3733 /*
3734  * Re-target the irq to the specified CPU and enable the specified MMR located
3735  * on the specified blade to allow the sending of MSIs to the specified CPU.
3736  */
3737 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3738                        unsigned long mmr_offset)
3739 {
3740         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3741         struct irq_cfg *cfg;
3742         int mmr_pnode;
3743         unsigned long mmr_value;
3744         struct uv_IO_APIC_route_entry *entry;
3745         unsigned long flags;
3746         int err;
3747
3748         cfg = irq_cfg(irq);
3749
3750         err = assign_irq_vector(irq, cfg, eligible_cpu);
3751         if (err != 0)
3752                 return err;
3753
3754         spin_lock_irqsave(&vector_lock, flags);
3755         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3756                                       irq_name);
3757         spin_unlock_irqrestore(&vector_lock, flags);
3758
3759         mmr_value = 0;
3760         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3761         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3762
3763         entry->vector = cfg->vector;
3764         entry->delivery_mode = apic->irq_delivery_mode;
3765         entry->dest_mode = apic->irq_dest_mode;
3766         entry->polarity = 0;
3767         entry->trigger = 0;
3768         entry->mask = 0;
3769         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3770
3771         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3772         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3773
3774         return irq;
3775 }
3776
3777 /*
3778  * Disable the specified MMR located on the specified blade so that MSIs are
3779  * longer allowed to be sent.
3780  */
3781 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3782 {
3783         unsigned long mmr_value;
3784         struct uv_IO_APIC_route_entry *entry;
3785         int mmr_pnode;
3786
3787         mmr_value = 0;
3788         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3789         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3790
3791         entry->mask = 1;
3792
3793         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3794         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3795 }
3796 #endif /* CONFIG_X86_64 */
3797
3798 int __init io_apic_get_redir_entries (int ioapic)
3799 {
3800         union IO_APIC_reg_01    reg_01;
3801         unsigned long flags;
3802
3803         spin_lock_irqsave(&ioapic_lock, flags);
3804         reg_01.raw = io_apic_read(ioapic, 1);
3805         spin_unlock_irqrestore(&ioapic_lock, flags);
3806
3807         return reg_01.bits.entries;
3808 }
3809
3810 void __init probe_nr_irqs_gsi(void)
3811 {
3812         int idx;
3813         int nr = 0;
3814
3815         for (idx = 0; idx < nr_ioapics; idx++)
3816                 nr += io_apic_get_redir_entries(idx) + 1;
3817
3818         if (nr > nr_irqs_gsi)
3819                 nr_irqs_gsi = nr;
3820 }
3821
3822 #ifdef CONFIG_SPARSE_IRQ
3823 int __init arch_probe_nr_irqs(void)
3824 {
3825         int nr;
3826
3827         nr = ((8 * nr_cpu_ids) > (32 * nr_ioapics) ?
3828                 (NR_VECTORS + (8 * nr_cpu_ids)) :
3829                 (NR_VECTORS + (32 * nr_ioapics)));
3830
3831         if (nr < nr_irqs && nr > nr_irqs_gsi)
3832                 nr_irqs = nr;
3833
3834         return 0;
3835 }
3836 #endif
3837
3838 /* --------------------------------------------------------------------------
3839                           ACPI-based IOAPIC Configuration
3840    -------------------------------------------------------------------------- */
3841
3842 #ifdef CONFIG_ACPI
3843
3844 #ifdef CONFIG_X86_32
3845 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3846 {
3847         union IO_APIC_reg_00 reg_00;
3848         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3849         physid_mask_t tmp;
3850         unsigned long flags;
3851         int i = 0;
3852
3853         /*
3854          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3855          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3856          * supports up to 16 on one shared APIC bus.
3857          *
3858          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3859          *      advantage of new APIC bus architecture.
3860          */
3861
3862         if (physids_empty(apic_id_map))
3863                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3864
3865         spin_lock_irqsave(&ioapic_lock, flags);
3866         reg_00.raw = io_apic_read(ioapic, 0);
3867         spin_unlock_irqrestore(&ioapic_lock, flags);
3868
3869         if (apic_id >= get_physical_broadcast()) {
3870                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3871                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3872                 apic_id = reg_00.bits.ID;
3873         }
3874
3875         /*
3876          * Every APIC in a system must have a unique ID or we get lots of nice
3877          * 'stuck on smp_invalidate_needed IPI wait' messages.
3878          */
3879         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3880
3881                 for (i = 0; i < get_physical_broadcast(); i++) {
3882                         if (!apic->check_apicid_used(apic_id_map, i))
3883                                 break;
3884                 }
3885
3886                 if (i == get_physical_broadcast())
3887                         panic("Max apic_id exceeded!\n");
3888
3889                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3890                         "trying %d\n", ioapic, apic_id, i);
3891
3892                 apic_id = i;
3893         }
3894
3895         tmp = apic->apicid_to_cpu_present(apic_id);
3896         physids_or(apic_id_map, apic_id_map, tmp);
3897
3898         if (reg_00.bits.ID != apic_id) {
3899                 reg_00.bits.ID = apic_id;
3900
3901                 spin_lock_irqsave(&ioapic_lock, flags);
3902                 io_apic_write(ioapic, 0, reg_00.raw);
3903                 reg_00.raw = io_apic_read(ioapic, 0);
3904                 spin_unlock_irqrestore(&ioapic_lock, flags);
3905
3906                 /* Sanity check */
3907                 if (reg_00.bits.ID != apic_id) {
3908                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3909                         return -1;
3910                 }
3911         }
3912
3913         apic_printk(APIC_VERBOSE, KERN_INFO
3914                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3915
3916         return apic_id;
3917 }
3918
3919 int __init io_apic_get_version(int ioapic)
3920 {
3921         union IO_APIC_reg_01    reg_01;
3922         unsigned long flags;
3923
3924         spin_lock_irqsave(&ioapic_lock, flags);
3925         reg_01.raw = io_apic_read(ioapic, 1);
3926         spin_unlock_irqrestore(&ioapic_lock, flags);
3927
3928         return reg_01.bits.version;
3929 }
3930 #endif
3931
3932 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3933 {
3934         struct irq_desc *desc;
3935         struct irq_cfg *cfg;
3936         int cpu = boot_cpu_id;
3937
3938         if (!IO_APIC_IRQ(irq)) {
3939                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3940                         ioapic);
3941                 return -EINVAL;
3942         }
3943
3944         desc = irq_to_desc_alloc_cpu(irq, cpu);
3945         if (!desc) {
3946                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3947                 return 0;
3948         }
3949
3950         /*
3951          * IRQs < 16 are already in the irq_2_pin[] map
3952          */
3953         if (irq >= NR_IRQS_LEGACY) {
3954                 cfg = desc->chip_data;
3955                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3956         }
3957
3958         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3959
3960         return 0;
3961 }
3962
3963
3964 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3965 {
3966         int i;
3967
3968         if (skip_ioapic_setup)
3969                 return -1;
3970
3971         for (i = 0; i < mp_irq_entries; i++)
3972                 if (mp_irqs[i].irqtype == mp_INT &&
3973                     mp_irqs[i].srcbusirq == bus_irq)
3974                         break;
3975         if (i >= mp_irq_entries)
3976                 return -1;
3977
3978         *trigger = irq_trigger(i);
3979         *polarity = irq_polarity(i);
3980         return 0;
3981 }
3982
3983 #endif /* CONFIG_ACPI */
3984
3985 /*
3986  * This function currently is only a helper for the i386 smp boot process where
3987  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3988  * so mask in all cases should simply be apic->target_cpus()
3989  */
3990 #ifdef CONFIG_SMP
3991 void __init setup_ioapic_dest(void)
3992 {
3993         int pin, ioapic, irq, irq_entry;
3994         struct irq_desc *desc;
3995         struct irq_cfg *cfg;
3996         const struct cpumask *mask;
3997
3998         if (skip_ioapic_setup == 1)
3999                 return;
4000
4001         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4002                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4003                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4004                         if (irq_entry == -1)
4005                                 continue;
4006                         irq = pin_2_irq(irq_entry, ioapic, pin);
4007
4008                         /* setup_IO_APIC_irqs could fail to get vector for some device
4009                          * when you have too many devices, because at that time only boot
4010                          * cpu is online.
4011                          */
4012                         desc = irq_to_desc(irq);
4013                         cfg = desc->chip_data;
4014                         if (!cfg->vector) {
4015                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4016                                                   irq_trigger(irq_entry),
4017                                                   irq_polarity(irq_entry));
4018                                 continue;
4019
4020                         }
4021
4022                         /*
4023                          * Honour affinities which have been set in early boot
4024                          */
4025                         if (desc->status &
4026                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4027                                 mask = desc->affinity;
4028                         else
4029                                 mask = apic->target_cpus();
4030
4031 #ifdef CONFIG_INTR_REMAP
4032                         if (intr_remapping_enabled)
4033                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4034                         else
4035 #endif
4036                                 set_ioapic_affinity_irq_desc(desc, mask);
4037                 }
4038
4039         }
4040 }
4041 #endif
4042
4043 #define IOAPIC_RESOURCE_NAME_SIZE 11
4044
4045 static struct resource *ioapic_resources;
4046
4047 static struct resource * __init ioapic_setup_resources(void)
4048 {
4049         unsigned long n;
4050         struct resource *res;
4051         char *mem;
4052         int i;
4053
4054         if (nr_ioapics <= 0)
4055                 return NULL;
4056
4057         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4058         n *= nr_ioapics;
4059
4060         mem = alloc_bootmem(n);
4061         res = (void *)mem;
4062
4063         if (mem != NULL) {
4064                 mem += sizeof(struct resource) * nr_ioapics;
4065
4066                 for (i = 0; i < nr_ioapics; i++) {
4067                         res[i].name = mem;
4068                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4069                         sprintf(mem,  "IOAPIC %u", i);
4070                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4071                 }
4072         }
4073
4074         ioapic_resources = res;
4075
4076         return res;
4077 }
4078
4079 void __init ioapic_init_mappings(void)
4080 {
4081         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4082         struct resource *ioapic_res;
4083         int i;
4084
4085         ioapic_res = ioapic_setup_resources();
4086         for (i = 0; i < nr_ioapics; i++) {
4087                 if (smp_found_config) {
4088                         ioapic_phys = mp_ioapics[i].apicaddr;
4089 #ifdef CONFIG_X86_32
4090                         if (!ioapic_phys) {
4091                                 printk(KERN_ERR
4092                                        "WARNING: bogus zero IO-APIC "
4093                                        "address found in MPTABLE, "
4094                                        "disabling IO/APIC support!\n");
4095                                 smp_found_config = 0;
4096                                 skip_ioapic_setup = 1;
4097                                 goto fake_ioapic_page;
4098                         }
4099 #endif
4100                 } else {
4101 #ifdef CONFIG_X86_32
4102 fake_ioapic_page:
4103 #endif
4104                         ioapic_phys = (unsigned long)
4105                                 alloc_bootmem_pages(PAGE_SIZE);
4106                         ioapic_phys = __pa(ioapic_phys);
4107                 }
4108                 set_fixmap_nocache(idx, ioapic_phys);
4109                 apic_printk(APIC_VERBOSE,
4110                             "mapped IOAPIC to %08lx (%08lx)\n",
4111                             __fix_to_virt(idx), ioapic_phys);
4112                 idx++;
4113
4114                 if (ioapic_res != NULL) {
4115                         ioapic_res->start = ioapic_phys;
4116                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4117                         ioapic_res++;
4118                 }
4119         }
4120 }
4121
4122 static int __init ioapic_insert_resources(void)
4123 {
4124         int i;
4125         struct resource *r = ioapic_resources;
4126
4127         if (!r) {
4128                 printk(KERN_ERR
4129                        "IO APIC resources could be not be allocated.\n");
4130                 return -1;
4131         }
4132
4133         for (i = 0; i < nr_ioapics; i++) {
4134                 insert_resource(&iomem_resource, r);
4135                 r++;
4136         }
4137
4138         return 0;
4139 }
4140
4141 /* Insert the IO APIC resources after PCI initialization has occured to handle
4142  * IO APICS that are mapped in on a BAR in PCI space. */
4143 late_initcall(ioapic_insert_resources);