perf, x86: Change x86_pmu.{enable,disable} calling convention
[linux-2.6.git] / arch / x86 / kernel / cpu / perf_event.c
1 /*
2  * Performance events x86 architecture code
3  *
4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6  *  Copyright (C) 2009 Jaswinder Singh Rajput
7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
11  *
12  *  For licencing details see kernel-base/COPYING
13  */
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27
28 #include <asm/apic.h>
29 #include <asm/stacktrace.h>
30 #include <asm/nmi.h>
31
32 static u64 perf_event_mask __read_mostly;
33
34 /* The maximal number of PEBS events: */
35 #define MAX_PEBS_EVENTS 4
36
37 /* The size of a BTS record in bytes: */
38 #define BTS_RECORD_SIZE         24
39
40 /* The size of a per-cpu BTS buffer in bytes: */
41 #define BTS_BUFFER_SIZE         (BTS_RECORD_SIZE * 2048)
42
43 /* The BTS overflow threshold in bytes from the end of the buffer: */
44 #define BTS_OVFL_TH             (BTS_RECORD_SIZE * 128)
45
46
47 /*
48  * Bits in the debugctlmsr controlling branch tracing.
49  */
50 #define X86_DEBUGCTL_TR                 (1 << 6)
51 #define X86_DEBUGCTL_BTS                (1 << 7)
52 #define X86_DEBUGCTL_BTINT              (1 << 8)
53 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
54 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
55
56 /*
57  * A debug store configuration.
58  *
59  * We only support architectures that use 64bit fields.
60  */
61 struct debug_store {
62         u64     bts_buffer_base;
63         u64     bts_index;
64         u64     bts_absolute_maximum;
65         u64     bts_interrupt_threshold;
66         u64     pebs_buffer_base;
67         u64     pebs_index;
68         u64     pebs_absolute_maximum;
69         u64     pebs_interrupt_threshold;
70         u64     pebs_event_reset[MAX_PEBS_EVENTS];
71 };
72
73 struct event_constraint {
74         union {
75                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
76                 u64             idxmsk64;
77         };
78         u64     code;
79         u64     cmask;
80         int     weight;
81 };
82
83 struct amd_nb {
84         int nb_id;  /* NorthBridge id */
85         int refcnt; /* reference count */
86         struct perf_event *owners[X86_PMC_IDX_MAX];
87         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
88 };
89
90 struct cpu_hw_events {
91         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
92         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
93         unsigned long           interrupts;
94         int                     enabled;
95         struct debug_store      *ds;
96
97         int                     n_events;
98         int                     n_added;
99         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
100         u64                     tags[X86_PMC_IDX_MAX];
101         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
102         struct amd_nb           *amd_nb;
103 };
104
105 #define __EVENT_CONSTRAINT(c, n, m, w) {\
106         { .idxmsk64 = (n) },            \
107         .code = (c),                    \
108         .cmask = (m),                   \
109         .weight = (w),                  \
110 }
111
112 #define EVENT_CONSTRAINT(c, n, m)       \
113         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
114
115 #define INTEL_EVENT_CONSTRAINT(c, n)    \
116         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
117
118 #define FIXED_EVENT_CONSTRAINT(c, n)    \
119         EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
120
121 #define EVENT_CONSTRAINT_END            \
122         EVENT_CONSTRAINT(0, 0, 0)
123
124 #define for_each_event_constraint(e, c) \
125         for ((e) = (c); (e)->cmask; (e)++)
126
127 /*
128  * struct x86_pmu - generic x86 pmu
129  */
130 struct x86_pmu {
131         const char      *name;
132         int             version;
133         int             (*handle_irq)(struct pt_regs *);
134         void            (*disable_all)(void);
135         void            (*enable_all)(void);
136         void            (*enable)(struct perf_event *);
137         void            (*disable)(struct perf_event *);
138         unsigned        eventsel;
139         unsigned        perfctr;
140         u64             (*event_map)(int);
141         u64             (*raw_event)(u64);
142         int             max_events;
143         int             num_events;
144         int             num_events_fixed;
145         int             event_bits;
146         u64             event_mask;
147         int             apic;
148         u64             max_period;
149         u64             intel_ctrl;
150         void            (*enable_bts)(u64 config);
151         void            (*disable_bts)(void);
152
153         struct event_constraint *
154                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
155                                                  struct perf_event *event);
156
157         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
158                                                  struct perf_event *event);
159         struct event_constraint *event_constraints;
160
161         void            (*cpu_prepare)(int cpu);
162         void            (*cpu_starting)(int cpu);
163         void            (*cpu_dying)(int cpu);
164         void            (*cpu_dead)(int cpu);
165 };
166
167 static struct x86_pmu x86_pmu __read_mostly;
168
169 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
170         .enabled = 1,
171 };
172
173 static int x86_perf_event_set_period(struct perf_event *event);
174
175 /*
176  * Generalized hw caching related hw_event table, filled
177  * in on a per model basis. A value of 0 means
178  * 'not supported', -1 means 'hw_event makes no sense on
179  * this CPU', any other value means the raw hw_event
180  * ID.
181  */
182
183 #define C(x) PERF_COUNT_HW_CACHE_##x
184
185 static u64 __read_mostly hw_cache_event_ids
186                                 [PERF_COUNT_HW_CACHE_MAX]
187                                 [PERF_COUNT_HW_CACHE_OP_MAX]
188                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
189
190 /*
191  * Propagate event elapsed time into the generic event.
192  * Can only be executed on the CPU where the event is active.
193  * Returns the delta events processed.
194  */
195 static u64
196 x86_perf_event_update(struct perf_event *event)
197 {
198         struct hw_perf_event *hwc = &event->hw;
199         int shift = 64 - x86_pmu.event_bits;
200         u64 prev_raw_count, new_raw_count;
201         int idx = hwc->idx;
202         s64 delta;
203
204         if (idx == X86_PMC_IDX_FIXED_BTS)
205                 return 0;
206
207         /*
208          * Careful: an NMI might modify the previous event value.
209          *
210          * Our tactic to handle this is to first atomically read and
211          * exchange a new raw count - then add that new-prev delta
212          * count to the generic event atomically:
213          */
214 again:
215         prev_raw_count = atomic64_read(&hwc->prev_count);
216         rdmsrl(hwc->event_base + idx, new_raw_count);
217
218         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
219                                         new_raw_count) != prev_raw_count)
220                 goto again;
221
222         /*
223          * Now we have the new raw value and have updated the prev
224          * timestamp already. We can now calculate the elapsed delta
225          * (event-)time and add that to the generic event.
226          *
227          * Careful, not all hw sign-extends above the physical width
228          * of the count.
229          */
230         delta = (new_raw_count << shift) - (prev_raw_count << shift);
231         delta >>= shift;
232
233         atomic64_add(delta, &event->count);
234         atomic64_sub(delta, &hwc->period_left);
235
236         return new_raw_count;
237 }
238
239 static atomic_t active_events;
240 static DEFINE_MUTEX(pmc_reserve_mutex);
241
242 static bool reserve_pmc_hardware(void)
243 {
244 #ifdef CONFIG_X86_LOCAL_APIC
245         int i;
246
247         if (nmi_watchdog == NMI_LOCAL_APIC)
248                 disable_lapic_nmi_watchdog();
249
250         for (i = 0; i < x86_pmu.num_events; i++) {
251                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
252                         goto perfctr_fail;
253         }
254
255         for (i = 0; i < x86_pmu.num_events; i++) {
256                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
257                         goto eventsel_fail;
258         }
259 #endif
260
261         return true;
262
263 #ifdef CONFIG_X86_LOCAL_APIC
264 eventsel_fail:
265         for (i--; i >= 0; i--)
266                 release_evntsel_nmi(x86_pmu.eventsel + i);
267
268         i = x86_pmu.num_events;
269
270 perfctr_fail:
271         for (i--; i >= 0; i--)
272                 release_perfctr_nmi(x86_pmu.perfctr + i);
273
274         if (nmi_watchdog == NMI_LOCAL_APIC)
275                 enable_lapic_nmi_watchdog();
276
277         return false;
278 #endif
279 }
280
281 static void release_pmc_hardware(void)
282 {
283 #ifdef CONFIG_X86_LOCAL_APIC
284         int i;
285
286         for (i = 0; i < x86_pmu.num_events; i++) {
287                 release_perfctr_nmi(x86_pmu.perfctr + i);
288                 release_evntsel_nmi(x86_pmu.eventsel + i);
289         }
290
291         if (nmi_watchdog == NMI_LOCAL_APIC)
292                 enable_lapic_nmi_watchdog();
293 #endif
294 }
295
296 static inline bool bts_available(void)
297 {
298         return x86_pmu.enable_bts != NULL;
299 }
300
301 static void init_debug_store_on_cpu(int cpu)
302 {
303         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
304
305         if (!ds)
306                 return;
307
308         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
309                      (u32)((u64)(unsigned long)ds),
310                      (u32)((u64)(unsigned long)ds >> 32));
311 }
312
313 static void fini_debug_store_on_cpu(int cpu)
314 {
315         if (!per_cpu(cpu_hw_events, cpu).ds)
316                 return;
317
318         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
319 }
320
321 static void release_bts_hardware(void)
322 {
323         int cpu;
324
325         if (!bts_available())
326                 return;
327
328         get_online_cpus();
329
330         for_each_online_cpu(cpu)
331                 fini_debug_store_on_cpu(cpu);
332
333         for_each_possible_cpu(cpu) {
334                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
335
336                 if (!ds)
337                         continue;
338
339                 per_cpu(cpu_hw_events, cpu).ds = NULL;
340
341                 kfree((void *)(unsigned long)ds->bts_buffer_base);
342                 kfree(ds);
343         }
344
345         put_online_cpus();
346 }
347
348 static int reserve_bts_hardware(void)
349 {
350         int cpu, err = 0;
351
352         if (!bts_available())
353                 return 0;
354
355         get_online_cpus();
356
357         for_each_possible_cpu(cpu) {
358                 struct debug_store *ds;
359                 void *buffer;
360
361                 err = -ENOMEM;
362                 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
363                 if (unlikely(!buffer))
364                         break;
365
366                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
367                 if (unlikely(!ds)) {
368                         kfree(buffer);
369                         break;
370                 }
371
372                 ds->bts_buffer_base = (u64)(unsigned long)buffer;
373                 ds->bts_index = ds->bts_buffer_base;
374                 ds->bts_absolute_maximum =
375                         ds->bts_buffer_base + BTS_BUFFER_SIZE;
376                 ds->bts_interrupt_threshold =
377                         ds->bts_absolute_maximum - BTS_OVFL_TH;
378
379                 per_cpu(cpu_hw_events, cpu).ds = ds;
380                 err = 0;
381         }
382
383         if (err)
384                 release_bts_hardware();
385         else {
386                 for_each_online_cpu(cpu)
387                         init_debug_store_on_cpu(cpu);
388         }
389
390         put_online_cpus();
391
392         return err;
393 }
394
395 static void hw_perf_event_destroy(struct perf_event *event)
396 {
397         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
398                 release_pmc_hardware();
399                 release_bts_hardware();
400                 mutex_unlock(&pmc_reserve_mutex);
401         }
402 }
403
404 static inline int x86_pmu_initialized(void)
405 {
406         return x86_pmu.handle_irq != NULL;
407 }
408
409 static inline int
410 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
411 {
412         unsigned int cache_type, cache_op, cache_result;
413         u64 config, val;
414
415         config = attr->config;
416
417         cache_type = (config >>  0) & 0xff;
418         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
419                 return -EINVAL;
420
421         cache_op = (config >>  8) & 0xff;
422         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
423                 return -EINVAL;
424
425         cache_result = (config >> 16) & 0xff;
426         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
427                 return -EINVAL;
428
429         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
430
431         if (val == 0)
432                 return -ENOENT;
433
434         if (val == -1)
435                 return -EINVAL;
436
437         hwc->config |= val;
438
439         return 0;
440 }
441
442 /*
443  * Setup the hardware configuration for a given attr_type
444  */
445 static int __hw_perf_event_init(struct perf_event *event)
446 {
447         struct perf_event_attr *attr = &event->attr;
448         struct hw_perf_event *hwc = &event->hw;
449         u64 config;
450         int err;
451
452         if (!x86_pmu_initialized())
453                 return -ENODEV;
454
455         err = 0;
456         if (!atomic_inc_not_zero(&active_events)) {
457                 mutex_lock(&pmc_reserve_mutex);
458                 if (atomic_read(&active_events) == 0) {
459                         if (!reserve_pmc_hardware())
460                                 err = -EBUSY;
461                         else
462                                 err = reserve_bts_hardware();
463                 }
464                 if (!err)
465                         atomic_inc(&active_events);
466                 mutex_unlock(&pmc_reserve_mutex);
467         }
468         if (err)
469                 return err;
470
471         event->destroy = hw_perf_event_destroy;
472
473         /*
474          * Generate PMC IRQs:
475          * (keep 'enabled' bit clear for now)
476          */
477         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
478
479         hwc->idx = -1;
480         hwc->last_cpu = -1;
481         hwc->last_tag = ~0ULL;
482
483         /*
484          * Count user and OS events unless requested not to.
485          */
486         if (!attr->exclude_user)
487                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
488         if (!attr->exclude_kernel)
489                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
490
491         if (!hwc->sample_period) {
492                 hwc->sample_period = x86_pmu.max_period;
493                 hwc->last_period = hwc->sample_period;
494                 atomic64_set(&hwc->period_left, hwc->sample_period);
495         } else {
496                 /*
497                  * If we have a PMU initialized but no APIC
498                  * interrupts, we cannot sample hardware
499                  * events (user-space has to fall back and
500                  * sample via a hrtimer based software event):
501                  */
502                 if (!x86_pmu.apic)
503                         return -EOPNOTSUPP;
504         }
505
506         /*
507          * Raw hw_event type provide the config in the hw_event structure
508          */
509         if (attr->type == PERF_TYPE_RAW) {
510                 hwc->config |= x86_pmu.raw_event(attr->config);
511                 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
512                     perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
513                         return -EACCES;
514                 return 0;
515         }
516
517         if (attr->type == PERF_TYPE_HW_CACHE)
518                 return set_ext_hw_attr(hwc, attr);
519
520         if (attr->config >= x86_pmu.max_events)
521                 return -EINVAL;
522
523         /*
524          * The generic map:
525          */
526         config = x86_pmu.event_map(attr->config);
527
528         if (config == 0)
529                 return -ENOENT;
530
531         if (config == -1LL)
532                 return -EINVAL;
533
534         /*
535          * Branch tracing:
536          */
537         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
538             (hwc->sample_period == 1)) {
539                 /* BTS is not supported by this architecture. */
540                 if (!bts_available())
541                         return -EOPNOTSUPP;
542
543                 /* BTS is currently only allowed for user-mode. */
544                 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
545                         return -EOPNOTSUPP;
546         }
547
548         hwc->config |= config;
549
550         return 0;
551 }
552
553 static void x86_pmu_disable_all(void)
554 {
555         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
556         int idx;
557
558         for (idx = 0; idx < x86_pmu.num_events; idx++) {
559                 u64 val;
560
561                 if (!test_bit(idx, cpuc->active_mask))
562                         continue;
563                 rdmsrl(x86_pmu.eventsel + idx, val);
564                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
565                         continue;
566                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
567                 wrmsrl(x86_pmu.eventsel + idx, val);
568         }
569 }
570
571 void hw_perf_disable(void)
572 {
573         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
574
575         if (!x86_pmu_initialized())
576                 return;
577
578         if (!cpuc->enabled)
579                 return;
580
581         cpuc->n_added = 0;
582         cpuc->enabled = 0;
583         barrier();
584
585         x86_pmu.disable_all();
586 }
587
588 static void x86_pmu_enable_all(void)
589 {
590         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
591         int idx;
592
593         for (idx = 0; idx < x86_pmu.num_events; idx++) {
594                 struct perf_event *event = cpuc->events[idx];
595                 u64 val;
596
597                 if (!test_bit(idx, cpuc->active_mask))
598                         continue;
599
600                 val = event->hw.config;
601                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
602                 wrmsrl(x86_pmu.eventsel + idx, val);
603         }
604 }
605
606 static const struct pmu pmu;
607
608 static inline int is_x86_event(struct perf_event *event)
609 {
610         return event->pmu == &pmu;
611 }
612
613 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
614 {
615         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
616         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
617         int i, j, w, wmax, num = 0;
618         struct hw_perf_event *hwc;
619
620         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
621
622         for (i = 0; i < n; i++) {
623                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
624                 constraints[i] = c;
625         }
626
627         /*
628          * fastpath, try to reuse previous register
629          */
630         for (i = 0; i < n; i++) {
631                 hwc = &cpuc->event_list[i]->hw;
632                 c = constraints[i];
633
634                 /* never assigned */
635                 if (hwc->idx == -1)
636                         break;
637
638                 /* constraint still honored */
639                 if (!test_bit(hwc->idx, c->idxmsk))
640                         break;
641
642                 /* not already used */
643                 if (test_bit(hwc->idx, used_mask))
644                         break;
645
646                 set_bit(hwc->idx, used_mask);
647                 if (assign)
648                         assign[i] = hwc->idx;
649         }
650         if (i == n)
651                 goto done;
652
653         /*
654          * begin slow path
655          */
656
657         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
658
659         /*
660          * weight = number of possible counters
661          *
662          * 1    = most constrained, only works on one counter
663          * wmax = least constrained, works on any counter
664          *
665          * assign events to counters starting with most
666          * constrained events.
667          */
668         wmax = x86_pmu.num_events;
669
670         /*
671          * when fixed event counters are present,
672          * wmax is incremented by 1 to account
673          * for one more choice
674          */
675         if (x86_pmu.num_events_fixed)
676                 wmax++;
677
678         for (w = 1, num = n; num && w <= wmax; w++) {
679                 /* for each event */
680                 for (i = 0; num && i < n; i++) {
681                         c = constraints[i];
682                         hwc = &cpuc->event_list[i]->hw;
683
684                         if (c->weight != w)
685                                 continue;
686
687                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
688                                 if (!test_bit(j, used_mask))
689                                         break;
690                         }
691
692                         if (j == X86_PMC_IDX_MAX)
693                                 break;
694
695                         set_bit(j, used_mask);
696
697                         if (assign)
698                                 assign[i] = j;
699                         num--;
700                 }
701         }
702 done:
703         /*
704          * scheduling failed or is just a simulation,
705          * free resources if necessary
706          */
707         if (!assign || num) {
708                 for (i = 0; i < n; i++) {
709                         if (x86_pmu.put_event_constraints)
710                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
711                 }
712         }
713         return num ? -ENOSPC : 0;
714 }
715
716 /*
717  * dogrp: true if must collect siblings events (group)
718  * returns total number of events and error code
719  */
720 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
721 {
722         struct perf_event *event;
723         int n, max_count;
724
725         max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
726
727         /* current number of events already accepted */
728         n = cpuc->n_events;
729
730         if (is_x86_event(leader)) {
731                 if (n >= max_count)
732                         return -ENOSPC;
733                 cpuc->event_list[n] = leader;
734                 n++;
735         }
736         if (!dogrp)
737                 return n;
738
739         list_for_each_entry(event, &leader->sibling_list, group_entry) {
740                 if (!is_x86_event(event) ||
741                     event->state <= PERF_EVENT_STATE_OFF)
742                         continue;
743
744                 if (n >= max_count)
745                         return -ENOSPC;
746
747                 cpuc->event_list[n] = event;
748                 n++;
749         }
750         return n;
751 }
752
753 static inline void x86_assign_hw_event(struct perf_event *event,
754                                 struct cpu_hw_events *cpuc, int i)
755 {
756         struct hw_perf_event *hwc = &event->hw;
757
758         hwc->idx = cpuc->assign[i];
759         hwc->last_cpu = smp_processor_id();
760         hwc->last_tag = ++cpuc->tags[i];
761
762         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
763                 hwc->config_base = 0;
764                 hwc->event_base = 0;
765         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
766                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
767                 /*
768                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
769                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
770                  */
771                 hwc->event_base =
772                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
773         } else {
774                 hwc->config_base = x86_pmu.eventsel;
775                 hwc->event_base  = x86_pmu.perfctr;
776         }
777 }
778
779 static inline int match_prev_assignment(struct hw_perf_event *hwc,
780                                         struct cpu_hw_events *cpuc,
781                                         int i)
782 {
783         return hwc->idx == cpuc->assign[i] &&
784                 hwc->last_cpu == smp_processor_id() &&
785                 hwc->last_tag == cpuc->tags[i];
786 }
787
788 static void x86_pmu_stop(struct perf_event *event);
789
790 void hw_perf_enable(void)
791 {
792         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
793         struct perf_event *event;
794         struct hw_perf_event *hwc;
795         int i;
796
797         if (!x86_pmu_initialized())
798                 return;
799
800         if (cpuc->enabled)
801                 return;
802
803         if (cpuc->n_added) {
804                 /*
805                  * apply assignment obtained either from
806                  * hw_perf_group_sched_in() or x86_pmu_enable()
807                  *
808                  * step1: save events moving to new counters
809                  * step2: reprogram moved events into new counters
810                  */
811                 for (i = 0; i < cpuc->n_events; i++) {
812
813                         event = cpuc->event_list[i];
814                         hwc = &event->hw;
815
816                         /*
817                          * we can avoid reprogramming counter if:
818                          * - assigned same counter as last time
819                          * - running on same CPU as last time
820                          * - no other event has used the counter since
821                          */
822                         if (hwc->idx == -1 ||
823                             match_prev_assignment(hwc, cpuc, i))
824                                 continue;
825
826                         x86_pmu_stop(event);
827
828                         hwc->idx = -1;
829                 }
830
831                 for (i = 0; i < cpuc->n_events; i++) {
832
833                         event = cpuc->event_list[i];
834                         hwc = &event->hw;
835
836                         if (hwc->idx == -1) {
837                                 x86_assign_hw_event(event, cpuc, i);
838                                 x86_perf_event_set_period(event);
839                         }
840                         /*
841                          * need to mark as active because x86_pmu_disable()
842                          * clear active_mask and events[] yet it preserves
843                          * idx
844                          */
845                         set_bit(hwc->idx, cpuc->active_mask);
846                         cpuc->events[hwc->idx] = event;
847
848                         x86_pmu.enable(event);
849                         perf_event_update_userpage(event);
850                 }
851                 cpuc->n_added = 0;
852                 perf_events_lapic_init();
853         }
854
855         cpuc->enabled = 1;
856         barrier();
857
858         x86_pmu.enable_all();
859 }
860
861 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
862 {
863         (void)checking_wrmsrl(hwc->config_base + hwc->idx,
864                               hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
865 }
866
867 static inline void x86_pmu_disable_event(struct perf_event *event)
868 {
869         struct hw_perf_event *hwc = &event->hw;
870         (void)checking_wrmsrl(hwc->config_base + hwc->idx, hwc->config);
871 }
872
873 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
874
875 /*
876  * Set the next IRQ period, based on the hwc->period_left value.
877  * To be called with the event disabled in hw:
878  */
879 static int
880 x86_perf_event_set_period(struct perf_event *event)
881 {
882         struct hw_perf_event *hwc = &event->hw;
883         s64 left = atomic64_read(&hwc->period_left);
884         s64 period = hwc->sample_period;
885         int err, ret = 0, idx = hwc->idx;
886
887         if (idx == X86_PMC_IDX_FIXED_BTS)
888                 return 0;
889
890         /*
891          * If we are way outside a reasonable range then just skip forward:
892          */
893         if (unlikely(left <= -period)) {
894                 left = period;
895                 atomic64_set(&hwc->period_left, left);
896                 hwc->last_period = period;
897                 ret = 1;
898         }
899
900         if (unlikely(left <= 0)) {
901                 left += period;
902                 atomic64_set(&hwc->period_left, left);
903                 hwc->last_period = period;
904                 ret = 1;
905         }
906         /*
907          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
908          */
909         if (unlikely(left < 2))
910                 left = 2;
911
912         if (left > x86_pmu.max_period)
913                 left = x86_pmu.max_period;
914
915         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
916
917         /*
918          * The hw event starts counting from this event offset,
919          * mark it to be able to extra future deltas:
920          */
921         atomic64_set(&hwc->prev_count, (u64)-left);
922
923         err = checking_wrmsrl(hwc->event_base + idx,
924                              (u64)(-left) & x86_pmu.event_mask);
925
926         perf_event_update_userpage(event);
927
928         return ret;
929 }
930
931 static void x86_pmu_enable_event(struct perf_event *event)
932 {
933         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
934         if (cpuc->enabled)
935                 __x86_pmu_enable_event(&event->hw);
936 }
937
938 /*
939  * activate a single event
940  *
941  * The event is added to the group of enabled events
942  * but only if it can be scehduled with existing events.
943  *
944  * Called with PMU disabled. If successful and return value 1,
945  * then guaranteed to call perf_enable() and hw_perf_enable()
946  */
947 static int x86_pmu_enable(struct perf_event *event)
948 {
949         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
950         struct hw_perf_event *hwc;
951         int assign[X86_PMC_IDX_MAX];
952         int n, n0, ret;
953
954         hwc = &event->hw;
955
956         n0 = cpuc->n_events;
957         n = collect_events(cpuc, event, false);
958         if (n < 0)
959                 return n;
960
961         ret = x86_schedule_events(cpuc, n, assign);
962         if (ret)
963                 return ret;
964         /*
965          * copy new assignment, now we know it is possible
966          * will be used by hw_perf_enable()
967          */
968         memcpy(cpuc->assign, assign, n*sizeof(int));
969
970         cpuc->n_events = n;
971         cpuc->n_added  = n - n0;
972
973         return 0;
974 }
975
976 static int x86_pmu_start(struct perf_event *event)
977 {
978         if (event->hw.idx == -1)
979                 return -EAGAIN;
980
981         x86_perf_event_set_period(event);
982         x86_pmu.enable(event);
983
984         return 0;
985 }
986
987 static void x86_pmu_unthrottle(struct perf_event *event)
988 {
989         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
990         struct hw_perf_event *hwc = &event->hw;
991
992         if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
993                                 cpuc->events[hwc->idx] != event))
994                 return;
995
996         x86_pmu.enable(event);
997 }
998
999 void perf_event_print_debug(void)
1000 {
1001         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1002         struct cpu_hw_events *cpuc;
1003         unsigned long flags;
1004         int cpu, idx;
1005
1006         if (!x86_pmu.num_events)
1007                 return;
1008
1009         local_irq_save(flags);
1010
1011         cpu = smp_processor_id();
1012         cpuc = &per_cpu(cpu_hw_events, cpu);
1013
1014         if (x86_pmu.version >= 2) {
1015                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1016                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1017                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1018                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1019
1020                 pr_info("\n");
1021                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1022                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1023                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1024                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1025         }
1026         pr_info("CPU#%d: active:       %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1027
1028         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1029                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1030                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1031
1032                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1033
1034                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1035                         cpu, idx, pmc_ctrl);
1036                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1037                         cpu, idx, pmc_count);
1038                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1039                         cpu, idx, prev_left);
1040         }
1041         for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1042                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1043
1044                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1045                         cpu, idx, pmc_count);
1046         }
1047         local_irq_restore(flags);
1048 }
1049
1050 static void x86_pmu_stop(struct perf_event *event)
1051 {
1052         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1053         struct hw_perf_event *hwc = &event->hw;
1054         int idx = hwc->idx;
1055
1056         /*
1057          * Must be done before we disable, otherwise the nmi handler
1058          * could reenable again:
1059          */
1060         clear_bit(idx, cpuc->active_mask);
1061         x86_pmu.disable(event);
1062
1063         /*
1064          * Drain the remaining delta count out of a event
1065          * that we are disabling:
1066          */
1067         x86_perf_event_update(event);
1068
1069         cpuc->events[idx] = NULL;
1070 }
1071
1072 static void x86_pmu_disable(struct perf_event *event)
1073 {
1074         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1075         int i;
1076
1077         x86_pmu_stop(event);
1078
1079         for (i = 0; i < cpuc->n_events; i++) {
1080                 if (event == cpuc->event_list[i]) {
1081
1082                         if (x86_pmu.put_event_constraints)
1083                                 x86_pmu.put_event_constraints(cpuc, event);
1084
1085                         while (++i < cpuc->n_events)
1086                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1087
1088                         --cpuc->n_events;
1089                         break;
1090                 }
1091         }
1092         perf_event_update_userpage(event);
1093 }
1094
1095 static int x86_pmu_handle_irq(struct pt_regs *regs)
1096 {
1097         struct perf_sample_data data;
1098         struct cpu_hw_events *cpuc;
1099         struct perf_event *event;
1100         struct hw_perf_event *hwc;
1101         int idx, handled = 0;
1102         u64 val;
1103
1104         perf_sample_data_init(&data, 0);
1105
1106         cpuc = &__get_cpu_var(cpu_hw_events);
1107
1108         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1109                 if (!test_bit(idx, cpuc->active_mask))
1110                         continue;
1111
1112                 event = cpuc->events[idx];
1113                 hwc = &event->hw;
1114
1115                 val = x86_perf_event_update(event);
1116                 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1117                         continue;
1118
1119                 /*
1120                  * event overflow
1121                  */
1122                 handled         = 1;
1123                 data.period     = event->hw.last_period;
1124
1125                 if (!x86_perf_event_set_period(event))
1126                         continue;
1127
1128                 if (perf_event_overflow(event, 1, &data, regs))
1129                         x86_pmu.disable(event);
1130         }
1131
1132         if (handled)
1133                 inc_irq_stat(apic_perf_irqs);
1134
1135         return handled;
1136 }
1137
1138 void smp_perf_pending_interrupt(struct pt_regs *regs)
1139 {
1140         irq_enter();
1141         ack_APIC_irq();
1142         inc_irq_stat(apic_pending_irqs);
1143         perf_event_do_pending();
1144         irq_exit();
1145 }
1146
1147 void set_perf_event_pending(void)
1148 {
1149 #ifdef CONFIG_X86_LOCAL_APIC
1150         if (!x86_pmu.apic || !x86_pmu_initialized())
1151                 return;
1152
1153         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1154 #endif
1155 }
1156
1157 void perf_events_lapic_init(void)
1158 {
1159 #ifdef CONFIG_X86_LOCAL_APIC
1160         if (!x86_pmu.apic || !x86_pmu_initialized())
1161                 return;
1162
1163         /*
1164          * Always use NMI for PMU
1165          */
1166         apic_write(APIC_LVTPC, APIC_DM_NMI);
1167 #endif
1168 }
1169
1170 static int __kprobes
1171 perf_event_nmi_handler(struct notifier_block *self,
1172                          unsigned long cmd, void *__args)
1173 {
1174         struct die_args *args = __args;
1175         struct pt_regs *regs;
1176
1177         if (!atomic_read(&active_events))
1178                 return NOTIFY_DONE;
1179
1180         switch (cmd) {
1181         case DIE_NMI:
1182         case DIE_NMI_IPI:
1183                 break;
1184
1185         default:
1186                 return NOTIFY_DONE;
1187         }
1188
1189         regs = args->regs;
1190
1191 #ifdef CONFIG_X86_LOCAL_APIC
1192         apic_write(APIC_LVTPC, APIC_DM_NMI);
1193 #endif
1194         /*
1195          * Can't rely on the handled return value to say it was our NMI, two
1196          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1197          *
1198          * If the first NMI handles both, the latter will be empty and daze
1199          * the CPU.
1200          */
1201         x86_pmu.handle_irq(regs);
1202
1203         return NOTIFY_STOP;
1204 }
1205
1206 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1207         .notifier_call          = perf_event_nmi_handler,
1208         .next                   = NULL,
1209         .priority               = 1
1210 };
1211
1212 static struct event_constraint unconstrained;
1213 static struct event_constraint emptyconstraint;
1214
1215 static struct event_constraint *
1216 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1217 {
1218         struct event_constraint *c;
1219
1220         if (x86_pmu.event_constraints) {
1221                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1222                         if ((event->hw.config & c->cmask) == c->code)
1223                                 return c;
1224                 }
1225         }
1226
1227         return &unconstrained;
1228 }
1229
1230 static int x86_event_sched_in(struct perf_event *event,
1231                           struct perf_cpu_context *cpuctx)
1232 {
1233         int ret = 0;
1234
1235         event->state = PERF_EVENT_STATE_ACTIVE;
1236         event->oncpu = smp_processor_id();
1237         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1238
1239         if (!is_x86_event(event))
1240                 ret = event->pmu->enable(event);
1241
1242         if (!ret && !is_software_event(event))
1243                 cpuctx->active_oncpu++;
1244
1245         if (!ret && event->attr.exclusive)
1246                 cpuctx->exclusive = 1;
1247
1248         return ret;
1249 }
1250
1251 static void x86_event_sched_out(struct perf_event *event,
1252                             struct perf_cpu_context *cpuctx)
1253 {
1254         event->state = PERF_EVENT_STATE_INACTIVE;
1255         event->oncpu = -1;
1256
1257         if (!is_x86_event(event))
1258                 event->pmu->disable(event);
1259
1260         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1261
1262         if (!is_software_event(event))
1263                 cpuctx->active_oncpu--;
1264
1265         if (event->attr.exclusive || !cpuctx->active_oncpu)
1266                 cpuctx->exclusive = 0;
1267 }
1268
1269 /*
1270  * Called to enable a whole group of events.
1271  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1272  * Assumes the caller has disabled interrupts and has
1273  * frozen the PMU with hw_perf_save_disable.
1274  *
1275  * called with PMU disabled. If successful and return value 1,
1276  * then guaranteed to call perf_enable() and hw_perf_enable()
1277  */
1278 int hw_perf_group_sched_in(struct perf_event *leader,
1279                struct perf_cpu_context *cpuctx,
1280                struct perf_event_context *ctx)
1281 {
1282         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1283         struct perf_event *sub;
1284         int assign[X86_PMC_IDX_MAX];
1285         int n0, n1, ret;
1286
1287         /* n0 = total number of events */
1288         n0 = collect_events(cpuc, leader, true);
1289         if (n0 < 0)
1290                 return n0;
1291
1292         ret = x86_schedule_events(cpuc, n0, assign);
1293         if (ret)
1294                 return ret;
1295
1296         ret = x86_event_sched_in(leader, cpuctx);
1297         if (ret)
1298                 return ret;
1299
1300         n1 = 1;
1301         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1302                 if (sub->state > PERF_EVENT_STATE_OFF) {
1303                         ret = x86_event_sched_in(sub, cpuctx);
1304                         if (ret)
1305                                 goto undo;
1306                         ++n1;
1307                 }
1308         }
1309         /*
1310          * copy new assignment, now we know it is possible
1311          * will be used by hw_perf_enable()
1312          */
1313         memcpy(cpuc->assign, assign, n0*sizeof(int));
1314
1315         cpuc->n_events  = n0;
1316         cpuc->n_added   = n1;
1317         ctx->nr_active += n1;
1318
1319         /*
1320          * 1 means successful and events are active
1321          * This is not quite true because we defer
1322          * actual activation until hw_perf_enable() but
1323          * this way we* ensure caller won't try to enable
1324          * individual events
1325          */
1326         return 1;
1327 undo:
1328         x86_event_sched_out(leader, cpuctx);
1329         n0  = 1;
1330         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1331                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1332                         x86_event_sched_out(sub, cpuctx);
1333                         if (++n0 == n1)
1334                                 break;
1335                 }
1336         }
1337         return ret;
1338 }
1339
1340 #include "perf_event_amd.c"
1341 #include "perf_event_p6.c"
1342 #include "perf_event_intel.c"
1343
1344 static int __cpuinit
1345 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1346 {
1347         unsigned int cpu = (long)hcpu;
1348
1349         switch (action & ~CPU_TASKS_FROZEN) {
1350         case CPU_UP_PREPARE:
1351                 if (x86_pmu.cpu_prepare)
1352                         x86_pmu.cpu_prepare(cpu);
1353                 break;
1354
1355         case CPU_STARTING:
1356                 if (x86_pmu.cpu_starting)
1357                         x86_pmu.cpu_starting(cpu);
1358                 break;
1359
1360         case CPU_DYING:
1361                 if (x86_pmu.cpu_dying)
1362                         x86_pmu.cpu_dying(cpu);
1363                 break;
1364
1365         case CPU_DEAD:
1366                 if (x86_pmu.cpu_dead)
1367                         x86_pmu.cpu_dead(cpu);
1368                 break;
1369
1370         default:
1371                 break;
1372         }
1373
1374         return NOTIFY_OK;
1375 }
1376
1377 static void __init pmu_check_apic(void)
1378 {
1379         if (cpu_has_apic)
1380                 return;
1381
1382         x86_pmu.apic = 0;
1383         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1384         pr_info("no hardware sampling interrupt available.\n");
1385 }
1386
1387 void __init init_hw_perf_events(void)
1388 {
1389         struct event_constraint *c;
1390         int err;
1391
1392         pr_info("Performance Events: ");
1393
1394         switch (boot_cpu_data.x86_vendor) {
1395         case X86_VENDOR_INTEL:
1396                 err = intel_pmu_init();
1397                 break;
1398         case X86_VENDOR_AMD:
1399                 err = amd_pmu_init();
1400                 break;
1401         default:
1402                 return;
1403         }
1404         if (err != 0) {
1405                 pr_cont("no PMU driver, software events only.\n");
1406                 return;
1407         }
1408
1409         pmu_check_apic();
1410
1411         pr_cont("%s PMU driver.\n", x86_pmu.name);
1412
1413         if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1414                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1415                      x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1416                 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1417         }
1418         perf_event_mask = (1 << x86_pmu.num_events) - 1;
1419         perf_max_events = x86_pmu.num_events;
1420
1421         if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1422                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1423                      x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1424                 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1425         }
1426
1427         perf_event_mask |=
1428                 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1429         x86_pmu.intel_ctrl = perf_event_mask;
1430
1431         perf_events_lapic_init();
1432         register_die_notifier(&perf_event_nmi_notifier);
1433
1434         unconstrained = (struct event_constraint)
1435                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1436                                    0, x86_pmu.num_events);
1437
1438         if (x86_pmu.event_constraints) {
1439                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1440                         if (c->cmask != INTEL_ARCH_FIXED_MASK)
1441                                 continue;
1442
1443                         c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1444                         c->weight += x86_pmu.num_events;
1445                 }
1446         }
1447
1448         pr_info("... version:                %d\n",     x86_pmu.version);
1449         pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
1450         pr_info("... generic registers:      %d\n",     x86_pmu.num_events);
1451         pr_info("... value mask:             %016Lx\n", x86_pmu.event_mask);
1452         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1453         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_events_fixed);
1454         pr_info("... event mask:             %016Lx\n", perf_event_mask);
1455
1456         perf_cpu_notifier(x86_pmu_notifier);
1457 }
1458
1459 static inline void x86_pmu_read(struct perf_event *event)
1460 {
1461         x86_perf_event_update(event);
1462 }
1463
1464 static const struct pmu pmu = {
1465         .enable         = x86_pmu_enable,
1466         .disable        = x86_pmu_disable,
1467         .start          = x86_pmu_start,
1468         .stop           = x86_pmu_stop,
1469         .read           = x86_pmu_read,
1470         .unthrottle     = x86_pmu_unthrottle,
1471 };
1472
1473 /*
1474  * validate a single event group
1475  *
1476  * validation include:
1477  *      - check events are compatible which each other
1478  *      - events do not compete for the same counter
1479  *      - number of events <= number of counters
1480  *
1481  * validation ensures the group can be loaded onto the
1482  * PMU if it was the only group available.
1483  */
1484 static int validate_group(struct perf_event *event)
1485 {
1486         struct perf_event *leader = event->group_leader;
1487         struct cpu_hw_events *fake_cpuc;
1488         int ret, n;
1489
1490         ret = -ENOMEM;
1491         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1492         if (!fake_cpuc)
1493                 goto out;
1494
1495         /*
1496          * the event is not yet connected with its
1497          * siblings therefore we must first collect
1498          * existing siblings, then add the new event
1499          * before we can simulate the scheduling
1500          */
1501         ret = -ENOSPC;
1502         n = collect_events(fake_cpuc, leader, true);
1503         if (n < 0)
1504                 goto out_free;
1505
1506         fake_cpuc->n_events = n;
1507         n = collect_events(fake_cpuc, event, false);
1508         if (n < 0)
1509                 goto out_free;
1510
1511         fake_cpuc->n_events = n;
1512
1513         ret = x86_schedule_events(fake_cpuc, n, NULL);
1514
1515 out_free:
1516         kfree(fake_cpuc);
1517 out:
1518         return ret;
1519 }
1520
1521 const struct pmu *hw_perf_event_init(struct perf_event *event)
1522 {
1523         const struct pmu *tmp;
1524         int err;
1525
1526         err = __hw_perf_event_init(event);
1527         if (!err) {
1528                 /*
1529                  * we temporarily connect event to its pmu
1530                  * such that validate_group() can classify
1531                  * it as an x86 event using is_x86_event()
1532                  */
1533                 tmp = event->pmu;
1534                 event->pmu = &pmu;
1535
1536                 if (event->group_leader != event)
1537                         err = validate_group(event);
1538
1539                 event->pmu = tmp;
1540         }
1541         if (err) {
1542                 if (event->destroy)
1543                         event->destroy(event);
1544                 return ERR_PTR(err);
1545         }
1546
1547         return &pmu;
1548 }
1549
1550 /*
1551  * callchain support
1552  */
1553
1554 static inline
1555 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1556 {
1557         if (entry->nr < PERF_MAX_STACK_DEPTH)
1558                 entry->ip[entry->nr++] = ip;
1559 }
1560
1561 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1562 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1563
1564
1565 static void
1566 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1567 {
1568         /* Ignore warnings */
1569 }
1570
1571 static void backtrace_warning(void *data, char *msg)
1572 {
1573         /* Ignore warnings */
1574 }
1575
1576 static int backtrace_stack(void *data, char *name)
1577 {
1578         return 0;
1579 }
1580
1581 static void backtrace_address(void *data, unsigned long addr, int reliable)
1582 {
1583         struct perf_callchain_entry *entry = data;
1584
1585         if (reliable)
1586                 callchain_store(entry, addr);
1587 }
1588
1589 static const struct stacktrace_ops backtrace_ops = {
1590         .warning                = backtrace_warning,
1591         .warning_symbol         = backtrace_warning_symbol,
1592         .stack                  = backtrace_stack,
1593         .address                = backtrace_address,
1594         .walk_stack             = print_context_stack_bp,
1595 };
1596
1597 #include "../dumpstack.h"
1598
1599 static void
1600 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1601 {
1602         callchain_store(entry, PERF_CONTEXT_KERNEL);
1603         callchain_store(entry, regs->ip);
1604
1605         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1606 }
1607
1608 /*
1609  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1610  */
1611 static unsigned long
1612 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1613 {
1614         unsigned long offset, addr = (unsigned long)from;
1615         int type = in_nmi() ? KM_NMI : KM_IRQ0;
1616         unsigned long size, len = 0;
1617         struct page *page;
1618         void *map;
1619         int ret;
1620
1621         do {
1622                 ret = __get_user_pages_fast(addr, 1, 0, &page);
1623                 if (!ret)
1624                         break;
1625
1626                 offset = addr & (PAGE_SIZE - 1);
1627                 size = min(PAGE_SIZE - offset, n - len);
1628
1629                 map = kmap_atomic(page, type);
1630                 memcpy(to, map+offset, size);
1631                 kunmap_atomic(map, type);
1632                 put_page(page);
1633
1634                 len  += size;
1635                 to   += size;
1636                 addr += size;
1637
1638         } while (len < n);
1639
1640         return len;
1641 }
1642
1643 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1644 {
1645         unsigned long bytes;
1646
1647         bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1648
1649         return bytes == sizeof(*frame);
1650 }
1651
1652 static void
1653 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1654 {
1655         struct stack_frame frame;
1656         const void __user *fp;
1657
1658         if (!user_mode(regs))
1659                 regs = task_pt_regs(current);
1660
1661         fp = (void __user *)regs->bp;
1662
1663         callchain_store(entry, PERF_CONTEXT_USER);
1664         callchain_store(entry, regs->ip);
1665
1666         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1667                 frame.next_frame             = NULL;
1668                 frame.return_address = 0;
1669
1670                 if (!copy_stack_frame(fp, &frame))
1671                         break;
1672
1673                 if ((unsigned long)fp < regs->sp)
1674                         break;
1675
1676                 callchain_store(entry, frame.return_address);
1677                 fp = frame.next_frame;
1678         }
1679 }
1680
1681 static void
1682 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1683 {
1684         int is_user;
1685
1686         if (!regs)
1687                 return;
1688
1689         is_user = user_mode(regs);
1690
1691         if (is_user && current->state != TASK_RUNNING)
1692                 return;
1693
1694         if (!is_user)
1695                 perf_callchain_kernel(regs, entry);
1696
1697         if (current->mm)
1698                 perf_callchain_user(regs, entry);
1699 }
1700
1701 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1702 {
1703         struct perf_callchain_entry *entry;
1704
1705         if (in_nmi())
1706                 entry = &__get_cpu_var(pmc_nmi_entry);
1707         else
1708                 entry = &__get_cpu_var(pmc_irq_entry);
1709
1710         entry->nr = 0;
1711
1712         perf_do_callchain(regs, entry);
1713
1714         return entry;
1715 }