Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6.git] / arch / x86 / kernel / cpu / perf_event.c
1 /*
2  * Performance events x86 architecture code
3  *
4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6  *  Copyright (C) 2009 Jaswinder Singh Rajput
7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
11  *
12  *  For licencing details see kernel-base/COPYING
13  */
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
28
29 #include <asm/apic.h>
30 #include <asm/stacktrace.h>
31 #include <asm/nmi.h>
32 #include <asm/compat.h>
33
34 #if 0
35 #undef wrmsrl
36 #define wrmsrl(msr, val)                                        \
37 do {                                                            \
38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39                         (unsigned long)(val));                  \
40         native_write_msr((msr), (u32)((u64)(val)),              \
41                         (u32)((u64)(val) >> 32));               \
42 } while (0)
43 #endif
44
45 /*
46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
47  */
48 static unsigned long
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
50 {
51         unsigned long offset, addr = (unsigned long)from;
52         unsigned long size, len = 0;
53         struct page *page;
54         void *map;
55         int ret;
56
57         do {
58                 ret = __get_user_pages_fast(addr, 1, 0, &page);
59                 if (!ret)
60                         break;
61
62                 offset = addr & (PAGE_SIZE - 1);
63                 size = min(PAGE_SIZE - offset, n - len);
64
65                 map = kmap_atomic(page);
66                 memcpy(to, map+offset, size);
67                 kunmap_atomic(map);
68                 put_page(page);
69
70                 len  += size;
71                 to   += size;
72                 addr += size;
73
74         } while (len < n);
75
76         return len;
77 }
78
79 struct event_constraint {
80         union {
81                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
82                 u64             idxmsk64;
83         };
84         u64     code;
85         u64     cmask;
86         int     weight;
87 };
88
89 struct amd_nb {
90         int nb_id;  /* NorthBridge id */
91         int refcnt; /* reference count */
92         struct perf_event *owners[X86_PMC_IDX_MAX];
93         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
94 };
95
96 #define MAX_LBR_ENTRIES         16
97
98 struct cpu_hw_events {
99         /*
100          * Generic x86 PMC bits
101          */
102         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
103         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
104         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
105         int                     enabled;
106
107         int                     n_events;
108         int                     n_added;
109         int                     n_txn;
110         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
111         u64                     tags[X86_PMC_IDX_MAX];
112         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
113
114         unsigned int            group_flag;
115
116         /*
117          * Intel DebugStore bits
118          */
119         struct debug_store      *ds;
120         u64                     pebs_enabled;
121
122         /*
123          * Intel LBR bits
124          */
125         int                             lbr_users;
126         void                            *lbr_context;
127         struct perf_branch_stack        lbr_stack;
128         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
129
130         /*
131          * AMD specific bits
132          */
133         struct amd_nb           *amd_nb;
134 };
135
136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
137         { .idxmsk64 = (n) },            \
138         .code = (c),                    \
139         .cmask = (m),                   \
140         .weight = (w),                  \
141 }
142
143 #define EVENT_CONSTRAINT(c, n, m)       \
144         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
145
146 /*
147  * Constraint on the Event code.
148  */
149 #define INTEL_EVENT_CONSTRAINT(c, n)    \
150         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
151
152 /*
153  * Constraint on the Event code + UMask + fixed-mask
154  *
155  * filter mask to validate fixed counter events.
156  * the following filters disqualify for fixed counters:
157  *  - inv
158  *  - edge
159  *  - cnt-mask
160  *  The other filters are supported by fixed counters.
161  *  The any-thread option is supported starting with v3.
162  */
163 #define FIXED_EVENT_CONSTRAINT(c, n)    \
164         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
165
166 /*
167  * Constraint on the Event code + UMask
168  */
169 #define PEBS_EVENT_CONSTRAINT(c, n)     \
170         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
171
172 #define EVENT_CONSTRAINT_END            \
173         EVENT_CONSTRAINT(0, 0, 0)
174
175 #define for_each_event_constraint(e, c) \
176         for ((e) = (c); (e)->weight; (e)++)
177
178 union perf_capabilities {
179         struct {
180                 u64     lbr_format    : 6;
181                 u64     pebs_trap     : 1;
182                 u64     pebs_arch_reg : 1;
183                 u64     pebs_format   : 4;
184                 u64     smm_freeze    : 1;
185         };
186         u64     capabilities;
187 };
188
189 /*
190  * struct x86_pmu - generic x86 pmu
191  */
192 struct x86_pmu {
193         /*
194          * Generic x86 PMC bits
195          */
196         const char      *name;
197         int             version;
198         int             (*handle_irq)(struct pt_regs *);
199         void            (*disable_all)(void);
200         void            (*enable_all)(int added);
201         void            (*enable)(struct perf_event *);
202         void            (*disable)(struct perf_event *);
203         int             (*hw_config)(struct perf_event *event);
204         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
205         unsigned        eventsel;
206         unsigned        perfctr;
207         u64             (*event_map)(int);
208         int             max_events;
209         int             num_counters;
210         int             num_counters_fixed;
211         int             cntval_bits;
212         u64             cntval_mask;
213         int             apic;
214         u64             max_period;
215         struct event_constraint *
216                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
217                                                  struct perf_event *event);
218
219         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
220                                                  struct perf_event *event);
221         struct event_constraint *event_constraints;
222         void            (*quirks)(void);
223         int             perfctr_second_write;
224
225         int             (*cpu_prepare)(int cpu);
226         void            (*cpu_starting)(int cpu);
227         void            (*cpu_dying)(int cpu);
228         void            (*cpu_dead)(int cpu);
229
230         /*
231          * Intel Arch Perfmon v2+
232          */
233         u64                     intel_ctrl;
234         union perf_capabilities intel_cap;
235
236         /*
237          * Intel DebugStore bits
238          */
239         int             bts, pebs;
240         int             bts_active, pebs_active;
241         int             pebs_record_size;
242         void            (*drain_pebs)(struct pt_regs *regs);
243         struct event_constraint *pebs_constraints;
244
245         /*
246          * Intel LBR
247          */
248         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
249         int             lbr_nr;                    /* hardware stack size */
250 };
251
252 static struct x86_pmu x86_pmu __read_mostly;
253
254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
255         .enabled = 1,
256 };
257
258 static int x86_perf_event_set_period(struct perf_event *event);
259
260 /*
261  * Generalized hw caching related hw_event table, filled
262  * in on a per model basis. A value of 0 means
263  * 'not supported', -1 means 'hw_event makes no sense on
264  * this CPU', any other value means the raw hw_event
265  * ID.
266  */
267
268 #define C(x) PERF_COUNT_HW_CACHE_##x
269
270 static u64 __read_mostly hw_cache_event_ids
271                                 [PERF_COUNT_HW_CACHE_MAX]
272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
274
275 /*
276  * Propagate event elapsed time into the generic event.
277  * Can only be executed on the CPU where the event is active.
278  * Returns the delta events processed.
279  */
280 static u64
281 x86_perf_event_update(struct perf_event *event)
282 {
283         struct hw_perf_event *hwc = &event->hw;
284         int shift = 64 - x86_pmu.cntval_bits;
285         u64 prev_raw_count, new_raw_count;
286         int idx = hwc->idx;
287         s64 delta;
288
289         if (idx == X86_PMC_IDX_FIXED_BTS)
290                 return 0;
291
292         /*
293          * Careful: an NMI might modify the previous event value.
294          *
295          * Our tactic to handle this is to first atomically read and
296          * exchange a new raw count - then add that new-prev delta
297          * count to the generic event atomically:
298          */
299 again:
300         prev_raw_count = local64_read(&hwc->prev_count);
301         rdmsrl(hwc->event_base + idx, new_raw_count);
302
303         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
304                                         new_raw_count) != prev_raw_count)
305                 goto again;
306
307         /*
308          * Now we have the new raw value and have updated the prev
309          * timestamp already. We can now calculate the elapsed delta
310          * (event-)time and add that to the generic event.
311          *
312          * Careful, not all hw sign-extends above the physical width
313          * of the count.
314          */
315         delta = (new_raw_count << shift) - (prev_raw_count << shift);
316         delta >>= shift;
317
318         local64_add(delta, &event->count);
319         local64_sub(delta, &hwc->period_left);
320
321         return new_raw_count;
322 }
323
324 static atomic_t active_events;
325 static DEFINE_MUTEX(pmc_reserve_mutex);
326
327 #ifdef CONFIG_X86_LOCAL_APIC
328
329 static bool reserve_pmc_hardware(void)
330 {
331         int i;
332
333         if (nmi_watchdog == NMI_LOCAL_APIC)
334                 disable_lapic_nmi_watchdog();
335
336         for (i = 0; i < x86_pmu.num_counters; i++) {
337                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
338                         goto perfctr_fail;
339         }
340
341         for (i = 0; i < x86_pmu.num_counters; i++) {
342                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
343                         goto eventsel_fail;
344         }
345
346         return true;
347
348 eventsel_fail:
349         for (i--; i >= 0; i--)
350                 release_evntsel_nmi(x86_pmu.eventsel + i);
351
352         i = x86_pmu.num_counters;
353
354 perfctr_fail:
355         for (i--; i >= 0; i--)
356                 release_perfctr_nmi(x86_pmu.perfctr + i);
357
358         if (nmi_watchdog == NMI_LOCAL_APIC)
359                 enable_lapic_nmi_watchdog();
360
361         return false;
362 }
363
364 static void release_pmc_hardware(void)
365 {
366         int i;
367
368         for (i = 0; i < x86_pmu.num_counters; i++) {
369                 release_perfctr_nmi(x86_pmu.perfctr + i);
370                 release_evntsel_nmi(x86_pmu.eventsel + i);
371         }
372
373         if (nmi_watchdog == NMI_LOCAL_APIC)
374                 enable_lapic_nmi_watchdog();
375 }
376
377 #else
378
379 static bool reserve_pmc_hardware(void) { return true; }
380 static void release_pmc_hardware(void) {}
381
382 #endif
383
384 static void reserve_ds_buffers(void);
385 static void release_ds_buffers(void);
386
387 static void hw_perf_event_destroy(struct perf_event *event)
388 {
389         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
390                 release_pmc_hardware();
391                 release_ds_buffers();
392                 mutex_unlock(&pmc_reserve_mutex);
393         }
394 }
395
396 static inline int x86_pmu_initialized(void)
397 {
398         return x86_pmu.handle_irq != NULL;
399 }
400
401 static inline int
402 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
403 {
404         unsigned int cache_type, cache_op, cache_result;
405         u64 config, val;
406
407         config = attr->config;
408
409         cache_type = (config >>  0) & 0xff;
410         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
411                 return -EINVAL;
412
413         cache_op = (config >>  8) & 0xff;
414         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
415                 return -EINVAL;
416
417         cache_result = (config >> 16) & 0xff;
418         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
419                 return -EINVAL;
420
421         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
422
423         if (val == 0)
424                 return -ENOENT;
425
426         if (val == -1)
427                 return -EINVAL;
428
429         hwc->config |= val;
430
431         return 0;
432 }
433
434 static int x86_setup_perfctr(struct perf_event *event)
435 {
436         struct perf_event_attr *attr = &event->attr;
437         struct hw_perf_event *hwc = &event->hw;
438         u64 config;
439
440         if (!hwc->sample_period) {
441                 hwc->sample_period = x86_pmu.max_period;
442                 hwc->last_period = hwc->sample_period;
443                 local64_set(&hwc->period_left, hwc->sample_period);
444         } else {
445                 /*
446                  * If we have a PMU initialized but no APIC
447                  * interrupts, we cannot sample hardware
448                  * events (user-space has to fall back and
449                  * sample via a hrtimer based software event):
450                  */
451                 if (!x86_pmu.apic)
452                         return -EOPNOTSUPP;
453         }
454
455         if (attr->type == PERF_TYPE_RAW)
456                 return 0;
457
458         if (attr->type == PERF_TYPE_HW_CACHE)
459                 return set_ext_hw_attr(hwc, attr);
460
461         if (attr->config >= x86_pmu.max_events)
462                 return -EINVAL;
463
464         /*
465          * The generic map:
466          */
467         config = x86_pmu.event_map(attr->config);
468
469         if (config == 0)
470                 return -ENOENT;
471
472         if (config == -1LL)
473                 return -EINVAL;
474
475         /*
476          * Branch tracing:
477          */
478         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
479             (hwc->sample_period == 1)) {
480                 /* BTS is not supported by this architecture. */
481                 if (!x86_pmu.bts_active)
482                         return -EOPNOTSUPP;
483
484                 /* BTS is currently only allowed for user-mode. */
485                 if (!attr->exclude_kernel)
486                         return -EOPNOTSUPP;
487         }
488
489         hwc->config |= config;
490
491         return 0;
492 }
493
494 static int x86_pmu_hw_config(struct perf_event *event)
495 {
496         if (event->attr.precise_ip) {
497                 int precise = 0;
498
499                 /* Support for constant skid */
500                 if (x86_pmu.pebs_active) {
501                         precise++;
502
503                         /* Support for IP fixup */
504                         if (x86_pmu.lbr_nr)
505                                 precise++;
506                 }
507
508                 if (event->attr.precise_ip > precise)
509                         return -EOPNOTSUPP;
510         }
511
512         /*
513          * Generate PMC IRQs:
514          * (keep 'enabled' bit clear for now)
515          */
516         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
517
518         /*
519          * Count user and OS events unless requested not to
520          */
521         if (!event->attr.exclude_user)
522                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
523         if (!event->attr.exclude_kernel)
524                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
525
526         if (event->attr.type == PERF_TYPE_RAW)
527                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
528
529         return x86_setup_perfctr(event);
530 }
531
532 /*
533  * Setup the hardware configuration for a given attr_type
534  */
535 static int __x86_pmu_event_init(struct perf_event *event)
536 {
537         int err;
538
539         if (!x86_pmu_initialized())
540                 return -ENODEV;
541
542         err = 0;
543         if (!atomic_inc_not_zero(&active_events)) {
544                 mutex_lock(&pmc_reserve_mutex);
545                 if (atomic_read(&active_events) == 0) {
546                         if (!reserve_pmc_hardware())
547                                 err = -EBUSY;
548                         else
549                                 reserve_ds_buffers();
550                 }
551                 if (!err)
552                         atomic_inc(&active_events);
553                 mutex_unlock(&pmc_reserve_mutex);
554         }
555         if (err)
556                 return err;
557
558         event->destroy = hw_perf_event_destroy;
559
560         event->hw.idx = -1;
561         event->hw.last_cpu = -1;
562         event->hw.last_tag = ~0ULL;
563
564         return x86_pmu.hw_config(event);
565 }
566
567 static void x86_pmu_disable_all(void)
568 {
569         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
570         int idx;
571
572         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
573                 u64 val;
574
575                 if (!test_bit(idx, cpuc->active_mask))
576                         continue;
577                 rdmsrl(x86_pmu.eventsel + idx, val);
578                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
579                         continue;
580                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
581                 wrmsrl(x86_pmu.eventsel + idx, val);
582         }
583 }
584
585 static void x86_pmu_disable(struct pmu *pmu)
586 {
587         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
588
589         if (!x86_pmu_initialized())
590                 return;
591
592         if (!cpuc->enabled)
593                 return;
594
595         cpuc->n_added = 0;
596         cpuc->enabled = 0;
597         barrier();
598
599         x86_pmu.disable_all();
600 }
601
602 static void x86_pmu_enable_all(int added)
603 {
604         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
605         int idx;
606
607         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
608                 struct perf_event *event = cpuc->events[idx];
609                 u64 val;
610
611                 if (!test_bit(idx, cpuc->active_mask))
612                         continue;
613
614                 val = event->hw.config;
615                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
616                 wrmsrl(x86_pmu.eventsel + idx, val);
617         }
618 }
619
620 static struct pmu pmu;
621
622 static inline int is_x86_event(struct perf_event *event)
623 {
624         return event->pmu == &pmu;
625 }
626
627 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
628 {
629         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
630         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
631         int i, j, w, wmax, num = 0;
632         struct hw_perf_event *hwc;
633
634         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
635
636         for (i = 0; i < n; i++) {
637                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
638                 constraints[i] = c;
639         }
640
641         /*
642          * fastpath, try to reuse previous register
643          */
644         for (i = 0; i < n; i++) {
645                 hwc = &cpuc->event_list[i]->hw;
646                 c = constraints[i];
647
648                 /* never assigned */
649                 if (hwc->idx == -1)
650                         break;
651
652                 /* constraint still honored */
653                 if (!test_bit(hwc->idx, c->idxmsk))
654                         break;
655
656                 /* not already used */
657                 if (test_bit(hwc->idx, used_mask))
658                         break;
659
660                 __set_bit(hwc->idx, used_mask);
661                 if (assign)
662                         assign[i] = hwc->idx;
663         }
664         if (i == n)
665                 goto done;
666
667         /*
668          * begin slow path
669          */
670
671         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
672
673         /*
674          * weight = number of possible counters
675          *
676          * 1    = most constrained, only works on one counter
677          * wmax = least constrained, works on any counter
678          *
679          * assign events to counters starting with most
680          * constrained events.
681          */
682         wmax = x86_pmu.num_counters;
683
684         /*
685          * when fixed event counters are present,
686          * wmax is incremented by 1 to account
687          * for one more choice
688          */
689         if (x86_pmu.num_counters_fixed)
690                 wmax++;
691
692         for (w = 1, num = n; num && w <= wmax; w++) {
693                 /* for each event */
694                 for (i = 0; num && i < n; i++) {
695                         c = constraints[i];
696                         hwc = &cpuc->event_list[i]->hw;
697
698                         if (c->weight != w)
699                                 continue;
700
701                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
702                                 if (!test_bit(j, used_mask))
703                                         break;
704                         }
705
706                         if (j == X86_PMC_IDX_MAX)
707                                 break;
708
709                         __set_bit(j, used_mask);
710
711                         if (assign)
712                                 assign[i] = j;
713                         num--;
714                 }
715         }
716 done:
717         /*
718          * scheduling failed or is just a simulation,
719          * free resources if necessary
720          */
721         if (!assign || num) {
722                 for (i = 0; i < n; i++) {
723                         if (x86_pmu.put_event_constraints)
724                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
725                 }
726         }
727         return num ? -ENOSPC : 0;
728 }
729
730 /*
731  * dogrp: true if must collect siblings events (group)
732  * returns total number of events and error code
733  */
734 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
735 {
736         struct perf_event *event;
737         int n, max_count;
738
739         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
740
741         /* current number of events already accepted */
742         n = cpuc->n_events;
743
744         if (is_x86_event(leader)) {
745                 if (n >= max_count)
746                         return -ENOSPC;
747                 cpuc->event_list[n] = leader;
748                 n++;
749         }
750         if (!dogrp)
751                 return n;
752
753         list_for_each_entry(event, &leader->sibling_list, group_entry) {
754                 if (!is_x86_event(event) ||
755                     event->state <= PERF_EVENT_STATE_OFF)
756                         continue;
757
758                 if (n >= max_count)
759                         return -ENOSPC;
760
761                 cpuc->event_list[n] = event;
762                 n++;
763         }
764         return n;
765 }
766
767 static inline void x86_assign_hw_event(struct perf_event *event,
768                                 struct cpu_hw_events *cpuc, int i)
769 {
770         struct hw_perf_event *hwc = &event->hw;
771
772         hwc->idx = cpuc->assign[i];
773         hwc->last_cpu = smp_processor_id();
774         hwc->last_tag = ++cpuc->tags[i];
775
776         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
777                 hwc->config_base = 0;
778                 hwc->event_base = 0;
779         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
780                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
781                 /*
782                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
783                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
784                  */
785                 hwc->event_base =
786                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
787         } else {
788                 hwc->config_base = x86_pmu.eventsel;
789                 hwc->event_base  = x86_pmu.perfctr;
790         }
791 }
792
793 static inline int match_prev_assignment(struct hw_perf_event *hwc,
794                                         struct cpu_hw_events *cpuc,
795                                         int i)
796 {
797         return hwc->idx == cpuc->assign[i] &&
798                 hwc->last_cpu == smp_processor_id() &&
799                 hwc->last_tag == cpuc->tags[i];
800 }
801
802 static void x86_pmu_start(struct perf_event *event, int flags);
803 static void x86_pmu_stop(struct perf_event *event, int flags);
804
805 static void x86_pmu_enable(struct pmu *pmu)
806 {
807         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
808         struct perf_event *event;
809         struct hw_perf_event *hwc;
810         int i, added = cpuc->n_added;
811
812         if (!x86_pmu_initialized())
813                 return;
814
815         if (cpuc->enabled)
816                 return;
817
818         if (cpuc->n_added) {
819                 int n_running = cpuc->n_events - cpuc->n_added;
820                 /*
821                  * apply assignment obtained either from
822                  * hw_perf_group_sched_in() or x86_pmu_enable()
823                  *
824                  * step1: save events moving to new counters
825                  * step2: reprogram moved events into new counters
826                  */
827                 for (i = 0; i < n_running; i++) {
828                         event = cpuc->event_list[i];
829                         hwc = &event->hw;
830
831                         /*
832                          * we can avoid reprogramming counter if:
833                          * - assigned same counter as last time
834                          * - running on same CPU as last time
835                          * - no other event has used the counter since
836                          */
837                         if (hwc->idx == -1 ||
838                             match_prev_assignment(hwc, cpuc, i))
839                                 continue;
840
841                         /*
842                          * Ensure we don't accidentally enable a stopped
843                          * counter simply because we rescheduled.
844                          */
845                         if (hwc->state & PERF_HES_STOPPED)
846                                 hwc->state |= PERF_HES_ARCH;
847
848                         x86_pmu_stop(event, PERF_EF_UPDATE);
849                 }
850
851                 for (i = 0; i < cpuc->n_events; i++) {
852                         event = cpuc->event_list[i];
853                         hwc = &event->hw;
854
855                         if (!match_prev_assignment(hwc, cpuc, i))
856                                 x86_assign_hw_event(event, cpuc, i);
857                         else if (i < n_running)
858                                 continue;
859
860                         if (hwc->state & PERF_HES_ARCH)
861                                 continue;
862
863                         x86_pmu_start(event, PERF_EF_RELOAD);
864                 }
865                 cpuc->n_added = 0;
866                 perf_events_lapic_init();
867         }
868
869         cpuc->enabled = 1;
870         barrier();
871
872         x86_pmu.enable_all(added);
873 }
874
875 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
876                                           u64 enable_mask)
877 {
878         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
879 }
880
881 static inline void x86_pmu_disable_event(struct perf_event *event)
882 {
883         struct hw_perf_event *hwc = &event->hw;
884
885         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
886 }
887
888 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
889
890 /*
891  * Set the next IRQ period, based on the hwc->period_left value.
892  * To be called with the event disabled in hw:
893  */
894 static int
895 x86_perf_event_set_period(struct perf_event *event)
896 {
897         struct hw_perf_event *hwc = &event->hw;
898         s64 left = local64_read(&hwc->period_left);
899         s64 period = hwc->sample_period;
900         int ret = 0, idx = hwc->idx;
901
902         if (idx == X86_PMC_IDX_FIXED_BTS)
903                 return 0;
904
905         /*
906          * If we are way outside a reasonable range then just skip forward:
907          */
908         if (unlikely(left <= -period)) {
909                 left = period;
910                 local64_set(&hwc->period_left, left);
911                 hwc->last_period = period;
912                 ret = 1;
913         }
914
915         if (unlikely(left <= 0)) {
916                 left += period;
917                 local64_set(&hwc->period_left, left);
918                 hwc->last_period = period;
919                 ret = 1;
920         }
921         /*
922          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
923          */
924         if (unlikely(left < 2))
925                 left = 2;
926
927         if (left > x86_pmu.max_period)
928                 left = x86_pmu.max_period;
929
930         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
931
932         /*
933          * The hw event starts counting from this event offset,
934          * mark it to be able to extra future deltas:
935          */
936         local64_set(&hwc->prev_count, (u64)-left);
937
938         wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
939
940         /*
941          * Due to erratum on certan cpu we need
942          * a second write to be sure the register
943          * is updated properly
944          */
945         if (x86_pmu.perfctr_second_write) {
946                 wrmsrl(hwc->event_base + idx,
947                         (u64)(-left) & x86_pmu.cntval_mask);
948         }
949
950         perf_event_update_userpage(event);
951
952         return ret;
953 }
954
955 static void x86_pmu_enable_event(struct perf_event *event)
956 {
957         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
958         if (cpuc->enabled)
959                 __x86_pmu_enable_event(&event->hw,
960                                        ARCH_PERFMON_EVENTSEL_ENABLE);
961 }
962
963 /*
964  * Add a single event to the PMU.
965  *
966  * The event is added to the group of enabled events
967  * but only if it can be scehduled with existing events.
968  */
969 static int x86_pmu_add(struct perf_event *event, int flags)
970 {
971         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
972         struct hw_perf_event *hwc;
973         int assign[X86_PMC_IDX_MAX];
974         int n, n0, ret;
975
976         hwc = &event->hw;
977
978         perf_pmu_disable(event->pmu);
979         n0 = cpuc->n_events;
980         ret = n = collect_events(cpuc, event, false);
981         if (ret < 0)
982                 goto out;
983
984         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
985         if (!(flags & PERF_EF_START))
986                 hwc->state |= PERF_HES_ARCH;
987
988         /*
989          * If group events scheduling transaction was started,
990          * skip the schedulability test here, it will be peformed
991          * at commit time (->commit_txn) as a whole
992          */
993         if (cpuc->group_flag & PERF_EVENT_TXN)
994                 goto done_collect;
995
996         ret = x86_pmu.schedule_events(cpuc, n, assign);
997         if (ret)
998                 goto out;
999         /*
1000          * copy new assignment, now we know it is possible
1001          * will be used by hw_perf_enable()
1002          */
1003         memcpy(cpuc->assign, assign, n*sizeof(int));
1004
1005 done_collect:
1006         cpuc->n_events = n;
1007         cpuc->n_added += n - n0;
1008         cpuc->n_txn += n - n0;
1009
1010         ret = 0;
1011 out:
1012         perf_pmu_enable(event->pmu);
1013         return ret;
1014 }
1015
1016 static void x86_pmu_start(struct perf_event *event, int flags)
1017 {
1018         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1019         int idx = event->hw.idx;
1020
1021         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1022                 return;
1023
1024         if (WARN_ON_ONCE(idx == -1))
1025                 return;
1026
1027         if (flags & PERF_EF_RELOAD) {
1028                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1029                 x86_perf_event_set_period(event);
1030         }
1031
1032         event->hw.state = 0;
1033
1034         cpuc->events[idx] = event;
1035         __set_bit(idx, cpuc->active_mask);
1036         __set_bit(idx, cpuc->running);
1037         x86_pmu.enable(event);
1038         perf_event_update_userpage(event);
1039 }
1040
1041 void perf_event_print_debug(void)
1042 {
1043         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1044         u64 pebs;
1045         struct cpu_hw_events *cpuc;
1046         unsigned long flags;
1047         int cpu, idx;
1048
1049         if (!x86_pmu.num_counters)
1050                 return;
1051
1052         local_irq_save(flags);
1053
1054         cpu = smp_processor_id();
1055         cpuc = &per_cpu(cpu_hw_events, cpu);
1056
1057         if (x86_pmu.version >= 2) {
1058                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1059                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1060                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1061                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1062                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1063
1064                 pr_info("\n");
1065                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1066                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1067                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1068                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1069                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1070         }
1071         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1072
1073         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1074                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1075                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1076
1077                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1078
1079                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1080                         cpu, idx, pmc_ctrl);
1081                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1082                         cpu, idx, pmc_count);
1083                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1084                         cpu, idx, prev_left);
1085         }
1086         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1087                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1088
1089                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1090                         cpu, idx, pmc_count);
1091         }
1092         local_irq_restore(flags);
1093 }
1094
1095 static void x86_pmu_stop(struct perf_event *event, int flags)
1096 {
1097         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1098         struct hw_perf_event *hwc = &event->hw;
1099
1100         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1101                 x86_pmu.disable(event);
1102                 cpuc->events[hwc->idx] = NULL;
1103                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1104                 hwc->state |= PERF_HES_STOPPED;
1105         }
1106
1107         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1108                 /*
1109                  * Drain the remaining delta count out of a event
1110                  * that we are disabling:
1111                  */
1112                 x86_perf_event_update(event);
1113                 hwc->state |= PERF_HES_UPTODATE;
1114         }
1115 }
1116
1117 static void x86_pmu_del(struct perf_event *event, int flags)
1118 {
1119         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1120         int i;
1121
1122         /*
1123          * If we're called during a txn, we don't need to do anything.
1124          * The events never got scheduled and ->cancel_txn will truncate
1125          * the event_list.
1126          */
1127         if (cpuc->group_flag & PERF_EVENT_TXN)
1128                 return;
1129
1130         x86_pmu_stop(event, PERF_EF_UPDATE);
1131
1132         for (i = 0; i < cpuc->n_events; i++) {
1133                 if (event == cpuc->event_list[i]) {
1134
1135                         if (x86_pmu.put_event_constraints)
1136                                 x86_pmu.put_event_constraints(cpuc, event);
1137
1138                         while (++i < cpuc->n_events)
1139                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1140
1141                         --cpuc->n_events;
1142                         break;
1143                 }
1144         }
1145         perf_event_update_userpage(event);
1146 }
1147
1148 static int x86_pmu_handle_irq(struct pt_regs *regs)
1149 {
1150         struct perf_sample_data data;
1151         struct cpu_hw_events *cpuc;
1152         struct perf_event *event;
1153         int idx, handled = 0;
1154         u64 val;
1155
1156         perf_sample_data_init(&data, 0);
1157
1158         cpuc = &__get_cpu_var(cpu_hw_events);
1159
1160         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1161                 if (!test_bit(idx, cpuc->active_mask)) {
1162                         /*
1163                          * Though we deactivated the counter some cpus
1164                          * might still deliver spurious interrupts still
1165                          * in flight. Catch them:
1166                          */
1167                         if (__test_and_clear_bit(idx, cpuc->running))
1168                                 handled++;
1169                         continue;
1170                 }
1171
1172                 event = cpuc->events[idx];
1173
1174                 val = x86_perf_event_update(event);
1175                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1176                         continue;
1177
1178                 /*
1179                  * event overflow
1180                  */
1181                 handled++;
1182                 data.period     = event->hw.last_period;
1183
1184                 if (!x86_perf_event_set_period(event))
1185                         continue;
1186
1187                 if (perf_event_overflow(event, 1, &data, regs))
1188                         x86_pmu_stop(event, 0);
1189         }
1190
1191         if (handled)
1192                 inc_irq_stat(apic_perf_irqs);
1193
1194         return handled;
1195 }
1196
1197 void perf_events_lapic_init(void)
1198 {
1199         if (!x86_pmu.apic || !x86_pmu_initialized())
1200                 return;
1201
1202         /*
1203          * Always use NMI for PMU
1204          */
1205         apic_write(APIC_LVTPC, APIC_DM_NMI);
1206 }
1207
1208 struct pmu_nmi_state {
1209         unsigned int    marked;
1210         int             handled;
1211 };
1212
1213 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1214
1215 static int __kprobes
1216 perf_event_nmi_handler(struct notifier_block *self,
1217                          unsigned long cmd, void *__args)
1218 {
1219         struct die_args *args = __args;
1220         unsigned int this_nmi;
1221         int handled;
1222
1223         if (!atomic_read(&active_events))
1224                 return NOTIFY_DONE;
1225
1226         switch (cmd) {
1227         case DIE_NMI:
1228         case DIE_NMI_IPI:
1229                 break;
1230         case DIE_NMIUNKNOWN:
1231                 this_nmi = percpu_read(irq_stat.__nmi_count);
1232                 if (this_nmi != __get_cpu_var(pmu_nmi).marked)
1233                         /* let the kernel handle the unknown nmi */
1234                         return NOTIFY_DONE;
1235                 /*
1236                  * This one is a PMU back-to-back nmi. Two events
1237                  * trigger 'simultaneously' raising two back-to-back
1238                  * NMIs. If the first NMI handles both, the latter
1239                  * will be empty and daze the CPU. So, we drop it to
1240                  * avoid false-positive 'unknown nmi' messages.
1241                  */
1242                 return NOTIFY_STOP;
1243         default:
1244                 return NOTIFY_DONE;
1245         }
1246
1247         apic_write(APIC_LVTPC, APIC_DM_NMI);
1248
1249         handled = x86_pmu.handle_irq(args->regs);
1250         if (!handled)
1251                 return NOTIFY_DONE;
1252
1253         this_nmi = percpu_read(irq_stat.__nmi_count);
1254         if ((handled > 1) ||
1255                 /* the next nmi could be a back-to-back nmi */
1256             ((__get_cpu_var(pmu_nmi).marked == this_nmi) &&
1257              (__get_cpu_var(pmu_nmi).handled > 1))) {
1258                 /*
1259                  * We could have two subsequent back-to-back nmis: The
1260                  * first handles more than one counter, the 2nd
1261                  * handles only one counter and the 3rd handles no
1262                  * counter.
1263                  *
1264                  * This is the 2nd nmi because the previous was
1265                  * handling more than one counter. We will mark the
1266                  * next (3rd) and then drop it if unhandled.
1267                  */
1268                 __get_cpu_var(pmu_nmi).marked   = this_nmi + 1;
1269                 __get_cpu_var(pmu_nmi).handled  = handled;
1270         }
1271
1272         return NOTIFY_STOP;
1273 }
1274
1275 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1276         .notifier_call          = perf_event_nmi_handler,
1277         .next                   = NULL,
1278         .priority               = 1
1279 };
1280
1281 static struct event_constraint unconstrained;
1282 static struct event_constraint emptyconstraint;
1283
1284 static struct event_constraint *
1285 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1286 {
1287         struct event_constraint *c;
1288
1289         if (x86_pmu.event_constraints) {
1290                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1291                         if ((event->hw.config & c->cmask) == c->code)
1292                                 return c;
1293                 }
1294         }
1295
1296         return &unconstrained;
1297 }
1298
1299 #include "perf_event_amd.c"
1300 #include "perf_event_p6.c"
1301 #include "perf_event_p4.c"
1302 #include "perf_event_intel_lbr.c"
1303 #include "perf_event_intel_ds.c"
1304 #include "perf_event_intel.c"
1305
1306 static int __cpuinit
1307 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1308 {
1309         unsigned int cpu = (long)hcpu;
1310         int ret = NOTIFY_OK;
1311
1312         switch (action & ~CPU_TASKS_FROZEN) {
1313         case CPU_UP_PREPARE:
1314                 if (x86_pmu.cpu_prepare)
1315                         ret = x86_pmu.cpu_prepare(cpu);
1316                 break;
1317
1318         case CPU_STARTING:
1319                 if (x86_pmu.cpu_starting)
1320                         x86_pmu.cpu_starting(cpu);
1321                 break;
1322
1323         case CPU_DYING:
1324                 if (x86_pmu.cpu_dying)
1325                         x86_pmu.cpu_dying(cpu);
1326                 break;
1327
1328         case CPU_UP_CANCELED:
1329         case CPU_DEAD:
1330                 if (x86_pmu.cpu_dead)
1331                         x86_pmu.cpu_dead(cpu);
1332                 break;
1333
1334         default:
1335                 break;
1336         }
1337
1338         return ret;
1339 }
1340
1341 static void __init pmu_check_apic(void)
1342 {
1343         if (cpu_has_apic)
1344                 return;
1345
1346         x86_pmu.apic = 0;
1347         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1348         pr_info("no hardware sampling interrupt available.\n");
1349 }
1350
1351 void __init init_hw_perf_events(void)
1352 {
1353         struct event_constraint *c;
1354         int err;
1355
1356         pr_info("Performance Events: ");
1357
1358         switch (boot_cpu_data.x86_vendor) {
1359         case X86_VENDOR_INTEL:
1360                 err = intel_pmu_init();
1361                 break;
1362         case X86_VENDOR_AMD:
1363                 err = amd_pmu_init();
1364                 break;
1365         default:
1366                 return;
1367         }
1368         if (err != 0) {
1369                 pr_cont("no PMU driver, software events only.\n");
1370                 return;
1371         }
1372
1373         pmu_check_apic();
1374
1375         pr_cont("%s PMU driver.\n", x86_pmu.name);
1376
1377         if (x86_pmu.quirks)
1378                 x86_pmu.quirks();
1379
1380         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1381                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1382                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1383                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1384         }
1385         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1386
1387         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1388                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1389                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1390                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1391         }
1392
1393         x86_pmu.intel_ctrl |=
1394                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1395
1396         perf_events_lapic_init();
1397         register_die_notifier(&perf_event_nmi_notifier);
1398
1399         unconstrained = (struct event_constraint)
1400                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1401                                    0, x86_pmu.num_counters);
1402
1403         if (x86_pmu.event_constraints) {
1404                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1405                         if (c->cmask != X86_RAW_EVENT_MASK)
1406                                 continue;
1407
1408                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1409                         c->weight += x86_pmu.num_counters;
1410                 }
1411         }
1412
1413         pr_info("... version:                %d\n",     x86_pmu.version);
1414         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1415         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1416         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1417         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1418         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1419         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1420
1421         perf_pmu_register(&pmu);
1422         perf_cpu_notifier(x86_pmu_notifier);
1423 }
1424
1425 static inline void x86_pmu_read(struct perf_event *event)
1426 {
1427         x86_perf_event_update(event);
1428 }
1429
1430 /*
1431  * Start group events scheduling transaction
1432  * Set the flag to make pmu::enable() not perform the
1433  * schedulability test, it will be performed at commit time
1434  */
1435 static void x86_pmu_start_txn(struct pmu *pmu)
1436 {
1437         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1438
1439         perf_pmu_disable(pmu);
1440         cpuc->group_flag |= PERF_EVENT_TXN;
1441         cpuc->n_txn = 0;
1442 }
1443
1444 /*
1445  * Stop group events scheduling transaction
1446  * Clear the flag and pmu::enable() will perform the
1447  * schedulability test.
1448  */
1449 static void x86_pmu_cancel_txn(struct pmu *pmu)
1450 {
1451         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1452
1453         cpuc->group_flag &= ~PERF_EVENT_TXN;
1454         /*
1455          * Truncate the collected events.
1456          */
1457         cpuc->n_added -= cpuc->n_txn;
1458         cpuc->n_events -= cpuc->n_txn;
1459         perf_pmu_enable(pmu);
1460 }
1461
1462 /*
1463  * Commit group events scheduling transaction
1464  * Perform the group schedulability test as a whole
1465  * Return 0 if success
1466  */
1467 static int x86_pmu_commit_txn(struct pmu *pmu)
1468 {
1469         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1470         int assign[X86_PMC_IDX_MAX];
1471         int n, ret;
1472
1473         n = cpuc->n_events;
1474
1475         if (!x86_pmu_initialized())
1476                 return -EAGAIN;
1477
1478         ret = x86_pmu.schedule_events(cpuc, n, assign);
1479         if (ret)
1480                 return ret;
1481
1482         /*
1483          * copy new assignment, now we know it is possible
1484          * will be used by hw_perf_enable()
1485          */
1486         memcpy(cpuc->assign, assign, n*sizeof(int));
1487
1488         cpuc->group_flag &= ~PERF_EVENT_TXN;
1489         perf_pmu_enable(pmu);
1490         return 0;
1491 }
1492
1493 /*
1494  * validate that we can schedule this event
1495  */
1496 static int validate_event(struct perf_event *event)
1497 {
1498         struct cpu_hw_events *fake_cpuc;
1499         struct event_constraint *c;
1500         int ret = 0;
1501
1502         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1503         if (!fake_cpuc)
1504                 return -ENOMEM;
1505
1506         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1507
1508         if (!c || !c->weight)
1509                 ret = -ENOSPC;
1510
1511         if (x86_pmu.put_event_constraints)
1512                 x86_pmu.put_event_constraints(fake_cpuc, event);
1513
1514         kfree(fake_cpuc);
1515
1516         return ret;
1517 }
1518
1519 /*
1520  * validate a single event group
1521  *
1522  * validation include:
1523  *      - check events are compatible which each other
1524  *      - events do not compete for the same counter
1525  *      - number of events <= number of counters
1526  *
1527  * validation ensures the group can be loaded onto the
1528  * PMU if it was the only group available.
1529  */
1530 static int validate_group(struct perf_event *event)
1531 {
1532         struct perf_event *leader = event->group_leader;
1533         struct cpu_hw_events *fake_cpuc;
1534         int ret, n;
1535
1536         ret = -ENOMEM;
1537         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1538         if (!fake_cpuc)
1539                 goto out;
1540
1541         /*
1542          * the event is not yet connected with its
1543          * siblings therefore we must first collect
1544          * existing siblings, then add the new event
1545          * before we can simulate the scheduling
1546          */
1547         ret = -ENOSPC;
1548         n = collect_events(fake_cpuc, leader, true);
1549         if (n < 0)
1550                 goto out_free;
1551
1552         fake_cpuc->n_events = n;
1553         n = collect_events(fake_cpuc, event, false);
1554         if (n < 0)
1555                 goto out_free;
1556
1557         fake_cpuc->n_events = n;
1558
1559         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1560
1561 out_free:
1562         kfree(fake_cpuc);
1563 out:
1564         return ret;
1565 }
1566
1567 int x86_pmu_event_init(struct perf_event *event)
1568 {
1569         struct pmu *tmp;
1570         int err;
1571
1572         switch (event->attr.type) {
1573         case PERF_TYPE_RAW:
1574         case PERF_TYPE_HARDWARE:
1575         case PERF_TYPE_HW_CACHE:
1576                 break;
1577
1578         default:
1579                 return -ENOENT;
1580         }
1581
1582         err = __x86_pmu_event_init(event);
1583         if (!err) {
1584                 /*
1585                  * we temporarily connect event to its pmu
1586                  * such that validate_group() can classify
1587                  * it as an x86 event using is_x86_event()
1588                  */
1589                 tmp = event->pmu;
1590                 event->pmu = &pmu;
1591
1592                 if (event->group_leader != event)
1593                         err = validate_group(event);
1594                 else
1595                         err = validate_event(event);
1596
1597                 event->pmu = tmp;
1598         }
1599         if (err) {
1600                 if (event->destroy)
1601                         event->destroy(event);
1602         }
1603
1604         return err;
1605 }
1606
1607 static struct pmu pmu = {
1608         .pmu_enable     = x86_pmu_enable,
1609         .pmu_disable    = x86_pmu_disable,
1610
1611         .event_init     = x86_pmu_event_init,
1612
1613         .add            = x86_pmu_add,
1614         .del            = x86_pmu_del,
1615         .start          = x86_pmu_start,
1616         .stop           = x86_pmu_stop,
1617         .read           = x86_pmu_read,
1618
1619         .start_txn      = x86_pmu_start_txn,
1620         .cancel_txn     = x86_pmu_cancel_txn,
1621         .commit_txn     = x86_pmu_commit_txn,
1622 };
1623
1624 /*
1625  * callchain support
1626  */
1627
1628 static void
1629 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1630 {
1631         /* Ignore warnings */
1632 }
1633
1634 static void backtrace_warning(void *data, char *msg)
1635 {
1636         /* Ignore warnings */
1637 }
1638
1639 static int backtrace_stack(void *data, char *name)
1640 {
1641         return 0;
1642 }
1643
1644 static void backtrace_address(void *data, unsigned long addr, int reliable)
1645 {
1646         struct perf_callchain_entry *entry = data;
1647
1648         perf_callchain_store(entry, addr);
1649 }
1650
1651 static const struct stacktrace_ops backtrace_ops = {
1652         .warning                = backtrace_warning,
1653         .warning_symbol         = backtrace_warning_symbol,
1654         .stack                  = backtrace_stack,
1655         .address                = backtrace_address,
1656         .walk_stack             = print_context_stack_bp,
1657 };
1658
1659 void
1660 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1661 {
1662         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1663                 /* TODO: We don't support guest os callchain now */
1664                 return;
1665         }
1666
1667         perf_callchain_store(entry, regs->ip);
1668
1669         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1670 }
1671
1672 #ifdef CONFIG_COMPAT
1673 static inline int
1674 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1675 {
1676         /* 32-bit process in 64-bit kernel. */
1677         struct stack_frame_ia32 frame;
1678         const void __user *fp;
1679
1680         if (!test_thread_flag(TIF_IA32))
1681                 return 0;
1682
1683         fp = compat_ptr(regs->bp);
1684         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1685                 unsigned long bytes;
1686                 frame.next_frame     = 0;
1687                 frame.return_address = 0;
1688
1689                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1690                 if (bytes != sizeof(frame))
1691                         break;
1692
1693                 if (fp < compat_ptr(regs->sp))
1694                         break;
1695
1696                 perf_callchain_store(entry, frame.return_address);
1697                 fp = compat_ptr(frame.next_frame);
1698         }
1699         return 1;
1700 }
1701 #else
1702 static inline int
1703 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1704 {
1705     return 0;
1706 }
1707 #endif
1708
1709 void
1710 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1711 {
1712         struct stack_frame frame;
1713         const void __user *fp;
1714
1715         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1716                 /* TODO: We don't support guest os callchain now */
1717                 return;
1718         }
1719
1720         fp = (void __user *)regs->bp;
1721
1722         perf_callchain_store(entry, regs->ip);
1723
1724         if (perf_callchain_user32(regs, entry))
1725                 return;
1726
1727         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1728                 unsigned long bytes;
1729                 frame.next_frame             = NULL;
1730                 frame.return_address = 0;
1731
1732                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1733                 if (bytes != sizeof(frame))
1734                         break;
1735
1736                 if ((unsigned long)fp < regs->sp)
1737                         break;
1738
1739                 perf_callchain_store(entry, frame.return_address);
1740                 fp = frame.next_frame;
1741         }
1742 }
1743
1744 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1745 {
1746         unsigned long ip;
1747
1748         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1749                 ip = perf_guest_cbs->get_guest_ip();
1750         else
1751                 ip = instruction_pointer(regs);
1752
1753         return ip;
1754 }
1755
1756 unsigned long perf_misc_flags(struct pt_regs *regs)
1757 {
1758         int misc = 0;
1759
1760         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1761                 if (perf_guest_cbs->is_user_mode())
1762                         misc |= PERF_RECORD_MISC_GUEST_USER;
1763                 else
1764                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1765         } else {
1766                 if (user_mode(regs))
1767                         misc |= PERF_RECORD_MISC_USER;
1768                 else
1769                         misc |= PERF_RECORD_MISC_KERNEL;
1770         }
1771
1772         if (regs->flags & PERF_EFLAGS_EXACT)
1773                 misc |= PERF_RECORD_MISC_EXACT_IP;
1774
1775         return misc;
1776 }