cf10839f20ea4814999b13812fa9c97db9cdb110
[linux-2.6.git] / arch / x86 / kernel / cpu / perf_event.c
1 /*
2  * Performance events x86 architecture code
3  *
4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6  *  Copyright (C) 2009 Jaswinder Singh Rajput
7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
11  *
12  *  For licencing details see kernel-base/COPYING
13  */
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27
28 #include <asm/apic.h>
29 #include <asm/stacktrace.h>
30 #include <asm/nmi.h>
31
32 static u64 perf_event_mask __read_mostly;
33
34 /* The maximal number of PEBS events: */
35 #define MAX_PEBS_EVENTS 4
36
37 /* The size of a BTS record in bytes: */
38 #define BTS_RECORD_SIZE         24
39
40 /* The size of a per-cpu BTS buffer in bytes: */
41 #define BTS_BUFFER_SIZE         (BTS_RECORD_SIZE * 2048)
42
43 /* The BTS overflow threshold in bytes from the end of the buffer: */
44 #define BTS_OVFL_TH             (BTS_RECORD_SIZE * 128)
45
46
47 /*
48  * Bits in the debugctlmsr controlling branch tracing.
49  */
50 #define X86_DEBUGCTL_TR                 (1 << 6)
51 #define X86_DEBUGCTL_BTS                (1 << 7)
52 #define X86_DEBUGCTL_BTINT              (1 << 8)
53 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
54 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
55
56 /*
57  * A debug store configuration.
58  *
59  * We only support architectures that use 64bit fields.
60  */
61 struct debug_store {
62         u64     bts_buffer_base;
63         u64     bts_index;
64         u64     bts_absolute_maximum;
65         u64     bts_interrupt_threshold;
66         u64     pebs_buffer_base;
67         u64     pebs_index;
68         u64     pebs_absolute_maximum;
69         u64     pebs_interrupt_threshold;
70         u64     pebs_event_reset[MAX_PEBS_EVENTS];
71 };
72
73 struct event_constraint {
74         union {
75                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
76                 u64             idxmsk64[1];
77         };
78         int     code;
79         int     cmask;
80         int     weight;
81 };
82
83 struct cpu_hw_events {
84         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
85         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
86         unsigned long           interrupts;
87         int                     enabled;
88         struct debug_store      *ds;
89
90         int                     n_events;
91         int                     n_added;
92         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
93         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
94 };
95
96 #define EVENT_CONSTRAINT(c, n, m) {     \
97         { .idxmsk64[0] = (n) },         \
98         .code = (c),                    \
99         .cmask = (m),                   \
100         .weight = HWEIGHT64((u64)(n)),  \
101 }
102
103 #define INTEL_EVENT_CONSTRAINT(c, n)    \
104         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
105
106 #define FIXED_EVENT_CONSTRAINT(c, n)    \
107         EVENT_CONSTRAINT(c, n, INTEL_ARCH_FIXED_MASK)
108
109 #define EVENT_CONSTRAINT_END            \
110         EVENT_CONSTRAINT(0, 0, 0)
111
112 #define for_each_event_constraint(e, c) \
113         for ((e) = (c); (e)->cmask; (e)++)
114
115 /*
116  * struct x86_pmu - generic x86 pmu
117  */
118 struct x86_pmu {
119         const char      *name;
120         int             version;
121         int             (*handle_irq)(struct pt_regs *);
122         void            (*disable_all)(void);
123         void            (*enable_all)(void);
124         void            (*enable)(struct hw_perf_event *, int);
125         void            (*disable)(struct hw_perf_event *, int);
126         unsigned        eventsel;
127         unsigned        perfctr;
128         u64             (*event_map)(int);
129         u64             (*raw_event)(u64);
130         int             max_events;
131         int             num_events;
132         int             num_events_fixed;
133         int             event_bits;
134         u64             event_mask;
135         int             apic;
136         u64             max_period;
137         u64             intel_ctrl;
138         void            (*enable_bts)(u64 config);
139         void            (*disable_bts)(void);
140
141         struct event_constraint *
142                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
143                                                  struct perf_event *event);
144
145         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
146                                                  struct perf_event *event);
147         struct event_constraint *event_constraints;
148 };
149
150 static struct x86_pmu x86_pmu __read_mostly;
151
152 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
153         .enabled = 1,
154 };
155
156 static int x86_perf_event_set_period(struct perf_event *event,
157                              struct hw_perf_event *hwc, int idx);
158
159 /*
160  * Not sure about some of these
161  */
162 static const u64 p6_perfmon_event_map[] =
163 {
164   [PERF_COUNT_HW_CPU_CYCLES]            = 0x0079,
165   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
166   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0f2e,
167   [PERF_COUNT_HW_CACHE_MISSES]          = 0x012e,
168   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
169   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
170   [PERF_COUNT_HW_BUS_CYCLES]            = 0x0062,
171 };
172
173 static u64 p6_pmu_event_map(int hw_event)
174 {
175         return p6_perfmon_event_map[hw_event];
176 }
177
178 /*
179  * Event setting that is specified not to count anything.
180  * We use this to effectively disable a counter.
181  *
182  * L2_RQSTS with 0 MESI unit mask.
183  */
184 #define P6_NOP_EVENT                    0x0000002EULL
185
186 static u64 p6_pmu_raw_event(u64 hw_event)
187 {
188 #define P6_EVNTSEL_EVENT_MASK           0x000000FFULL
189 #define P6_EVNTSEL_UNIT_MASK            0x0000FF00ULL
190 #define P6_EVNTSEL_EDGE_MASK            0x00040000ULL
191 #define P6_EVNTSEL_INV_MASK             0x00800000ULL
192 #define P6_EVNTSEL_REG_MASK             0xFF000000ULL
193
194 #define P6_EVNTSEL_MASK                 \
195         (P6_EVNTSEL_EVENT_MASK |        \
196          P6_EVNTSEL_UNIT_MASK  |        \
197          P6_EVNTSEL_EDGE_MASK  |        \
198          P6_EVNTSEL_INV_MASK   |        \
199          P6_EVNTSEL_REG_MASK)
200
201         return hw_event & P6_EVNTSEL_MASK;
202 }
203
204 static struct event_constraint intel_p6_event_constraints[] =
205 {
206         INTEL_EVENT_CONSTRAINT(0xc1, 0x1),      /* FLOPS */
207         INTEL_EVENT_CONSTRAINT(0x10, 0x1),      /* FP_COMP_OPS_EXE */
208         INTEL_EVENT_CONSTRAINT(0x11, 0x1),      /* FP_ASSIST */
209         INTEL_EVENT_CONSTRAINT(0x12, 0x2),      /* MUL */
210         INTEL_EVENT_CONSTRAINT(0x13, 0x2),      /* DIV */
211         INTEL_EVENT_CONSTRAINT(0x14, 0x1),      /* CYCLES_DIV_BUSY */
212         EVENT_CONSTRAINT_END
213 };
214
215 /*
216  * Intel PerfMon v3. Used on Core2 and later.
217  */
218 static const u64 intel_perfmon_event_map[] =
219 {
220   [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
221   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
222   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
223   [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
224   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
225   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
226   [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
227 };
228
229 static struct event_constraint intel_core_event_constraints[] =
230 {
231         FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
232         FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
233         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
234         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
235         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
236         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
237         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
238         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
239         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
240         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
241         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
242         EVENT_CONSTRAINT_END
243 };
244
245 static struct event_constraint intel_nehalem_event_constraints[] =
246 {
247         FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
248         FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
249         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
250         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
251         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
252         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
253         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
254         INTEL_EVENT_CONSTRAINT(0x4c, 0x3), /* LOAD_HIT_PRE */
255         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
256         INTEL_EVENT_CONSTRAINT(0x52, 0x3), /* L1D_CACHE_PREFETCH_LOCK_FB_HIT */
257         INTEL_EVENT_CONSTRAINT(0x53, 0x3), /* L1D_CACHE_LOCK_FB_HIT */
258         INTEL_EVENT_CONSTRAINT(0xc5, 0x3), /* CACHE_LOCK_CYCLES */
259         EVENT_CONSTRAINT_END
260 };
261
262 static struct event_constraint intel_gen_event_constraints[] =
263 {
264         FIXED_EVENT_CONSTRAINT(0xc0, (0x3|(1ULL<<32))), /* INSTRUCTIONS_RETIRED */
265         FIXED_EVENT_CONSTRAINT(0x3c, (0x3|(1ULL<<33))), /* UNHALTED_CORE_CYCLES */
266         EVENT_CONSTRAINT_END
267 };
268
269 static u64 intel_pmu_event_map(int hw_event)
270 {
271         return intel_perfmon_event_map[hw_event];
272 }
273
274 /*
275  * Generalized hw caching related hw_event table, filled
276  * in on a per model basis. A value of 0 means
277  * 'not supported', -1 means 'hw_event makes no sense on
278  * this CPU', any other value means the raw hw_event
279  * ID.
280  */
281
282 #define C(x) PERF_COUNT_HW_CACHE_##x
283
284 static u64 __read_mostly hw_cache_event_ids
285                                 [PERF_COUNT_HW_CACHE_MAX]
286                                 [PERF_COUNT_HW_CACHE_OP_MAX]
287                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
288
289 static __initconst u64 nehalem_hw_cache_event_ids
290                                 [PERF_COUNT_HW_CACHE_MAX]
291                                 [PERF_COUNT_HW_CACHE_OP_MAX]
292                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
293 {
294  [ C(L1D) ] = {
295         [ C(OP_READ) ] = {
296                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI            */
297                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE         */
298         },
299         [ C(OP_WRITE) ] = {
300                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI            */
301                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE         */
302         },
303         [ C(OP_PREFETCH) ] = {
304                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
305                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
306         },
307  },
308  [ C(L1I ) ] = {
309         [ C(OP_READ) ] = {
310                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
311                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
312         },
313         [ C(OP_WRITE) ] = {
314                 [ C(RESULT_ACCESS) ] = -1,
315                 [ C(RESULT_MISS)   ] = -1,
316         },
317         [ C(OP_PREFETCH) ] = {
318                 [ C(RESULT_ACCESS) ] = 0x0,
319                 [ C(RESULT_MISS)   ] = 0x0,
320         },
321  },
322  [ C(LL  ) ] = {
323         [ C(OP_READ) ] = {
324                 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
325                 [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
326         },
327         [ C(OP_WRITE) ] = {
328                 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
329                 [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
330         },
331         [ C(OP_PREFETCH) ] = {
332                 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
333                 [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
334         },
335  },
336  [ C(DTLB) ] = {
337         [ C(OP_READ) ] = {
338                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
339                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
340         },
341         [ C(OP_WRITE) ] = {
342                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
343                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
344         },
345         [ C(OP_PREFETCH) ] = {
346                 [ C(RESULT_ACCESS) ] = 0x0,
347                 [ C(RESULT_MISS)   ] = 0x0,
348         },
349  },
350  [ C(ITLB) ] = {
351         [ C(OP_READ) ] = {
352                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
353                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
354         },
355         [ C(OP_WRITE) ] = {
356                 [ C(RESULT_ACCESS) ] = -1,
357                 [ C(RESULT_MISS)   ] = -1,
358         },
359         [ C(OP_PREFETCH) ] = {
360                 [ C(RESULT_ACCESS) ] = -1,
361                 [ C(RESULT_MISS)   ] = -1,
362         },
363  },
364  [ C(BPU ) ] = {
365         [ C(OP_READ) ] = {
366                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
367                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
368         },
369         [ C(OP_WRITE) ] = {
370                 [ C(RESULT_ACCESS) ] = -1,
371                 [ C(RESULT_MISS)   ] = -1,
372         },
373         [ C(OP_PREFETCH) ] = {
374                 [ C(RESULT_ACCESS) ] = -1,
375                 [ C(RESULT_MISS)   ] = -1,
376         },
377  },
378 };
379
380 static __initconst u64 core2_hw_cache_event_ids
381                                 [PERF_COUNT_HW_CACHE_MAX]
382                                 [PERF_COUNT_HW_CACHE_OP_MAX]
383                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
384 {
385  [ C(L1D) ] = {
386         [ C(OP_READ) ] = {
387                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
388                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
389         },
390         [ C(OP_WRITE) ] = {
391                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
392                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
393         },
394         [ C(OP_PREFETCH) ] = {
395                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
396                 [ C(RESULT_MISS)   ] = 0,
397         },
398  },
399  [ C(L1I ) ] = {
400         [ C(OP_READ) ] = {
401                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
402                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
403         },
404         [ C(OP_WRITE) ] = {
405                 [ C(RESULT_ACCESS) ] = -1,
406                 [ C(RESULT_MISS)   ] = -1,
407         },
408         [ C(OP_PREFETCH) ] = {
409                 [ C(RESULT_ACCESS) ] = 0,
410                 [ C(RESULT_MISS)   ] = 0,
411         },
412  },
413  [ C(LL  ) ] = {
414         [ C(OP_READ) ] = {
415                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
416                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
417         },
418         [ C(OP_WRITE) ] = {
419                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
420                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
421         },
422         [ C(OP_PREFETCH) ] = {
423                 [ C(RESULT_ACCESS) ] = 0,
424                 [ C(RESULT_MISS)   ] = 0,
425         },
426  },
427  [ C(DTLB) ] = {
428         [ C(OP_READ) ] = {
429                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
430                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
431         },
432         [ C(OP_WRITE) ] = {
433                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
434                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
435         },
436         [ C(OP_PREFETCH) ] = {
437                 [ C(RESULT_ACCESS) ] = 0,
438                 [ C(RESULT_MISS)   ] = 0,
439         },
440  },
441  [ C(ITLB) ] = {
442         [ C(OP_READ) ] = {
443                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
444                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
445         },
446         [ C(OP_WRITE) ] = {
447                 [ C(RESULT_ACCESS) ] = -1,
448                 [ C(RESULT_MISS)   ] = -1,
449         },
450         [ C(OP_PREFETCH) ] = {
451                 [ C(RESULT_ACCESS) ] = -1,
452                 [ C(RESULT_MISS)   ] = -1,
453         },
454  },
455  [ C(BPU ) ] = {
456         [ C(OP_READ) ] = {
457                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
458                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
459         },
460         [ C(OP_WRITE) ] = {
461                 [ C(RESULT_ACCESS) ] = -1,
462                 [ C(RESULT_MISS)   ] = -1,
463         },
464         [ C(OP_PREFETCH) ] = {
465                 [ C(RESULT_ACCESS) ] = -1,
466                 [ C(RESULT_MISS)   ] = -1,
467         },
468  },
469 };
470
471 static __initconst u64 atom_hw_cache_event_ids
472                                 [PERF_COUNT_HW_CACHE_MAX]
473                                 [PERF_COUNT_HW_CACHE_OP_MAX]
474                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
475 {
476  [ C(L1D) ] = {
477         [ C(OP_READ) ] = {
478                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
479                 [ C(RESULT_MISS)   ] = 0,
480         },
481         [ C(OP_WRITE) ] = {
482                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
483                 [ C(RESULT_MISS)   ] = 0,
484         },
485         [ C(OP_PREFETCH) ] = {
486                 [ C(RESULT_ACCESS) ] = 0x0,
487                 [ C(RESULT_MISS)   ] = 0,
488         },
489  },
490  [ C(L1I ) ] = {
491         [ C(OP_READ) ] = {
492                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
493                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
494         },
495         [ C(OP_WRITE) ] = {
496                 [ C(RESULT_ACCESS) ] = -1,
497                 [ C(RESULT_MISS)   ] = -1,
498         },
499         [ C(OP_PREFETCH) ] = {
500                 [ C(RESULT_ACCESS) ] = 0,
501                 [ C(RESULT_MISS)   ] = 0,
502         },
503  },
504  [ C(LL  ) ] = {
505         [ C(OP_READ) ] = {
506                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
507                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
508         },
509         [ C(OP_WRITE) ] = {
510                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
511                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
512         },
513         [ C(OP_PREFETCH) ] = {
514                 [ C(RESULT_ACCESS) ] = 0,
515                 [ C(RESULT_MISS)   ] = 0,
516         },
517  },
518  [ C(DTLB) ] = {
519         [ C(OP_READ) ] = {
520                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
521                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
522         },
523         [ C(OP_WRITE) ] = {
524                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
525                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
526         },
527         [ C(OP_PREFETCH) ] = {
528                 [ C(RESULT_ACCESS) ] = 0,
529                 [ C(RESULT_MISS)   ] = 0,
530         },
531  },
532  [ C(ITLB) ] = {
533         [ C(OP_READ) ] = {
534                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
535                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
536         },
537         [ C(OP_WRITE) ] = {
538                 [ C(RESULT_ACCESS) ] = -1,
539                 [ C(RESULT_MISS)   ] = -1,
540         },
541         [ C(OP_PREFETCH) ] = {
542                 [ C(RESULT_ACCESS) ] = -1,
543                 [ C(RESULT_MISS)   ] = -1,
544         },
545  },
546  [ C(BPU ) ] = {
547         [ C(OP_READ) ] = {
548                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
549                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
550         },
551         [ C(OP_WRITE) ] = {
552                 [ C(RESULT_ACCESS) ] = -1,
553                 [ C(RESULT_MISS)   ] = -1,
554         },
555         [ C(OP_PREFETCH) ] = {
556                 [ C(RESULT_ACCESS) ] = -1,
557                 [ C(RESULT_MISS)   ] = -1,
558         },
559  },
560 };
561
562 static u64 intel_pmu_raw_event(u64 hw_event)
563 {
564 #define CORE_EVNTSEL_EVENT_MASK         0x000000FFULL
565 #define CORE_EVNTSEL_UNIT_MASK          0x0000FF00ULL
566 #define CORE_EVNTSEL_EDGE_MASK          0x00040000ULL
567 #define CORE_EVNTSEL_INV_MASK           0x00800000ULL
568 #define CORE_EVNTSEL_REG_MASK           0xFF000000ULL
569
570 #define CORE_EVNTSEL_MASK               \
571         (INTEL_ARCH_EVTSEL_MASK |       \
572          INTEL_ARCH_UNIT_MASK   |       \
573          INTEL_ARCH_EDGE_MASK   |       \
574          INTEL_ARCH_INV_MASK    |       \
575          INTEL_ARCH_CNT_MASK)
576
577         return hw_event & CORE_EVNTSEL_MASK;
578 }
579
580 static __initconst u64 amd_hw_cache_event_ids
581                                 [PERF_COUNT_HW_CACHE_MAX]
582                                 [PERF_COUNT_HW_CACHE_OP_MAX]
583                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
584 {
585  [ C(L1D) ] = {
586         [ C(OP_READ) ] = {
587                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
588                 [ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
589         },
590         [ C(OP_WRITE) ] = {
591                 [ C(RESULT_ACCESS) ] = 0x0142, /* Data Cache Refills :system */
592                 [ C(RESULT_MISS)   ] = 0,
593         },
594         [ C(OP_PREFETCH) ] = {
595                 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */
596                 [ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */
597         },
598  },
599  [ C(L1I ) ] = {
600         [ C(OP_READ) ] = {
601                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */
602                 [ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */
603         },
604         [ C(OP_WRITE) ] = {
605                 [ C(RESULT_ACCESS) ] = -1,
606                 [ C(RESULT_MISS)   ] = -1,
607         },
608         [ C(OP_PREFETCH) ] = {
609                 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
610                 [ C(RESULT_MISS)   ] = 0,
611         },
612  },
613  [ C(LL  ) ] = {
614         [ C(OP_READ) ] = {
615                 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
616                 [ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */
617         },
618         [ C(OP_WRITE) ] = {
619                 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */
620                 [ C(RESULT_MISS)   ] = 0,
621         },
622         [ C(OP_PREFETCH) ] = {
623                 [ C(RESULT_ACCESS) ] = 0,
624                 [ C(RESULT_MISS)   ] = 0,
625         },
626  },
627  [ C(DTLB) ] = {
628         [ C(OP_READ) ] = {
629                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
630                 [ C(RESULT_MISS)   ] = 0x0046, /* L1 DTLB and L2 DLTB Miss   */
631         },
632         [ C(OP_WRITE) ] = {
633                 [ C(RESULT_ACCESS) ] = 0,
634                 [ C(RESULT_MISS)   ] = 0,
635         },
636         [ C(OP_PREFETCH) ] = {
637                 [ C(RESULT_ACCESS) ] = 0,
638                 [ C(RESULT_MISS)   ] = 0,
639         },
640  },
641  [ C(ITLB) ] = {
642         [ C(OP_READ) ] = {
643                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
644                 [ C(RESULT_MISS)   ] = 0x0085, /* Instr. fetch ITLB misses   */
645         },
646         [ C(OP_WRITE) ] = {
647                 [ C(RESULT_ACCESS) ] = -1,
648                 [ C(RESULT_MISS)   ] = -1,
649         },
650         [ C(OP_PREFETCH) ] = {
651                 [ C(RESULT_ACCESS) ] = -1,
652                 [ C(RESULT_MISS)   ] = -1,
653         },
654  },
655  [ C(BPU ) ] = {
656         [ C(OP_READ) ] = {
657                 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */
658                 [ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */
659         },
660         [ C(OP_WRITE) ] = {
661                 [ C(RESULT_ACCESS) ] = -1,
662                 [ C(RESULT_MISS)   ] = -1,
663         },
664         [ C(OP_PREFETCH) ] = {
665                 [ C(RESULT_ACCESS) ] = -1,
666                 [ C(RESULT_MISS)   ] = -1,
667         },
668  },
669 };
670
671 /*
672  * AMD Performance Monitor K7 and later.
673  */
674 static const u64 amd_perfmon_event_map[] =
675 {
676   [PERF_COUNT_HW_CPU_CYCLES]            = 0x0076,
677   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
678   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0080,
679   [PERF_COUNT_HW_CACHE_MISSES]          = 0x0081,
680   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
681   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
682 };
683
684 static u64 amd_pmu_event_map(int hw_event)
685 {
686         return amd_perfmon_event_map[hw_event];
687 }
688
689 static u64 amd_pmu_raw_event(u64 hw_event)
690 {
691 #define K7_EVNTSEL_EVENT_MASK   0x7000000FFULL
692 #define K7_EVNTSEL_UNIT_MASK    0x00000FF00ULL
693 #define K7_EVNTSEL_EDGE_MASK    0x000040000ULL
694 #define K7_EVNTSEL_INV_MASK     0x000800000ULL
695 #define K7_EVNTSEL_REG_MASK     0x0FF000000ULL
696
697 #define K7_EVNTSEL_MASK                 \
698         (K7_EVNTSEL_EVENT_MASK |        \
699          K7_EVNTSEL_UNIT_MASK  |        \
700          K7_EVNTSEL_EDGE_MASK  |        \
701          K7_EVNTSEL_INV_MASK   |        \
702          K7_EVNTSEL_REG_MASK)
703
704         return hw_event & K7_EVNTSEL_MASK;
705 }
706
707 /*
708  * Propagate event elapsed time into the generic event.
709  * Can only be executed on the CPU where the event is active.
710  * Returns the delta events processed.
711  */
712 static u64
713 x86_perf_event_update(struct perf_event *event,
714                         struct hw_perf_event *hwc, int idx)
715 {
716         int shift = 64 - x86_pmu.event_bits;
717         u64 prev_raw_count, new_raw_count;
718         s64 delta;
719
720         if (idx == X86_PMC_IDX_FIXED_BTS)
721                 return 0;
722
723         /*
724          * Careful: an NMI might modify the previous event value.
725          *
726          * Our tactic to handle this is to first atomically read and
727          * exchange a new raw count - then add that new-prev delta
728          * count to the generic event atomically:
729          */
730 again:
731         prev_raw_count = atomic64_read(&hwc->prev_count);
732         rdmsrl(hwc->event_base + idx, new_raw_count);
733
734         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
735                                         new_raw_count) != prev_raw_count)
736                 goto again;
737
738         /*
739          * Now we have the new raw value and have updated the prev
740          * timestamp already. We can now calculate the elapsed delta
741          * (event-)time and add that to the generic event.
742          *
743          * Careful, not all hw sign-extends above the physical width
744          * of the count.
745          */
746         delta = (new_raw_count << shift) - (prev_raw_count << shift);
747         delta >>= shift;
748
749         atomic64_add(delta, &event->count);
750         atomic64_sub(delta, &hwc->period_left);
751
752         return new_raw_count;
753 }
754
755 static atomic_t active_events;
756 static DEFINE_MUTEX(pmc_reserve_mutex);
757
758 static bool reserve_pmc_hardware(void)
759 {
760 #ifdef CONFIG_X86_LOCAL_APIC
761         int i;
762
763         if (nmi_watchdog == NMI_LOCAL_APIC)
764                 disable_lapic_nmi_watchdog();
765
766         for (i = 0; i < x86_pmu.num_events; i++) {
767                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
768                         goto perfctr_fail;
769         }
770
771         for (i = 0; i < x86_pmu.num_events; i++) {
772                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
773                         goto eventsel_fail;
774         }
775 #endif
776
777         return true;
778
779 #ifdef CONFIG_X86_LOCAL_APIC
780 eventsel_fail:
781         for (i--; i >= 0; i--)
782                 release_evntsel_nmi(x86_pmu.eventsel + i);
783
784         i = x86_pmu.num_events;
785
786 perfctr_fail:
787         for (i--; i >= 0; i--)
788                 release_perfctr_nmi(x86_pmu.perfctr + i);
789
790         if (nmi_watchdog == NMI_LOCAL_APIC)
791                 enable_lapic_nmi_watchdog();
792
793         return false;
794 #endif
795 }
796
797 static void release_pmc_hardware(void)
798 {
799 #ifdef CONFIG_X86_LOCAL_APIC
800         int i;
801
802         for (i = 0; i < x86_pmu.num_events; i++) {
803                 release_perfctr_nmi(x86_pmu.perfctr + i);
804                 release_evntsel_nmi(x86_pmu.eventsel + i);
805         }
806
807         if (nmi_watchdog == NMI_LOCAL_APIC)
808                 enable_lapic_nmi_watchdog();
809 #endif
810 }
811
812 static inline bool bts_available(void)
813 {
814         return x86_pmu.enable_bts != NULL;
815 }
816
817 static inline void init_debug_store_on_cpu(int cpu)
818 {
819         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
820
821         if (!ds)
822                 return;
823
824         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
825                      (u32)((u64)(unsigned long)ds),
826                      (u32)((u64)(unsigned long)ds >> 32));
827 }
828
829 static inline void fini_debug_store_on_cpu(int cpu)
830 {
831         if (!per_cpu(cpu_hw_events, cpu).ds)
832                 return;
833
834         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
835 }
836
837 static void release_bts_hardware(void)
838 {
839         int cpu;
840
841         if (!bts_available())
842                 return;
843
844         get_online_cpus();
845
846         for_each_online_cpu(cpu)
847                 fini_debug_store_on_cpu(cpu);
848
849         for_each_possible_cpu(cpu) {
850                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
851
852                 if (!ds)
853                         continue;
854
855                 per_cpu(cpu_hw_events, cpu).ds = NULL;
856
857                 kfree((void *)(unsigned long)ds->bts_buffer_base);
858                 kfree(ds);
859         }
860
861         put_online_cpus();
862 }
863
864 static int reserve_bts_hardware(void)
865 {
866         int cpu, err = 0;
867
868         if (!bts_available())
869                 return 0;
870
871         get_online_cpus();
872
873         for_each_possible_cpu(cpu) {
874                 struct debug_store *ds;
875                 void *buffer;
876
877                 err = -ENOMEM;
878                 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
879                 if (unlikely(!buffer))
880                         break;
881
882                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
883                 if (unlikely(!ds)) {
884                         kfree(buffer);
885                         break;
886                 }
887
888                 ds->bts_buffer_base = (u64)(unsigned long)buffer;
889                 ds->bts_index = ds->bts_buffer_base;
890                 ds->bts_absolute_maximum =
891                         ds->bts_buffer_base + BTS_BUFFER_SIZE;
892                 ds->bts_interrupt_threshold =
893                         ds->bts_absolute_maximum - BTS_OVFL_TH;
894
895                 per_cpu(cpu_hw_events, cpu).ds = ds;
896                 err = 0;
897         }
898
899         if (err)
900                 release_bts_hardware();
901         else {
902                 for_each_online_cpu(cpu)
903                         init_debug_store_on_cpu(cpu);
904         }
905
906         put_online_cpus();
907
908         return err;
909 }
910
911 static void hw_perf_event_destroy(struct perf_event *event)
912 {
913         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
914                 release_pmc_hardware();
915                 release_bts_hardware();
916                 mutex_unlock(&pmc_reserve_mutex);
917         }
918 }
919
920 static inline int x86_pmu_initialized(void)
921 {
922         return x86_pmu.handle_irq != NULL;
923 }
924
925 static inline int
926 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
927 {
928         unsigned int cache_type, cache_op, cache_result;
929         u64 config, val;
930
931         config = attr->config;
932
933         cache_type = (config >>  0) & 0xff;
934         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
935                 return -EINVAL;
936
937         cache_op = (config >>  8) & 0xff;
938         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
939                 return -EINVAL;
940
941         cache_result = (config >> 16) & 0xff;
942         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
943                 return -EINVAL;
944
945         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
946
947         if (val == 0)
948                 return -ENOENT;
949
950         if (val == -1)
951                 return -EINVAL;
952
953         hwc->config |= val;
954
955         return 0;
956 }
957
958 static void intel_pmu_enable_bts(u64 config)
959 {
960         unsigned long debugctlmsr;
961
962         debugctlmsr = get_debugctlmsr();
963
964         debugctlmsr |= X86_DEBUGCTL_TR;
965         debugctlmsr |= X86_DEBUGCTL_BTS;
966         debugctlmsr |= X86_DEBUGCTL_BTINT;
967
968         if (!(config & ARCH_PERFMON_EVENTSEL_OS))
969                 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
970
971         if (!(config & ARCH_PERFMON_EVENTSEL_USR))
972                 debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
973
974         update_debugctlmsr(debugctlmsr);
975 }
976
977 static void intel_pmu_disable_bts(void)
978 {
979         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
980         unsigned long debugctlmsr;
981
982         if (!cpuc->ds)
983                 return;
984
985         debugctlmsr = get_debugctlmsr();
986
987         debugctlmsr &=
988                 ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
989                   X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
990
991         update_debugctlmsr(debugctlmsr);
992 }
993
994 /*
995  * Setup the hardware configuration for a given attr_type
996  */
997 static int __hw_perf_event_init(struct perf_event *event)
998 {
999         struct perf_event_attr *attr = &event->attr;
1000         struct hw_perf_event *hwc = &event->hw;
1001         u64 config;
1002         int err;
1003
1004         if (!x86_pmu_initialized())
1005                 return -ENODEV;
1006
1007         err = 0;
1008         if (!atomic_inc_not_zero(&active_events)) {
1009                 mutex_lock(&pmc_reserve_mutex);
1010                 if (atomic_read(&active_events) == 0) {
1011                         if (!reserve_pmc_hardware())
1012                                 err = -EBUSY;
1013                         else
1014                                 err = reserve_bts_hardware();
1015                 }
1016                 if (!err)
1017                         atomic_inc(&active_events);
1018                 mutex_unlock(&pmc_reserve_mutex);
1019         }
1020         if (err)
1021                 return err;
1022
1023         event->destroy = hw_perf_event_destroy;
1024
1025         /*
1026          * Generate PMC IRQs:
1027          * (keep 'enabled' bit clear for now)
1028          */
1029         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
1030
1031         hwc->idx = -1;
1032
1033         /*
1034          * Count user and OS events unless requested not to.
1035          */
1036         if (!attr->exclude_user)
1037                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
1038         if (!attr->exclude_kernel)
1039                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
1040
1041         if (!hwc->sample_period) {
1042                 hwc->sample_period = x86_pmu.max_period;
1043                 hwc->last_period = hwc->sample_period;
1044                 atomic64_set(&hwc->period_left, hwc->sample_period);
1045         } else {
1046                 /*
1047                  * If we have a PMU initialized but no APIC
1048                  * interrupts, we cannot sample hardware
1049                  * events (user-space has to fall back and
1050                  * sample via a hrtimer based software event):
1051                  */
1052                 if (!x86_pmu.apic)
1053                         return -EOPNOTSUPP;
1054         }
1055
1056         /*
1057          * Raw hw_event type provide the config in the hw_event structure
1058          */
1059         if (attr->type == PERF_TYPE_RAW) {
1060                 hwc->config |= x86_pmu.raw_event(attr->config);
1061                 return 0;
1062         }
1063
1064         if (attr->type == PERF_TYPE_HW_CACHE)
1065                 return set_ext_hw_attr(hwc, attr);
1066
1067         if (attr->config >= x86_pmu.max_events)
1068                 return -EINVAL;
1069
1070         /*
1071          * The generic map:
1072          */
1073         config = x86_pmu.event_map(attr->config);
1074
1075         if (config == 0)
1076                 return -ENOENT;
1077
1078         if (config == -1LL)
1079                 return -EINVAL;
1080
1081         /*
1082          * Branch tracing:
1083          */
1084         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
1085             (hwc->sample_period == 1)) {
1086                 /* BTS is not supported by this architecture. */
1087                 if (!bts_available())
1088                         return -EOPNOTSUPP;
1089
1090                 /* BTS is currently only allowed for user-mode. */
1091                 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1092                         return -EOPNOTSUPP;
1093         }
1094
1095         hwc->config |= config;
1096
1097         return 0;
1098 }
1099
1100 static void p6_pmu_disable_all(void)
1101 {
1102         u64 val;
1103
1104         /* p6 only has one enable register */
1105         rdmsrl(MSR_P6_EVNTSEL0, val);
1106         val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1107         wrmsrl(MSR_P6_EVNTSEL0, val);
1108 }
1109
1110 static void intel_pmu_disable_all(void)
1111 {
1112         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1113
1114         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1115
1116         if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
1117                 intel_pmu_disable_bts();
1118 }
1119
1120 static void amd_pmu_disable_all(void)
1121 {
1122         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1123         int idx;
1124
1125         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1126                 u64 val;
1127
1128                 if (!test_bit(idx, cpuc->active_mask))
1129                         continue;
1130                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
1131                 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
1132                         continue;
1133                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
1134                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1135         }
1136 }
1137
1138 void hw_perf_disable(void)
1139 {
1140         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1141
1142         if (!x86_pmu_initialized())
1143                 return;
1144
1145         if (!cpuc->enabled)
1146                 return;
1147
1148         cpuc->n_added = 0;
1149         cpuc->enabled = 0;
1150         barrier();
1151
1152         x86_pmu.disable_all();
1153 }
1154
1155 static void p6_pmu_enable_all(void)
1156 {
1157         unsigned long val;
1158
1159         /* p6 only has one enable register */
1160         rdmsrl(MSR_P6_EVNTSEL0, val);
1161         val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1162         wrmsrl(MSR_P6_EVNTSEL0, val);
1163 }
1164
1165 static void intel_pmu_enable_all(void)
1166 {
1167         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1168
1169         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1170
1171         if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
1172                 struct perf_event *event =
1173                         cpuc->events[X86_PMC_IDX_FIXED_BTS];
1174
1175                 if (WARN_ON_ONCE(!event))
1176                         return;
1177
1178                 intel_pmu_enable_bts(event->hw.config);
1179         }
1180 }
1181
1182 static void amd_pmu_enable_all(void)
1183 {
1184         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1185         int idx;
1186
1187         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1188                 struct perf_event *event = cpuc->events[idx];
1189                 u64 val;
1190
1191                 if (!test_bit(idx, cpuc->active_mask))
1192                         continue;
1193
1194                 val = event->hw.config;
1195                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1196                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
1197         }
1198 }
1199
1200 static const struct pmu pmu;
1201
1202 static inline int is_x86_event(struct perf_event *event)
1203 {
1204         return event->pmu == &pmu;
1205 }
1206
1207 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
1208 {
1209         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
1210         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
1211         int i, j, w, wmax, num = 0;
1212         struct hw_perf_event *hwc;
1213
1214         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1215
1216         for (i = 0; i < n; i++) {
1217                 constraints[i] =
1218                   x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
1219         }
1220
1221         /*
1222          * fastpath, try to reuse previous register
1223          */
1224         for (i = 0; i < n; i++) {
1225                 hwc = &cpuc->event_list[i]->hw;
1226                 c = constraints[i];
1227
1228                 /* never assigned */
1229                 if (hwc->idx == -1)
1230                         break;
1231
1232                 /* constraint still honored */
1233                 if (!test_bit(hwc->idx, c->idxmsk))
1234                         break;
1235
1236                 /* not already used */
1237                 if (test_bit(hwc->idx, used_mask))
1238                         break;
1239
1240                 set_bit(hwc->idx, used_mask);
1241                 if (assign)
1242                         assign[i] = hwc->idx;
1243         }
1244         if (i == n)
1245                 goto done;
1246
1247         /*
1248          * begin slow path
1249          */
1250
1251         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
1252
1253         /*
1254          * weight = number of possible counters
1255          *
1256          * 1    = most constrained, only works on one counter
1257          * wmax = least constrained, works on any counter
1258          *
1259          * assign events to counters starting with most
1260          * constrained events.
1261          */
1262         wmax = x86_pmu.num_events;
1263
1264         /*
1265          * when fixed event counters are present,
1266          * wmax is incremented by 1 to account
1267          * for one more choice
1268          */
1269         if (x86_pmu.num_events_fixed)
1270                 wmax++;
1271
1272         for (w = 1, num = n; num && w <= wmax; w++) {
1273                 /* for each event */
1274                 for (i = 0; num && i < n; i++) {
1275                         c = constraints[i];
1276                         hwc = &cpuc->event_list[i]->hw;
1277
1278                         if (c->weight != w)
1279                                 continue;
1280
1281                         for_each_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
1282                                 if (!test_bit(j, used_mask))
1283                                         break;
1284                         }
1285
1286                         if (j == X86_PMC_IDX_MAX)
1287                                 break;
1288
1289                         set_bit(j, used_mask);
1290
1291                         if (assign)
1292                                 assign[i] = j;
1293                         num--;
1294                 }
1295         }
1296 done:
1297         /*
1298          * scheduling failed or is just a simulation,
1299          * free resources if necessary
1300          */
1301         if (!assign || num) {
1302                 for (i = 0; i < n; i++) {
1303                         if (x86_pmu.put_event_constraints)
1304                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
1305                 }
1306         }
1307         return num ? -ENOSPC : 0;
1308 }
1309
1310 /*
1311  * dogrp: true if must collect siblings events (group)
1312  * returns total number of events and error code
1313  */
1314 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
1315 {
1316         struct perf_event *event;
1317         int n, max_count;
1318
1319         max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
1320
1321         /* current number of events already accepted */
1322         n = cpuc->n_events;
1323
1324         if (is_x86_event(leader)) {
1325                 if (n >= max_count)
1326                         return -ENOSPC;
1327                 cpuc->event_list[n] = leader;
1328                 n++;
1329         }
1330         if (!dogrp)
1331                 return n;
1332
1333         list_for_each_entry(event, &leader->sibling_list, group_entry) {
1334                 if (!is_x86_event(event) ||
1335                     event->state <= PERF_EVENT_STATE_OFF)
1336                         continue;
1337
1338                 if (n >= max_count)
1339                         return -ENOSPC;
1340
1341                 cpuc->event_list[n] = event;
1342                 n++;
1343         }
1344         return n;
1345 }
1346
1347
1348 static inline void x86_assign_hw_event(struct perf_event *event,
1349                                 struct hw_perf_event *hwc, int idx)
1350 {
1351         hwc->idx = idx;
1352
1353         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
1354                 hwc->config_base = 0;
1355                 hwc->event_base = 0;
1356         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
1357                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1358                 /*
1359                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
1360                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1361                  */
1362                 hwc->event_base =
1363                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1364         } else {
1365                 hwc->config_base = x86_pmu.eventsel;
1366                 hwc->event_base  = x86_pmu.perfctr;
1367         }
1368 }
1369
1370 static void __x86_pmu_disable(struct perf_event *event, struct cpu_hw_events *cpuc);
1371
1372 void hw_perf_enable(void)
1373 {
1374         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1375         struct perf_event *event;
1376         struct hw_perf_event *hwc;
1377         int i;
1378
1379         if (!x86_pmu_initialized())
1380                 return;
1381
1382         if (cpuc->enabled)
1383                 return;
1384
1385         if (cpuc->n_added) {
1386                 /*
1387                  * apply assignment obtained either from
1388                  * hw_perf_group_sched_in() or x86_pmu_enable()
1389                  *
1390                  * step1: save events moving to new counters
1391                  * step2: reprogram moved events into new counters
1392                  */
1393                 for (i = 0; i < cpuc->n_events; i++) {
1394
1395                         event = cpuc->event_list[i];
1396                         hwc = &event->hw;
1397
1398                         if (hwc->idx == -1 || hwc->idx == cpuc->assign[i])
1399                                 continue;
1400
1401                         __x86_pmu_disable(event, cpuc);
1402
1403                         hwc->idx = -1;
1404                 }
1405
1406                 for (i = 0; i < cpuc->n_events; i++) {
1407
1408                         event = cpuc->event_list[i];
1409                         hwc = &event->hw;
1410
1411                         if (hwc->idx == -1) {
1412                                 x86_assign_hw_event(event, hwc, cpuc->assign[i]);
1413                                 x86_perf_event_set_period(event, hwc, hwc->idx);
1414                         }
1415                         /*
1416                          * need to mark as active because x86_pmu_disable()
1417                          * clear active_mask and eventsp[] yet it preserves
1418                          * idx
1419                          */
1420                         set_bit(hwc->idx, cpuc->active_mask);
1421                         cpuc->events[hwc->idx] = event;
1422
1423                         x86_pmu.enable(hwc, hwc->idx);
1424                         perf_event_update_userpage(event);
1425                 }
1426                 cpuc->n_added = 0;
1427                 perf_events_lapic_init();
1428         }
1429
1430         cpuc->enabled = 1;
1431         barrier();
1432
1433         x86_pmu.enable_all();
1434 }
1435
1436 static inline u64 intel_pmu_get_status(void)
1437 {
1438         u64 status;
1439
1440         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1441
1442         return status;
1443 }
1444
1445 static inline void intel_pmu_ack_status(u64 ack)
1446 {
1447         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1448 }
1449
1450 static inline void x86_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1451 {
1452         (void)checking_wrmsrl(hwc->config_base + idx,
1453                               hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
1454 }
1455
1456 static inline void x86_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1457 {
1458         (void)checking_wrmsrl(hwc->config_base + idx, hwc->config);
1459 }
1460
1461 static inline void
1462 intel_pmu_disable_fixed(struct hw_perf_event *hwc, int __idx)
1463 {
1464         int idx = __idx - X86_PMC_IDX_FIXED;
1465         u64 ctrl_val, mask;
1466
1467         mask = 0xfULL << (idx * 4);
1468
1469         rdmsrl(hwc->config_base, ctrl_val);
1470         ctrl_val &= ~mask;
1471         (void)checking_wrmsrl(hwc->config_base, ctrl_val);
1472 }
1473
1474 static inline void
1475 p6_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1476 {
1477         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1478         u64 val = P6_NOP_EVENT;
1479
1480         if (cpuc->enabled)
1481                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1482
1483         (void)checking_wrmsrl(hwc->config_base + idx, val);
1484 }
1485
1486 static inline void
1487 intel_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1488 {
1489         if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1490                 intel_pmu_disable_bts();
1491                 return;
1492         }
1493
1494         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1495                 intel_pmu_disable_fixed(hwc, idx);
1496                 return;
1497         }
1498
1499         x86_pmu_disable_event(hwc, idx);
1500 }
1501
1502 static inline void
1503 amd_pmu_disable_event(struct hw_perf_event *hwc, int idx)
1504 {
1505         x86_pmu_disable_event(hwc, idx);
1506 }
1507
1508 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
1509
1510 /*
1511  * Set the next IRQ period, based on the hwc->period_left value.
1512  * To be called with the event disabled in hw:
1513  */
1514 static int
1515 x86_perf_event_set_period(struct perf_event *event,
1516                              struct hw_perf_event *hwc, int idx)
1517 {
1518         s64 left = atomic64_read(&hwc->period_left);
1519         s64 period = hwc->sample_period;
1520         int err, ret = 0;
1521
1522         if (idx == X86_PMC_IDX_FIXED_BTS)
1523                 return 0;
1524
1525         /*
1526          * If we are way outside a reasonable range then just skip forward:
1527          */
1528         if (unlikely(left <= -period)) {
1529                 left = period;
1530                 atomic64_set(&hwc->period_left, left);
1531                 hwc->last_period = period;
1532                 ret = 1;
1533         }
1534
1535         if (unlikely(left <= 0)) {
1536                 left += period;
1537                 atomic64_set(&hwc->period_left, left);
1538                 hwc->last_period = period;
1539                 ret = 1;
1540         }
1541         /*
1542          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
1543          */
1544         if (unlikely(left < 2))
1545                 left = 2;
1546
1547         if (left > x86_pmu.max_period)
1548                 left = x86_pmu.max_period;
1549
1550         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
1551
1552         /*
1553          * The hw event starts counting from this event offset,
1554          * mark it to be able to extra future deltas:
1555          */
1556         atomic64_set(&hwc->prev_count, (u64)-left);
1557
1558         err = checking_wrmsrl(hwc->event_base + idx,
1559                              (u64)(-left) & x86_pmu.event_mask);
1560
1561         perf_event_update_userpage(event);
1562
1563         return ret;
1564 }
1565
1566 static inline void
1567 intel_pmu_enable_fixed(struct hw_perf_event *hwc, int __idx)
1568 {
1569         int idx = __idx - X86_PMC_IDX_FIXED;
1570         u64 ctrl_val, bits, mask;
1571         int err;
1572
1573         /*
1574          * Enable IRQ generation (0x8),
1575          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1576          * if requested:
1577          */
1578         bits = 0x8ULL;
1579         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1580                 bits |= 0x2;
1581         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1582                 bits |= 0x1;
1583         bits <<= (idx * 4);
1584         mask = 0xfULL << (idx * 4);
1585
1586         rdmsrl(hwc->config_base, ctrl_val);
1587         ctrl_val &= ~mask;
1588         ctrl_val |= bits;
1589         err = checking_wrmsrl(hwc->config_base, ctrl_val);
1590 }
1591
1592 static void p6_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1593 {
1594         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1595         u64 val;
1596
1597         val = hwc->config;
1598         if (cpuc->enabled)
1599                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
1600
1601         (void)checking_wrmsrl(hwc->config_base + idx, val);
1602 }
1603
1604
1605 static void intel_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1606 {
1607         if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
1608                 if (!__get_cpu_var(cpu_hw_events).enabled)
1609                         return;
1610
1611                 intel_pmu_enable_bts(hwc->config);
1612                 return;
1613         }
1614
1615         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
1616                 intel_pmu_enable_fixed(hwc, idx);
1617                 return;
1618         }
1619
1620         x86_pmu_enable_event(hwc, idx);
1621 }
1622
1623 static void amd_pmu_enable_event(struct hw_perf_event *hwc, int idx)
1624 {
1625         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1626
1627         if (cpuc->enabled)
1628                 x86_pmu_enable_event(hwc, idx);
1629 }
1630
1631 /*
1632  * activate a single event
1633  *
1634  * The event is added to the group of enabled events
1635  * but only if it can be scehduled with existing events.
1636  *
1637  * Called with PMU disabled. If successful and return value 1,
1638  * then guaranteed to call perf_enable() and hw_perf_enable()
1639  */
1640 static int x86_pmu_enable(struct perf_event *event)
1641 {
1642         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1643         struct hw_perf_event *hwc;
1644         int assign[X86_PMC_IDX_MAX];
1645         int n, n0, ret;
1646
1647         hwc = &event->hw;
1648
1649         n0 = cpuc->n_events;
1650         n = collect_events(cpuc, event, false);
1651         if (n < 0)
1652                 return n;
1653
1654         ret = x86_schedule_events(cpuc, n, assign);
1655         if (ret)
1656                 return ret;
1657         /*
1658          * copy new assignment, now we know it is possible
1659          * will be used by hw_perf_enable()
1660          */
1661         memcpy(cpuc->assign, assign, n*sizeof(int));
1662
1663         cpuc->n_events = n;
1664         cpuc->n_added  = n - n0;
1665
1666         if (hwc->idx != -1)
1667                 x86_perf_event_set_period(event, hwc, hwc->idx);
1668
1669         return 0;
1670 }
1671
1672 static void x86_pmu_unthrottle(struct perf_event *event)
1673 {
1674         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1675         struct hw_perf_event *hwc = &event->hw;
1676
1677         if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1678                                 cpuc->events[hwc->idx] != event))
1679                 return;
1680
1681         x86_pmu.enable(hwc, hwc->idx);
1682 }
1683
1684 void perf_event_print_debug(void)
1685 {
1686         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1687         struct cpu_hw_events *cpuc;
1688         unsigned long flags;
1689         int cpu, idx;
1690
1691         if (!x86_pmu.num_events)
1692                 return;
1693
1694         local_irq_save(flags);
1695
1696         cpu = smp_processor_id();
1697         cpuc = &per_cpu(cpu_hw_events, cpu);
1698
1699         if (x86_pmu.version >= 2) {
1700                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1701                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1702                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1703                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1704
1705                 pr_info("\n");
1706                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1707                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1708                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1709                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1710         }
1711         pr_info("CPU#%d: active:       %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1712
1713         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1714                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1715                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1716
1717                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1718
1719                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1720                         cpu, idx, pmc_ctrl);
1721                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1722                         cpu, idx, pmc_count);
1723                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1724                         cpu, idx, prev_left);
1725         }
1726         for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1727                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1728
1729                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1730                         cpu, idx, pmc_count);
1731         }
1732         local_irq_restore(flags);
1733 }
1734
1735 static void intel_pmu_drain_bts_buffer(struct cpu_hw_events *cpuc)
1736 {
1737         struct debug_store *ds = cpuc->ds;
1738         struct bts_record {
1739                 u64     from;
1740                 u64     to;
1741                 u64     flags;
1742         };
1743         struct perf_event *event = cpuc->events[X86_PMC_IDX_FIXED_BTS];
1744         struct bts_record *at, *top;
1745         struct perf_output_handle handle;
1746         struct perf_event_header header;
1747         struct perf_sample_data data;
1748         struct pt_regs regs;
1749
1750         if (!event)
1751                 return;
1752
1753         if (!ds)
1754                 return;
1755
1756         at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
1757         top = (struct bts_record *)(unsigned long)ds->bts_index;
1758
1759         if (top <= at)
1760                 return;
1761
1762         ds->bts_index = ds->bts_buffer_base;
1763
1764
1765         data.period     = event->hw.last_period;
1766         data.addr       = 0;
1767         data.raw        = NULL;
1768         regs.ip         = 0;
1769
1770         /*
1771          * Prepare a generic sample, i.e. fill in the invariant fields.
1772          * We will overwrite the from and to address before we output
1773          * the sample.
1774          */
1775         perf_prepare_sample(&header, &data, event, &regs);
1776
1777         if (perf_output_begin(&handle, event,
1778                               header.size * (top - at), 1, 1))
1779                 return;
1780
1781         for (; at < top; at++) {
1782                 data.ip         = at->from;
1783                 data.addr       = at->to;
1784
1785                 perf_output_sample(&handle, &header, &data, event);
1786         }
1787
1788         perf_output_end(&handle);
1789
1790         /* There's new data available. */
1791         event->hw.interrupts++;
1792         event->pending_kill = POLL_IN;
1793 }
1794
1795 static void __x86_pmu_disable(struct perf_event *event, struct cpu_hw_events *cpuc)
1796 {
1797         struct hw_perf_event *hwc = &event->hw;
1798         int idx = hwc->idx;
1799
1800         /*
1801          * Must be done before we disable, otherwise the nmi handler
1802          * could reenable again:
1803          */
1804         clear_bit(idx, cpuc->active_mask);
1805         x86_pmu.disable(hwc, idx);
1806
1807         /*
1808          * Drain the remaining delta count out of a event
1809          * that we are disabling:
1810          */
1811         x86_perf_event_update(event, hwc, idx);
1812
1813         /* Drain the remaining BTS records. */
1814         if (unlikely(idx == X86_PMC_IDX_FIXED_BTS))
1815                 intel_pmu_drain_bts_buffer(cpuc);
1816
1817         cpuc->events[idx] = NULL;
1818 }
1819
1820 static void x86_pmu_disable(struct perf_event *event)
1821 {
1822         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1823         int i;
1824
1825         __x86_pmu_disable(event, cpuc);
1826
1827         for (i = 0; i < cpuc->n_events; i++) {
1828                 if (event == cpuc->event_list[i]) {
1829
1830                         if (x86_pmu.put_event_constraints)
1831                                 x86_pmu.put_event_constraints(cpuc, event);
1832
1833                         while (++i < cpuc->n_events)
1834                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1835
1836                         --cpuc->n_events;
1837                         break;
1838                 }
1839         }
1840         perf_event_update_userpage(event);
1841 }
1842
1843 /*
1844  * Save and restart an expired event. Called by NMI contexts,
1845  * so it has to be careful about preempting normal event ops:
1846  */
1847 static int intel_pmu_save_and_restart(struct perf_event *event)
1848 {
1849         struct hw_perf_event *hwc = &event->hw;
1850         int idx = hwc->idx;
1851         int ret;
1852
1853         x86_perf_event_update(event, hwc, idx);
1854         ret = x86_perf_event_set_period(event, hwc, idx);
1855
1856         if (event->state == PERF_EVENT_STATE_ACTIVE)
1857                 intel_pmu_enable_event(hwc, idx);
1858
1859         return ret;
1860 }
1861
1862 static void intel_pmu_reset(void)
1863 {
1864         struct debug_store *ds = __get_cpu_var(cpu_hw_events).ds;
1865         unsigned long flags;
1866         int idx;
1867
1868         if (!x86_pmu.num_events)
1869                 return;
1870
1871         local_irq_save(flags);
1872
1873         printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1874
1875         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1876                 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1877                 checking_wrmsrl(x86_pmu.perfctr  + idx, 0ull);
1878         }
1879         for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1880                 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1881         }
1882         if (ds)
1883                 ds->bts_index = ds->bts_buffer_base;
1884
1885         local_irq_restore(flags);
1886 }
1887
1888 static int p6_pmu_handle_irq(struct pt_regs *regs)
1889 {
1890         struct perf_sample_data data;
1891         struct cpu_hw_events *cpuc;
1892         struct perf_event *event;
1893         struct hw_perf_event *hwc;
1894         int idx, handled = 0;
1895         u64 val;
1896
1897         data.addr = 0;
1898         data.raw = NULL;
1899
1900         cpuc = &__get_cpu_var(cpu_hw_events);
1901
1902         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1903                 if (!test_bit(idx, cpuc->active_mask))
1904                         continue;
1905
1906                 event = cpuc->events[idx];
1907                 hwc = &event->hw;
1908
1909                 val = x86_perf_event_update(event, hwc, idx);
1910                 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1911                         continue;
1912
1913                 /*
1914                  * event overflow
1915                  */
1916                 handled         = 1;
1917                 data.period     = event->hw.last_period;
1918
1919                 if (!x86_perf_event_set_period(event, hwc, idx))
1920                         continue;
1921
1922                 if (perf_event_overflow(event, 1, &data, regs))
1923                         p6_pmu_disable_event(hwc, idx);
1924         }
1925
1926         if (handled)
1927                 inc_irq_stat(apic_perf_irqs);
1928
1929         return handled;
1930 }
1931
1932 /*
1933  * This handler is triggered by the local APIC, so the APIC IRQ handling
1934  * rules apply:
1935  */
1936 static int intel_pmu_handle_irq(struct pt_regs *regs)
1937 {
1938         struct perf_sample_data data;
1939         struct cpu_hw_events *cpuc;
1940         int bit, loops;
1941         u64 ack, status;
1942
1943         data.addr = 0;
1944         data.raw = NULL;
1945
1946         cpuc = &__get_cpu_var(cpu_hw_events);
1947
1948         perf_disable();
1949         intel_pmu_drain_bts_buffer(cpuc);
1950         status = intel_pmu_get_status();
1951         if (!status) {
1952                 perf_enable();
1953                 return 0;
1954         }
1955
1956         loops = 0;
1957 again:
1958         if (++loops > 100) {
1959                 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
1960                 perf_event_print_debug();
1961                 intel_pmu_reset();
1962                 perf_enable();
1963                 return 1;
1964         }
1965
1966         inc_irq_stat(apic_perf_irqs);
1967         ack = status;
1968         for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1969                 struct perf_event *event = cpuc->events[bit];
1970
1971                 clear_bit(bit, (unsigned long *) &status);
1972                 if (!test_bit(bit, cpuc->active_mask))
1973                         continue;
1974
1975                 if (!intel_pmu_save_and_restart(event))
1976                         continue;
1977
1978                 data.period = event->hw.last_period;
1979
1980                 if (perf_event_overflow(event, 1, &data, regs))
1981                         intel_pmu_disable_event(&event->hw, bit);
1982         }
1983
1984         intel_pmu_ack_status(ack);
1985
1986         /*
1987          * Repeat if there is more work to be done:
1988          */
1989         status = intel_pmu_get_status();
1990         if (status)
1991                 goto again;
1992
1993         perf_enable();
1994
1995         return 1;
1996 }
1997
1998 static int amd_pmu_handle_irq(struct pt_regs *regs)
1999 {
2000         struct perf_sample_data data;
2001         struct cpu_hw_events *cpuc;
2002         struct perf_event *event;
2003         struct hw_perf_event *hwc;
2004         int idx, handled = 0;
2005         u64 val;
2006
2007         data.addr = 0;
2008         data.raw = NULL;
2009
2010         cpuc = &__get_cpu_var(cpu_hw_events);
2011
2012         for (idx = 0; idx < x86_pmu.num_events; idx++) {
2013                 if (!test_bit(idx, cpuc->active_mask))
2014                         continue;
2015
2016                 event = cpuc->events[idx];
2017                 hwc = &event->hw;
2018
2019                 val = x86_perf_event_update(event, hwc, idx);
2020                 if (val & (1ULL << (x86_pmu.event_bits - 1)))
2021                         continue;
2022
2023                 /*
2024                  * event overflow
2025                  */
2026                 handled         = 1;
2027                 data.period     = event->hw.last_period;
2028
2029                 if (!x86_perf_event_set_period(event, hwc, idx))
2030                         continue;
2031
2032                 if (perf_event_overflow(event, 1, &data, regs))
2033                         amd_pmu_disable_event(hwc, idx);
2034         }
2035
2036         if (handled)
2037                 inc_irq_stat(apic_perf_irqs);
2038
2039         return handled;
2040 }
2041
2042 void smp_perf_pending_interrupt(struct pt_regs *regs)
2043 {
2044         irq_enter();
2045         ack_APIC_irq();
2046         inc_irq_stat(apic_pending_irqs);
2047         perf_event_do_pending();
2048         irq_exit();
2049 }
2050
2051 void set_perf_event_pending(void)
2052 {
2053 #ifdef CONFIG_X86_LOCAL_APIC
2054         if (!x86_pmu.apic || !x86_pmu_initialized())
2055                 return;
2056
2057         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
2058 #endif
2059 }
2060
2061 void perf_events_lapic_init(void)
2062 {
2063 #ifdef CONFIG_X86_LOCAL_APIC
2064         if (!x86_pmu.apic || !x86_pmu_initialized())
2065                 return;
2066
2067         /*
2068          * Always use NMI for PMU
2069          */
2070         apic_write(APIC_LVTPC, APIC_DM_NMI);
2071 #endif
2072 }
2073
2074 static int __kprobes
2075 perf_event_nmi_handler(struct notifier_block *self,
2076                          unsigned long cmd, void *__args)
2077 {
2078         struct die_args *args = __args;
2079         struct pt_regs *regs;
2080
2081         if (!atomic_read(&active_events))
2082                 return NOTIFY_DONE;
2083
2084         switch (cmd) {
2085         case DIE_NMI:
2086         case DIE_NMI_IPI:
2087                 break;
2088
2089         default:
2090                 return NOTIFY_DONE;
2091         }
2092
2093         regs = args->regs;
2094
2095 #ifdef CONFIG_X86_LOCAL_APIC
2096         apic_write(APIC_LVTPC, APIC_DM_NMI);
2097 #endif
2098         /*
2099          * Can't rely on the handled return value to say it was our NMI, two
2100          * events could trigger 'simultaneously' raising two back-to-back NMIs.
2101          *
2102          * If the first NMI handles both, the latter will be empty and daze
2103          * the CPU.
2104          */
2105         x86_pmu.handle_irq(regs);
2106
2107         return NOTIFY_STOP;
2108 }
2109
2110 static struct event_constraint unconstrained;
2111
2112 static struct event_constraint bts_constraint =
2113         EVENT_CONSTRAINT(0, 1ULL << X86_PMC_IDX_FIXED_BTS, 0);
2114
2115 static struct event_constraint *
2116 intel_special_constraints(struct perf_event *event)
2117 {
2118         unsigned int hw_event;
2119
2120         hw_event = event->hw.config & INTEL_ARCH_EVENT_MASK;
2121
2122         if (unlikely((hw_event ==
2123                       x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
2124                      (event->hw.sample_period == 1))) {
2125
2126                 return &bts_constraint;
2127         }
2128         return NULL;
2129 }
2130
2131 static struct event_constraint *
2132 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
2133 {
2134         struct event_constraint *c;
2135
2136         c = intel_special_constraints(event);
2137         if (c)
2138                 return c;
2139
2140         if (x86_pmu.event_constraints) {
2141                 for_each_event_constraint(c, x86_pmu.event_constraints) {
2142                         if ((event->hw.config & c->cmask) == c->code)
2143                                 return c;
2144                 }
2145         }
2146
2147         return &unconstrained;
2148 }
2149
2150 static struct event_constraint *
2151 amd_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
2152 {
2153         return &unconstrained;
2154 }
2155
2156 static int x86_event_sched_in(struct perf_event *event,
2157                           struct perf_cpu_context *cpuctx, int cpu)
2158 {
2159         int ret = 0;
2160
2161         event->state = PERF_EVENT_STATE_ACTIVE;
2162         event->oncpu = cpu;
2163         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
2164
2165         if (!is_x86_event(event))
2166                 ret = event->pmu->enable(event);
2167
2168         if (!ret && !is_software_event(event))
2169                 cpuctx->active_oncpu++;
2170
2171         if (!ret && event->attr.exclusive)
2172                 cpuctx->exclusive = 1;
2173
2174         return ret;
2175 }
2176
2177 static void x86_event_sched_out(struct perf_event *event,
2178                             struct perf_cpu_context *cpuctx, int cpu)
2179 {
2180         event->state = PERF_EVENT_STATE_INACTIVE;
2181         event->oncpu = -1;
2182
2183         if (!is_x86_event(event))
2184                 event->pmu->disable(event);
2185
2186         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
2187
2188         if (!is_software_event(event))
2189                 cpuctx->active_oncpu--;
2190
2191         if (event->attr.exclusive || !cpuctx->active_oncpu)
2192                 cpuctx->exclusive = 0;
2193 }
2194
2195 /*
2196  * Called to enable a whole group of events.
2197  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
2198  * Assumes the caller has disabled interrupts and has
2199  * frozen the PMU with hw_perf_save_disable.
2200  *
2201  * called with PMU disabled. If successful and return value 1,
2202  * then guaranteed to call perf_enable() and hw_perf_enable()
2203  */
2204 int hw_perf_group_sched_in(struct perf_event *leader,
2205                struct perf_cpu_context *cpuctx,
2206                struct perf_event_context *ctx, int cpu)
2207 {
2208         struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
2209         struct perf_event *sub;
2210         int assign[X86_PMC_IDX_MAX];
2211         int n0, n1, ret;
2212
2213         /* n0 = total number of events */
2214         n0 = collect_events(cpuc, leader, true);
2215         if (n0 < 0)
2216                 return n0;
2217
2218         ret = x86_schedule_events(cpuc, n0, assign);
2219         if (ret)
2220                 return ret;
2221
2222         ret = x86_event_sched_in(leader, cpuctx, cpu);
2223         if (ret)
2224                 return ret;
2225
2226         n1 = 1;
2227         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
2228                 if (sub->state > PERF_EVENT_STATE_OFF) {
2229                         ret = x86_event_sched_in(sub, cpuctx, cpu);
2230                         if (ret)
2231                                 goto undo;
2232                         ++n1;
2233                 }
2234         }
2235         /*
2236          * copy new assignment, now we know it is possible
2237          * will be used by hw_perf_enable()
2238          */
2239         memcpy(cpuc->assign, assign, n0*sizeof(int));
2240
2241         cpuc->n_events  = n0;
2242         cpuc->n_added   = n1;
2243         ctx->nr_active += n1;
2244
2245         /*
2246          * 1 means successful and events are active
2247          * This is not quite true because we defer
2248          * actual activation until hw_perf_enable() but
2249          * this way we* ensure caller won't try to enable
2250          * individual events
2251          */
2252         return 1;
2253 undo:
2254         x86_event_sched_out(leader, cpuctx, cpu);
2255         n0  = 1;
2256         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
2257                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
2258                         x86_event_sched_out(sub, cpuctx, cpu);
2259                         if (++n0 == n1)
2260                                 break;
2261                 }
2262         }
2263         return ret;
2264 }
2265
2266 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
2267         .notifier_call          = perf_event_nmi_handler,
2268         .next                   = NULL,
2269         .priority               = 1
2270 };
2271
2272 static __initconst struct x86_pmu p6_pmu = {
2273         .name                   = "p6",
2274         .handle_irq             = p6_pmu_handle_irq,
2275         .disable_all            = p6_pmu_disable_all,
2276         .enable_all             = p6_pmu_enable_all,
2277         .enable                 = p6_pmu_enable_event,
2278         .disable                = p6_pmu_disable_event,
2279         .eventsel               = MSR_P6_EVNTSEL0,
2280         .perfctr                = MSR_P6_PERFCTR0,
2281         .event_map              = p6_pmu_event_map,
2282         .raw_event              = p6_pmu_raw_event,
2283         .max_events             = ARRAY_SIZE(p6_perfmon_event_map),
2284         .apic                   = 1,
2285         .max_period             = (1ULL << 31) - 1,
2286         .version                = 0,
2287         .num_events             = 2,
2288         /*
2289          * Events have 40 bits implemented. However they are designed such
2290          * that bits [32-39] are sign extensions of bit 31. As such the
2291          * effective width of a event for P6-like PMU is 32 bits only.
2292          *
2293          * See IA-32 Intel Architecture Software developer manual Vol 3B
2294          */
2295         .event_bits             = 32,
2296         .event_mask             = (1ULL << 32) - 1,
2297         .get_event_constraints  = intel_get_event_constraints,
2298         .event_constraints      = intel_p6_event_constraints
2299 };
2300
2301 static __initconst struct x86_pmu intel_pmu = {
2302         .name                   = "Intel",
2303         .handle_irq             = intel_pmu_handle_irq,
2304         .disable_all            = intel_pmu_disable_all,
2305         .enable_all             = intel_pmu_enable_all,
2306         .enable                 = intel_pmu_enable_event,
2307         .disable                = intel_pmu_disable_event,
2308         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
2309         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
2310         .event_map              = intel_pmu_event_map,
2311         .raw_event              = intel_pmu_raw_event,
2312         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
2313         .apic                   = 1,
2314         /*
2315          * Intel PMCs cannot be accessed sanely above 32 bit width,
2316          * so we install an artificial 1<<31 period regardless of
2317          * the generic event period:
2318          */
2319         .max_period             = (1ULL << 31) - 1,
2320         .enable_bts             = intel_pmu_enable_bts,
2321         .disable_bts            = intel_pmu_disable_bts,
2322         .get_event_constraints  = intel_get_event_constraints
2323 };
2324
2325 static __initconst struct x86_pmu amd_pmu = {
2326         .name                   = "AMD",
2327         .handle_irq             = amd_pmu_handle_irq,
2328         .disable_all            = amd_pmu_disable_all,
2329         .enable_all             = amd_pmu_enable_all,
2330         .enable                 = amd_pmu_enable_event,
2331         .disable                = amd_pmu_disable_event,
2332         .eventsel               = MSR_K7_EVNTSEL0,
2333         .perfctr                = MSR_K7_PERFCTR0,
2334         .event_map              = amd_pmu_event_map,
2335         .raw_event              = amd_pmu_raw_event,
2336         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
2337         .num_events             = 4,
2338         .event_bits             = 48,
2339         .event_mask             = (1ULL << 48) - 1,
2340         .apic                   = 1,
2341         /* use highest bit to detect overflow */
2342         .max_period             = (1ULL << 47) - 1,
2343         .get_event_constraints  = amd_get_event_constraints
2344 };
2345
2346 static __init int p6_pmu_init(void)
2347 {
2348         switch (boot_cpu_data.x86_model) {
2349         case 1:
2350         case 3:  /* Pentium Pro */
2351         case 5:
2352         case 6:  /* Pentium II */
2353         case 7:
2354         case 8:
2355         case 11: /* Pentium III */
2356         case 9:
2357         case 13:
2358                 /* Pentium M */
2359                 break;
2360         default:
2361                 pr_cont("unsupported p6 CPU model %d ",
2362                         boot_cpu_data.x86_model);
2363                 return -ENODEV;
2364         }
2365
2366         x86_pmu = p6_pmu;
2367
2368         return 0;
2369 }
2370
2371 static __init int intel_pmu_init(void)
2372 {
2373         union cpuid10_edx edx;
2374         union cpuid10_eax eax;
2375         unsigned int unused;
2376         unsigned int ebx;
2377         int version;
2378
2379         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
2380                 /* check for P6 processor family */
2381            if (boot_cpu_data.x86 == 6) {
2382                 return p6_pmu_init();
2383            } else {
2384                 return -ENODEV;
2385            }
2386         }
2387
2388         /*
2389          * Check whether the Architectural PerfMon supports
2390          * Branch Misses Retired hw_event or not.
2391          */
2392         cpuid(10, &eax.full, &ebx, &unused, &edx.full);
2393         if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
2394                 return -ENODEV;
2395
2396         version = eax.split.version_id;
2397         if (version < 2)
2398                 return -ENODEV;
2399
2400         x86_pmu                         = intel_pmu;
2401         x86_pmu.version                 = version;
2402         x86_pmu.num_events              = eax.split.num_events;
2403         x86_pmu.event_bits              = eax.split.bit_width;
2404         x86_pmu.event_mask              = (1ULL << eax.split.bit_width) - 1;
2405
2406         /*
2407          * Quirk: v2 perfmon does not report fixed-purpose events, so
2408          * assume at least 3 events:
2409          */
2410         x86_pmu.num_events_fixed        = max((int)edx.split.num_events_fixed, 3);
2411
2412         /*
2413          * Install the hw-cache-events table:
2414          */
2415         switch (boot_cpu_data.x86_model) {
2416         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
2417         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
2418         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
2419         case 29: /* six-core 45 nm xeon "Dunnington" */
2420                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
2421                        sizeof(hw_cache_event_ids));
2422
2423                 x86_pmu.event_constraints = intel_core_event_constraints;
2424                 pr_cont("Core2 events, ");
2425                 break;
2426         case 26:
2427                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
2428                        sizeof(hw_cache_event_ids));
2429
2430                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
2431                 pr_cont("Nehalem/Corei7 events, ");
2432                 break;
2433         case 28:
2434                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
2435                        sizeof(hw_cache_event_ids));
2436
2437                 x86_pmu.event_constraints = intel_gen_event_constraints;
2438                 pr_cont("Atom events, ");
2439                 break;
2440         default:
2441                 /*
2442                  * default constraints for v2 and up
2443                  */
2444                 x86_pmu.event_constraints = intel_gen_event_constraints;
2445                 pr_cont("generic architected perfmon, ");
2446         }
2447         return 0;
2448 }
2449
2450 static __init int amd_pmu_init(void)
2451 {
2452         /* Performance-monitoring supported from K7 and later: */
2453         if (boot_cpu_data.x86 < 6)
2454                 return -ENODEV;
2455
2456         x86_pmu = amd_pmu;
2457
2458         /* Events are common for all AMDs */
2459         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
2460                sizeof(hw_cache_event_ids));
2461
2462         return 0;
2463 }
2464
2465 static void __init pmu_check_apic(void)
2466 {
2467         if (cpu_has_apic)
2468                 return;
2469
2470         x86_pmu.apic = 0;
2471         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
2472         pr_info("no hardware sampling interrupt available.\n");
2473 }
2474
2475 void __init init_hw_perf_events(void)
2476 {
2477         int err;
2478
2479         pr_info("Performance Events: ");
2480
2481         switch (boot_cpu_data.x86_vendor) {
2482         case X86_VENDOR_INTEL:
2483                 err = intel_pmu_init();
2484                 break;
2485         case X86_VENDOR_AMD:
2486                 err = amd_pmu_init();
2487                 break;
2488         default:
2489                 return;
2490         }
2491         if (err != 0) {
2492                 pr_cont("no PMU driver, software events only.\n");
2493                 return;
2494         }
2495
2496         pmu_check_apic();
2497
2498         pr_cont("%s PMU driver.\n", x86_pmu.name);
2499
2500         if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
2501                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
2502                      x86_pmu.num_events, X86_PMC_MAX_GENERIC);
2503                 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
2504         }
2505         perf_event_mask = (1 << x86_pmu.num_events) - 1;
2506         perf_max_events = x86_pmu.num_events;
2507
2508         if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
2509                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
2510                      x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
2511                 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
2512         }
2513
2514         perf_event_mask |=
2515                 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
2516         x86_pmu.intel_ctrl = perf_event_mask;
2517
2518         perf_events_lapic_init();
2519         register_die_notifier(&perf_event_nmi_notifier);
2520
2521         unconstrained = (struct event_constraint)
2522                 EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1, 0);
2523
2524         pr_info("... version:                %d\n",     x86_pmu.version);
2525         pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
2526         pr_info("... generic registers:      %d\n",     x86_pmu.num_events);
2527         pr_info("... value mask:             %016Lx\n", x86_pmu.event_mask);
2528         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
2529         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_events_fixed);
2530         pr_info("... event mask:             %016Lx\n", perf_event_mask);
2531 }
2532
2533 static inline void x86_pmu_read(struct perf_event *event)
2534 {
2535         x86_perf_event_update(event, &event->hw, event->hw.idx);
2536 }
2537
2538 static const struct pmu pmu = {
2539         .enable         = x86_pmu_enable,
2540         .disable        = x86_pmu_disable,
2541         .read           = x86_pmu_read,
2542         .unthrottle     = x86_pmu_unthrottle,
2543 };
2544
2545 /*
2546  * validate a single event group
2547  *
2548  * validation include:
2549  *      - check events are compatible which each other
2550  *      - events do not compete for the same counter
2551  *      - number of events <= number of counters
2552  *
2553  * validation ensures the group can be loaded onto the
2554  * PMU if it was the only group available.
2555  */
2556 static int validate_group(struct perf_event *event)
2557 {
2558         struct perf_event *leader = event->group_leader;
2559         struct cpu_hw_events *fake_cpuc;
2560         int ret, n;
2561
2562         ret = -ENOMEM;
2563         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
2564         if (!fake_cpuc)
2565                 goto out;
2566
2567         /*
2568          * the event is not yet connected with its
2569          * siblings therefore we must first collect
2570          * existing siblings, then add the new event
2571          * before we can simulate the scheduling
2572          */
2573         ret = -ENOSPC;
2574         n = collect_events(fake_cpuc, leader, true);
2575         if (n < 0)
2576                 goto out_free;
2577
2578         fake_cpuc->n_events = n;
2579         n = collect_events(fake_cpuc, event, false);
2580         if (n < 0)
2581                 goto out_free;
2582
2583         fake_cpuc->n_events = n;
2584
2585         ret = x86_schedule_events(fake_cpuc, n, NULL);
2586
2587 out_free:
2588         kfree(fake_cpuc);
2589 out:
2590         return ret;
2591 }
2592
2593 const struct pmu *hw_perf_event_init(struct perf_event *event)
2594 {
2595         const struct pmu *tmp;
2596         int err;
2597
2598         err = __hw_perf_event_init(event);
2599         if (!err) {
2600                 /*
2601                  * we temporarily connect event to its pmu
2602                  * such that validate_group() can classify
2603                  * it as an x86 event using is_x86_event()
2604                  */
2605                 tmp = event->pmu;
2606                 event->pmu = &pmu;
2607
2608                 if (event->group_leader != event)
2609                         err = validate_group(event);
2610
2611                 event->pmu = tmp;
2612         }
2613         if (err) {
2614                 if (event->destroy)
2615                         event->destroy(event);
2616                 return ERR_PTR(err);
2617         }
2618
2619         return &pmu;
2620 }
2621
2622 /*
2623  * callchain support
2624  */
2625
2626 static inline
2627 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
2628 {
2629         if (entry->nr < PERF_MAX_STACK_DEPTH)
2630                 entry->ip[entry->nr++] = ip;
2631 }
2632
2633 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
2634 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
2635
2636
2637 static void
2638 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
2639 {
2640         /* Ignore warnings */
2641 }
2642
2643 static void backtrace_warning(void *data, char *msg)
2644 {
2645         /* Ignore warnings */
2646 }
2647
2648 static int backtrace_stack(void *data, char *name)
2649 {
2650         return 0;
2651 }
2652
2653 static void backtrace_address(void *data, unsigned long addr, int reliable)
2654 {
2655         struct perf_callchain_entry *entry = data;
2656
2657         if (reliable)
2658                 callchain_store(entry, addr);
2659 }
2660
2661 static const struct stacktrace_ops backtrace_ops = {
2662         .warning                = backtrace_warning,
2663         .warning_symbol         = backtrace_warning_symbol,
2664         .stack                  = backtrace_stack,
2665         .address                = backtrace_address,
2666         .walk_stack             = print_context_stack_bp,
2667 };
2668
2669 #include "../dumpstack.h"
2670
2671 static void
2672 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
2673 {
2674         callchain_store(entry, PERF_CONTEXT_KERNEL);
2675         callchain_store(entry, regs->ip);
2676
2677         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
2678 }
2679
2680 /*
2681  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
2682  */
2683 static unsigned long
2684 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
2685 {
2686         unsigned long offset, addr = (unsigned long)from;
2687         int type = in_nmi() ? KM_NMI : KM_IRQ0;
2688         unsigned long size, len = 0;
2689         struct page *page;
2690         void *map;
2691         int ret;
2692
2693         do {
2694                 ret = __get_user_pages_fast(addr, 1, 0, &page);
2695                 if (!ret)
2696                         break;
2697
2698                 offset = addr & (PAGE_SIZE - 1);
2699                 size = min(PAGE_SIZE - offset, n - len);
2700
2701                 map = kmap_atomic(page, type);
2702                 memcpy(to, map+offset, size);
2703                 kunmap_atomic(map, type);
2704                 put_page(page);
2705
2706                 len  += size;
2707                 to   += size;
2708                 addr += size;
2709
2710         } while (len < n);
2711
2712         return len;
2713 }
2714
2715 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
2716 {
2717         unsigned long bytes;
2718
2719         bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
2720
2721         return bytes == sizeof(*frame);
2722 }
2723
2724 static void
2725 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
2726 {
2727         struct stack_frame frame;
2728         const void __user *fp;
2729
2730         if (!user_mode(regs))
2731                 regs = task_pt_regs(current);
2732
2733         fp = (void __user *)regs->bp;
2734
2735         callchain_store(entry, PERF_CONTEXT_USER);
2736         callchain_store(entry, regs->ip);
2737
2738         while (entry->nr < PERF_MAX_STACK_DEPTH) {
2739                 frame.next_frame             = NULL;
2740                 frame.return_address = 0;
2741
2742                 if (!copy_stack_frame(fp, &frame))
2743                         break;
2744
2745                 if ((unsigned long)fp < regs->sp)
2746                         break;
2747
2748                 callchain_store(entry, frame.return_address);
2749                 fp = frame.next_frame;
2750         }
2751 }
2752
2753 static void
2754 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
2755 {
2756         int is_user;
2757
2758         if (!regs)
2759                 return;
2760
2761         is_user = user_mode(regs);
2762
2763         if (is_user && current->state != TASK_RUNNING)
2764                 return;
2765
2766         if (!is_user)
2767                 perf_callchain_kernel(regs, entry);
2768
2769         if (current->mm)
2770                 perf_callchain_user(regs, entry);
2771 }
2772
2773 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
2774 {
2775         struct perf_callchain_entry *entry;
2776
2777         if (in_nmi())
2778                 entry = &__get_cpu_var(pmc_nmi_entry);
2779         else
2780                 entry = &__get_cpu_var(pmc_irq_entry);
2781
2782         entry->nr = 0;
2783
2784         perf_do_callchain(regs, entry);
2785
2786         return entry;
2787 }
2788
2789 void hw_perf_event_setup_online(int cpu)
2790 {
2791         init_debug_store_on_cpu(cpu);
2792 }