53ea4cf1a8784f23893ed5cab38c560d34ca634a
[linux-2.6.git] / arch / x86 / kernel / cpu / perf_event.c
1 /*
2  * Performance events x86 architecture code
3  *
4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6  *  Copyright (C) 2009 Jaswinder Singh Rajput
7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
11  *
12  *  For licencing details see kernel-base/COPYING
13  */
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/highmem.h>
25 #include <linux/cpu.h>
26 #include <linux/bitops.h>
27
28 #include <asm/apic.h>
29 #include <asm/stacktrace.h>
30 #include <asm/nmi.h>
31 #include <asm/compat.h>
32
33 static u64 perf_event_mask __read_mostly;
34
35 /* The maximal number of PEBS events: */
36 #define MAX_PEBS_EVENTS 4
37
38 /* The size of a BTS record in bytes: */
39 #define BTS_RECORD_SIZE         24
40
41 /* The size of a per-cpu BTS buffer in bytes: */
42 #define BTS_BUFFER_SIZE         (BTS_RECORD_SIZE * 2048)
43
44 /* The BTS overflow threshold in bytes from the end of the buffer: */
45 #define BTS_OVFL_TH             (BTS_RECORD_SIZE * 128)
46
47
48 /*
49  * Bits in the debugctlmsr controlling branch tracing.
50  */
51 #define X86_DEBUGCTL_TR                 (1 << 6)
52 #define X86_DEBUGCTL_BTS                (1 << 7)
53 #define X86_DEBUGCTL_BTINT              (1 << 8)
54 #define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
55 #define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
56
57 /*
58  * A debug store configuration.
59  *
60  * We only support architectures that use 64bit fields.
61  */
62 struct debug_store {
63         u64     bts_buffer_base;
64         u64     bts_index;
65         u64     bts_absolute_maximum;
66         u64     bts_interrupt_threshold;
67         u64     pebs_buffer_base;
68         u64     pebs_index;
69         u64     pebs_absolute_maximum;
70         u64     pebs_interrupt_threshold;
71         u64     pebs_event_reset[MAX_PEBS_EVENTS];
72 };
73
74 struct event_constraint {
75         union {
76                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
77                 u64             idxmsk64;
78         };
79         u64     code;
80         u64     cmask;
81         int     weight;
82 };
83
84 struct amd_nb {
85         int nb_id;  /* NorthBridge id */
86         int refcnt; /* reference count */
87         struct perf_event *owners[X86_PMC_IDX_MAX];
88         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
89 };
90
91 struct cpu_hw_events {
92         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
93         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
94         unsigned long           interrupts;
95         int                     enabled;
96         struct debug_store      *ds;
97
98         int                     n_events;
99         int                     n_added;
100         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
101         u64                     tags[X86_PMC_IDX_MAX];
102         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
103         struct amd_nb           *amd_nb;
104 };
105
106 #define __EVENT_CONSTRAINT(c, n, m, w) {\
107         { .idxmsk64 = (n) },            \
108         .code = (c),                    \
109         .cmask = (m),                   \
110         .weight = (w),                  \
111 }
112
113 #define EVENT_CONSTRAINT(c, n, m)       \
114         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
115
116 #define INTEL_EVENT_CONSTRAINT(c, n)    \
117         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVTSEL_MASK)
118
119 #define FIXED_EVENT_CONSTRAINT(c, n)    \
120         EVENT_CONSTRAINT(c, (1ULL << (32+n)), INTEL_ARCH_FIXED_MASK)
121
122 #define EVENT_CONSTRAINT_END            \
123         EVENT_CONSTRAINT(0, 0, 0)
124
125 #define for_each_event_constraint(e, c) \
126         for ((e) = (c); (e)->cmask; (e)++)
127
128 /*
129  * struct x86_pmu - generic x86 pmu
130  */
131 struct x86_pmu {
132         const char      *name;
133         int             version;
134         int             (*handle_irq)(struct pt_regs *);
135         void            (*disable_all)(void);
136         void            (*enable_all)(void);
137         void            (*enable)(struct perf_event *);
138         void            (*disable)(struct perf_event *);
139         unsigned        eventsel;
140         unsigned        perfctr;
141         u64             (*event_map)(int);
142         u64             (*raw_event)(u64);
143         int             max_events;
144         int             num_events;
145         int             num_events_fixed;
146         int             event_bits;
147         u64             event_mask;
148         int             apic;
149         u64             max_period;
150         u64             intel_ctrl;
151         void            (*enable_bts)(u64 config);
152         void            (*disable_bts)(void);
153
154         struct event_constraint *
155                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
156                                                  struct perf_event *event);
157
158         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
159                                                  struct perf_event *event);
160         struct event_constraint *event_constraints;
161
162         int             (*cpu_prepare)(int cpu);
163         void            (*cpu_starting)(int cpu);
164         void            (*cpu_dying)(int cpu);
165         void            (*cpu_dead)(int cpu);
166 };
167
168 static struct x86_pmu x86_pmu __read_mostly;
169
170 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
171         .enabled = 1,
172 };
173
174 static int x86_perf_event_set_period(struct perf_event *event);
175
176 /*
177  * Generalized hw caching related hw_event table, filled
178  * in on a per model basis. A value of 0 means
179  * 'not supported', -1 means 'hw_event makes no sense on
180  * this CPU', any other value means the raw hw_event
181  * ID.
182  */
183
184 #define C(x) PERF_COUNT_HW_CACHE_##x
185
186 static u64 __read_mostly hw_cache_event_ids
187                                 [PERF_COUNT_HW_CACHE_MAX]
188                                 [PERF_COUNT_HW_CACHE_OP_MAX]
189                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
190
191 /*
192  * Propagate event elapsed time into the generic event.
193  * Can only be executed on the CPU where the event is active.
194  * Returns the delta events processed.
195  */
196 static u64
197 x86_perf_event_update(struct perf_event *event)
198 {
199         struct hw_perf_event *hwc = &event->hw;
200         int shift = 64 - x86_pmu.event_bits;
201         u64 prev_raw_count, new_raw_count;
202         int idx = hwc->idx;
203         s64 delta;
204
205         if (idx == X86_PMC_IDX_FIXED_BTS)
206                 return 0;
207
208         /*
209          * Careful: an NMI might modify the previous event value.
210          *
211          * Our tactic to handle this is to first atomically read and
212          * exchange a new raw count - then add that new-prev delta
213          * count to the generic event atomically:
214          */
215 again:
216         prev_raw_count = atomic64_read(&hwc->prev_count);
217         rdmsrl(hwc->event_base + idx, new_raw_count);
218
219         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
220                                         new_raw_count) != prev_raw_count)
221                 goto again;
222
223         /*
224          * Now we have the new raw value and have updated the prev
225          * timestamp already. We can now calculate the elapsed delta
226          * (event-)time and add that to the generic event.
227          *
228          * Careful, not all hw sign-extends above the physical width
229          * of the count.
230          */
231         delta = (new_raw_count << shift) - (prev_raw_count << shift);
232         delta >>= shift;
233
234         atomic64_add(delta, &event->count);
235         atomic64_sub(delta, &hwc->period_left);
236
237         return new_raw_count;
238 }
239
240 static atomic_t active_events;
241 static DEFINE_MUTEX(pmc_reserve_mutex);
242
243 static bool reserve_pmc_hardware(void)
244 {
245 #ifdef CONFIG_X86_LOCAL_APIC
246         int i;
247
248         if (nmi_watchdog == NMI_LOCAL_APIC)
249                 disable_lapic_nmi_watchdog();
250
251         for (i = 0; i < x86_pmu.num_events; i++) {
252                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
253                         goto perfctr_fail;
254         }
255
256         for (i = 0; i < x86_pmu.num_events; i++) {
257                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
258                         goto eventsel_fail;
259         }
260 #endif
261
262         return true;
263
264 #ifdef CONFIG_X86_LOCAL_APIC
265 eventsel_fail:
266         for (i--; i >= 0; i--)
267                 release_evntsel_nmi(x86_pmu.eventsel + i);
268
269         i = x86_pmu.num_events;
270
271 perfctr_fail:
272         for (i--; i >= 0; i--)
273                 release_perfctr_nmi(x86_pmu.perfctr + i);
274
275         if (nmi_watchdog == NMI_LOCAL_APIC)
276                 enable_lapic_nmi_watchdog();
277
278         return false;
279 #endif
280 }
281
282 static void release_pmc_hardware(void)
283 {
284 #ifdef CONFIG_X86_LOCAL_APIC
285         int i;
286
287         for (i = 0; i < x86_pmu.num_events; i++) {
288                 release_perfctr_nmi(x86_pmu.perfctr + i);
289                 release_evntsel_nmi(x86_pmu.eventsel + i);
290         }
291
292         if (nmi_watchdog == NMI_LOCAL_APIC)
293                 enable_lapic_nmi_watchdog();
294 #endif
295 }
296
297 static inline bool bts_available(void)
298 {
299         return x86_pmu.enable_bts != NULL;
300 }
301
302 static void init_debug_store_on_cpu(int cpu)
303 {
304         struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
305
306         if (!ds)
307                 return;
308
309         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
310                      (u32)((u64)(unsigned long)ds),
311                      (u32)((u64)(unsigned long)ds >> 32));
312 }
313
314 static void fini_debug_store_on_cpu(int cpu)
315 {
316         if (!per_cpu(cpu_hw_events, cpu).ds)
317                 return;
318
319         wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
320 }
321
322 static void release_bts_hardware(void)
323 {
324         int cpu;
325
326         if (!bts_available())
327                 return;
328
329         get_online_cpus();
330
331         for_each_online_cpu(cpu)
332                 fini_debug_store_on_cpu(cpu);
333
334         for_each_possible_cpu(cpu) {
335                 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
336
337                 if (!ds)
338                         continue;
339
340                 per_cpu(cpu_hw_events, cpu).ds = NULL;
341
342                 kfree((void *)(unsigned long)ds->bts_buffer_base);
343                 kfree(ds);
344         }
345
346         put_online_cpus();
347 }
348
349 static int reserve_bts_hardware(void)
350 {
351         int cpu, err = 0;
352
353         if (!bts_available())
354                 return 0;
355
356         get_online_cpus();
357
358         for_each_possible_cpu(cpu) {
359                 struct debug_store *ds;
360                 void *buffer;
361
362                 err = -ENOMEM;
363                 buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
364                 if (unlikely(!buffer))
365                         break;
366
367                 ds = kzalloc(sizeof(*ds), GFP_KERNEL);
368                 if (unlikely(!ds)) {
369                         kfree(buffer);
370                         break;
371                 }
372
373                 ds->bts_buffer_base = (u64)(unsigned long)buffer;
374                 ds->bts_index = ds->bts_buffer_base;
375                 ds->bts_absolute_maximum =
376                         ds->bts_buffer_base + BTS_BUFFER_SIZE;
377                 ds->bts_interrupt_threshold =
378                         ds->bts_absolute_maximum - BTS_OVFL_TH;
379
380                 per_cpu(cpu_hw_events, cpu).ds = ds;
381                 err = 0;
382         }
383
384         if (err)
385                 release_bts_hardware();
386         else {
387                 for_each_online_cpu(cpu)
388                         init_debug_store_on_cpu(cpu);
389         }
390
391         put_online_cpus();
392
393         return err;
394 }
395
396 static void hw_perf_event_destroy(struct perf_event *event)
397 {
398         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
399                 release_pmc_hardware();
400                 release_bts_hardware();
401                 mutex_unlock(&pmc_reserve_mutex);
402         }
403 }
404
405 static inline int x86_pmu_initialized(void)
406 {
407         return x86_pmu.handle_irq != NULL;
408 }
409
410 static inline int
411 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
412 {
413         unsigned int cache_type, cache_op, cache_result;
414         u64 config, val;
415
416         config = attr->config;
417
418         cache_type = (config >>  0) & 0xff;
419         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
420                 return -EINVAL;
421
422         cache_op = (config >>  8) & 0xff;
423         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
424                 return -EINVAL;
425
426         cache_result = (config >> 16) & 0xff;
427         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
428                 return -EINVAL;
429
430         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
431
432         if (val == 0)
433                 return -ENOENT;
434
435         if (val == -1)
436                 return -EINVAL;
437
438         hwc->config |= val;
439
440         return 0;
441 }
442
443 /*
444  * Setup the hardware configuration for a given attr_type
445  */
446 static int __hw_perf_event_init(struct perf_event *event)
447 {
448         struct perf_event_attr *attr = &event->attr;
449         struct hw_perf_event *hwc = &event->hw;
450         u64 config;
451         int err;
452
453         if (!x86_pmu_initialized())
454                 return -ENODEV;
455
456         err = 0;
457         if (!atomic_inc_not_zero(&active_events)) {
458                 mutex_lock(&pmc_reserve_mutex);
459                 if (atomic_read(&active_events) == 0) {
460                         if (!reserve_pmc_hardware())
461                                 err = -EBUSY;
462                         else
463                                 err = reserve_bts_hardware();
464                 }
465                 if (!err)
466                         atomic_inc(&active_events);
467                 mutex_unlock(&pmc_reserve_mutex);
468         }
469         if (err)
470                 return err;
471
472         event->destroy = hw_perf_event_destroy;
473
474         /*
475          * Generate PMC IRQs:
476          * (keep 'enabled' bit clear for now)
477          */
478         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
479
480         hwc->idx = -1;
481         hwc->last_cpu = -1;
482         hwc->last_tag = ~0ULL;
483
484         /*
485          * Count user and OS events unless requested not to.
486          */
487         if (!attr->exclude_user)
488                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
489         if (!attr->exclude_kernel)
490                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
491
492         if (!hwc->sample_period) {
493                 hwc->sample_period = x86_pmu.max_period;
494                 hwc->last_period = hwc->sample_period;
495                 atomic64_set(&hwc->period_left, hwc->sample_period);
496         } else {
497                 /*
498                  * If we have a PMU initialized but no APIC
499                  * interrupts, we cannot sample hardware
500                  * events (user-space has to fall back and
501                  * sample via a hrtimer based software event):
502                  */
503                 if (!x86_pmu.apic)
504                         return -EOPNOTSUPP;
505         }
506
507         /*
508          * Raw hw_event type provide the config in the hw_event structure
509          */
510         if (attr->type == PERF_TYPE_RAW) {
511                 hwc->config |= x86_pmu.raw_event(attr->config);
512                 if ((hwc->config & ARCH_PERFMON_EVENTSEL_ANY) &&
513                     perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
514                         return -EACCES;
515                 return 0;
516         }
517
518         if (attr->type == PERF_TYPE_HW_CACHE)
519                 return set_ext_hw_attr(hwc, attr);
520
521         if (attr->config >= x86_pmu.max_events)
522                 return -EINVAL;
523
524         /*
525          * The generic map:
526          */
527         config = x86_pmu.event_map(attr->config);
528
529         if (config == 0)
530                 return -ENOENT;
531
532         if (config == -1LL)
533                 return -EINVAL;
534
535         /*
536          * Branch tracing:
537          */
538         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
539             (hwc->sample_period == 1)) {
540                 /* BTS is not supported by this architecture. */
541                 if (!bts_available())
542                         return -EOPNOTSUPP;
543
544                 /* BTS is currently only allowed for user-mode. */
545                 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
546                         return -EOPNOTSUPP;
547         }
548
549         hwc->config |= config;
550
551         return 0;
552 }
553
554 static void x86_pmu_disable_all(void)
555 {
556         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
557         int idx;
558
559         for (idx = 0; idx < x86_pmu.num_events; idx++) {
560                 u64 val;
561
562                 if (!test_bit(idx, cpuc->active_mask))
563                         continue;
564                 rdmsrl(x86_pmu.eventsel + idx, val);
565                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
566                         continue;
567                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
568                 wrmsrl(x86_pmu.eventsel + idx, val);
569         }
570 }
571
572 void hw_perf_disable(void)
573 {
574         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
575
576         if (!x86_pmu_initialized())
577                 return;
578
579         if (!cpuc->enabled)
580                 return;
581
582         cpuc->n_added = 0;
583         cpuc->enabled = 0;
584         barrier();
585
586         x86_pmu.disable_all();
587 }
588
589 static void x86_pmu_enable_all(void)
590 {
591         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
592         int idx;
593
594         for (idx = 0; idx < x86_pmu.num_events; idx++) {
595                 struct perf_event *event = cpuc->events[idx];
596                 u64 val;
597
598                 if (!test_bit(idx, cpuc->active_mask))
599                         continue;
600
601                 val = event->hw.config;
602                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
603                 wrmsrl(x86_pmu.eventsel + idx, val);
604         }
605 }
606
607 static const struct pmu pmu;
608
609 static inline int is_x86_event(struct perf_event *event)
610 {
611         return event->pmu == &pmu;
612 }
613
614 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
615 {
616         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
617         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
618         int i, j, w, wmax, num = 0;
619         struct hw_perf_event *hwc;
620
621         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
622
623         for (i = 0; i < n; i++) {
624                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
625                 constraints[i] = c;
626         }
627
628         /*
629          * fastpath, try to reuse previous register
630          */
631         for (i = 0; i < n; i++) {
632                 hwc = &cpuc->event_list[i]->hw;
633                 c = constraints[i];
634
635                 /* never assigned */
636                 if (hwc->idx == -1)
637                         break;
638
639                 /* constraint still honored */
640                 if (!test_bit(hwc->idx, c->idxmsk))
641                         break;
642
643                 /* not already used */
644                 if (test_bit(hwc->idx, used_mask))
645                         break;
646
647                 __set_bit(hwc->idx, used_mask);
648                 if (assign)
649                         assign[i] = hwc->idx;
650         }
651         if (i == n)
652                 goto done;
653
654         /*
655          * begin slow path
656          */
657
658         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
659
660         /*
661          * weight = number of possible counters
662          *
663          * 1    = most constrained, only works on one counter
664          * wmax = least constrained, works on any counter
665          *
666          * assign events to counters starting with most
667          * constrained events.
668          */
669         wmax = x86_pmu.num_events;
670
671         /*
672          * when fixed event counters are present,
673          * wmax is incremented by 1 to account
674          * for one more choice
675          */
676         if (x86_pmu.num_events_fixed)
677                 wmax++;
678
679         for (w = 1, num = n; num && w <= wmax; w++) {
680                 /* for each event */
681                 for (i = 0; num && i < n; i++) {
682                         c = constraints[i];
683                         hwc = &cpuc->event_list[i]->hw;
684
685                         if (c->weight != w)
686                                 continue;
687
688                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
689                                 if (!test_bit(j, used_mask))
690                                         break;
691                         }
692
693                         if (j == X86_PMC_IDX_MAX)
694                                 break;
695
696                         __set_bit(j, used_mask);
697
698                         if (assign)
699                                 assign[i] = j;
700                         num--;
701                 }
702         }
703 done:
704         /*
705          * scheduling failed or is just a simulation,
706          * free resources if necessary
707          */
708         if (!assign || num) {
709                 for (i = 0; i < n; i++) {
710                         if (x86_pmu.put_event_constraints)
711                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
712                 }
713         }
714         return num ? -ENOSPC : 0;
715 }
716
717 /*
718  * dogrp: true if must collect siblings events (group)
719  * returns total number of events and error code
720  */
721 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
722 {
723         struct perf_event *event;
724         int n, max_count;
725
726         max_count = x86_pmu.num_events + x86_pmu.num_events_fixed;
727
728         /* current number of events already accepted */
729         n = cpuc->n_events;
730
731         if (is_x86_event(leader)) {
732                 if (n >= max_count)
733                         return -ENOSPC;
734                 cpuc->event_list[n] = leader;
735                 n++;
736         }
737         if (!dogrp)
738                 return n;
739
740         list_for_each_entry(event, &leader->sibling_list, group_entry) {
741                 if (!is_x86_event(event) ||
742                     event->state <= PERF_EVENT_STATE_OFF)
743                         continue;
744
745                 if (n >= max_count)
746                         return -ENOSPC;
747
748                 cpuc->event_list[n] = event;
749                 n++;
750         }
751         return n;
752 }
753
754 static inline void x86_assign_hw_event(struct perf_event *event,
755                                 struct cpu_hw_events *cpuc, int i)
756 {
757         struct hw_perf_event *hwc = &event->hw;
758
759         hwc->idx = cpuc->assign[i];
760         hwc->last_cpu = smp_processor_id();
761         hwc->last_tag = ++cpuc->tags[i];
762
763         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
764                 hwc->config_base = 0;
765                 hwc->event_base = 0;
766         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
767                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
768                 /*
769                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
770                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
771                  */
772                 hwc->event_base =
773                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
774         } else {
775                 hwc->config_base = x86_pmu.eventsel;
776                 hwc->event_base  = x86_pmu.perfctr;
777         }
778 }
779
780 static inline int match_prev_assignment(struct hw_perf_event *hwc,
781                                         struct cpu_hw_events *cpuc,
782                                         int i)
783 {
784         return hwc->idx == cpuc->assign[i] &&
785                 hwc->last_cpu == smp_processor_id() &&
786                 hwc->last_tag == cpuc->tags[i];
787 }
788
789 static int x86_pmu_start(struct perf_event *event);
790 static void x86_pmu_stop(struct perf_event *event);
791
792 void hw_perf_enable(void)
793 {
794         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
795         struct perf_event *event;
796         struct hw_perf_event *hwc;
797         int i;
798
799         if (!x86_pmu_initialized())
800                 return;
801
802         if (cpuc->enabled)
803                 return;
804
805         if (cpuc->n_added) {
806                 int n_running = cpuc->n_events - cpuc->n_added;
807                 /*
808                  * apply assignment obtained either from
809                  * hw_perf_group_sched_in() or x86_pmu_enable()
810                  *
811                  * step1: save events moving to new counters
812                  * step2: reprogram moved events into new counters
813                  */
814                 for (i = 0; i < n_running; i++) {
815                         event = cpuc->event_list[i];
816                         hwc = &event->hw;
817
818                         /*
819                          * we can avoid reprogramming counter if:
820                          * - assigned same counter as last time
821                          * - running on same CPU as last time
822                          * - no other event has used the counter since
823                          */
824                         if (hwc->idx == -1 ||
825                             match_prev_assignment(hwc, cpuc, i))
826                                 continue;
827
828                         x86_pmu_stop(event);
829                 }
830
831                 for (i = 0; i < cpuc->n_events; i++) {
832                         event = cpuc->event_list[i];
833                         hwc = &event->hw;
834
835                         if (!match_prev_assignment(hwc, cpuc, i))
836                                 x86_assign_hw_event(event, cpuc, i);
837                         else if (i < n_running)
838                                 continue;
839
840                         x86_pmu_start(event);
841                 }
842                 cpuc->n_added = 0;
843                 perf_events_lapic_init();
844         }
845
846         cpuc->enabled = 1;
847         barrier();
848
849         x86_pmu.enable_all();
850 }
851
852 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc)
853 {
854         (void)checking_wrmsrl(hwc->config_base + hwc->idx,
855                               hwc->config | ARCH_PERFMON_EVENTSEL_ENABLE);
856 }
857
858 static inline void x86_pmu_disable_event(struct perf_event *event)
859 {
860         struct hw_perf_event *hwc = &event->hw;
861         (void)checking_wrmsrl(hwc->config_base + hwc->idx, hwc->config);
862 }
863
864 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
865
866 /*
867  * Set the next IRQ period, based on the hwc->period_left value.
868  * To be called with the event disabled in hw:
869  */
870 static int
871 x86_perf_event_set_period(struct perf_event *event)
872 {
873         struct hw_perf_event *hwc = &event->hw;
874         s64 left = atomic64_read(&hwc->period_left);
875         s64 period = hwc->sample_period;
876         int err, ret = 0, idx = hwc->idx;
877
878         if (idx == X86_PMC_IDX_FIXED_BTS)
879                 return 0;
880
881         /*
882          * If we are way outside a reasonable range then just skip forward:
883          */
884         if (unlikely(left <= -period)) {
885                 left = period;
886                 atomic64_set(&hwc->period_left, left);
887                 hwc->last_period = period;
888                 ret = 1;
889         }
890
891         if (unlikely(left <= 0)) {
892                 left += period;
893                 atomic64_set(&hwc->period_left, left);
894                 hwc->last_period = period;
895                 ret = 1;
896         }
897         /*
898          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
899          */
900         if (unlikely(left < 2))
901                 left = 2;
902
903         if (left > x86_pmu.max_period)
904                 left = x86_pmu.max_period;
905
906         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
907
908         /*
909          * The hw event starts counting from this event offset,
910          * mark it to be able to extra future deltas:
911          */
912         atomic64_set(&hwc->prev_count, (u64)-left);
913
914         err = checking_wrmsrl(hwc->event_base + idx,
915                              (u64)(-left) & x86_pmu.event_mask);
916
917         perf_event_update_userpage(event);
918
919         return ret;
920 }
921
922 static void x86_pmu_enable_event(struct perf_event *event)
923 {
924         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
925         if (cpuc->enabled)
926                 __x86_pmu_enable_event(&event->hw);
927 }
928
929 /*
930  * activate a single event
931  *
932  * The event is added to the group of enabled events
933  * but only if it can be scehduled with existing events.
934  *
935  * Called with PMU disabled. If successful and return value 1,
936  * then guaranteed to call perf_enable() and hw_perf_enable()
937  */
938 static int x86_pmu_enable(struct perf_event *event)
939 {
940         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
941         struct hw_perf_event *hwc;
942         int assign[X86_PMC_IDX_MAX];
943         int n, n0, ret;
944
945         hwc = &event->hw;
946
947         n0 = cpuc->n_events;
948         n = collect_events(cpuc, event, false);
949         if (n < 0)
950                 return n;
951
952         ret = x86_schedule_events(cpuc, n, assign);
953         if (ret)
954                 return ret;
955         /*
956          * copy new assignment, now we know it is possible
957          * will be used by hw_perf_enable()
958          */
959         memcpy(cpuc->assign, assign, n*sizeof(int));
960
961         cpuc->n_events = n;
962         cpuc->n_added += n - n0;
963
964         return 0;
965 }
966
967 static int x86_pmu_start(struct perf_event *event)
968 {
969         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
970         int idx = event->hw.idx;
971
972         if (idx == -1)
973                 return -EAGAIN;
974
975         x86_perf_event_set_period(event);
976         cpuc->events[idx] = event;
977         __set_bit(idx, cpuc->active_mask);
978         x86_pmu.enable(event);
979         perf_event_update_userpage(event);
980
981         return 0;
982 }
983
984 static void x86_pmu_unthrottle(struct perf_event *event)
985 {
986         int ret = x86_pmu_start(event);
987         WARN_ON_ONCE(ret);
988 }
989
990 void perf_event_print_debug(void)
991 {
992         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
993         struct cpu_hw_events *cpuc;
994         unsigned long flags;
995         int cpu, idx;
996
997         if (!x86_pmu.num_events)
998                 return;
999
1000         local_irq_save(flags);
1001
1002         cpu = smp_processor_id();
1003         cpuc = &per_cpu(cpu_hw_events, cpu);
1004
1005         if (x86_pmu.version >= 2) {
1006                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1007                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1008                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1009                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1010
1011                 pr_info("\n");
1012                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1013                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1014                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1015                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1016         }
1017         pr_info("CPU#%d: active:       %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1018
1019         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1020                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1021                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1022
1023                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1024
1025                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1026                         cpu, idx, pmc_ctrl);
1027                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1028                         cpu, idx, pmc_count);
1029                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1030                         cpu, idx, prev_left);
1031         }
1032         for (idx = 0; idx < x86_pmu.num_events_fixed; idx++) {
1033                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1034
1035                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1036                         cpu, idx, pmc_count);
1037         }
1038         local_irq_restore(flags);
1039 }
1040
1041 static void x86_pmu_stop(struct perf_event *event)
1042 {
1043         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1044         struct hw_perf_event *hwc = &event->hw;
1045         int idx = hwc->idx;
1046
1047         if (!__test_and_clear_bit(idx, cpuc->active_mask))
1048                 return;
1049
1050         x86_pmu.disable(event);
1051
1052         /*
1053          * Drain the remaining delta count out of a event
1054          * that we are disabling:
1055          */
1056         x86_perf_event_update(event);
1057
1058         cpuc->events[idx] = NULL;
1059 }
1060
1061 static void x86_pmu_disable(struct perf_event *event)
1062 {
1063         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1064         int i;
1065
1066         x86_pmu_stop(event);
1067
1068         for (i = 0; i < cpuc->n_events; i++) {
1069                 if (event == cpuc->event_list[i]) {
1070
1071                         if (x86_pmu.put_event_constraints)
1072                                 x86_pmu.put_event_constraints(cpuc, event);
1073
1074                         while (++i < cpuc->n_events)
1075                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1076
1077                         --cpuc->n_events;
1078                         break;
1079                 }
1080         }
1081         perf_event_update_userpage(event);
1082 }
1083
1084 static int x86_pmu_handle_irq(struct pt_regs *regs)
1085 {
1086         struct perf_sample_data data;
1087         struct cpu_hw_events *cpuc;
1088         struct perf_event *event;
1089         struct hw_perf_event *hwc;
1090         int idx, handled = 0;
1091         u64 val;
1092
1093         perf_sample_data_init(&data, 0);
1094
1095         cpuc = &__get_cpu_var(cpu_hw_events);
1096
1097         for (idx = 0; idx < x86_pmu.num_events; idx++) {
1098                 if (!test_bit(idx, cpuc->active_mask))
1099                         continue;
1100
1101                 event = cpuc->events[idx];
1102                 hwc = &event->hw;
1103
1104                 val = x86_perf_event_update(event);
1105                 if (val & (1ULL << (x86_pmu.event_bits - 1)))
1106                         continue;
1107
1108                 /*
1109                  * event overflow
1110                  */
1111                 handled         = 1;
1112                 data.period     = event->hw.last_period;
1113
1114                 if (!x86_perf_event_set_period(event))
1115                         continue;
1116
1117                 if (perf_event_overflow(event, 1, &data, regs))
1118                         x86_pmu_stop(event);
1119         }
1120
1121         if (handled)
1122                 inc_irq_stat(apic_perf_irqs);
1123
1124         return handled;
1125 }
1126
1127 void smp_perf_pending_interrupt(struct pt_regs *regs)
1128 {
1129         irq_enter();
1130         ack_APIC_irq();
1131         inc_irq_stat(apic_pending_irqs);
1132         perf_event_do_pending();
1133         irq_exit();
1134 }
1135
1136 void set_perf_event_pending(void)
1137 {
1138 #ifdef CONFIG_X86_LOCAL_APIC
1139         if (!x86_pmu.apic || !x86_pmu_initialized())
1140                 return;
1141
1142         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1143 #endif
1144 }
1145
1146 void perf_events_lapic_init(void)
1147 {
1148 #ifdef CONFIG_X86_LOCAL_APIC
1149         if (!x86_pmu.apic || !x86_pmu_initialized())
1150                 return;
1151
1152         /*
1153          * Always use NMI for PMU
1154          */
1155         apic_write(APIC_LVTPC, APIC_DM_NMI);
1156 #endif
1157 }
1158
1159 static int __kprobes
1160 perf_event_nmi_handler(struct notifier_block *self,
1161                          unsigned long cmd, void *__args)
1162 {
1163         struct die_args *args = __args;
1164         struct pt_regs *regs;
1165
1166         if (!atomic_read(&active_events))
1167                 return NOTIFY_DONE;
1168
1169         switch (cmd) {
1170         case DIE_NMI:
1171         case DIE_NMI_IPI:
1172                 break;
1173
1174         default:
1175                 return NOTIFY_DONE;
1176         }
1177
1178         regs = args->regs;
1179
1180 #ifdef CONFIG_X86_LOCAL_APIC
1181         apic_write(APIC_LVTPC, APIC_DM_NMI);
1182 #endif
1183         /*
1184          * Can't rely on the handled return value to say it was our NMI, two
1185          * events could trigger 'simultaneously' raising two back-to-back NMIs.
1186          *
1187          * If the first NMI handles both, the latter will be empty and daze
1188          * the CPU.
1189          */
1190         x86_pmu.handle_irq(regs);
1191
1192         return NOTIFY_STOP;
1193 }
1194
1195 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1196         .notifier_call          = perf_event_nmi_handler,
1197         .next                   = NULL,
1198         .priority               = 1
1199 };
1200
1201 static struct event_constraint unconstrained;
1202 static struct event_constraint emptyconstraint;
1203
1204 static struct event_constraint *
1205 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1206 {
1207         struct event_constraint *c;
1208
1209         if (x86_pmu.event_constraints) {
1210                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1211                         if ((event->hw.config & c->cmask) == c->code)
1212                                 return c;
1213                 }
1214         }
1215
1216         return &unconstrained;
1217 }
1218
1219 static int x86_event_sched_in(struct perf_event *event,
1220                           struct perf_cpu_context *cpuctx)
1221 {
1222         int ret = 0;
1223
1224         event->state = PERF_EVENT_STATE_ACTIVE;
1225         event->oncpu = smp_processor_id();
1226         event->tstamp_running += event->ctx->time - event->tstamp_stopped;
1227
1228         if (!is_x86_event(event))
1229                 ret = event->pmu->enable(event);
1230
1231         if (!ret && !is_software_event(event))
1232                 cpuctx->active_oncpu++;
1233
1234         if (!ret && event->attr.exclusive)
1235                 cpuctx->exclusive = 1;
1236
1237         return ret;
1238 }
1239
1240 static void x86_event_sched_out(struct perf_event *event,
1241                             struct perf_cpu_context *cpuctx)
1242 {
1243         event->state = PERF_EVENT_STATE_INACTIVE;
1244         event->oncpu = -1;
1245
1246         if (!is_x86_event(event))
1247                 event->pmu->disable(event);
1248
1249         event->tstamp_running -= event->ctx->time - event->tstamp_stopped;
1250
1251         if (!is_software_event(event))
1252                 cpuctx->active_oncpu--;
1253
1254         if (event->attr.exclusive || !cpuctx->active_oncpu)
1255                 cpuctx->exclusive = 0;
1256 }
1257
1258 /*
1259  * Called to enable a whole group of events.
1260  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
1261  * Assumes the caller has disabled interrupts and has
1262  * frozen the PMU with hw_perf_save_disable.
1263  *
1264  * called with PMU disabled. If successful and return value 1,
1265  * then guaranteed to call perf_enable() and hw_perf_enable()
1266  */
1267 int hw_perf_group_sched_in(struct perf_event *leader,
1268                struct perf_cpu_context *cpuctx,
1269                struct perf_event_context *ctx)
1270 {
1271         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1272         struct perf_event *sub;
1273         int assign[X86_PMC_IDX_MAX];
1274         int n0, n1, ret;
1275
1276         /* n0 = total number of events */
1277         n0 = collect_events(cpuc, leader, true);
1278         if (n0 < 0)
1279                 return n0;
1280
1281         ret = x86_schedule_events(cpuc, n0, assign);
1282         if (ret)
1283                 return ret;
1284
1285         ret = x86_event_sched_in(leader, cpuctx);
1286         if (ret)
1287                 return ret;
1288
1289         n1 = 1;
1290         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1291                 if (sub->state > PERF_EVENT_STATE_OFF) {
1292                         ret = x86_event_sched_in(sub, cpuctx);
1293                         if (ret)
1294                                 goto undo;
1295                         ++n1;
1296                 }
1297         }
1298         /*
1299          * copy new assignment, now we know it is possible
1300          * will be used by hw_perf_enable()
1301          */
1302         memcpy(cpuc->assign, assign, n0*sizeof(int));
1303
1304         cpuc->n_events  = n0;
1305         cpuc->n_added  += n1;
1306         ctx->nr_active += n1;
1307
1308         /*
1309          * 1 means successful and events are active
1310          * This is not quite true because we defer
1311          * actual activation until hw_perf_enable() but
1312          * this way we* ensure caller won't try to enable
1313          * individual events
1314          */
1315         return 1;
1316 undo:
1317         x86_event_sched_out(leader, cpuctx);
1318         n0  = 1;
1319         list_for_each_entry(sub, &leader->sibling_list, group_entry) {
1320                 if (sub->state == PERF_EVENT_STATE_ACTIVE) {
1321                         x86_event_sched_out(sub, cpuctx);
1322                         if (++n0 == n1)
1323                                 break;
1324                 }
1325         }
1326         return ret;
1327 }
1328
1329 #include "perf_event_amd.c"
1330 #include "perf_event_p6.c"
1331 #include "perf_event_intel.c"
1332
1333 static int __cpuinit
1334 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1335 {
1336         unsigned int cpu = (long)hcpu;
1337         int ret = NOTIFY_OK;
1338
1339         switch (action & ~CPU_TASKS_FROZEN) {
1340         case CPU_UP_PREPARE:
1341                 if (x86_pmu.cpu_prepare)
1342                         ret = x86_pmu.cpu_prepare(cpu);
1343                 break;
1344
1345         case CPU_STARTING:
1346                 if (x86_pmu.cpu_starting)
1347                         x86_pmu.cpu_starting(cpu);
1348                 break;
1349
1350         case CPU_DYING:
1351                 if (x86_pmu.cpu_dying)
1352                         x86_pmu.cpu_dying(cpu);
1353                 break;
1354
1355         case CPU_UP_CANCELED:
1356         case CPU_DEAD:
1357                 if (x86_pmu.cpu_dead)
1358                         x86_pmu.cpu_dead(cpu);
1359                 break;
1360
1361         default:
1362                 break;
1363         }
1364
1365         return ret;
1366 }
1367
1368 static void __init pmu_check_apic(void)
1369 {
1370         if (cpu_has_apic)
1371                 return;
1372
1373         x86_pmu.apic = 0;
1374         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1375         pr_info("no hardware sampling interrupt available.\n");
1376 }
1377
1378 void __init init_hw_perf_events(void)
1379 {
1380         struct event_constraint *c;
1381         int err;
1382
1383         pr_info("Performance Events: ");
1384
1385         switch (boot_cpu_data.x86_vendor) {
1386         case X86_VENDOR_INTEL:
1387                 err = intel_pmu_init();
1388                 break;
1389         case X86_VENDOR_AMD:
1390                 err = amd_pmu_init();
1391                 break;
1392         default:
1393                 return;
1394         }
1395         if (err != 0) {
1396                 pr_cont("no PMU driver, software events only.\n");
1397                 return;
1398         }
1399
1400         pmu_check_apic();
1401
1402         pr_cont("%s PMU driver.\n", x86_pmu.name);
1403
1404         if (x86_pmu.num_events > X86_PMC_MAX_GENERIC) {
1405                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1406                      x86_pmu.num_events, X86_PMC_MAX_GENERIC);
1407                 x86_pmu.num_events = X86_PMC_MAX_GENERIC;
1408         }
1409         perf_event_mask = (1 << x86_pmu.num_events) - 1;
1410         perf_max_events = x86_pmu.num_events;
1411
1412         if (x86_pmu.num_events_fixed > X86_PMC_MAX_FIXED) {
1413                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1414                      x86_pmu.num_events_fixed, X86_PMC_MAX_FIXED);
1415                 x86_pmu.num_events_fixed = X86_PMC_MAX_FIXED;
1416         }
1417
1418         perf_event_mask |=
1419                 ((1LL << x86_pmu.num_events_fixed)-1) << X86_PMC_IDX_FIXED;
1420         x86_pmu.intel_ctrl = perf_event_mask;
1421
1422         perf_events_lapic_init();
1423         register_die_notifier(&perf_event_nmi_notifier);
1424
1425         unconstrained = (struct event_constraint)
1426                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_events) - 1,
1427                                    0, x86_pmu.num_events);
1428
1429         if (x86_pmu.event_constraints) {
1430                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1431                         if (c->cmask != INTEL_ARCH_FIXED_MASK)
1432                                 continue;
1433
1434                         c->idxmsk64 |= (1ULL << x86_pmu.num_events) - 1;
1435                         c->weight += x86_pmu.num_events;
1436                 }
1437         }
1438
1439         pr_info("... version:                %d\n",     x86_pmu.version);
1440         pr_info("... bit width:              %d\n",     x86_pmu.event_bits);
1441         pr_info("... generic registers:      %d\n",     x86_pmu.num_events);
1442         pr_info("... value mask:             %016Lx\n", x86_pmu.event_mask);
1443         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1444         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_events_fixed);
1445         pr_info("... event mask:             %016Lx\n", perf_event_mask);
1446
1447         perf_cpu_notifier(x86_pmu_notifier);
1448 }
1449
1450 static inline void x86_pmu_read(struct perf_event *event)
1451 {
1452         x86_perf_event_update(event);
1453 }
1454
1455 static const struct pmu pmu = {
1456         .enable         = x86_pmu_enable,
1457         .disable        = x86_pmu_disable,
1458         .start          = x86_pmu_start,
1459         .stop           = x86_pmu_stop,
1460         .read           = x86_pmu_read,
1461         .unthrottle     = x86_pmu_unthrottle,
1462 };
1463
1464 /*
1465  * validate a single event group
1466  *
1467  * validation include:
1468  *      - check events are compatible which each other
1469  *      - events do not compete for the same counter
1470  *      - number of events <= number of counters
1471  *
1472  * validation ensures the group can be loaded onto the
1473  * PMU if it was the only group available.
1474  */
1475 static int validate_group(struct perf_event *event)
1476 {
1477         struct perf_event *leader = event->group_leader;
1478         struct cpu_hw_events *fake_cpuc;
1479         int ret, n;
1480
1481         ret = -ENOMEM;
1482         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1483         if (!fake_cpuc)
1484                 goto out;
1485
1486         /*
1487          * the event is not yet connected with its
1488          * siblings therefore we must first collect
1489          * existing siblings, then add the new event
1490          * before we can simulate the scheduling
1491          */
1492         ret = -ENOSPC;
1493         n = collect_events(fake_cpuc, leader, true);
1494         if (n < 0)
1495                 goto out_free;
1496
1497         fake_cpuc->n_events = n;
1498         n = collect_events(fake_cpuc, event, false);
1499         if (n < 0)
1500                 goto out_free;
1501
1502         fake_cpuc->n_events = n;
1503
1504         ret = x86_schedule_events(fake_cpuc, n, NULL);
1505
1506 out_free:
1507         kfree(fake_cpuc);
1508 out:
1509         return ret;
1510 }
1511
1512 const struct pmu *hw_perf_event_init(struct perf_event *event)
1513 {
1514         const struct pmu *tmp;
1515         int err;
1516
1517         err = __hw_perf_event_init(event);
1518         if (!err) {
1519                 /*
1520                  * we temporarily connect event to its pmu
1521                  * such that validate_group() can classify
1522                  * it as an x86 event using is_x86_event()
1523                  */
1524                 tmp = event->pmu;
1525                 event->pmu = &pmu;
1526
1527                 if (event->group_leader != event)
1528                         err = validate_group(event);
1529
1530                 event->pmu = tmp;
1531         }
1532         if (err) {
1533                 if (event->destroy)
1534                         event->destroy(event);
1535                 return ERR_PTR(err);
1536         }
1537
1538         return &pmu;
1539 }
1540
1541 /*
1542  * callchain support
1543  */
1544
1545 static inline
1546 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1547 {
1548         if (entry->nr < PERF_MAX_STACK_DEPTH)
1549                 entry->ip[entry->nr++] = ip;
1550 }
1551
1552 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_irq_entry);
1553 static DEFINE_PER_CPU(struct perf_callchain_entry, pmc_nmi_entry);
1554
1555
1556 static void
1557 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1558 {
1559         /* Ignore warnings */
1560 }
1561
1562 static void backtrace_warning(void *data, char *msg)
1563 {
1564         /* Ignore warnings */
1565 }
1566
1567 static int backtrace_stack(void *data, char *name)
1568 {
1569         return 0;
1570 }
1571
1572 static void backtrace_address(void *data, unsigned long addr, int reliable)
1573 {
1574         struct perf_callchain_entry *entry = data;
1575
1576         if (reliable)
1577                 callchain_store(entry, addr);
1578 }
1579
1580 static const struct stacktrace_ops backtrace_ops = {
1581         .warning                = backtrace_warning,
1582         .warning_symbol         = backtrace_warning_symbol,
1583         .stack                  = backtrace_stack,
1584         .address                = backtrace_address,
1585         .walk_stack             = print_context_stack_bp,
1586 };
1587
1588 #include "../dumpstack.h"
1589
1590 static void
1591 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1592 {
1593         callchain_store(entry, PERF_CONTEXT_KERNEL);
1594         callchain_store(entry, regs->ip);
1595
1596         dump_trace(NULL, regs, NULL, regs->bp, &backtrace_ops, entry);
1597 }
1598
1599 /*
1600  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1601  */
1602 static unsigned long
1603 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1604 {
1605         unsigned long offset, addr = (unsigned long)from;
1606         int type = in_nmi() ? KM_NMI : KM_IRQ0;
1607         unsigned long size, len = 0;
1608         struct page *page;
1609         void *map;
1610         int ret;
1611
1612         do {
1613                 ret = __get_user_pages_fast(addr, 1, 0, &page);
1614                 if (!ret)
1615                         break;
1616
1617                 offset = addr & (PAGE_SIZE - 1);
1618                 size = min(PAGE_SIZE - offset, n - len);
1619
1620                 map = kmap_atomic(page, type);
1621                 memcpy(to, map+offset, size);
1622                 kunmap_atomic(map, type);
1623                 put_page(page);
1624
1625                 len  += size;
1626                 to   += size;
1627                 addr += size;
1628
1629         } while (len < n);
1630
1631         return len;
1632 }
1633
1634 #ifdef CONFIG_COMPAT
1635 static inline int
1636 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1637 {
1638         /* 32-bit process in 64-bit kernel. */
1639         struct stack_frame_ia32 frame;
1640         const void __user *fp;
1641
1642         if (!test_thread_flag(TIF_IA32))
1643                 return 0;
1644
1645         fp = compat_ptr(regs->bp);
1646         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1647                 unsigned long bytes;
1648                 frame.next_frame     = 0;
1649                 frame.return_address = 0;
1650
1651                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1652                 if (bytes != sizeof(frame))
1653                         break;
1654
1655                 if (fp < compat_ptr(regs->sp))
1656                         break;
1657
1658                 callchain_store(entry, frame.return_address);
1659                 fp = compat_ptr(frame.next_frame);
1660         }
1661         return 1;
1662 }
1663 #else
1664 static inline int
1665 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1666 {
1667     return 0;
1668 }
1669 #endif
1670
1671 static void
1672 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1673 {
1674         struct stack_frame frame;
1675         const void __user *fp;
1676
1677         if (!user_mode(regs))
1678                 regs = task_pt_regs(current);
1679
1680         fp = (void __user *)regs->bp;
1681
1682         callchain_store(entry, PERF_CONTEXT_USER);
1683         callchain_store(entry, regs->ip);
1684
1685         if (perf_callchain_user32(regs, entry))
1686                 return;
1687
1688         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1689                 unsigned long bytes;
1690                 frame.next_frame             = NULL;
1691                 frame.return_address = 0;
1692
1693                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1694                 if (bytes != sizeof(frame))
1695                         break;
1696
1697                 if ((unsigned long)fp < regs->sp)
1698                         break;
1699
1700                 callchain_store(entry, frame.return_address);
1701                 fp = frame.next_frame;
1702         }
1703 }
1704
1705 static void
1706 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1707 {
1708         int is_user;
1709
1710         if (!regs)
1711                 return;
1712
1713         is_user = user_mode(regs);
1714
1715         if (is_user && current->state != TASK_RUNNING)
1716                 return;
1717
1718         if (!is_user)
1719                 perf_callchain_kernel(regs, entry);
1720
1721         if (current->mm)
1722                 perf_callchain_user(regs, entry);
1723 }
1724
1725 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1726 {
1727         struct perf_callchain_entry *entry;
1728
1729         if (in_nmi())
1730                 entry = &__get_cpu_var(pmc_nmi_entry);
1731         else
1732                 entry = &__get_cpu_var(pmc_irq_entry);
1733
1734         entry->nr = 0;
1735
1736         perf_do_callchain(regs, entry);
1737
1738         return entry;
1739 }
1740
1741 void perf_arch_fetch_caller_regs(struct pt_regs *regs, unsigned long ip, int skip)
1742 {
1743         regs->ip = ip;
1744         /*
1745          * perf_arch_fetch_caller_regs adds another call, we need to increment
1746          * the skip level
1747          */
1748         regs->bp = rewind_frame_pointer(skip + 1);
1749         regs->cs = __KERNEL_CS;
1750         local_save_flags(regs->flags);
1751 }