Merge branch 'for-2.6.38' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/percpu
[linux-2.6.git] / arch / x86 / kernel / cpu / perf_event.c
1 /*
2  * Performance events x86 architecture code
3  *
4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6  *  Copyright (C) 2009 Jaswinder Singh Rajput
7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9  *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10  *  Copyright (C) 2009 Google, Inc., Stephane Eranian
11  *
12  *  For licencing details see kernel-base/COPYING
13  */
14
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
28
29 #include <asm/apic.h>
30 #include <asm/stacktrace.h>
31 #include <asm/nmi.h>
32 #include <asm/compat.h>
33
34 #if 0
35 #undef wrmsrl
36 #define wrmsrl(msr, val)                                        \
37 do {                                                            \
38         trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39                         (unsigned long)(val));                  \
40         native_write_msr((msr), (u32)((u64)(val)),              \
41                         (u32)((u64)(val) >> 32));               \
42 } while (0)
43 #endif
44
45 /*
46  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
47  */
48 static unsigned long
49 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
50 {
51         unsigned long offset, addr = (unsigned long)from;
52         unsigned long size, len = 0;
53         struct page *page;
54         void *map;
55         int ret;
56
57         do {
58                 ret = __get_user_pages_fast(addr, 1, 0, &page);
59                 if (!ret)
60                         break;
61
62                 offset = addr & (PAGE_SIZE - 1);
63                 size = min(PAGE_SIZE - offset, n - len);
64
65                 map = kmap_atomic(page);
66                 memcpy(to, map+offset, size);
67                 kunmap_atomic(map);
68                 put_page(page);
69
70                 len  += size;
71                 to   += size;
72                 addr += size;
73
74         } while (len < n);
75
76         return len;
77 }
78
79 struct event_constraint {
80         union {
81                 unsigned long   idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
82                 u64             idxmsk64;
83         };
84         u64     code;
85         u64     cmask;
86         int     weight;
87 };
88
89 struct amd_nb {
90         int nb_id;  /* NorthBridge id */
91         int refcnt; /* reference count */
92         struct perf_event *owners[X86_PMC_IDX_MAX];
93         struct event_constraint event_constraints[X86_PMC_IDX_MAX];
94 };
95
96 #define MAX_LBR_ENTRIES         16
97
98 struct cpu_hw_events {
99         /*
100          * Generic x86 PMC bits
101          */
102         struct perf_event       *events[X86_PMC_IDX_MAX]; /* in counter order */
103         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
104         unsigned long           running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
105         int                     enabled;
106
107         int                     n_events;
108         int                     n_added;
109         int                     n_txn;
110         int                     assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
111         u64                     tags[X86_PMC_IDX_MAX];
112         struct perf_event       *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
113
114         unsigned int            group_flag;
115
116         /*
117          * Intel DebugStore bits
118          */
119         struct debug_store      *ds;
120         u64                     pebs_enabled;
121
122         /*
123          * Intel LBR bits
124          */
125         int                             lbr_users;
126         void                            *lbr_context;
127         struct perf_branch_stack        lbr_stack;
128         struct perf_branch_entry        lbr_entries[MAX_LBR_ENTRIES];
129
130         /*
131          * AMD specific bits
132          */
133         struct amd_nb           *amd_nb;
134 };
135
136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
137         { .idxmsk64 = (n) },            \
138         .code = (c),                    \
139         .cmask = (m),                   \
140         .weight = (w),                  \
141 }
142
143 #define EVENT_CONSTRAINT(c, n, m)       \
144         __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
145
146 /*
147  * Constraint on the Event code.
148  */
149 #define INTEL_EVENT_CONSTRAINT(c, n)    \
150         EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
151
152 /*
153  * Constraint on the Event code + UMask + fixed-mask
154  *
155  * filter mask to validate fixed counter events.
156  * the following filters disqualify for fixed counters:
157  *  - inv
158  *  - edge
159  *  - cnt-mask
160  *  The other filters are supported by fixed counters.
161  *  The any-thread option is supported starting with v3.
162  */
163 #define FIXED_EVENT_CONSTRAINT(c, n)    \
164         EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
165
166 /*
167  * Constraint on the Event code + UMask
168  */
169 #define PEBS_EVENT_CONSTRAINT(c, n)     \
170         EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
171
172 #define EVENT_CONSTRAINT_END            \
173         EVENT_CONSTRAINT(0, 0, 0)
174
175 #define for_each_event_constraint(e, c) \
176         for ((e) = (c); (e)->weight; (e)++)
177
178 union perf_capabilities {
179         struct {
180                 u64     lbr_format    : 6;
181                 u64     pebs_trap     : 1;
182                 u64     pebs_arch_reg : 1;
183                 u64     pebs_format   : 4;
184                 u64     smm_freeze    : 1;
185         };
186         u64     capabilities;
187 };
188
189 /*
190  * struct x86_pmu - generic x86 pmu
191  */
192 struct x86_pmu {
193         /*
194          * Generic x86 PMC bits
195          */
196         const char      *name;
197         int             version;
198         int             (*handle_irq)(struct pt_regs *);
199         void            (*disable_all)(void);
200         void            (*enable_all)(int added);
201         void            (*enable)(struct perf_event *);
202         void            (*disable)(struct perf_event *);
203         int             (*hw_config)(struct perf_event *event);
204         int             (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
205         unsigned        eventsel;
206         unsigned        perfctr;
207         u64             (*event_map)(int);
208         int             max_events;
209         int             num_counters;
210         int             num_counters_fixed;
211         int             cntval_bits;
212         u64             cntval_mask;
213         int             apic;
214         u64             max_period;
215         struct event_constraint *
216                         (*get_event_constraints)(struct cpu_hw_events *cpuc,
217                                                  struct perf_event *event);
218
219         void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
220                                                  struct perf_event *event);
221         struct event_constraint *event_constraints;
222         void            (*quirks)(void);
223         int             perfctr_second_write;
224
225         int             (*cpu_prepare)(int cpu);
226         void            (*cpu_starting)(int cpu);
227         void            (*cpu_dying)(int cpu);
228         void            (*cpu_dead)(int cpu);
229
230         /*
231          * Intel Arch Perfmon v2+
232          */
233         u64                     intel_ctrl;
234         union perf_capabilities intel_cap;
235
236         /*
237          * Intel DebugStore bits
238          */
239         int             bts, pebs;
240         int             bts_active, pebs_active;
241         int             pebs_record_size;
242         void            (*drain_pebs)(struct pt_regs *regs);
243         struct event_constraint *pebs_constraints;
244
245         /*
246          * Intel LBR
247          */
248         unsigned long   lbr_tos, lbr_from, lbr_to; /* MSR base regs       */
249         int             lbr_nr;                    /* hardware stack size */
250 };
251
252 static struct x86_pmu x86_pmu __read_mostly;
253
254 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
255         .enabled = 1,
256 };
257
258 static int x86_perf_event_set_period(struct perf_event *event);
259
260 /*
261  * Generalized hw caching related hw_event table, filled
262  * in on a per model basis. A value of 0 means
263  * 'not supported', -1 means 'hw_event makes no sense on
264  * this CPU', any other value means the raw hw_event
265  * ID.
266  */
267
268 #define C(x) PERF_COUNT_HW_CACHE_##x
269
270 static u64 __read_mostly hw_cache_event_ids
271                                 [PERF_COUNT_HW_CACHE_MAX]
272                                 [PERF_COUNT_HW_CACHE_OP_MAX]
273                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
274
275 /*
276  * Propagate event elapsed time into the generic event.
277  * Can only be executed on the CPU where the event is active.
278  * Returns the delta events processed.
279  */
280 static u64
281 x86_perf_event_update(struct perf_event *event)
282 {
283         struct hw_perf_event *hwc = &event->hw;
284         int shift = 64 - x86_pmu.cntval_bits;
285         u64 prev_raw_count, new_raw_count;
286         int idx = hwc->idx;
287         s64 delta;
288
289         if (idx == X86_PMC_IDX_FIXED_BTS)
290                 return 0;
291
292         /*
293          * Careful: an NMI might modify the previous event value.
294          *
295          * Our tactic to handle this is to first atomically read and
296          * exchange a new raw count - then add that new-prev delta
297          * count to the generic event atomically:
298          */
299 again:
300         prev_raw_count = local64_read(&hwc->prev_count);
301         rdmsrl(hwc->event_base + idx, new_raw_count);
302
303         if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
304                                         new_raw_count) != prev_raw_count)
305                 goto again;
306
307         /*
308          * Now we have the new raw value and have updated the prev
309          * timestamp already. We can now calculate the elapsed delta
310          * (event-)time and add that to the generic event.
311          *
312          * Careful, not all hw sign-extends above the physical width
313          * of the count.
314          */
315         delta = (new_raw_count << shift) - (prev_raw_count << shift);
316         delta >>= shift;
317
318         local64_add(delta, &event->count);
319         local64_sub(delta, &hwc->period_left);
320
321         return new_raw_count;
322 }
323
324 static atomic_t active_events;
325 static DEFINE_MUTEX(pmc_reserve_mutex);
326
327 #ifdef CONFIG_X86_LOCAL_APIC
328
329 static bool reserve_pmc_hardware(void)
330 {
331         int i;
332
333         for (i = 0; i < x86_pmu.num_counters; i++) {
334                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
335                         goto perfctr_fail;
336         }
337
338         for (i = 0; i < x86_pmu.num_counters; i++) {
339                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
340                         goto eventsel_fail;
341         }
342
343         return true;
344
345 eventsel_fail:
346         for (i--; i >= 0; i--)
347                 release_evntsel_nmi(x86_pmu.eventsel + i);
348
349         i = x86_pmu.num_counters;
350
351 perfctr_fail:
352         for (i--; i >= 0; i--)
353                 release_perfctr_nmi(x86_pmu.perfctr + i);
354
355         return false;
356 }
357
358 static void release_pmc_hardware(void)
359 {
360         int i;
361
362         for (i = 0; i < x86_pmu.num_counters; i++) {
363                 release_perfctr_nmi(x86_pmu.perfctr + i);
364                 release_evntsel_nmi(x86_pmu.eventsel + i);
365         }
366 }
367
368 #else
369
370 static bool reserve_pmc_hardware(void) { return true; }
371 static void release_pmc_hardware(void) {}
372
373 #endif
374
375 static bool check_hw_exists(void)
376 {
377         u64 val, val_new = 0;
378         int i, reg, ret = 0;
379
380         /*
381          * Check to see if the BIOS enabled any of the counters, if so
382          * complain and bail.
383          */
384         for (i = 0; i < x86_pmu.num_counters; i++) {
385                 reg = x86_pmu.eventsel + i;
386                 ret = rdmsrl_safe(reg, &val);
387                 if (ret)
388                         goto msr_fail;
389                 if (val & ARCH_PERFMON_EVENTSEL_ENABLE)
390                         goto bios_fail;
391         }
392
393         if (x86_pmu.num_counters_fixed) {
394                 reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
395                 ret = rdmsrl_safe(reg, &val);
396                 if (ret)
397                         goto msr_fail;
398                 for (i = 0; i < x86_pmu.num_counters_fixed; i++) {
399                         if (val & (0x03 << i*4))
400                                 goto bios_fail;
401                 }
402         }
403
404         /*
405          * Now write a value and read it back to see if it matches,
406          * this is needed to detect certain hardware emulators (qemu/kvm)
407          * that don't trap on the MSR access and always return 0s.
408          */
409         val = 0xabcdUL;
410         ret = checking_wrmsrl(x86_pmu.perfctr, val);
411         ret |= rdmsrl_safe(x86_pmu.perfctr, &val_new);
412         if (ret || val != val_new)
413                 goto msr_fail;
414
415         return true;
416
417 bios_fail:
418         printk(KERN_CONT "Broken BIOS detected, using software events only.\n");
419         printk(KERN_ERR FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", reg, val);
420         return false;
421
422 msr_fail:
423         printk(KERN_CONT "Broken PMU hardware detected, using software events only.\n");
424         return false;
425 }
426
427 static void reserve_ds_buffers(void);
428 static void release_ds_buffers(void);
429
430 static void hw_perf_event_destroy(struct perf_event *event)
431 {
432         if (atomic_dec_and_mutex_lock(&active_events, &pmc_reserve_mutex)) {
433                 release_pmc_hardware();
434                 release_ds_buffers();
435                 mutex_unlock(&pmc_reserve_mutex);
436         }
437 }
438
439 static inline int x86_pmu_initialized(void)
440 {
441         return x86_pmu.handle_irq != NULL;
442 }
443
444 static inline int
445 set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event_attr *attr)
446 {
447         unsigned int cache_type, cache_op, cache_result;
448         u64 config, val;
449
450         config = attr->config;
451
452         cache_type = (config >>  0) & 0xff;
453         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
454                 return -EINVAL;
455
456         cache_op = (config >>  8) & 0xff;
457         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
458                 return -EINVAL;
459
460         cache_result = (config >> 16) & 0xff;
461         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
462                 return -EINVAL;
463
464         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
465
466         if (val == 0)
467                 return -ENOENT;
468
469         if (val == -1)
470                 return -EINVAL;
471
472         hwc->config |= val;
473
474         return 0;
475 }
476
477 static int x86_setup_perfctr(struct perf_event *event)
478 {
479         struct perf_event_attr *attr = &event->attr;
480         struct hw_perf_event *hwc = &event->hw;
481         u64 config;
482
483         if (!is_sampling_event(event)) {
484                 hwc->sample_period = x86_pmu.max_period;
485                 hwc->last_period = hwc->sample_period;
486                 local64_set(&hwc->period_left, hwc->sample_period);
487         } else {
488                 /*
489                  * If we have a PMU initialized but no APIC
490                  * interrupts, we cannot sample hardware
491                  * events (user-space has to fall back and
492                  * sample via a hrtimer based software event):
493                  */
494                 if (!x86_pmu.apic)
495                         return -EOPNOTSUPP;
496         }
497
498         if (attr->type == PERF_TYPE_RAW)
499                 return 0;
500
501         if (attr->type == PERF_TYPE_HW_CACHE)
502                 return set_ext_hw_attr(hwc, attr);
503
504         if (attr->config >= x86_pmu.max_events)
505                 return -EINVAL;
506
507         /*
508          * The generic map:
509          */
510         config = x86_pmu.event_map(attr->config);
511
512         if (config == 0)
513                 return -ENOENT;
514
515         if (config == -1LL)
516                 return -EINVAL;
517
518         /*
519          * Branch tracing:
520          */
521         if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
522             (hwc->sample_period == 1)) {
523                 /* BTS is not supported by this architecture. */
524                 if (!x86_pmu.bts_active)
525                         return -EOPNOTSUPP;
526
527                 /* BTS is currently only allowed for user-mode. */
528                 if (!attr->exclude_kernel)
529                         return -EOPNOTSUPP;
530         }
531
532         hwc->config |= config;
533
534         return 0;
535 }
536
537 static int x86_pmu_hw_config(struct perf_event *event)
538 {
539         if (event->attr.precise_ip) {
540                 int precise = 0;
541
542                 /* Support for constant skid */
543                 if (x86_pmu.pebs_active) {
544                         precise++;
545
546                         /* Support for IP fixup */
547                         if (x86_pmu.lbr_nr)
548                                 precise++;
549                 }
550
551                 if (event->attr.precise_ip > precise)
552                         return -EOPNOTSUPP;
553         }
554
555         /*
556          * Generate PMC IRQs:
557          * (keep 'enabled' bit clear for now)
558          */
559         event->hw.config = ARCH_PERFMON_EVENTSEL_INT;
560
561         /*
562          * Count user and OS events unless requested not to
563          */
564         if (!event->attr.exclude_user)
565                 event->hw.config |= ARCH_PERFMON_EVENTSEL_USR;
566         if (!event->attr.exclude_kernel)
567                 event->hw.config |= ARCH_PERFMON_EVENTSEL_OS;
568
569         if (event->attr.type == PERF_TYPE_RAW)
570                 event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK;
571
572         return x86_setup_perfctr(event);
573 }
574
575 /*
576  * Setup the hardware configuration for a given attr_type
577  */
578 static int __x86_pmu_event_init(struct perf_event *event)
579 {
580         int err;
581
582         if (!x86_pmu_initialized())
583                 return -ENODEV;
584
585         err = 0;
586         if (!atomic_inc_not_zero(&active_events)) {
587                 mutex_lock(&pmc_reserve_mutex);
588                 if (atomic_read(&active_events) == 0) {
589                         if (!reserve_pmc_hardware())
590                                 err = -EBUSY;
591                         else
592                                 reserve_ds_buffers();
593                 }
594                 if (!err)
595                         atomic_inc(&active_events);
596                 mutex_unlock(&pmc_reserve_mutex);
597         }
598         if (err)
599                 return err;
600
601         event->destroy = hw_perf_event_destroy;
602
603         event->hw.idx = -1;
604         event->hw.last_cpu = -1;
605         event->hw.last_tag = ~0ULL;
606
607         return x86_pmu.hw_config(event);
608 }
609
610 static void x86_pmu_disable_all(void)
611 {
612         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
613         int idx;
614
615         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
616                 u64 val;
617
618                 if (!test_bit(idx, cpuc->active_mask))
619                         continue;
620                 rdmsrl(x86_pmu.eventsel + idx, val);
621                 if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE))
622                         continue;
623                 val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
624                 wrmsrl(x86_pmu.eventsel + idx, val);
625         }
626 }
627
628 static void x86_pmu_disable(struct pmu *pmu)
629 {
630         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
631
632         if (!x86_pmu_initialized())
633                 return;
634
635         if (!cpuc->enabled)
636                 return;
637
638         cpuc->n_added = 0;
639         cpuc->enabled = 0;
640         barrier();
641
642         x86_pmu.disable_all();
643 }
644
645 static void x86_pmu_enable_all(int added)
646 {
647         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
648         int idx;
649
650         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
651                 struct perf_event *event = cpuc->events[idx];
652                 u64 val;
653
654                 if (!test_bit(idx, cpuc->active_mask))
655                         continue;
656
657                 val = event->hw.config;
658                 val |= ARCH_PERFMON_EVENTSEL_ENABLE;
659                 wrmsrl(x86_pmu.eventsel + idx, val);
660         }
661 }
662
663 static struct pmu pmu;
664
665 static inline int is_x86_event(struct perf_event *event)
666 {
667         return event->pmu == &pmu;
668 }
669
670 static int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
671 {
672         struct event_constraint *c, *constraints[X86_PMC_IDX_MAX];
673         unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
674         int i, j, w, wmax, num = 0;
675         struct hw_perf_event *hwc;
676
677         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
678
679         for (i = 0; i < n; i++) {
680                 c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
681                 constraints[i] = c;
682         }
683
684         /*
685          * fastpath, try to reuse previous register
686          */
687         for (i = 0; i < n; i++) {
688                 hwc = &cpuc->event_list[i]->hw;
689                 c = constraints[i];
690
691                 /* never assigned */
692                 if (hwc->idx == -1)
693                         break;
694
695                 /* constraint still honored */
696                 if (!test_bit(hwc->idx, c->idxmsk))
697                         break;
698
699                 /* not already used */
700                 if (test_bit(hwc->idx, used_mask))
701                         break;
702
703                 __set_bit(hwc->idx, used_mask);
704                 if (assign)
705                         assign[i] = hwc->idx;
706         }
707         if (i == n)
708                 goto done;
709
710         /*
711          * begin slow path
712          */
713
714         bitmap_zero(used_mask, X86_PMC_IDX_MAX);
715
716         /*
717          * weight = number of possible counters
718          *
719          * 1    = most constrained, only works on one counter
720          * wmax = least constrained, works on any counter
721          *
722          * assign events to counters starting with most
723          * constrained events.
724          */
725         wmax = x86_pmu.num_counters;
726
727         /*
728          * when fixed event counters are present,
729          * wmax is incremented by 1 to account
730          * for one more choice
731          */
732         if (x86_pmu.num_counters_fixed)
733                 wmax++;
734
735         for (w = 1, num = n; num && w <= wmax; w++) {
736                 /* for each event */
737                 for (i = 0; num && i < n; i++) {
738                         c = constraints[i];
739                         hwc = &cpuc->event_list[i]->hw;
740
741                         if (c->weight != w)
742                                 continue;
743
744                         for_each_set_bit(j, c->idxmsk, X86_PMC_IDX_MAX) {
745                                 if (!test_bit(j, used_mask))
746                                         break;
747                         }
748
749                         if (j == X86_PMC_IDX_MAX)
750                                 break;
751
752                         __set_bit(j, used_mask);
753
754                         if (assign)
755                                 assign[i] = j;
756                         num--;
757                 }
758         }
759 done:
760         /*
761          * scheduling failed or is just a simulation,
762          * free resources if necessary
763          */
764         if (!assign || num) {
765                 for (i = 0; i < n; i++) {
766                         if (x86_pmu.put_event_constraints)
767                                 x86_pmu.put_event_constraints(cpuc, cpuc->event_list[i]);
768                 }
769         }
770         return num ? -ENOSPC : 0;
771 }
772
773 /*
774  * dogrp: true if must collect siblings events (group)
775  * returns total number of events and error code
776  */
777 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
778 {
779         struct perf_event *event;
780         int n, max_count;
781
782         max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
783
784         /* current number of events already accepted */
785         n = cpuc->n_events;
786
787         if (is_x86_event(leader)) {
788                 if (n >= max_count)
789                         return -ENOSPC;
790                 cpuc->event_list[n] = leader;
791                 n++;
792         }
793         if (!dogrp)
794                 return n;
795
796         list_for_each_entry(event, &leader->sibling_list, group_entry) {
797                 if (!is_x86_event(event) ||
798                     event->state <= PERF_EVENT_STATE_OFF)
799                         continue;
800
801                 if (n >= max_count)
802                         return -ENOSPC;
803
804                 cpuc->event_list[n] = event;
805                 n++;
806         }
807         return n;
808 }
809
810 static inline void x86_assign_hw_event(struct perf_event *event,
811                                 struct cpu_hw_events *cpuc, int i)
812 {
813         struct hw_perf_event *hwc = &event->hw;
814
815         hwc->idx = cpuc->assign[i];
816         hwc->last_cpu = smp_processor_id();
817         hwc->last_tag = ++cpuc->tags[i];
818
819         if (hwc->idx == X86_PMC_IDX_FIXED_BTS) {
820                 hwc->config_base = 0;
821                 hwc->event_base = 0;
822         } else if (hwc->idx >= X86_PMC_IDX_FIXED) {
823                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
824                 /*
825                  * We set it so that event_base + idx in wrmsr/rdmsr maps to
826                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
827                  */
828                 hwc->event_base =
829                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
830         } else {
831                 hwc->config_base = x86_pmu.eventsel;
832                 hwc->event_base  = x86_pmu.perfctr;
833         }
834 }
835
836 static inline int match_prev_assignment(struct hw_perf_event *hwc,
837                                         struct cpu_hw_events *cpuc,
838                                         int i)
839 {
840         return hwc->idx == cpuc->assign[i] &&
841                 hwc->last_cpu == smp_processor_id() &&
842                 hwc->last_tag == cpuc->tags[i];
843 }
844
845 static void x86_pmu_start(struct perf_event *event, int flags);
846 static void x86_pmu_stop(struct perf_event *event, int flags);
847
848 static void x86_pmu_enable(struct pmu *pmu)
849 {
850         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
851         struct perf_event *event;
852         struct hw_perf_event *hwc;
853         int i, added = cpuc->n_added;
854
855         if (!x86_pmu_initialized())
856                 return;
857
858         if (cpuc->enabled)
859                 return;
860
861         if (cpuc->n_added) {
862                 int n_running = cpuc->n_events - cpuc->n_added;
863                 /*
864                  * apply assignment obtained either from
865                  * hw_perf_group_sched_in() or x86_pmu_enable()
866                  *
867                  * step1: save events moving to new counters
868                  * step2: reprogram moved events into new counters
869                  */
870                 for (i = 0; i < n_running; i++) {
871                         event = cpuc->event_list[i];
872                         hwc = &event->hw;
873
874                         /*
875                          * we can avoid reprogramming counter if:
876                          * - assigned same counter as last time
877                          * - running on same CPU as last time
878                          * - no other event has used the counter since
879                          */
880                         if (hwc->idx == -1 ||
881                             match_prev_assignment(hwc, cpuc, i))
882                                 continue;
883
884                         /*
885                          * Ensure we don't accidentally enable a stopped
886                          * counter simply because we rescheduled.
887                          */
888                         if (hwc->state & PERF_HES_STOPPED)
889                                 hwc->state |= PERF_HES_ARCH;
890
891                         x86_pmu_stop(event, PERF_EF_UPDATE);
892                 }
893
894                 for (i = 0; i < cpuc->n_events; i++) {
895                         event = cpuc->event_list[i];
896                         hwc = &event->hw;
897
898                         if (!match_prev_assignment(hwc, cpuc, i))
899                                 x86_assign_hw_event(event, cpuc, i);
900                         else if (i < n_running)
901                                 continue;
902
903                         if (hwc->state & PERF_HES_ARCH)
904                                 continue;
905
906                         x86_pmu_start(event, PERF_EF_RELOAD);
907                 }
908                 cpuc->n_added = 0;
909                 perf_events_lapic_init();
910         }
911
912         cpuc->enabled = 1;
913         barrier();
914
915         x86_pmu.enable_all(added);
916 }
917
918 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
919                                           u64 enable_mask)
920 {
921         wrmsrl(hwc->config_base + hwc->idx, hwc->config | enable_mask);
922 }
923
924 static inline void x86_pmu_disable_event(struct perf_event *event)
925 {
926         struct hw_perf_event *hwc = &event->hw;
927
928         wrmsrl(hwc->config_base + hwc->idx, hwc->config);
929 }
930
931 static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left);
932
933 /*
934  * Set the next IRQ period, based on the hwc->period_left value.
935  * To be called with the event disabled in hw:
936  */
937 static int
938 x86_perf_event_set_period(struct perf_event *event)
939 {
940         struct hw_perf_event *hwc = &event->hw;
941         s64 left = local64_read(&hwc->period_left);
942         s64 period = hwc->sample_period;
943         int ret = 0, idx = hwc->idx;
944
945         if (idx == X86_PMC_IDX_FIXED_BTS)
946                 return 0;
947
948         /*
949          * If we are way outside a reasonable range then just skip forward:
950          */
951         if (unlikely(left <= -period)) {
952                 left = period;
953                 local64_set(&hwc->period_left, left);
954                 hwc->last_period = period;
955                 ret = 1;
956         }
957
958         if (unlikely(left <= 0)) {
959                 left += period;
960                 local64_set(&hwc->period_left, left);
961                 hwc->last_period = period;
962                 ret = 1;
963         }
964         /*
965          * Quirk: certain CPUs dont like it if just 1 hw_event is left:
966          */
967         if (unlikely(left < 2))
968                 left = 2;
969
970         if (left > x86_pmu.max_period)
971                 left = x86_pmu.max_period;
972
973         per_cpu(pmc_prev_left[idx], smp_processor_id()) = left;
974
975         /*
976          * The hw event starts counting from this event offset,
977          * mark it to be able to extra future deltas:
978          */
979         local64_set(&hwc->prev_count, (u64)-left);
980
981         wrmsrl(hwc->event_base + idx, (u64)(-left) & x86_pmu.cntval_mask);
982
983         /*
984          * Due to erratum on certan cpu we need
985          * a second write to be sure the register
986          * is updated properly
987          */
988         if (x86_pmu.perfctr_second_write) {
989                 wrmsrl(hwc->event_base + idx,
990                         (u64)(-left) & x86_pmu.cntval_mask);
991         }
992
993         perf_event_update_userpage(event);
994
995         return ret;
996 }
997
998 static void x86_pmu_enable_event(struct perf_event *event)
999 {
1000         if (__this_cpu_read(cpu_hw_events.enabled))
1001                 __x86_pmu_enable_event(&event->hw,
1002                                        ARCH_PERFMON_EVENTSEL_ENABLE);
1003 }
1004
1005 /*
1006  * Add a single event to the PMU.
1007  *
1008  * The event is added to the group of enabled events
1009  * but only if it can be scehduled with existing events.
1010  */
1011 static int x86_pmu_add(struct perf_event *event, int flags)
1012 {
1013         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1014         struct hw_perf_event *hwc;
1015         int assign[X86_PMC_IDX_MAX];
1016         int n, n0, ret;
1017
1018         hwc = &event->hw;
1019
1020         perf_pmu_disable(event->pmu);
1021         n0 = cpuc->n_events;
1022         ret = n = collect_events(cpuc, event, false);
1023         if (ret < 0)
1024                 goto out;
1025
1026         hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
1027         if (!(flags & PERF_EF_START))
1028                 hwc->state |= PERF_HES_ARCH;
1029
1030         /*
1031          * If group events scheduling transaction was started,
1032          * skip the schedulability test here, it will be peformed
1033          * at commit time (->commit_txn) as a whole
1034          */
1035         if (cpuc->group_flag & PERF_EVENT_TXN)
1036                 goto done_collect;
1037
1038         ret = x86_pmu.schedule_events(cpuc, n, assign);
1039         if (ret)
1040                 goto out;
1041         /*
1042          * copy new assignment, now we know it is possible
1043          * will be used by hw_perf_enable()
1044          */
1045         memcpy(cpuc->assign, assign, n*sizeof(int));
1046
1047 done_collect:
1048         cpuc->n_events = n;
1049         cpuc->n_added += n - n0;
1050         cpuc->n_txn += n - n0;
1051
1052         ret = 0;
1053 out:
1054         perf_pmu_enable(event->pmu);
1055         return ret;
1056 }
1057
1058 static void x86_pmu_start(struct perf_event *event, int flags)
1059 {
1060         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1061         int idx = event->hw.idx;
1062
1063         if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
1064                 return;
1065
1066         if (WARN_ON_ONCE(idx == -1))
1067                 return;
1068
1069         if (flags & PERF_EF_RELOAD) {
1070                 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1071                 x86_perf_event_set_period(event);
1072         }
1073
1074         event->hw.state = 0;
1075
1076         cpuc->events[idx] = event;
1077         __set_bit(idx, cpuc->active_mask);
1078         __set_bit(idx, cpuc->running);
1079         x86_pmu.enable(event);
1080         perf_event_update_userpage(event);
1081 }
1082
1083 void perf_event_print_debug(void)
1084 {
1085         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1086         u64 pebs;
1087         struct cpu_hw_events *cpuc;
1088         unsigned long flags;
1089         int cpu, idx;
1090
1091         if (!x86_pmu.num_counters)
1092                 return;
1093
1094         local_irq_save(flags);
1095
1096         cpu = smp_processor_id();
1097         cpuc = &per_cpu(cpu_hw_events, cpu);
1098
1099         if (x86_pmu.version >= 2) {
1100                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1101                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1102                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1103                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1104                 rdmsrl(MSR_IA32_PEBS_ENABLE, pebs);
1105
1106                 pr_info("\n");
1107                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1108                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1109                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1110                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1111                 pr_info("CPU#%d: pebs:       %016llx\n", cpu, pebs);
1112         }
1113         pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
1114
1115         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1116                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1117                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1118
1119                 prev_left = per_cpu(pmc_prev_left[idx], cpu);
1120
1121                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1122                         cpu, idx, pmc_ctrl);
1123                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1124                         cpu, idx, pmc_count);
1125                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1126                         cpu, idx, prev_left);
1127         }
1128         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1129                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1130
1131                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1132                         cpu, idx, pmc_count);
1133         }
1134         local_irq_restore(flags);
1135 }
1136
1137 static void x86_pmu_stop(struct perf_event *event, int flags)
1138 {
1139         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1140         struct hw_perf_event *hwc = &event->hw;
1141
1142         if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) {
1143                 x86_pmu.disable(event);
1144                 cpuc->events[hwc->idx] = NULL;
1145                 WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
1146                 hwc->state |= PERF_HES_STOPPED;
1147         }
1148
1149         if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) {
1150                 /*
1151                  * Drain the remaining delta count out of a event
1152                  * that we are disabling:
1153                  */
1154                 x86_perf_event_update(event);
1155                 hwc->state |= PERF_HES_UPTODATE;
1156         }
1157 }
1158
1159 static void x86_pmu_del(struct perf_event *event, int flags)
1160 {
1161         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1162         int i;
1163
1164         /*
1165          * If we're called during a txn, we don't need to do anything.
1166          * The events never got scheduled and ->cancel_txn will truncate
1167          * the event_list.
1168          */
1169         if (cpuc->group_flag & PERF_EVENT_TXN)
1170                 return;
1171
1172         x86_pmu_stop(event, PERF_EF_UPDATE);
1173
1174         for (i = 0; i < cpuc->n_events; i++) {
1175                 if (event == cpuc->event_list[i]) {
1176
1177                         if (x86_pmu.put_event_constraints)
1178                                 x86_pmu.put_event_constraints(cpuc, event);
1179
1180                         while (++i < cpuc->n_events)
1181                                 cpuc->event_list[i-1] = cpuc->event_list[i];
1182
1183                         --cpuc->n_events;
1184                         break;
1185                 }
1186         }
1187         perf_event_update_userpage(event);
1188 }
1189
1190 static int x86_pmu_handle_irq(struct pt_regs *regs)
1191 {
1192         struct perf_sample_data data;
1193         struct cpu_hw_events *cpuc;
1194         struct perf_event *event;
1195         int idx, handled = 0;
1196         u64 val;
1197
1198         perf_sample_data_init(&data, 0);
1199
1200         cpuc = &__get_cpu_var(cpu_hw_events);
1201
1202         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1203                 if (!test_bit(idx, cpuc->active_mask)) {
1204                         /*
1205                          * Though we deactivated the counter some cpus
1206                          * might still deliver spurious interrupts still
1207                          * in flight. Catch them:
1208                          */
1209                         if (__test_and_clear_bit(idx, cpuc->running))
1210                                 handled++;
1211                         continue;
1212                 }
1213
1214                 event = cpuc->events[idx];
1215
1216                 val = x86_perf_event_update(event);
1217                 if (val & (1ULL << (x86_pmu.cntval_bits - 1)))
1218                         continue;
1219
1220                 /*
1221                  * event overflow
1222                  */
1223                 handled++;
1224                 data.period     = event->hw.last_period;
1225
1226                 if (!x86_perf_event_set_period(event))
1227                         continue;
1228
1229                 if (perf_event_overflow(event, 1, &data, regs))
1230                         x86_pmu_stop(event, 0);
1231         }
1232
1233         if (handled)
1234                 inc_irq_stat(apic_perf_irqs);
1235
1236         return handled;
1237 }
1238
1239 void perf_events_lapic_init(void)
1240 {
1241         if (!x86_pmu.apic || !x86_pmu_initialized())
1242                 return;
1243
1244         /*
1245          * Always use NMI for PMU
1246          */
1247         apic_write(APIC_LVTPC, APIC_DM_NMI);
1248 }
1249
1250 struct pmu_nmi_state {
1251         unsigned int    marked;
1252         int             handled;
1253 };
1254
1255 static DEFINE_PER_CPU(struct pmu_nmi_state, pmu_nmi);
1256
1257 static int __kprobes
1258 perf_event_nmi_handler(struct notifier_block *self,
1259                          unsigned long cmd, void *__args)
1260 {
1261         struct die_args *args = __args;
1262         unsigned int this_nmi;
1263         int handled;
1264
1265         if (!atomic_read(&active_events))
1266                 return NOTIFY_DONE;
1267
1268         switch (cmd) {
1269         case DIE_NMI:
1270         case DIE_NMI_IPI:
1271                 break;
1272         case DIE_NMIUNKNOWN:
1273                 this_nmi = percpu_read(irq_stat.__nmi_count);
1274                 if (this_nmi != __this_cpu_read(pmu_nmi.marked))
1275                         /* let the kernel handle the unknown nmi */
1276                         return NOTIFY_DONE;
1277                 /*
1278                  * This one is a PMU back-to-back nmi. Two events
1279                  * trigger 'simultaneously' raising two back-to-back
1280                  * NMIs. If the first NMI handles both, the latter
1281                  * will be empty and daze the CPU. So, we drop it to
1282                  * avoid false-positive 'unknown nmi' messages.
1283                  */
1284                 return NOTIFY_STOP;
1285         default:
1286                 return NOTIFY_DONE;
1287         }
1288
1289         apic_write(APIC_LVTPC, APIC_DM_NMI);
1290
1291         handled = x86_pmu.handle_irq(args->regs);
1292         if (!handled)
1293                 return NOTIFY_DONE;
1294
1295         this_nmi = percpu_read(irq_stat.__nmi_count);
1296         if ((handled > 1) ||
1297                 /* the next nmi could be a back-to-back nmi */
1298             ((__this_cpu_read(pmu_nmi.marked) == this_nmi) &&
1299              (__this_cpu_read(pmu_nmi.handled) > 1))) {
1300                 /*
1301                  * We could have two subsequent back-to-back nmis: The
1302                  * first handles more than one counter, the 2nd
1303                  * handles only one counter and the 3rd handles no
1304                  * counter.
1305                  *
1306                  * This is the 2nd nmi because the previous was
1307                  * handling more than one counter. We will mark the
1308                  * next (3rd) and then drop it if unhandled.
1309                  */
1310                 __this_cpu_write(pmu_nmi.marked, this_nmi + 1);
1311                 __this_cpu_write(pmu_nmi.handled, handled);
1312         }
1313
1314         return NOTIFY_STOP;
1315 }
1316
1317 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1318         .notifier_call          = perf_event_nmi_handler,
1319         .next                   = NULL,
1320         .priority               = 1
1321 };
1322
1323 static struct event_constraint unconstrained;
1324 static struct event_constraint emptyconstraint;
1325
1326 static struct event_constraint *
1327 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
1328 {
1329         struct event_constraint *c;
1330
1331         if (x86_pmu.event_constraints) {
1332                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1333                         if ((event->hw.config & c->cmask) == c->code)
1334                                 return c;
1335                 }
1336         }
1337
1338         return &unconstrained;
1339 }
1340
1341 #include "perf_event_amd.c"
1342 #include "perf_event_p6.c"
1343 #include "perf_event_p4.c"
1344 #include "perf_event_intel_lbr.c"
1345 #include "perf_event_intel_ds.c"
1346 #include "perf_event_intel.c"
1347
1348 static int __cpuinit
1349 x86_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
1350 {
1351         unsigned int cpu = (long)hcpu;
1352         int ret = NOTIFY_OK;
1353
1354         switch (action & ~CPU_TASKS_FROZEN) {
1355         case CPU_UP_PREPARE:
1356                 if (x86_pmu.cpu_prepare)
1357                         ret = x86_pmu.cpu_prepare(cpu);
1358                 break;
1359
1360         case CPU_STARTING:
1361                 if (x86_pmu.cpu_starting)
1362                         x86_pmu.cpu_starting(cpu);
1363                 break;
1364
1365         case CPU_DYING:
1366                 if (x86_pmu.cpu_dying)
1367                         x86_pmu.cpu_dying(cpu);
1368                 break;
1369
1370         case CPU_UP_CANCELED:
1371         case CPU_DEAD:
1372                 if (x86_pmu.cpu_dead)
1373                         x86_pmu.cpu_dead(cpu);
1374                 break;
1375
1376         default:
1377                 break;
1378         }
1379
1380         return ret;
1381 }
1382
1383 static void __init pmu_check_apic(void)
1384 {
1385         if (cpu_has_apic)
1386                 return;
1387
1388         x86_pmu.apic = 0;
1389         pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1390         pr_info("no hardware sampling interrupt available.\n");
1391 }
1392
1393 int __init init_hw_perf_events(void)
1394 {
1395         struct event_constraint *c;
1396         int err;
1397
1398         pr_info("Performance Events: ");
1399
1400         switch (boot_cpu_data.x86_vendor) {
1401         case X86_VENDOR_INTEL:
1402                 err = intel_pmu_init();
1403                 break;
1404         case X86_VENDOR_AMD:
1405                 err = amd_pmu_init();
1406                 break;
1407         default:
1408                 return 0;
1409         }
1410         if (err != 0) {
1411                 pr_cont("no PMU driver, software events only.\n");
1412                 return 0;
1413         }
1414
1415         pmu_check_apic();
1416
1417         /* sanity check that the hardware exists or is emulated */
1418         if (!check_hw_exists())
1419                 return 0;
1420
1421         pr_cont("%s PMU driver.\n", x86_pmu.name);
1422
1423         if (x86_pmu.quirks)
1424                 x86_pmu.quirks();
1425
1426         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1427                 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
1428                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1429                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1430         }
1431         x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
1432
1433         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1434                 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
1435                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1436                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1437         }
1438
1439         x86_pmu.intel_ctrl |=
1440                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1441
1442         perf_events_lapic_init();
1443         register_die_notifier(&perf_event_nmi_notifier);
1444
1445         unconstrained = (struct event_constraint)
1446                 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1,
1447                                    0, x86_pmu.num_counters);
1448
1449         if (x86_pmu.event_constraints) {
1450                 for_each_event_constraint(c, x86_pmu.event_constraints) {
1451                         if (c->cmask != X86_RAW_EVENT_MASK)
1452                                 continue;
1453
1454                         c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
1455                         c->weight += x86_pmu.num_counters;
1456                 }
1457         }
1458
1459         pr_info("... version:                %d\n",     x86_pmu.version);
1460         pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
1461         pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
1462         pr_info("... value mask:             %016Lx\n", x86_pmu.cntval_mask);
1463         pr_info("... max period:             %016Lx\n", x86_pmu.max_period);
1464         pr_info("... fixed-purpose events:   %d\n",     x86_pmu.num_counters_fixed);
1465         pr_info("... event mask:             %016Lx\n", x86_pmu.intel_ctrl);
1466
1467         perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1468         perf_cpu_notifier(x86_pmu_notifier);
1469
1470         return 0;
1471 }
1472 early_initcall(init_hw_perf_events);
1473
1474 static inline void x86_pmu_read(struct perf_event *event)
1475 {
1476         x86_perf_event_update(event);
1477 }
1478
1479 /*
1480  * Start group events scheduling transaction
1481  * Set the flag to make pmu::enable() not perform the
1482  * schedulability test, it will be performed at commit time
1483  */
1484 static void x86_pmu_start_txn(struct pmu *pmu)
1485 {
1486         perf_pmu_disable(pmu);
1487         __this_cpu_or(cpu_hw_events.group_flag, PERF_EVENT_TXN);
1488         __this_cpu_write(cpu_hw_events.n_txn, 0);
1489 }
1490
1491 /*
1492  * Stop group events scheduling transaction
1493  * Clear the flag and pmu::enable() will perform the
1494  * schedulability test.
1495  */
1496 static void x86_pmu_cancel_txn(struct pmu *pmu)
1497 {
1498         __this_cpu_and(cpu_hw_events.group_flag, ~PERF_EVENT_TXN);
1499         /*
1500          * Truncate the collected events.
1501          */
1502         __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn));
1503         __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn));
1504         perf_pmu_enable(pmu);
1505 }
1506
1507 /*
1508  * Commit group events scheduling transaction
1509  * Perform the group schedulability test as a whole
1510  * Return 0 if success
1511  */
1512 static int x86_pmu_commit_txn(struct pmu *pmu)
1513 {
1514         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1515         int assign[X86_PMC_IDX_MAX];
1516         int n, ret;
1517
1518         n = cpuc->n_events;
1519
1520         if (!x86_pmu_initialized())
1521                 return -EAGAIN;
1522
1523         ret = x86_pmu.schedule_events(cpuc, n, assign);
1524         if (ret)
1525                 return ret;
1526
1527         /*
1528          * copy new assignment, now we know it is possible
1529          * will be used by hw_perf_enable()
1530          */
1531         memcpy(cpuc->assign, assign, n*sizeof(int));
1532
1533         cpuc->group_flag &= ~PERF_EVENT_TXN;
1534         perf_pmu_enable(pmu);
1535         return 0;
1536 }
1537
1538 /*
1539  * validate that we can schedule this event
1540  */
1541 static int validate_event(struct perf_event *event)
1542 {
1543         struct cpu_hw_events *fake_cpuc;
1544         struct event_constraint *c;
1545         int ret = 0;
1546
1547         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1548         if (!fake_cpuc)
1549                 return -ENOMEM;
1550
1551         c = x86_pmu.get_event_constraints(fake_cpuc, event);
1552
1553         if (!c || !c->weight)
1554                 ret = -ENOSPC;
1555
1556         if (x86_pmu.put_event_constraints)
1557                 x86_pmu.put_event_constraints(fake_cpuc, event);
1558
1559         kfree(fake_cpuc);
1560
1561         return ret;
1562 }
1563
1564 /*
1565  * validate a single event group
1566  *
1567  * validation include:
1568  *      - check events are compatible which each other
1569  *      - events do not compete for the same counter
1570  *      - number of events <= number of counters
1571  *
1572  * validation ensures the group can be loaded onto the
1573  * PMU if it was the only group available.
1574  */
1575 static int validate_group(struct perf_event *event)
1576 {
1577         struct perf_event *leader = event->group_leader;
1578         struct cpu_hw_events *fake_cpuc;
1579         int ret, n;
1580
1581         ret = -ENOMEM;
1582         fake_cpuc = kmalloc(sizeof(*fake_cpuc), GFP_KERNEL | __GFP_ZERO);
1583         if (!fake_cpuc)
1584                 goto out;
1585
1586         /*
1587          * the event is not yet connected with its
1588          * siblings therefore we must first collect
1589          * existing siblings, then add the new event
1590          * before we can simulate the scheduling
1591          */
1592         ret = -ENOSPC;
1593         n = collect_events(fake_cpuc, leader, true);
1594         if (n < 0)
1595                 goto out_free;
1596
1597         fake_cpuc->n_events = n;
1598         n = collect_events(fake_cpuc, event, false);
1599         if (n < 0)
1600                 goto out_free;
1601
1602         fake_cpuc->n_events = n;
1603
1604         ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
1605
1606 out_free:
1607         kfree(fake_cpuc);
1608 out:
1609         return ret;
1610 }
1611
1612 int x86_pmu_event_init(struct perf_event *event)
1613 {
1614         struct pmu *tmp;
1615         int err;
1616
1617         switch (event->attr.type) {
1618         case PERF_TYPE_RAW:
1619         case PERF_TYPE_HARDWARE:
1620         case PERF_TYPE_HW_CACHE:
1621                 break;
1622
1623         default:
1624                 return -ENOENT;
1625         }
1626
1627         err = __x86_pmu_event_init(event);
1628         if (!err) {
1629                 /*
1630                  * we temporarily connect event to its pmu
1631                  * such that validate_group() can classify
1632                  * it as an x86 event using is_x86_event()
1633                  */
1634                 tmp = event->pmu;
1635                 event->pmu = &pmu;
1636
1637                 if (event->group_leader != event)
1638                         err = validate_group(event);
1639                 else
1640                         err = validate_event(event);
1641
1642                 event->pmu = tmp;
1643         }
1644         if (err) {
1645                 if (event->destroy)
1646                         event->destroy(event);
1647         }
1648
1649         return err;
1650 }
1651
1652 static struct pmu pmu = {
1653         .pmu_enable     = x86_pmu_enable,
1654         .pmu_disable    = x86_pmu_disable,
1655
1656         .event_init     = x86_pmu_event_init,
1657
1658         .add            = x86_pmu_add,
1659         .del            = x86_pmu_del,
1660         .start          = x86_pmu_start,
1661         .stop           = x86_pmu_stop,
1662         .read           = x86_pmu_read,
1663
1664         .start_txn      = x86_pmu_start_txn,
1665         .cancel_txn     = x86_pmu_cancel_txn,
1666         .commit_txn     = x86_pmu_commit_txn,
1667 };
1668
1669 /*
1670  * callchain support
1671  */
1672
1673 static void
1674 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1675 {
1676         /* Ignore warnings */
1677 }
1678
1679 static void backtrace_warning(void *data, char *msg)
1680 {
1681         /* Ignore warnings */
1682 }
1683
1684 static int backtrace_stack(void *data, char *name)
1685 {
1686         return 0;
1687 }
1688
1689 static void backtrace_address(void *data, unsigned long addr, int reliable)
1690 {
1691         struct perf_callchain_entry *entry = data;
1692
1693         perf_callchain_store(entry, addr);
1694 }
1695
1696 static const struct stacktrace_ops backtrace_ops = {
1697         .warning                = backtrace_warning,
1698         .warning_symbol         = backtrace_warning_symbol,
1699         .stack                  = backtrace_stack,
1700         .address                = backtrace_address,
1701         .walk_stack             = print_context_stack_bp,
1702 };
1703
1704 void
1705 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
1706 {
1707         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1708                 /* TODO: We don't support guest os callchain now */
1709                 return;
1710         }
1711
1712         perf_callchain_store(entry, regs->ip);
1713
1714         dump_trace(NULL, regs, NULL, &backtrace_ops, entry);
1715 }
1716
1717 #ifdef CONFIG_COMPAT
1718 static inline int
1719 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1720 {
1721         /* 32-bit process in 64-bit kernel. */
1722         struct stack_frame_ia32 frame;
1723         const void __user *fp;
1724
1725         if (!test_thread_flag(TIF_IA32))
1726                 return 0;
1727
1728         fp = compat_ptr(regs->bp);
1729         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1730                 unsigned long bytes;
1731                 frame.next_frame     = 0;
1732                 frame.return_address = 0;
1733
1734                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1735                 if (bytes != sizeof(frame))
1736                         break;
1737
1738                 if (fp < compat_ptr(regs->sp))
1739                         break;
1740
1741                 perf_callchain_store(entry, frame.return_address);
1742                 fp = compat_ptr(frame.next_frame);
1743         }
1744         return 1;
1745 }
1746 #else
1747 static inline int
1748 perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry *entry)
1749 {
1750     return 0;
1751 }
1752 #endif
1753
1754 void
1755 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1756 {
1757         struct stack_frame frame;
1758         const void __user *fp;
1759
1760         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1761                 /* TODO: We don't support guest os callchain now */
1762                 return;
1763         }
1764
1765         fp = (void __user *)regs->bp;
1766
1767         perf_callchain_store(entry, regs->ip);
1768
1769         if (perf_callchain_user32(regs, entry))
1770                 return;
1771
1772         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1773                 unsigned long bytes;
1774                 frame.next_frame             = NULL;
1775                 frame.return_address = 0;
1776
1777                 bytes = copy_from_user_nmi(&frame, fp, sizeof(frame));
1778                 if (bytes != sizeof(frame))
1779                         break;
1780
1781                 if ((unsigned long)fp < regs->sp)
1782                         break;
1783
1784                 perf_callchain_store(entry, frame.return_address);
1785                 fp = frame.next_frame;
1786         }
1787 }
1788
1789 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1790 {
1791         unsigned long ip;
1792
1793         if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
1794                 ip = perf_guest_cbs->get_guest_ip();
1795         else
1796                 ip = instruction_pointer(regs);
1797
1798         return ip;
1799 }
1800
1801 unsigned long perf_misc_flags(struct pt_regs *regs)
1802 {
1803         int misc = 0;
1804
1805         if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
1806                 if (perf_guest_cbs->is_user_mode())
1807                         misc |= PERF_RECORD_MISC_GUEST_USER;
1808                 else
1809                         misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1810         } else {
1811                 if (user_mode(regs))
1812                         misc |= PERF_RECORD_MISC_USER;
1813                 else
1814                         misc |= PERF_RECORD_MISC_KERNEL;
1815         }
1816
1817         if (regs->flags & PERF_EFLAGS_EXACT)
1818                 misc |= PERF_RECORD_MISC_EXACT_IP;
1819
1820         return misc;
1821 }