76dfef23f78957aa4e17d3337d5dc5221bd18ade
[linux-2.6.git] / arch / x86 / kernel / cpu / perf_counter.c
1 /*
2  * Performance counter x86 architecture code
3  *
4  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6  *  Copyright (C) 2009 Jaswinder Singh Rajput
7  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9  *
10  *  For licencing details see kernel-base/COPYING
11  */
12
13 #include <linux/perf_counter.h>
14 #include <linux/capability.h>
15 #include <linux/notifier.h>
16 #include <linux/hardirq.h>
17 #include <linux/kprobes.h>
18 #include <linux/module.h>
19 #include <linux/kdebug.h>
20 #include <linux/sched.h>
21 #include <linux/uaccess.h>
22 #include <linux/highmem.h>
23
24 #include <asm/apic.h>
25 #include <asm/stacktrace.h>
26 #include <asm/nmi.h>
27
28 static u64 perf_counter_mask __read_mostly;
29
30 struct cpu_hw_counters {
31         struct perf_counter     *counters[X86_PMC_IDX_MAX];
32         unsigned long           used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
33         unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
34         unsigned long           interrupts;
35         int                     enabled;
36 };
37
38 /*
39  * struct x86_pmu - generic x86 pmu
40  */
41 struct x86_pmu {
42         const char      *name;
43         int             version;
44         int             (*handle_irq)(struct pt_regs *);
45         void            (*disable_all)(void);
46         void            (*enable_all)(void);
47         void            (*enable)(struct hw_perf_counter *, int);
48         void            (*disable)(struct hw_perf_counter *, int);
49         unsigned        eventsel;
50         unsigned        perfctr;
51         u64             (*event_map)(int);
52         u64             (*raw_event)(u64);
53         int             max_events;
54         int             num_counters;
55         int             num_counters_fixed;
56         int             counter_bits;
57         u64             counter_mask;
58         u64             max_period;
59         u64             intel_ctrl;
60 };
61
62 static struct x86_pmu x86_pmu __read_mostly;
63
64 static DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = {
65         .enabled = 1,
66 };
67
68 /*
69  * Intel PerfMon v3. Used on Core2 and later.
70  */
71 static const u64 intel_perfmon_event_map[] =
72 {
73   [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
74   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
75   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
76   [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
77   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
78   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
79   [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
80 };
81
82 static u64 intel_pmu_event_map(int event)
83 {
84         return intel_perfmon_event_map[event];
85 }
86
87 /*
88  * Generalized hw caching related event table, filled
89  * in on a per model basis. A value of 0 means
90  * 'not supported', -1 means 'event makes no sense on
91  * this CPU', any other value means the raw event
92  * ID.
93  */
94
95 #define C(x) PERF_COUNT_HW_CACHE_##x
96
97 static u64 __read_mostly hw_cache_event_ids
98                                 [PERF_COUNT_HW_CACHE_MAX]
99                                 [PERF_COUNT_HW_CACHE_OP_MAX]
100                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
101
102 static const u64 nehalem_hw_cache_event_ids
103                                 [PERF_COUNT_HW_CACHE_MAX]
104                                 [PERF_COUNT_HW_CACHE_OP_MAX]
105                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
106 {
107  [ C(L1D) ] = {
108         [ C(OP_READ) ] = {
109                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI            */
110                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE         */
111         },
112         [ C(OP_WRITE) ] = {
113                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI            */
114                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE         */
115         },
116         [ C(OP_PREFETCH) ] = {
117                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
118                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
119         },
120  },
121  [ C(L1I ) ] = {
122         [ C(OP_READ) ] = {
123                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
124                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
125         },
126         [ C(OP_WRITE) ] = {
127                 [ C(RESULT_ACCESS) ] = -1,
128                 [ C(RESULT_MISS)   ] = -1,
129         },
130         [ C(OP_PREFETCH) ] = {
131                 [ C(RESULT_ACCESS) ] = 0x0,
132                 [ C(RESULT_MISS)   ] = 0x0,
133         },
134  },
135  [ C(LL  ) ] = {
136         [ C(OP_READ) ] = {
137                 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
138                 [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
139         },
140         [ C(OP_WRITE) ] = {
141                 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
142                 [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
143         },
144         [ C(OP_PREFETCH) ] = {
145                 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
146                 [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
147         },
148  },
149  [ C(DTLB) ] = {
150         [ C(OP_READ) ] = {
151                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
152                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
153         },
154         [ C(OP_WRITE) ] = {
155                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
156                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
157         },
158         [ C(OP_PREFETCH) ] = {
159                 [ C(RESULT_ACCESS) ] = 0x0,
160                 [ C(RESULT_MISS)   ] = 0x0,
161         },
162  },
163  [ C(ITLB) ] = {
164         [ C(OP_READ) ] = {
165                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
166                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
167         },
168         [ C(OP_WRITE) ] = {
169                 [ C(RESULT_ACCESS) ] = -1,
170                 [ C(RESULT_MISS)   ] = -1,
171         },
172         [ C(OP_PREFETCH) ] = {
173                 [ C(RESULT_ACCESS) ] = -1,
174                 [ C(RESULT_MISS)   ] = -1,
175         },
176  },
177  [ C(BPU ) ] = {
178         [ C(OP_READ) ] = {
179                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
180                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
181         },
182         [ C(OP_WRITE) ] = {
183                 [ C(RESULT_ACCESS) ] = -1,
184                 [ C(RESULT_MISS)   ] = -1,
185         },
186         [ C(OP_PREFETCH) ] = {
187                 [ C(RESULT_ACCESS) ] = -1,
188                 [ C(RESULT_MISS)   ] = -1,
189         },
190  },
191 };
192
193 static const u64 core2_hw_cache_event_ids
194                                 [PERF_COUNT_HW_CACHE_MAX]
195                                 [PERF_COUNT_HW_CACHE_OP_MAX]
196                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
197 {
198  [ C(L1D) ] = {
199         [ C(OP_READ) ] = {
200                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
201                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
202         },
203         [ C(OP_WRITE) ] = {
204                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
205                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
206         },
207         [ C(OP_PREFETCH) ] = {
208                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
209                 [ C(RESULT_MISS)   ] = 0,
210         },
211  },
212  [ C(L1I ) ] = {
213         [ C(OP_READ) ] = {
214                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
215                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
216         },
217         [ C(OP_WRITE) ] = {
218                 [ C(RESULT_ACCESS) ] = -1,
219                 [ C(RESULT_MISS)   ] = -1,
220         },
221         [ C(OP_PREFETCH) ] = {
222                 [ C(RESULT_ACCESS) ] = 0,
223                 [ C(RESULT_MISS)   ] = 0,
224         },
225  },
226  [ C(LL  ) ] = {
227         [ C(OP_READ) ] = {
228                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
229                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
230         },
231         [ C(OP_WRITE) ] = {
232                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
233                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
234         },
235         [ C(OP_PREFETCH) ] = {
236                 [ C(RESULT_ACCESS) ] = 0,
237                 [ C(RESULT_MISS)   ] = 0,
238         },
239  },
240  [ C(DTLB) ] = {
241         [ C(OP_READ) ] = {
242                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
243                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
244         },
245         [ C(OP_WRITE) ] = {
246                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
247                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
248         },
249         [ C(OP_PREFETCH) ] = {
250                 [ C(RESULT_ACCESS) ] = 0,
251                 [ C(RESULT_MISS)   ] = 0,
252         },
253  },
254  [ C(ITLB) ] = {
255         [ C(OP_READ) ] = {
256                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
257                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
258         },
259         [ C(OP_WRITE) ] = {
260                 [ C(RESULT_ACCESS) ] = -1,
261                 [ C(RESULT_MISS)   ] = -1,
262         },
263         [ C(OP_PREFETCH) ] = {
264                 [ C(RESULT_ACCESS) ] = -1,
265                 [ C(RESULT_MISS)   ] = -1,
266         },
267  },
268  [ C(BPU ) ] = {
269         [ C(OP_READ) ] = {
270                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
271                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
272         },
273         [ C(OP_WRITE) ] = {
274                 [ C(RESULT_ACCESS) ] = -1,
275                 [ C(RESULT_MISS)   ] = -1,
276         },
277         [ C(OP_PREFETCH) ] = {
278                 [ C(RESULT_ACCESS) ] = -1,
279                 [ C(RESULT_MISS)   ] = -1,
280         },
281  },
282 };
283
284 static const u64 atom_hw_cache_event_ids
285                                 [PERF_COUNT_HW_CACHE_MAX]
286                                 [PERF_COUNT_HW_CACHE_OP_MAX]
287                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
288 {
289  [ C(L1D) ] = {
290         [ C(OP_READ) ] = {
291                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
292                 [ C(RESULT_MISS)   ] = 0,
293         },
294         [ C(OP_WRITE) ] = {
295                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
296                 [ C(RESULT_MISS)   ] = 0,
297         },
298         [ C(OP_PREFETCH) ] = {
299                 [ C(RESULT_ACCESS) ] = 0x0,
300                 [ C(RESULT_MISS)   ] = 0,
301         },
302  },
303  [ C(L1I ) ] = {
304         [ C(OP_READ) ] = {
305                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
306                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
307         },
308         [ C(OP_WRITE) ] = {
309                 [ C(RESULT_ACCESS) ] = -1,
310                 [ C(RESULT_MISS)   ] = -1,
311         },
312         [ C(OP_PREFETCH) ] = {
313                 [ C(RESULT_ACCESS) ] = 0,
314                 [ C(RESULT_MISS)   ] = 0,
315         },
316  },
317  [ C(LL  ) ] = {
318         [ C(OP_READ) ] = {
319                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
320                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
321         },
322         [ C(OP_WRITE) ] = {
323                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
324                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
325         },
326         [ C(OP_PREFETCH) ] = {
327                 [ C(RESULT_ACCESS) ] = 0,
328                 [ C(RESULT_MISS)   ] = 0,
329         },
330  },
331  [ C(DTLB) ] = {
332         [ C(OP_READ) ] = {
333                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
334                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
335         },
336         [ C(OP_WRITE) ] = {
337                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
338                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
339         },
340         [ C(OP_PREFETCH) ] = {
341                 [ C(RESULT_ACCESS) ] = 0,
342                 [ C(RESULT_MISS)   ] = 0,
343         },
344  },
345  [ C(ITLB) ] = {
346         [ C(OP_READ) ] = {
347                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
348                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
349         },
350         [ C(OP_WRITE) ] = {
351                 [ C(RESULT_ACCESS) ] = -1,
352                 [ C(RESULT_MISS)   ] = -1,
353         },
354         [ C(OP_PREFETCH) ] = {
355                 [ C(RESULT_ACCESS) ] = -1,
356                 [ C(RESULT_MISS)   ] = -1,
357         },
358  },
359  [ C(BPU ) ] = {
360         [ C(OP_READ) ] = {
361                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
362                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
363         },
364         [ C(OP_WRITE) ] = {
365                 [ C(RESULT_ACCESS) ] = -1,
366                 [ C(RESULT_MISS)   ] = -1,
367         },
368         [ C(OP_PREFETCH) ] = {
369                 [ C(RESULT_ACCESS) ] = -1,
370                 [ C(RESULT_MISS)   ] = -1,
371         },
372  },
373 };
374
375 static u64 intel_pmu_raw_event(u64 event)
376 {
377 #define CORE_EVNTSEL_EVENT_MASK         0x000000FFULL
378 #define CORE_EVNTSEL_UNIT_MASK          0x0000FF00ULL
379 #define CORE_EVNTSEL_EDGE_MASK          0x00040000ULL
380 #define CORE_EVNTSEL_INV_MASK           0x00800000ULL
381 #define CORE_EVNTSEL_COUNTER_MASK       0xFF000000ULL
382
383 #define CORE_EVNTSEL_MASK               \
384         (CORE_EVNTSEL_EVENT_MASK |      \
385          CORE_EVNTSEL_UNIT_MASK  |      \
386          CORE_EVNTSEL_EDGE_MASK  |      \
387          CORE_EVNTSEL_INV_MASK  |       \
388          CORE_EVNTSEL_COUNTER_MASK)
389
390         return event & CORE_EVNTSEL_MASK;
391 }
392
393 static const u64 amd_hw_cache_event_ids
394                                 [PERF_COUNT_HW_CACHE_MAX]
395                                 [PERF_COUNT_HW_CACHE_OP_MAX]
396                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
397 {
398  [ C(L1D) ] = {
399         [ C(OP_READ) ] = {
400                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
401                 [ C(RESULT_MISS)   ] = 0x0041, /* Data Cache Misses          */
402         },
403         [ C(OP_WRITE) ] = {
404                 [ C(RESULT_ACCESS) ] = 0x0042, /* Data Cache Refills from L2 */
405                 [ C(RESULT_MISS)   ] = 0,
406         },
407         [ C(OP_PREFETCH) ] = {
408                 [ C(RESULT_ACCESS) ] = 0x0267, /* Data Prefetcher :attempts  */
409                 [ C(RESULT_MISS)   ] = 0x0167, /* Data Prefetcher :cancelled */
410         },
411  },
412  [ C(L1I ) ] = {
413         [ C(OP_READ) ] = {
414                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction cache fetches  */
415                 [ C(RESULT_MISS)   ] = 0x0081, /* Instruction cache misses   */
416         },
417         [ C(OP_WRITE) ] = {
418                 [ C(RESULT_ACCESS) ] = -1,
419                 [ C(RESULT_MISS)   ] = -1,
420         },
421         [ C(OP_PREFETCH) ] = {
422                 [ C(RESULT_ACCESS) ] = 0x014B, /* Prefetch Instructions :Load */
423                 [ C(RESULT_MISS)   ] = 0,
424         },
425  },
426  [ C(LL  ) ] = {
427         [ C(OP_READ) ] = {
428                 [ C(RESULT_ACCESS) ] = 0x037D, /* Requests to L2 Cache :IC+DC */
429                 [ C(RESULT_MISS)   ] = 0x037E, /* L2 Cache Misses : IC+DC     */
430         },
431         [ C(OP_WRITE) ] = {
432                 [ C(RESULT_ACCESS) ] = 0x017F, /* L2 Fill/Writeback           */
433                 [ C(RESULT_MISS)   ] = 0,
434         },
435         [ C(OP_PREFETCH) ] = {
436                 [ C(RESULT_ACCESS) ] = 0,
437                 [ C(RESULT_MISS)   ] = 0,
438         },
439  },
440  [ C(DTLB) ] = {
441         [ C(OP_READ) ] = {
442                 [ C(RESULT_ACCESS) ] = 0x0040, /* Data Cache Accesses        */
443                 [ C(RESULT_MISS)   ] = 0x0046, /* L1 DTLB and L2 DLTB Miss   */
444         },
445         [ C(OP_WRITE) ] = {
446                 [ C(RESULT_ACCESS) ] = 0,
447                 [ C(RESULT_MISS)   ] = 0,
448         },
449         [ C(OP_PREFETCH) ] = {
450                 [ C(RESULT_ACCESS) ] = 0,
451                 [ C(RESULT_MISS)   ] = 0,
452         },
453  },
454  [ C(ITLB) ] = {
455         [ C(OP_READ) ] = {
456                 [ C(RESULT_ACCESS) ] = 0x0080, /* Instruction fecthes        */
457                 [ C(RESULT_MISS)   ] = 0x0085, /* Instr. fetch ITLB misses   */
458         },
459         [ C(OP_WRITE) ] = {
460                 [ C(RESULT_ACCESS) ] = -1,
461                 [ C(RESULT_MISS)   ] = -1,
462         },
463         [ C(OP_PREFETCH) ] = {
464                 [ C(RESULT_ACCESS) ] = -1,
465                 [ C(RESULT_MISS)   ] = -1,
466         },
467  },
468  [ C(BPU ) ] = {
469         [ C(OP_READ) ] = {
470                 [ C(RESULT_ACCESS) ] = 0x00c2, /* Retired Branch Instr.      */
471                 [ C(RESULT_MISS)   ] = 0x00c3, /* Retired Mispredicted BI    */
472         },
473         [ C(OP_WRITE) ] = {
474                 [ C(RESULT_ACCESS) ] = -1,
475                 [ C(RESULT_MISS)   ] = -1,
476         },
477         [ C(OP_PREFETCH) ] = {
478                 [ C(RESULT_ACCESS) ] = -1,
479                 [ C(RESULT_MISS)   ] = -1,
480         },
481  },
482 };
483
484 /*
485  * AMD Performance Monitor K7 and later.
486  */
487 static const u64 amd_perfmon_event_map[] =
488 {
489   [PERF_COUNT_HW_CPU_CYCLES]            = 0x0076,
490   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
491   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x0080,
492   [PERF_COUNT_HW_CACHE_MISSES]          = 0x0081,
493   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
494   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
495 };
496
497 static u64 amd_pmu_event_map(int event)
498 {
499         return amd_perfmon_event_map[event];
500 }
501
502 static u64 amd_pmu_raw_event(u64 event)
503 {
504 #define K7_EVNTSEL_EVENT_MASK   0x7000000FFULL
505 #define K7_EVNTSEL_UNIT_MASK    0x00000FF00ULL
506 #define K7_EVNTSEL_EDGE_MASK    0x000040000ULL
507 #define K7_EVNTSEL_INV_MASK     0x000800000ULL
508 #define K7_EVNTSEL_COUNTER_MASK 0x0FF000000ULL
509
510 #define K7_EVNTSEL_MASK                 \
511         (K7_EVNTSEL_EVENT_MASK |        \
512          K7_EVNTSEL_UNIT_MASK  |        \
513          K7_EVNTSEL_EDGE_MASK  |        \
514          K7_EVNTSEL_INV_MASK   |        \
515          K7_EVNTSEL_COUNTER_MASK)
516
517         return event & K7_EVNTSEL_MASK;
518 }
519
520 /*
521  * Propagate counter elapsed time into the generic counter.
522  * Can only be executed on the CPU where the counter is active.
523  * Returns the delta events processed.
524  */
525 static u64
526 x86_perf_counter_update(struct perf_counter *counter,
527                         struct hw_perf_counter *hwc, int idx)
528 {
529         int shift = 64 - x86_pmu.counter_bits;
530         u64 prev_raw_count, new_raw_count;
531         s64 delta;
532
533         /*
534          * Careful: an NMI might modify the previous counter value.
535          *
536          * Our tactic to handle this is to first atomically read and
537          * exchange a new raw count - then add that new-prev delta
538          * count to the generic counter atomically:
539          */
540 again:
541         prev_raw_count = atomic64_read(&hwc->prev_count);
542         rdmsrl(hwc->counter_base + idx, new_raw_count);
543
544         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
545                                         new_raw_count) != prev_raw_count)
546                 goto again;
547
548         /*
549          * Now we have the new raw value and have updated the prev
550          * timestamp already. We can now calculate the elapsed delta
551          * (counter-)time and add that to the generic counter.
552          *
553          * Careful, not all hw sign-extends above the physical width
554          * of the count.
555          */
556         delta = (new_raw_count << shift) - (prev_raw_count << shift);
557         delta >>= shift;
558
559         atomic64_add(delta, &counter->count);
560         atomic64_sub(delta, &hwc->period_left);
561
562         return new_raw_count;
563 }
564
565 static atomic_t active_counters;
566 static DEFINE_MUTEX(pmc_reserve_mutex);
567
568 static bool reserve_pmc_hardware(void)
569 {
570         int i;
571
572         if (nmi_watchdog == NMI_LOCAL_APIC)
573                 disable_lapic_nmi_watchdog();
574
575         for (i = 0; i < x86_pmu.num_counters; i++) {
576                 if (!reserve_perfctr_nmi(x86_pmu.perfctr + i))
577                         goto perfctr_fail;
578         }
579
580         for (i = 0; i < x86_pmu.num_counters; i++) {
581                 if (!reserve_evntsel_nmi(x86_pmu.eventsel + i))
582                         goto eventsel_fail;
583         }
584
585         return true;
586
587 eventsel_fail:
588         for (i--; i >= 0; i--)
589                 release_evntsel_nmi(x86_pmu.eventsel + i);
590
591         i = x86_pmu.num_counters;
592
593 perfctr_fail:
594         for (i--; i >= 0; i--)
595                 release_perfctr_nmi(x86_pmu.perfctr + i);
596
597         if (nmi_watchdog == NMI_LOCAL_APIC)
598                 enable_lapic_nmi_watchdog();
599
600         return false;
601 }
602
603 static void release_pmc_hardware(void)
604 {
605         int i;
606
607         for (i = 0; i < x86_pmu.num_counters; i++) {
608                 release_perfctr_nmi(x86_pmu.perfctr + i);
609                 release_evntsel_nmi(x86_pmu.eventsel + i);
610         }
611
612         if (nmi_watchdog == NMI_LOCAL_APIC)
613                 enable_lapic_nmi_watchdog();
614 }
615
616 static void hw_perf_counter_destroy(struct perf_counter *counter)
617 {
618         if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
619                 release_pmc_hardware();
620                 mutex_unlock(&pmc_reserve_mutex);
621         }
622 }
623
624 static inline int x86_pmu_initialized(void)
625 {
626         return x86_pmu.handle_irq != NULL;
627 }
628
629 static inline int
630 set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr)
631 {
632         unsigned int cache_type, cache_op, cache_result;
633         u64 config, val;
634
635         config = attr->config;
636
637         cache_type = (config >>  0) & 0xff;
638         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
639                 return -EINVAL;
640
641         cache_op = (config >>  8) & 0xff;
642         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
643                 return -EINVAL;
644
645         cache_result = (config >> 16) & 0xff;
646         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
647                 return -EINVAL;
648
649         val = hw_cache_event_ids[cache_type][cache_op][cache_result];
650
651         if (val == 0)
652                 return -ENOENT;
653
654         if (val == -1)
655                 return -EINVAL;
656
657         hwc->config |= val;
658
659         return 0;
660 }
661
662 /*
663  * Setup the hardware configuration for a given attr_type
664  */
665 static int __hw_perf_counter_init(struct perf_counter *counter)
666 {
667         struct perf_counter_attr *attr = &counter->attr;
668         struct hw_perf_counter *hwc = &counter->hw;
669         int err;
670
671         if (!x86_pmu_initialized())
672                 return -ENODEV;
673
674         err = 0;
675         if (!atomic_inc_not_zero(&active_counters)) {
676                 mutex_lock(&pmc_reserve_mutex);
677                 if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
678                         err = -EBUSY;
679                 else
680                         atomic_inc(&active_counters);
681                 mutex_unlock(&pmc_reserve_mutex);
682         }
683         if (err)
684                 return err;
685
686         /*
687          * Generate PMC IRQs:
688          * (keep 'enabled' bit clear for now)
689          */
690         hwc->config = ARCH_PERFMON_EVENTSEL_INT;
691
692         /*
693          * Count user and OS events unless requested not to.
694          */
695         if (!attr->exclude_user)
696                 hwc->config |= ARCH_PERFMON_EVENTSEL_USR;
697         if (!attr->exclude_kernel)
698                 hwc->config |= ARCH_PERFMON_EVENTSEL_OS;
699
700         if (!hwc->sample_period) {
701                 hwc->sample_period = x86_pmu.max_period;
702                 hwc->last_period = hwc->sample_period;
703                 atomic64_set(&hwc->period_left, hwc->sample_period);
704         }
705
706         counter->destroy = hw_perf_counter_destroy;
707
708         /*
709          * Raw event type provide the config in the event structure
710          */
711         if (attr->type == PERF_TYPE_RAW) {
712                 hwc->config |= x86_pmu.raw_event(attr->config);
713                 return 0;
714         }
715
716         if (attr->type == PERF_TYPE_HW_CACHE)
717                 return set_ext_hw_attr(hwc, attr);
718
719         if (attr->config >= x86_pmu.max_events)
720                 return -EINVAL;
721         /*
722          * The generic map:
723          */
724         hwc->config |= x86_pmu.event_map(attr->config);
725
726         return 0;
727 }
728
729 static void intel_pmu_disable_all(void)
730 {
731         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
732 }
733
734 static void amd_pmu_disable_all(void)
735 {
736         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
737         int idx;
738
739         if (!cpuc->enabled)
740                 return;
741
742         cpuc->enabled = 0;
743         /*
744          * ensure we write the disable before we start disabling the
745          * counters proper, so that amd_pmu_enable_counter() does the
746          * right thing.
747          */
748         barrier();
749
750         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
751                 u64 val;
752
753                 if (!test_bit(idx, cpuc->active_mask))
754                         continue;
755                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
756                 if (!(val & ARCH_PERFMON_EVENTSEL0_ENABLE))
757                         continue;
758                 val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
759                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
760         }
761 }
762
763 void hw_perf_disable(void)
764 {
765         if (!x86_pmu_initialized())
766                 return;
767         return x86_pmu.disable_all();
768 }
769
770 static void intel_pmu_enable_all(void)
771 {
772         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
773 }
774
775 static void amd_pmu_enable_all(void)
776 {
777         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
778         int idx;
779
780         if (cpuc->enabled)
781                 return;
782
783         cpuc->enabled = 1;
784         barrier();
785
786         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
787                 u64 val;
788
789                 if (!test_bit(idx, cpuc->active_mask))
790                         continue;
791                 rdmsrl(MSR_K7_EVNTSEL0 + idx, val);
792                 if (val & ARCH_PERFMON_EVENTSEL0_ENABLE)
793                         continue;
794                 val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
795                 wrmsrl(MSR_K7_EVNTSEL0 + idx, val);
796         }
797 }
798
799 void hw_perf_enable(void)
800 {
801         if (!x86_pmu_initialized())
802                 return;
803         x86_pmu.enable_all();
804 }
805
806 static inline u64 intel_pmu_get_status(void)
807 {
808         u64 status;
809
810         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
811
812         return status;
813 }
814
815 static inline void intel_pmu_ack_status(u64 ack)
816 {
817         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
818 }
819
820 static inline void x86_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
821 {
822         int err;
823         err = checking_wrmsrl(hwc->config_base + idx,
824                               hwc->config | ARCH_PERFMON_EVENTSEL0_ENABLE);
825 }
826
827 static inline void x86_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
828 {
829         int err;
830         err = checking_wrmsrl(hwc->config_base + idx,
831                               hwc->config);
832 }
833
834 static inline void
835 intel_pmu_disable_fixed(struct hw_perf_counter *hwc, int __idx)
836 {
837         int idx = __idx - X86_PMC_IDX_FIXED;
838         u64 ctrl_val, mask;
839         int err;
840
841         mask = 0xfULL << (idx * 4);
842
843         rdmsrl(hwc->config_base, ctrl_val);
844         ctrl_val &= ~mask;
845         err = checking_wrmsrl(hwc->config_base, ctrl_val);
846 }
847
848 static inline void
849 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
850 {
851         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
852                 intel_pmu_disable_fixed(hwc, idx);
853                 return;
854         }
855
856         x86_pmu_disable_counter(hwc, idx);
857 }
858
859 static inline void
860 amd_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
861 {
862         x86_pmu_disable_counter(hwc, idx);
863 }
864
865 static DEFINE_PER_CPU(u64, prev_left[X86_PMC_IDX_MAX]);
866
867 /*
868  * Set the next IRQ period, based on the hwc->period_left value.
869  * To be called with the counter disabled in hw:
870  */
871 static int
872 x86_perf_counter_set_period(struct perf_counter *counter,
873                              struct hw_perf_counter *hwc, int idx)
874 {
875         s64 left = atomic64_read(&hwc->period_left);
876         s64 period = hwc->sample_period;
877         int err, ret = 0;
878
879         /*
880          * If we are way outside a reasoable range then just skip forward:
881          */
882         if (unlikely(left <= -period)) {
883                 left = period;
884                 atomic64_set(&hwc->period_left, left);
885                 hwc->last_period = period;
886                 ret = 1;
887         }
888
889         if (unlikely(left <= 0)) {
890                 left += period;
891                 atomic64_set(&hwc->period_left, left);
892                 hwc->last_period = period;
893                 ret = 1;
894         }
895         /*
896          * Quirk: certain CPUs dont like it if just 1 event is left:
897          */
898         if (unlikely(left < 2))
899                 left = 2;
900
901         if (left > x86_pmu.max_period)
902                 left = x86_pmu.max_period;
903
904         per_cpu(prev_left[idx], smp_processor_id()) = left;
905
906         /*
907          * The hw counter starts counting from this counter offset,
908          * mark it to be able to extra future deltas:
909          */
910         atomic64_set(&hwc->prev_count, (u64)-left);
911
912         err = checking_wrmsrl(hwc->counter_base + idx,
913                              (u64)(-left) & x86_pmu.counter_mask);
914
915         return ret;
916 }
917
918 static inline void
919 intel_pmu_enable_fixed(struct hw_perf_counter *hwc, int __idx)
920 {
921         int idx = __idx - X86_PMC_IDX_FIXED;
922         u64 ctrl_val, bits, mask;
923         int err;
924
925         /*
926          * Enable IRQ generation (0x8),
927          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
928          * if requested:
929          */
930         bits = 0x8ULL;
931         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
932                 bits |= 0x2;
933         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
934                 bits |= 0x1;
935         bits <<= (idx * 4);
936         mask = 0xfULL << (idx * 4);
937
938         rdmsrl(hwc->config_base, ctrl_val);
939         ctrl_val &= ~mask;
940         ctrl_val |= bits;
941         err = checking_wrmsrl(hwc->config_base, ctrl_val);
942 }
943
944 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
945 {
946         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
947                 intel_pmu_enable_fixed(hwc, idx);
948                 return;
949         }
950
951         x86_pmu_enable_counter(hwc, idx);
952 }
953
954 static void amd_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
955 {
956         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
957
958         if (cpuc->enabled)
959                 x86_pmu_enable_counter(hwc, idx);
960         else
961                 x86_pmu_disable_counter(hwc, idx);
962 }
963
964 static int
965 fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
966 {
967         unsigned int event;
968
969         if (!x86_pmu.num_counters_fixed)
970                 return -1;
971
972         /*
973          * Quirk, IA32_FIXED_CTRs do not work on current Atom processors:
974          */
975         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
976                                         boot_cpu_data.x86_model == 28)
977                 return -1;
978
979         event = hwc->config & ARCH_PERFMON_EVENT_MASK;
980
981         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
982                 return X86_PMC_IDX_FIXED_INSTRUCTIONS;
983         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
984                 return X86_PMC_IDX_FIXED_CPU_CYCLES;
985         if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_BUS_CYCLES)))
986                 return X86_PMC_IDX_FIXED_BUS_CYCLES;
987
988         return -1;
989 }
990
991 /*
992  * Find a PMC slot for the freshly enabled / scheduled in counter:
993  */
994 static int x86_pmu_enable(struct perf_counter *counter)
995 {
996         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
997         struct hw_perf_counter *hwc = &counter->hw;
998         int idx;
999
1000         idx = fixed_mode_idx(counter, hwc);
1001         if (idx >= 0) {
1002                 /*
1003                  * Try to get the fixed counter, if that is already taken
1004                  * then try to get a generic counter:
1005                  */
1006                 if (test_and_set_bit(idx, cpuc->used_mask))
1007                         goto try_generic;
1008
1009                 hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL;
1010                 /*
1011                  * We set it so that counter_base + idx in wrmsr/rdmsr maps to
1012                  * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
1013                  */
1014                 hwc->counter_base =
1015                         MSR_ARCH_PERFMON_FIXED_CTR0 - X86_PMC_IDX_FIXED;
1016                 hwc->idx = idx;
1017         } else {
1018                 idx = hwc->idx;
1019                 /* Try to get the previous generic counter again */
1020                 if (test_and_set_bit(idx, cpuc->used_mask)) {
1021 try_generic:
1022                         idx = find_first_zero_bit(cpuc->used_mask,
1023                                                   x86_pmu.num_counters);
1024                         if (idx == x86_pmu.num_counters)
1025                                 return -EAGAIN;
1026
1027                         set_bit(idx, cpuc->used_mask);
1028                         hwc->idx = idx;
1029                 }
1030                 hwc->config_base  = x86_pmu.eventsel;
1031                 hwc->counter_base = x86_pmu.perfctr;
1032         }
1033
1034         perf_counters_lapic_init();
1035
1036         x86_pmu.disable(hwc, idx);
1037
1038         cpuc->counters[idx] = counter;
1039         set_bit(idx, cpuc->active_mask);
1040
1041         x86_perf_counter_set_period(counter, hwc, idx);
1042         x86_pmu.enable(hwc, idx);
1043
1044         return 0;
1045 }
1046
1047 static void x86_pmu_unthrottle(struct perf_counter *counter)
1048 {
1049         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1050         struct hw_perf_counter *hwc = &counter->hw;
1051
1052         if (WARN_ON_ONCE(hwc->idx >= X86_PMC_IDX_MAX ||
1053                                 cpuc->counters[hwc->idx] != counter))
1054                 return;
1055
1056         x86_pmu.enable(hwc, hwc->idx);
1057 }
1058
1059 void perf_counter_print_debug(void)
1060 {
1061         u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
1062         struct cpu_hw_counters *cpuc;
1063         unsigned long flags;
1064         int cpu, idx;
1065
1066         if (!x86_pmu.num_counters)
1067                 return;
1068
1069         local_irq_save(flags);
1070
1071         cpu = smp_processor_id();
1072         cpuc = &per_cpu(cpu_hw_counters, cpu);
1073
1074         if (x86_pmu.version >= 2) {
1075                 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
1076                 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1077                 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow);
1078                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed);
1079
1080                 pr_info("\n");
1081                 pr_info("CPU#%d: ctrl:       %016llx\n", cpu, ctrl);
1082                 pr_info("CPU#%d: status:     %016llx\n", cpu, status);
1083                 pr_info("CPU#%d: overflow:   %016llx\n", cpu, overflow);
1084                 pr_info("CPU#%d: fixed:      %016llx\n", cpu, fixed);
1085         }
1086         pr_info("CPU#%d: used:       %016llx\n", cpu, *(u64 *)cpuc->used_mask);
1087
1088         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1089                 rdmsrl(x86_pmu.eventsel + idx, pmc_ctrl);
1090                 rdmsrl(x86_pmu.perfctr  + idx, pmc_count);
1091
1092                 prev_left = per_cpu(prev_left[idx], cpu);
1093
1094                 pr_info("CPU#%d:   gen-PMC%d ctrl:  %016llx\n",
1095                         cpu, idx, pmc_ctrl);
1096                 pr_info("CPU#%d:   gen-PMC%d count: %016llx\n",
1097                         cpu, idx, pmc_count);
1098                 pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
1099                         cpu, idx, prev_left);
1100         }
1101         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1102                 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
1103
1104                 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1105                         cpu, idx, pmc_count);
1106         }
1107         local_irq_restore(flags);
1108 }
1109
1110 static void x86_pmu_disable(struct perf_counter *counter)
1111 {
1112         struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
1113         struct hw_perf_counter *hwc = &counter->hw;
1114         int idx = hwc->idx;
1115
1116         /*
1117          * Must be done before we disable, otherwise the nmi handler
1118          * could reenable again:
1119          */
1120         clear_bit(idx, cpuc->active_mask);
1121         x86_pmu.disable(hwc, idx);
1122
1123         /*
1124          * Make sure the cleared pointer becomes visible before we
1125          * (potentially) free the counter:
1126          */
1127         barrier();
1128
1129         /*
1130          * Drain the remaining delta count out of a counter
1131          * that we are disabling:
1132          */
1133         x86_perf_counter_update(counter, hwc, idx);
1134         cpuc->counters[idx] = NULL;
1135         clear_bit(idx, cpuc->used_mask);
1136 }
1137
1138 /*
1139  * Save and restart an expired counter. Called by NMI contexts,
1140  * so it has to be careful about preempting normal counter ops:
1141  */
1142 static int intel_pmu_save_and_restart(struct perf_counter *counter)
1143 {
1144         struct hw_perf_counter *hwc = &counter->hw;
1145         int idx = hwc->idx;
1146         int ret;
1147
1148         x86_perf_counter_update(counter, hwc, idx);
1149         ret = x86_perf_counter_set_period(counter, hwc, idx);
1150
1151         if (counter->state == PERF_COUNTER_STATE_ACTIVE)
1152                 intel_pmu_enable_counter(hwc, idx);
1153
1154         return ret;
1155 }
1156
1157 static void intel_pmu_reset(void)
1158 {
1159         unsigned long flags;
1160         int idx;
1161
1162         if (!x86_pmu.num_counters)
1163                 return;
1164
1165         local_irq_save(flags);
1166
1167         printk("clearing PMU state on CPU#%d\n", smp_processor_id());
1168
1169         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1170                 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
1171                 checking_wrmsrl(x86_pmu.perfctr  + idx, 0ull);
1172         }
1173         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
1174                 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
1175         }
1176
1177         local_irq_restore(flags);
1178 }
1179
1180
1181 /*
1182  * This handler is triggered by the local APIC, so the APIC IRQ handling
1183  * rules apply:
1184  */
1185 static int intel_pmu_handle_irq(struct pt_regs *regs)
1186 {
1187         struct perf_sample_data data;
1188         struct cpu_hw_counters *cpuc;
1189         int bit, cpu, loops;
1190         u64 ack, status;
1191
1192         data.regs = regs;
1193         data.addr = 0;
1194
1195         cpu = smp_processor_id();
1196         cpuc = &per_cpu(cpu_hw_counters, cpu);
1197
1198         perf_disable();
1199         status = intel_pmu_get_status();
1200         if (!status) {
1201                 perf_enable();
1202                 return 0;
1203         }
1204
1205         loops = 0;
1206 again:
1207         if (++loops > 100) {
1208                 WARN_ONCE(1, "perfcounters: irq loop stuck!\n");
1209                 perf_counter_print_debug();
1210                 intel_pmu_reset();
1211                 perf_enable();
1212                 return 1;
1213         }
1214
1215         inc_irq_stat(apic_perf_irqs);
1216         ack = status;
1217         for_each_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
1218                 struct perf_counter *counter = cpuc->counters[bit];
1219
1220                 clear_bit(bit, (unsigned long *) &status);
1221                 if (!test_bit(bit, cpuc->active_mask))
1222                         continue;
1223
1224                 if (!intel_pmu_save_and_restart(counter))
1225                         continue;
1226
1227                 data.period = counter->hw.last_period;
1228
1229                 if (perf_counter_overflow(counter, 1, &data))
1230                         intel_pmu_disable_counter(&counter->hw, bit);
1231         }
1232
1233         intel_pmu_ack_status(ack);
1234
1235         /*
1236          * Repeat if there is more work to be done:
1237          */
1238         status = intel_pmu_get_status();
1239         if (status)
1240                 goto again;
1241
1242         perf_enable();
1243
1244         return 1;
1245 }
1246
1247 static int amd_pmu_handle_irq(struct pt_regs *regs)
1248 {
1249         struct perf_sample_data data;
1250         struct cpu_hw_counters *cpuc;
1251         struct perf_counter *counter;
1252         struct hw_perf_counter *hwc;
1253         int cpu, idx, handled = 0;
1254         u64 val;
1255
1256         data.regs = regs;
1257         data.addr = 0;
1258
1259         cpu = smp_processor_id();
1260         cpuc = &per_cpu(cpu_hw_counters, cpu);
1261
1262         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
1263                 if (!test_bit(idx, cpuc->active_mask))
1264                         continue;
1265
1266                 counter = cpuc->counters[idx];
1267                 hwc = &counter->hw;
1268
1269                 val = x86_perf_counter_update(counter, hwc, idx);
1270                 if (val & (1ULL << (x86_pmu.counter_bits - 1)))
1271                         continue;
1272
1273                 /*
1274                  * counter overflow
1275                  */
1276                 handled         = 1;
1277                 data.period     = counter->hw.last_period;
1278
1279                 if (!x86_perf_counter_set_period(counter, hwc, idx))
1280                         continue;
1281
1282                 if (perf_counter_overflow(counter, 1, &data))
1283                         amd_pmu_disable_counter(hwc, idx);
1284         }
1285
1286         if (handled)
1287                 inc_irq_stat(apic_perf_irqs);
1288
1289         return handled;
1290 }
1291
1292 void smp_perf_pending_interrupt(struct pt_regs *regs)
1293 {
1294         irq_enter();
1295         ack_APIC_irq();
1296         inc_irq_stat(apic_pending_irqs);
1297         perf_counter_do_pending();
1298         irq_exit();
1299 }
1300
1301 void set_perf_counter_pending(void)
1302 {
1303         apic->send_IPI_self(LOCAL_PENDING_VECTOR);
1304 }
1305
1306 void perf_counters_lapic_init(void)
1307 {
1308         if (!x86_pmu_initialized())
1309                 return;
1310
1311         /*
1312          * Always use NMI for PMU
1313          */
1314         apic_write(APIC_LVTPC, APIC_DM_NMI);
1315 }
1316
1317 static int __kprobes
1318 perf_counter_nmi_handler(struct notifier_block *self,
1319                          unsigned long cmd, void *__args)
1320 {
1321         struct die_args *args = __args;
1322         struct pt_regs *regs;
1323
1324         if (!atomic_read(&active_counters))
1325                 return NOTIFY_DONE;
1326
1327         switch (cmd) {
1328         case DIE_NMI:
1329         case DIE_NMI_IPI:
1330                 break;
1331
1332         default:
1333                 return NOTIFY_DONE;
1334         }
1335
1336         regs = args->regs;
1337
1338         apic_write(APIC_LVTPC, APIC_DM_NMI);
1339         /*
1340          * Can't rely on the handled return value to say it was our NMI, two
1341          * counters could trigger 'simultaneously' raising two back-to-back NMIs.
1342          *
1343          * If the first NMI handles both, the latter will be empty and daze
1344          * the CPU.
1345          */
1346         x86_pmu.handle_irq(regs);
1347
1348         return NOTIFY_STOP;
1349 }
1350
1351 static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
1352         .notifier_call          = perf_counter_nmi_handler,
1353         .next                   = NULL,
1354         .priority               = 1
1355 };
1356
1357 static struct x86_pmu intel_pmu = {
1358         .name                   = "Intel",
1359         .handle_irq             = intel_pmu_handle_irq,
1360         .disable_all            = intel_pmu_disable_all,
1361         .enable_all             = intel_pmu_enable_all,
1362         .enable                 = intel_pmu_enable_counter,
1363         .disable                = intel_pmu_disable_counter,
1364         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
1365         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
1366         .event_map              = intel_pmu_event_map,
1367         .raw_event              = intel_pmu_raw_event,
1368         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
1369         /*
1370          * Intel PMCs cannot be accessed sanely above 32 bit width,
1371          * so we install an artificial 1<<31 period regardless of
1372          * the generic counter period:
1373          */
1374         .max_period             = (1ULL << 31) - 1,
1375 };
1376
1377 static struct x86_pmu amd_pmu = {
1378         .name                   = "AMD",
1379         .handle_irq             = amd_pmu_handle_irq,
1380         .disable_all            = amd_pmu_disable_all,
1381         .enable_all             = amd_pmu_enable_all,
1382         .enable                 = amd_pmu_enable_counter,
1383         .disable                = amd_pmu_disable_counter,
1384         .eventsel               = MSR_K7_EVNTSEL0,
1385         .perfctr                = MSR_K7_PERFCTR0,
1386         .event_map              = amd_pmu_event_map,
1387         .raw_event              = amd_pmu_raw_event,
1388         .max_events             = ARRAY_SIZE(amd_perfmon_event_map),
1389         .num_counters           = 4,
1390         .counter_bits           = 48,
1391         .counter_mask           = (1ULL << 48) - 1,
1392         /* use highest bit to detect overflow */
1393         .max_period             = (1ULL << 47) - 1,
1394 };
1395
1396 static int intel_pmu_init(void)
1397 {
1398         union cpuid10_edx edx;
1399         union cpuid10_eax eax;
1400         unsigned int unused;
1401         unsigned int ebx;
1402         int version;
1403
1404         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
1405                 return -ENODEV;
1406
1407         /*
1408          * Check whether the Architectural PerfMon supports
1409          * Branch Misses Retired Event or not.
1410          */
1411         cpuid(10, &eax.full, &ebx, &unused, &edx.full);
1412         if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
1413                 return -ENODEV;
1414
1415         version = eax.split.version_id;
1416         if (version < 2)
1417                 return -ENODEV;
1418
1419         x86_pmu                         = intel_pmu;
1420         x86_pmu.version                 = version;
1421         x86_pmu.num_counters            = eax.split.num_counters;
1422         x86_pmu.counter_bits            = eax.split.bit_width;
1423         x86_pmu.counter_mask            = (1ULL << eax.split.bit_width) - 1;
1424
1425         /*
1426          * Quirk: v2 perfmon does not report fixed-purpose counters, so
1427          * assume at least 3 counters:
1428          */
1429         x86_pmu.num_counters_fixed      = max((int)edx.split.num_counters_fixed, 3);
1430
1431         rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
1432
1433         /*
1434          * Install the hw-cache-events table:
1435          */
1436         switch (boot_cpu_data.x86_model) {
1437         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1438         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1439         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1440         case 29: /* six-core 45 nm xeon "Dunnington" */
1441                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1442                        sizeof(hw_cache_event_ids));
1443
1444                 pr_cont("Core2 events, ");
1445                 break;
1446         default:
1447         case 26:
1448                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1449                        sizeof(hw_cache_event_ids));
1450
1451                 pr_cont("Nehalem/Corei7 events, ");
1452                 break;
1453         case 28:
1454                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1455                        sizeof(hw_cache_event_ids));
1456
1457                 pr_cont("Atom events, ");
1458                 break;
1459         }
1460         return 0;
1461 }
1462
1463 static int amd_pmu_init(void)
1464 {
1465         /* Performance-monitoring supported from K7 and later: */
1466         if (boot_cpu_data.x86 < 6)
1467                 return -ENODEV;
1468
1469         x86_pmu = amd_pmu;
1470
1471         /* Events are common for all AMDs */
1472         memcpy(hw_cache_event_ids, amd_hw_cache_event_ids,
1473                sizeof(hw_cache_event_ids));
1474
1475         return 0;
1476 }
1477
1478 void __init init_hw_perf_counters(void)
1479 {
1480         int err;
1481
1482         pr_info("Performance Counters: ");
1483
1484         switch (boot_cpu_data.x86_vendor) {
1485         case X86_VENDOR_INTEL:
1486                 err = intel_pmu_init();
1487                 break;
1488         case X86_VENDOR_AMD:
1489                 err = amd_pmu_init();
1490                 break;
1491         default:
1492                 return;
1493         }
1494         if (err != 0) {
1495                 pr_cont("no PMU driver, software counters only.\n");
1496                 return;
1497         }
1498
1499         pr_cont("%s PMU driver.\n", x86_pmu.name);
1500
1501         if (x86_pmu.num_counters > X86_PMC_MAX_GENERIC) {
1502                 x86_pmu.num_counters = X86_PMC_MAX_GENERIC;
1503                 WARN(1, KERN_ERR "hw perf counters %d > max(%d), clipping!",
1504                      x86_pmu.num_counters, X86_PMC_MAX_GENERIC);
1505         }
1506         perf_counter_mask = (1 << x86_pmu.num_counters) - 1;
1507         perf_max_counters = x86_pmu.num_counters;
1508
1509         if (x86_pmu.num_counters_fixed > X86_PMC_MAX_FIXED) {
1510                 x86_pmu.num_counters_fixed = X86_PMC_MAX_FIXED;
1511                 WARN(1, KERN_ERR "hw perf counters fixed %d > max(%d), clipping!",
1512                      x86_pmu.num_counters_fixed, X86_PMC_MAX_FIXED);
1513         }
1514
1515         perf_counter_mask |=
1516                 ((1LL << x86_pmu.num_counters_fixed)-1) << X86_PMC_IDX_FIXED;
1517
1518         perf_counters_lapic_init();
1519         register_die_notifier(&perf_counter_nmi_notifier);
1520
1521         pr_info("... version:                 %d\n",     x86_pmu.version);
1522         pr_info("... bit width:               %d\n",     x86_pmu.counter_bits);
1523         pr_info("... generic counters:        %d\n",     x86_pmu.num_counters);
1524         pr_info("... value mask:              %016Lx\n", x86_pmu.counter_mask);
1525         pr_info("... max period:              %016Lx\n", x86_pmu.max_period);
1526         pr_info("... fixed-purpose counters:  %d\n",     x86_pmu.num_counters_fixed);
1527         pr_info("... counter mask:            %016Lx\n", perf_counter_mask);
1528 }
1529
1530 static inline void x86_pmu_read(struct perf_counter *counter)
1531 {
1532         x86_perf_counter_update(counter, &counter->hw, counter->hw.idx);
1533 }
1534
1535 static const struct pmu pmu = {
1536         .enable         = x86_pmu_enable,
1537         .disable        = x86_pmu_disable,
1538         .read           = x86_pmu_read,
1539         .unthrottle     = x86_pmu_unthrottle,
1540 };
1541
1542 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
1543 {
1544         int err;
1545
1546         err = __hw_perf_counter_init(counter);
1547         if (err)
1548                 return ERR_PTR(err);
1549
1550         return &pmu;
1551 }
1552
1553 /*
1554  * callchain support
1555  */
1556
1557 static inline
1558 void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1559 {
1560         if (entry->nr < PERF_MAX_STACK_DEPTH)
1561                 entry->ip[entry->nr++] = ip;
1562 }
1563
1564 static DEFINE_PER_CPU(struct perf_callchain_entry, irq_entry);
1565 static DEFINE_PER_CPU(struct perf_callchain_entry, nmi_entry);
1566
1567
1568 static void
1569 backtrace_warning_symbol(void *data, char *msg, unsigned long symbol)
1570 {
1571         /* Ignore warnings */
1572 }
1573
1574 static void backtrace_warning(void *data, char *msg)
1575 {
1576         /* Ignore warnings */
1577 }
1578
1579 static int backtrace_stack(void *data, char *name)
1580 {
1581         /* Process all stacks: */
1582         return 0;
1583 }
1584
1585 static void backtrace_address(void *data, unsigned long addr, int reliable)
1586 {
1587         struct perf_callchain_entry *entry = data;
1588
1589         if (reliable)
1590                 callchain_store(entry, addr);
1591 }
1592
1593 static const struct stacktrace_ops backtrace_ops = {
1594         .warning                = backtrace_warning,
1595         .warning_symbol         = backtrace_warning_symbol,
1596         .stack                  = backtrace_stack,
1597         .address                = backtrace_address,
1598 };
1599
1600 #include "../dumpstack.h"
1601
1602 static void
1603 perf_callchain_kernel(struct pt_regs *regs, struct perf_callchain_entry *entry)
1604 {
1605         callchain_store(entry, PERF_CONTEXT_KERNEL);
1606         callchain_store(entry, regs->ip);
1607
1608         dump_trace(NULL, regs, NULL, 0, &backtrace_ops, entry);
1609 }
1610
1611 /*
1612  * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
1613  */
1614 static unsigned long
1615 copy_from_user_nmi(void *to, const void __user *from, unsigned long n)
1616 {
1617         unsigned long offset, addr = (unsigned long)from;
1618         int type = in_nmi() ? KM_NMI : KM_IRQ0;
1619         unsigned long size, len = 0;
1620         struct page *page;
1621         void *map;
1622         int ret;
1623
1624         do {
1625                 ret = __get_user_pages_fast(addr, 1, 0, &page);
1626                 if (!ret)
1627                         break;
1628
1629                 offset = addr & (PAGE_SIZE - 1);
1630                 size = min(PAGE_SIZE - offset, n - len);
1631
1632                 map = kmap_atomic(page, type);
1633                 memcpy(to, map+offset, size);
1634                 kunmap_atomic(map, type);
1635                 put_page(page);
1636
1637                 len  += size;
1638                 to   += size;
1639                 addr += size;
1640
1641         } while (len < n);
1642
1643         return len;
1644 }
1645
1646 static int copy_stack_frame(const void __user *fp, struct stack_frame *frame)
1647 {
1648         unsigned long bytes;
1649
1650         bytes = copy_from_user_nmi(frame, fp, sizeof(*frame));
1651
1652         return bytes == sizeof(*frame);
1653 }
1654
1655 static void
1656 perf_callchain_user(struct pt_regs *regs, struct perf_callchain_entry *entry)
1657 {
1658         struct stack_frame frame;
1659         const void __user *fp;
1660
1661         if (!user_mode(regs))
1662                 regs = task_pt_regs(current);
1663
1664         fp = (void __user *)regs->bp;
1665
1666         callchain_store(entry, PERF_CONTEXT_USER);
1667         callchain_store(entry, regs->ip);
1668
1669         while (entry->nr < PERF_MAX_STACK_DEPTH) {
1670                 frame.next_frame             = NULL;
1671                 frame.return_address = 0;
1672
1673                 if (!copy_stack_frame(fp, &frame))
1674                         break;
1675
1676                 if ((unsigned long)fp < regs->sp)
1677                         break;
1678
1679                 callchain_store(entry, frame.return_address);
1680                 fp = frame.next_frame;
1681         }
1682 }
1683
1684 static void
1685 perf_do_callchain(struct pt_regs *regs, struct perf_callchain_entry *entry)
1686 {
1687         int is_user;
1688
1689         if (!regs)
1690                 return;
1691
1692         is_user = user_mode(regs);
1693
1694         if (!current || current->pid == 0)
1695                 return;
1696
1697         if (is_user && current->state != TASK_RUNNING)
1698                 return;
1699
1700         if (!is_user)
1701                 perf_callchain_kernel(regs, entry);
1702
1703         if (current->mm)
1704                 perf_callchain_user(regs, entry);
1705 }
1706
1707 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1708 {
1709         struct perf_callchain_entry *entry;
1710
1711         if (in_nmi())
1712                 entry = &__get_cpu_var(nmi_entry);
1713         else
1714                 entry = &__get_cpu_var(irq_entry);
1715
1716         entry->nr = 0;
1717
1718         perf_do_callchain(regs, entry);
1719
1720         return entry;
1721 }