Merge branch 'linus' into release
[linux-2.6.git] / arch / x86 / kernel / cpu / cpufreq / longhaul.c
1 /*
2  *  (C) 2001-2004  Dave Jones. <davej@redhat.com>
3  *  (C) 2002  Padraig Brady. <padraig@antefacto.com>
4  *
5  *  Licensed under the terms of the GNU GPL License version 2.
6  *  Based upon datasheets & sample CPUs kindly provided by VIA.
7  *
8  *  VIA have currently 3 different versions of Longhaul.
9  *  Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
10  *   It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
11  *  Version 2 of longhaul is backward compatible with v1, but adds
12  *   LONGHAUL MSR for purpose of both frequency and voltage scaling.
13  *   Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
14  *  Version 3 of longhaul got renamed to Powersaver and redesigned
15  *   to use only the POWERSAVER MSR at 0x110a.
16  *   It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
17  *   It's pretty much the same feature wise to longhaul v2, though
18  *   there is provision for scaling FSB too, but this doesn't work
19  *   too well in practice so we don't even try to use this.
20  *
21  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
22  */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/cpufreq.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/string.h>
32 #include <linux/delay.h>
33 #include <linux/timex.h>
34 #include <linux/io.h>
35 #include <linux/acpi.h>
36 #include <linux/kernel.h>
37
38 #include <asm/msr.h>
39 #include <acpi/processor.h>
40
41 #include "longhaul.h"
42
43 #define PFX "longhaul: "
44
45 #define TYPE_LONGHAUL_V1        1
46 #define TYPE_LONGHAUL_V2        2
47 #define TYPE_POWERSAVER         3
48
49 #define CPU_SAMUEL      1
50 #define CPU_SAMUEL2     2
51 #define CPU_EZRA        3
52 #define CPU_EZRA_T      4
53 #define CPU_NEHEMIAH    5
54 #define CPU_NEHEMIAH_C  6
55
56 /* Flags */
57 #define USE_ACPI_C3             (1 << 1)
58 #define USE_NORTHBRIDGE         (1 << 2)
59
60 static int cpu_model;
61 static unsigned int numscales = 16;
62 static unsigned int fsb;
63
64 static const struct mV_pos *vrm_mV_table;
65 static const unsigned char *mV_vrm_table;
66
67 static unsigned int highest_speed, lowest_speed; /* kHz */
68 static unsigned int minmult, maxmult;
69 static int can_scale_voltage;
70 static struct acpi_processor *pr;
71 static struct acpi_processor_cx *cx;
72 static u32 acpi_regs_addr;
73 static u8 longhaul_flags;
74 static unsigned int longhaul_index;
75
76 /* Module parameters */
77 static int scale_voltage;
78 static int disable_acpi_c3;
79 static int revid_errata;
80
81 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, \
82                 "longhaul", msg)
83
84
85 /* Clock ratios multiplied by 10 */
86 static int mults[32];
87 static int eblcr[32];
88 static int longhaul_version;
89 static struct cpufreq_frequency_table *longhaul_table;
90
91 #ifdef CONFIG_CPU_FREQ_DEBUG
92 static char speedbuffer[8];
93
94 static char *print_speed(int speed)
95 {
96         if (speed < 1000) {
97                 snprintf(speedbuffer, sizeof(speedbuffer), "%dMHz", speed);
98                 return speedbuffer;
99         }
100
101         if (speed%1000 == 0)
102                 snprintf(speedbuffer, sizeof(speedbuffer),
103                         "%dGHz", speed/1000);
104         else
105                 snprintf(speedbuffer, sizeof(speedbuffer),
106                         "%d.%dGHz", speed/1000, (speed%1000)/100);
107
108         return speedbuffer;
109 }
110 #endif
111
112
113 static unsigned int calc_speed(int mult)
114 {
115         int khz;
116         khz = (mult/10)*fsb;
117         if (mult%10)
118                 khz += fsb/2;
119         khz *= 1000;
120         return khz;
121 }
122
123
124 static int longhaul_get_cpu_mult(void)
125 {
126         unsigned long invalue = 0, lo, hi;
127
128         rdmsr(MSR_IA32_EBL_CR_POWERON, lo, hi);
129         invalue = (lo & (1<<22|1<<23|1<<24|1<<25))>>22;
130         if (longhaul_version == TYPE_LONGHAUL_V2 ||
131             longhaul_version == TYPE_POWERSAVER) {
132                 if (lo & (1<<27))
133                         invalue += 16;
134         }
135         return eblcr[invalue];
136 }
137
138 /* For processor with BCR2 MSR */
139
140 static void do_longhaul1(unsigned int mults_index)
141 {
142         union msr_bcr2 bcr2;
143
144         rdmsrl(MSR_VIA_BCR2, bcr2.val);
145         /* Enable software clock multiplier */
146         bcr2.bits.ESOFTBF = 1;
147         bcr2.bits.CLOCKMUL = mults_index & 0xff;
148
149         /* Sync to timer tick */
150         safe_halt();
151         /* Change frequency on next halt or sleep */
152         wrmsrl(MSR_VIA_BCR2, bcr2.val);
153         /* Invoke transition */
154         ACPI_FLUSH_CPU_CACHE();
155         halt();
156
157         /* Disable software clock multiplier */
158         local_irq_disable();
159         rdmsrl(MSR_VIA_BCR2, bcr2.val);
160         bcr2.bits.ESOFTBF = 0;
161         wrmsrl(MSR_VIA_BCR2, bcr2.val);
162 }
163
164 /* For processor with Longhaul MSR */
165
166 static void do_powersaver(int cx_address, unsigned int mults_index,
167                           unsigned int dir)
168 {
169         union msr_longhaul longhaul;
170         u32 t;
171
172         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
173         /* Setup new frequency */
174         if (!revid_errata)
175                 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
176         else
177                 longhaul.bits.RevisionKey = 0;
178         longhaul.bits.SoftBusRatio = mults_index & 0xf;
179         longhaul.bits.SoftBusRatio4 = (mults_index & 0x10) >> 4;
180         /* Setup new voltage */
181         if (can_scale_voltage)
182                 longhaul.bits.SoftVID = (mults_index >> 8) & 0x1f;
183         /* Sync to timer tick */
184         safe_halt();
185         /* Raise voltage if necessary */
186         if (can_scale_voltage && dir) {
187                 longhaul.bits.EnableSoftVID = 1;
188                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
189                 /* Change voltage */
190                 if (!cx_address) {
191                         ACPI_FLUSH_CPU_CACHE();
192                         halt();
193                 } else {
194                         ACPI_FLUSH_CPU_CACHE();
195                         /* Invoke C3 */
196                         inb(cx_address);
197                         /* Dummy op - must do something useless after P_LVL3
198                          * read */
199                         t = inl(acpi_gbl_FADT.xpm_timer_block.address);
200                 }
201                 longhaul.bits.EnableSoftVID = 0;
202                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
203         }
204
205         /* Change frequency on next halt or sleep */
206         longhaul.bits.EnableSoftBusRatio = 1;
207         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
208         if (!cx_address) {
209                 ACPI_FLUSH_CPU_CACHE();
210                 halt();
211         } else {
212                 ACPI_FLUSH_CPU_CACHE();
213                 /* Invoke C3 */
214                 inb(cx_address);
215                 /* Dummy op - must do something useless after P_LVL3 read */
216                 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
217         }
218         /* Disable bus ratio bit */
219         longhaul.bits.EnableSoftBusRatio = 0;
220         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
221
222         /* Reduce voltage if necessary */
223         if (can_scale_voltage && !dir) {
224                 longhaul.bits.EnableSoftVID = 1;
225                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
226                 /* Change voltage */
227                 if (!cx_address) {
228                         ACPI_FLUSH_CPU_CACHE();
229                         halt();
230                 } else {
231                         ACPI_FLUSH_CPU_CACHE();
232                         /* Invoke C3 */
233                         inb(cx_address);
234                         /* Dummy op - must do something useless after P_LVL3
235                          * read */
236                         t = inl(acpi_gbl_FADT.xpm_timer_block.address);
237                 }
238                 longhaul.bits.EnableSoftVID = 0;
239                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
240         }
241 }
242
243 /**
244  * longhaul_set_cpu_frequency()
245  * @mults_index : bitpattern of the new multiplier.
246  *
247  * Sets a new clock ratio.
248  */
249
250 static void longhaul_setstate(unsigned int table_index)
251 {
252         unsigned int mults_index;
253         int speed, mult;
254         struct cpufreq_freqs freqs;
255         unsigned long flags;
256         unsigned int pic1_mask, pic2_mask;
257         u16 bm_status = 0;
258         u32 bm_timeout = 1000;
259         unsigned int dir = 0;
260
261         mults_index = longhaul_table[table_index].index;
262         /* Safety precautions */
263         mult = mults[mults_index & 0x1f];
264         if (mult == -1)
265                 return;
266         speed = calc_speed(mult);
267         if ((speed > highest_speed) || (speed < lowest_speed))
268                 return;
269         /* Voltage transition before frequency transition? */
270         if (can_scale_voltage && longhaul_index < table_index)
271                 dir = 1;
272
273         freqs.old = calc_speed(longhaul_get_cpu_mult());
274         freqs.new = speed;
275         freqs.cpu = 0; /* longhaul.c is UP only driver */
276
277         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
278
279         dprintk("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
280                         fsb, mult/10, mult%10, print_speed(speed/1000));
281 retry_loop:
282         preempt_disable();
283         local_irq_save(flags);
284
285         pic2_mask = inb(0xA1);
286         pic1_mask = inb(0x21);  /* works on C3. save mask. */
287         outb(0xFF, 0xA1);       /* Overkill */
288         outb(0xFE, 0x21);       /* TMR0 only */
289
290         /* Wait while PCI bus is busy. */
291         if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
292             || ((pr != NULL) && pr->flags.bm_control))) {
293                 bm_status = inw(acpi_regs_addr);
294                 bm_status &= 1 << 4;
295                 while (bm_status && bm_timeout) {
296                         outw(1 << 4, acpi_regs_addr);
297                         bm_timeout--;
298                         bm_status = inw(acpi_regs_addr);
299                         bm_status &= 1 << 4;
300                 }
301         }
302
303         if (longhaul_flags & USE_NORTHBRIDGE) {
304                 /* Disable AGP and PCI arbiters */
305                 outb(3, 0x22);
306         } else if ((pr != NULL) && pr->flags.bm_control) {
307                 /* Disable bus master arbitration */
308                 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
309         }
310         switch (longhaul_version) {
311
312         /*
313          * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
314          * Software controlled multipliers only.
315          */
316         case TYPE_LONGHAUL_V1:
317                 do_longhaul1(mults_index);
318                 break;
319
320         /*
321          * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
322          *
323          * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
324          * Nehemiah can do FSB scaling too, but this has never been proven
325          * to work in practice.
326          */
327         case TYPE_LONGHAUL_V2:
328         case TYPE_POWERSAVER:
329                 if (longhaul_flags & USE_ACPI_C3) {
330                         /* Don't allow wakeup */
331                         acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
332                         do_powersaver(cx->address, mults_index, dir);
333                 } else {
334                         do_powersaver(0, mults_index, dir);
335                 }
336                 break;
337         }
338
339         if (longhaul_flags & USE_NORTHBRIDGE) {
340                 /* Enable arbiters */
341                 outb(0, 0x22);
342         } else if ((pr != NULL) && pr->flags.bm_control) {
343                 /* Enable bus master arbitration */
344                 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
345         }
346         outb(pic2_mask, 0xA1);  /* restore mask */
347         outb(pic1_mask, 0x21);
348
349         local_irq_restore(flags);
350         preempt_enable();
351
352         freqs.new = calc_speed(longhaul_get_cpu_mult());
353         /* Check if requested frequency is set. */
354         if (unlikely(freqs.new != speed)) {
355                 printk(KERN_INFO PFX "Failed to set requested frequency!\n");
356                 /* Revision ID = 1 but processor is expecting revision key
357                  * equal to 0. Jumpers at the bottom of processor will change
358                  * multiplier and FSB, but will not change bits in Longhaul
359                  * MSR nor enable voltage scaling. */
360                 if (!revid_errata) {
361                         printk(KERN_INFO PFX "Enabling \"Ignore Revision ID\" "
362                                                 "option.\n");
363                         revid_errata = 1;
364                         msleep(200);
365                         goto retry_loop;
366                 }
367                 /* Why ACPI C3 sometimes doesn't work is a mystery for me.
368                  * But it does happen. Processor is entering ACPI C3 state,
369                  * but it doesn't change frequency. I tried poking various
370                  * bits in northbridge registers, but without success. */
371                 if (longhaul_flags & USE_ACPI_C3) {
372                         printk(KERN_INFO PFX "Disabling ACPI C3 support.\n");
373                         longhaul_flags &= ~USE_ACPI_C3;
374                         if (revid_errata) {
375                                 printk(KERN_INFO PFX "Disabling \"Ignore "
376                                                 "Revision ID\" option.\n");
377                                 revid_errata = 0;
378                         }
379                         msleep(200);
380                         goto retry_loop;
381                 }
382                 /* This shouldn't happen. Longhaul ver. 2 was reported not
383                  * working on processors without voltage scaling, but with
384                  * RevID = 1. RevID errata will make things right. Just
385                  * to be 100% sure. */
386                 if (longhaul_version == TYPE_LONGHAUL_V2) {
387                         printk(KERN_INFO PFX "Switching to Longhaul ver. 1\n");
388                         longhaul_version = TYPE_LONGHAUL_V1;
389                         msleep(200);
390                         goto retry_loop;
391                 }
392         }
393         /* Report true CPU frequency */
394         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
395
396         if (!bm_timeout)
397                 printk(KERN_INFO PFX "Warning: Timeout while waiting for "
398                                 "idle PCI bus.\n");
399 }
400
401 /*
402  * Centaur decided to make life a little more tricky.
403  * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
404  * Samuel2 and above have to try and guess what the FSB is.
405  * We do this by assuming we booted at maximum multiplier, and interpolate
406  * between that value multiplied by possible FSBs and cpu_mhz which
407  * was calculated at boot time. Really ugly, but no other way to do this.
408  */
409
410 #define ROUNDING        0xf
411
412 static int guess_fsb(int mult)
413 {
414         int speed = cpu_khz / 1000;
415         int i;
416         int speeds[] = { 666, 1000, 1333, 2000 };
417         int f_max, f_min;
418
419         for (i = 0; i < 4; i++) {
420                 f_max = ((speeds[i] * mult) + 50) / 100;
421                 f_max += (ROUNDING / 2);
422                 f_min = f_max - ROUNDING;
423                 if ((speed <= f_max) && (speed >= f_min))
424                         return speeds[i] / 10;
425         }
426         return 0;
427 }
428
429
430 static int __init longhaul_get_ranges(void)
431 {
432         unsigned int i, j, k = 0;
433         unsigned int ratio;
434         int mult;
435
436         /* Get current frequency */
437         mult = longhaul_get_cpu_mult();
438         if (mult == -1) {
439                 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
440                 return -EINVAL;
441         }
442         fsb = guess_fsb(mult);
443         if (fsb == 0) {
444                 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
445                 return -EINVAL;
446         }
447         /* Get max multiplier - as we always did.
448          * Longhaul MSR is usefull only when voltage scaling is enabled.
449          * C3 is booting at max anyway. */
450         maxmult = mult;
451         /* Get min multiplier */
452         switch (cpu_model) {
453         case CPU_NEHEMIAH:
454                 minmult = 50;
455                 break;
456         case CPU_NEHEMIAH_C:
457                 minmult = 40;
458                 break;
459         default:
460                 minmult = 30;
461                 break;
462         }
463
464         dprintk("MinMult:%d.%dx MaxMult:%d.%dx\n",
465                  minmult/10, minmult%10, maxmult/10, maxmult%10);
466
467         highest_speed = calc_speed(maxmult);
468         lowest_speed = calc_speed(minmult);
469         dprintk("FSB:%dMHz  Lowest speed: %s   Highest speed:%s\n", fsb,
470                  print_speed(lowest_speed/1000),
471                  print_speed(highest_speed/1000));
472
473         if (lowest_speed == highest_speed) {
474                 printk(KERN_INFO PFX "highestspeed == lowest, aborting.\n");
475                 return -EINVAL;
476         }
477         if (lowest_speed > highest_speed) {
478                 printk(KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
479                         lowest_speed, highest_speed);
480                 return -EINVAL;
481         }
482
483         longhaul_table = kmalloc((numscales + 1) * sizeof(*longhaul_table),
484                         GFP_KERNEL);
485         if (!longhaul_table)
486                 return -ENOMEM;
487
488         for (j = 0; j < numscales; j++) {
489                 ratio = mults[j];
490                 if (ratio == -1)
491                         continue;
492                 if (ratio > maxmult || ratio < minmult)
493                         continue;
494                 longhaul_table[k].frequency = calc_speed(ratio);
495                 longhaul_table[k].index = j;
496                 k++;
497         }
498         if (k <= 1) {
499                 kfree(longhaul_table);
500                 return -ENODEV;
501         }
502         /* Sort */
503         for (j = 0; j < k - 1; j++) {
504                 unsigned int min_f, min_i;
505                 min_f = longhaul_table[j].frequency;
506                 min_i = j;
507                 for (i = j + 1; i < k; i++) {
508                         if (longhaul_table[i].frequency < min_f) {
509                                 min_f = longhaul_table[i].frequency;
510                                 min_i = i;
511                         }
512                 }
513                 if (min_i != j) {
514                         swap(longhaul_table[j].frequency,
515                              longhaul_table[min_i].frequency);
516                         swap(longhaul_table[j].index,
517                              longhaul_table[min_i].index);
518                 }
519         }
520
521         longhaul_table[k].frequency = CPUFREQ_TABLE_END;
522
523         /* Find index we are running on */
524         for (j = 0; j < k; j++) {
525                 if (mults[longhaul_table[j].index & 0x1f] == mult) {
526                         longhaul_index = j;
527                         break;
528                 }
529         }
530         return 0;
531 }
532
533
534 static void __init longhaul_setup_voltagescaling(void)
535 {
536         union msr_longhaul longhaul;
537         struct mV_pos minvid, maxvid, vid;
538         unsigned int j, speed, pos, kHz_step, numvscales;
539         int min_vid_speed;
540
541         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
542         if (!(longhaul.bits.RevisionID & 1)) {
543                 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
544                 return;
545         }
546
547         if (!longhaul.bits.VRMRev) {
548                 printk(KERN_INFO PFX "VRM 8.5\n");
549                 vrm_mV_table = &vrm85_mV[0];
550                 mV_vrm_table = &mV_vrm85[0];
551         } else {
552                 printk(KERN_INFO PFX "Mobile VRM\n");
553                 if (cpu_model < CPU_NEHEMIAH)
554                         return;
555                 vrm_mV_table = &mobilevrm_mV[0];
556                 mV_vrm_table = &mV_mobilevrm[0];
557         }
558
559         minvid = vrm_mV_table[longhaul.bits.MinimumVID];
560         maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
561
562         if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
563                 printk(KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
564                                         "Voltage scaling disabled.\n",
565                                         minvid.mV/1000, minvid.mV%1000,
566                                         maxvid.mV/1000, maxvid.mV%1000);
567                 return;
568         }
569
570         if (minvid.mV == maxvid.mV) {
571                 printk(KERN_INFO PFX "Claims to support voltage scaling but "
572                                 "min & max are both %d.%03d. "
573                                 "Voltage scaling disabled\n",
574                                 maxvid.mV/1000, maxvid.mV%1000);
575                 return;
576         }
577
578         /* How many voltage steps*/
579         numvscales = maxvid.pos - minvid.pos + 1;
580         printk(KERN_INFO PFX
581                 "Max VID=%d.%03d  "
582                 "Min VID=%d.%03d, "
583                 "%d possible voltage scales\n",
584                 maxvid.mV/1000, maxvid.mV%1000,
585                 minvid.mV/1000, minvid.mV%1000,
586                 numvscales);
587
588         /* Calculate max frequency at min voltage */
589         j = longhaul.bits.MinMHzBR;
590         if (longhaul.bits.MinMHzBR4)
591                 j += 16;
592         min_vid_speed = eblcr[j];
593         if (min_vid_speed == -1)
594                 return;
595         switch (longhaul.bits.MinMHzFSB) {
596         case 0:
597                 min_vid_speed *= 13333;
598                 break;
599         case 1:
600                 min_vid_speed *= 10000;
601                 break;
602         case 3:
603                 min_vid_speed *= 6666;
604                 break;
605         default:
606                 return;
607                 break;
608         }
609         if (min_vid_speed >= highest_speed)
610                 return;
611         /* Calculate kHz for one voltage step */
612         kHz_step = (highest_speed - min_vid_speed) / numvscales;
613
614         j = 0;
615         while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
616                 speed = longhaul_table[j].frequency;
617                 if (speed > min_vid_speed)
618                         pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
619                 else
620                         pos = minvid.pos;
621                 longhaul_table[j].index |= mV_vrm_table[pos] << 8;
622                 vid = vrm_mV_table[mV_vrm_table[pos]];
623                 printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n",
624                                 speed, j, vid.mV);
625                 j++;
626         }
627
628         can_scale_voltage = 1;
629         printk(KERN_INFO PFX "Voltage scaling enabled.\n");
630 }
631
632
633 static int longhaul_verify(struct cpufreq_policy *policy)
634 {
635         return cpufreq_frequency_table_verify(policy, longhaul_table);
636 }
637
638
639 static int longhaul_target(struct cpufreq_policy *policy,
640                             unsigned int target_freq, unsigned int relation)
641 {
642         unsigned int table_index = 0;
643         unsigned int i;
644         unsigned int dir = 0;
645         u8 vid, current_vid;
646
647         if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq,
648                                 relation, &table_index))
649                 return -EINVAL;
650
651         /* Don't set same frequency again */
652         if (longhaul_index == table_index)
653                 return 0;
654
655         if (!can_scale_voltage)
656                 longhaul_setstate(table_index);
657         else {
658                 /* On test system voltage transitions exceeding single
659                  * step up or down were turning motherboard off. Both
660                  * "ondemand" and "userspace" are unsafe. C7 is doing
661                  * this in hardware, C3 is old and we need to do this
662                  * in software. */
663                 i = longhaul_index;
664                 current_vid = (longhaul_table[longhaul_index].index >> 8);
665                 current_vid &= 0x1f;
666                 if (table_index > longhaul_index)
667                         dir = 1;
668                 while (i != table_index) {
669                         vid = (longhaul_table[i].index >> 8) & 0x1f;
670                         if (vid != current_vid) {
671                                 longhaul_setstate(i);
672                                 current_vid = vid;
673                                 msleep(200);
674                         }
675                         if (dir)
676                                 i++;
677                         else
678                                 i--;
679                 }
680                 longhaul_setstate(table_index);
681         }
682         longhaul_index = table_index;
683         return 0;
684 }
685
686
687 static unsigned int longhaul_get(unsigned int cpu)
688 {
689         if (cpu)
690                 return 0;
691         return calc_speed(longhaul_get_cpu_mult());
692 }
693
694 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
695                                           u32 nesting_level,
696                                           void *context, void **return_value)
697 {
698         struct acpi_device *d;
699
700         if (acpi_bus_get_device(obj_handle, &d))
701                 return 0;
702
703         *return_value = acpi_driver_data(d);
704         return 1;
705 }
706
707 /* VIA don't support PM2 reg, but have something similar */
708 static int enable_arbiter_disable(void)
709 {
710         struct pci_dev *dev;
711         int status = 1;
712         int reg;
713         u8 pci_cmd;
714
715         /* Find PLE133 host bridge */
716         reg = 0x78;
717         dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
718                              NULL);
719         /* Find PM133/VT8605 host bridge */
720         if (dev == NULL)
721                 dev = pci_get_device(PCI_VENDOR_ID_VIA,
722                                      PCI_DEVICE_ID_VIA_8605_0, NULL);
723         /* Find CLE266 host bridge */
724         if (dev == NULL) {
725                 reg = 0x76;
726                 dev = pci_get_device(PCI_VENDOR_ID_VIA,
727                                      PCI_DEVICE_ID_VIA_862X_0, NULL);
728                 /* Find CN400 V-Link host bridge */
729                 if (dev == NULL)
730                         dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
731         }
732         if (dev != NULL) {
733                 /* Enable access to port 0x22 */
734                 pci_read_config_byte(dev, reg, &pci_cmd);
735                 if (!(pci_cmd & 1<<7)) {
736                         pci_cmd |= 1<<7;
737                         pci_write_config_byte(dev, reg, pci_cmd);
738                         pci_read_config_byte(dev, reg, &pci_cmd);
739                         if (!(pci_cmd & 1<<7)) {
740                                 printk(KERN_ERR PFX
741                                         "Can't enable access to port 0x22.\n");
742                                 status = 0;
743                         }
744                 }
745                 pci_dev_put(dev);
746                 return status;
747         }
748         return 0;
749 }
750
751 static int longhaul_setup_southbridge(void)
752 {
753         struct pci_dev *dev;
754         u8 pci_cmd;
755
756         /* Find VT8235 southbridge */
757         dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
758         if (dev == NULL)
759                 /* Find VT8237 southbridge */
760                 dev = pci_get_device(PCI_VENDOR_ID_VIA,
761                                      PCI_DEVICE_ID_VIA_8237, NULL);
762         if (dev != NULL) {
763                 /* Set transition time to max */
764                 pci_read_config_byte(dev, 0xec, &pci_cmd);
765                 pci_cmd &= ~(1 << 2);
766                 pci_write_config_byte(dev, 0xec, pci_cmd);
767                 pci_read_config_byte(dev, 0xe4, &pci_cmd);
768                 pci_cmd &= ~(1 << 7);
769                 pci_write_config_byte(dev, 0xe4, pci_cmd);
770                 pci_read_config_byte(dev, 0xe5, &pci_cmd);
771                 pci_cmd |= 1 << 7;
772                 pci_write_config_byte(dev, 0xe5, pci_cmd);
773                 /* Get address of ACPI registers block*/
774                 pci_read_config_byte(dev, 0x81, &pci_cmd);
775                 if (pci_cmd & 1 << 7) {
776                         pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
777                         acpi_regs_addr &= 0xff00;
778                         printk(KERN_INFO PFX "ACPI I/O at 0x%x\n",
779                                         acpi_regs_addr);
780                 }
781
782                 pci_dev_put(dev);
783                 return 1;
784         }
785         return 0;
786 }
787
788 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
789 {
790         struct cpuinfo_x86 *c = &cpu_data(0);
791         char *cpuname = NULL;
792         int ret;
793         u32 lo, hi;
794
795         /* Check what we have on this motherboard */
796         switch (c->x86_model) {
797         case 6:
798                 cpu_model = CPU_SAMUEL;
799                 cpuname = "C3 'Samuel' [C5A]";
800                 longhaul_version = TYPE_LONGHAUL_V1;
801                 memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
802                 memcpy(eblcr, samuel1_eblcr, sizeof(samuel1_eblcr));
803                 break;
804
805         case 7:
806                 switch (c->x86_mask) {
807                 case 0:
808                         longhaul_version = TYPE_LONGHAUL_V1;
809                         cpu_model = CPU_SAMUEL2;
810                         cpuname = "C3 'Samuel 2' [C5B]";
811                         /* Note, this is not a typo, early Samuel2's had
812                          * Samuel1 ratios. */
813                         memcpy(mults, samuel1_mults, sizeof(samuel1_mults));
814                         memcpy(eblcr, samuel2_eblcr, sizeof(samuel2_eblcr));
815                         break;
816                 case 1 ... 15:
817                         longhaul_version = TYPE_LONGHAUL_V1;
818                         if (c->x86_mask < 8) {
819                                 cpu_model = CPU_SAMUEL2;
820                                 cpuname = "C3 'Samuel 2' [C5B]";
821                         } else {
822                                 cpu_model = CPU_EZRA;
823                                 cpuname = "C3 'Ezra' [C5C]";
824                         }
825                         memcpy(mults, ezra_mults, sizeof(ezra_mults));
826                         memcpy(eblcr, ezra_eblcr, sizeof(ezra_eblcr));
827                         break;
828                 }
829                 break;
830
831         case 8:
832                 cpu_model = CPU_EZRA_T;
833                 cpuname = "C3 'Ezra-T' [C5M]";
834                 longhaul_version = TYPE_POWERSAVER;
835                 numscales = 32;
836                 memcpy(mults, ezrat_mults, sizeof(ezrat_mults));
837                 memcpy(eblcr, ezrat_eblcr, sizeof(ezrat_eblcr));
838                 break;
839
840         case 9:
841                 longhaul_version = TYPE_POWERSAVER;
842                 numscales = 32;
843                 memcpy(mults, nehemiah_mults, sizeof(nehemiah_mults));
844                 memcpy(eblcr, nehemiah_eblcr, sizeof(nehemiah_eblcr));
845                 switch (c->x86_mask) {
846                 case 0 ... 1:
847                         cpu_model = CPU_NEHEMIAH;
848                         cpuname = "C3 'Nehemiah A' [C5XLOE]";
849                         break;
850                 case 2 ... 4:
851                         cpu_model = CPU_NEHEMIAH;
852                         cpuname = "C3 'Nehemiah B' [C5XLOH]";
853                         break;
854                 case 5 ... 15:
855                         cpu_model = CPU_NEHEMIAH_C;
856                         cpuname = "C3 'Nehemiah C' [C5P]";
857                         break;
858                 }
859                 break;
860
861         default:
862                 cpuname = "Unknown";
863                 break;
864         }
865         /* Check Longhaul ver. 2 */
866         if (longhaul_version == TYPE_LONGHAUL_V2) {
867                 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
868                 if (lo == 0 && hi == 0)
869                         /* Looks like MSR isn't present */
870                         longhaul_version = TYPE_LONGHAUL_V1;
871         }
872
873         printk(KERN_INFO PFX "VIA %s CPU detected.  ", cpuname);
874         switch (longhaul_version) {
875         case TYPE_LONGHAUL_V1:
876         case TYPE_LONGHAUL_V2:
877                 printk(KERN_CONT "Longhaul v%d supported.\n", longhaul_version);
878                 break;
879         case TYPE_POWERSAVER:
880                 printk(KERN_CONT "Powersaver supported.\n");
881                 break;
882         };
883
884         /* Doesn't hurt */
885         longhaul_setup_southbridge();
886
887         /* Find ACPI data for processor */
888         acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
889                                 ACPI_UINT32_MAX, &longhaul_walk_callback,
890                                 NULL, (void *)&pr);
891
892         /* Check ACPI support for C3 state */
893         if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
894                 cx = &pr->power.states[ACPI_STATE_C3];
895                 if (cx->address > 0 && cx->latency <= 1000)
896                         longhaul_flags |= USE_ACPI_C3;
897         }
898         /* Disable if it isn't working */
899         if (disable_acpi_c3)
900                 longhaul_flags &= ~USE_ACPI_C3;
901         /* Check if northbridge is friendly */
902         if (enable_arbiter_disable())
903                 longhaul_flags |= USE_NORTHBRIDGE;
904
905         /* Check ACPI support for bus master arbiter disable */
906         if (!(longhaul_flags & USE_ACPI_C3
907              || longhaul_flags & USE_NORTHBRIDGE)
908             && ((pr == NULL) || !(pr->flags.bm_control))) {
909                 printk(KERN_ERR PFX
910                         "No ACPI support. Unsupported northbridge.\n");
911                 return -ENODEV;
912         }
913
914         if (longhaul_flags & USE_NORTHBRIDGE)
915                 printk(KERN_INFO PFX "Using northbridge support.\n");
916         if (longhaul_flags & USE_ACPI_C3)
917                 printk(KERN_INFO PFX "Using ACPI support.\n");
918
919         ret = longhaul_get_ranges();
920         if (ret != 0)
921                 return ret;
922
923         if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
924                 longhaul_setup_voltagescaling();
925
926         policy->cpuinfo.transition_latency = 200000;    /* nsec */
927         policy->cur = calc_speed(longhaul_get_cpu_mult());
928
929         ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
930         if (ret)
931                 return ret;
932
933         cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
934
935         return 0;
936 }
937
938 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
939 {
940         cpufreq_frequency_table_put_attr(policy->cpu);
941         return 0;
942 }
943
944 static struct freq_attr *longhaul_attr[] = {
945         &cpufreq_freq_attr_scaling_available_freqs,
946         NULL,
947 };
948
949 static struct cpufreq_driver longhaul_driver = {
950         .verify = longhaul_verify,
951         .target = longhaul_target,
952         .get    = longhaul_get,
953         .init   = longhaul_cpu_init,
954         .exit   = __devexit_p(longhaul_cpu_exit),
955         .name   = "longhaul",
956         .owner  = THIS_MODULE,
957         .attr   = longhaul_attr,
958 };
959
960
961 static int __init longhaul_init(void)
962 {
963         struct cpuinfo_x86 *c = &cpu_data(0);
964
965         if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
966                 return -ENODEV;
967
968 #ifdef CONFIG_SMP
969         if (num_online_cpus() > 1) {
970                 printk(KERN_ERR PFX "More than 1 CPU detected, "
971                                 "longhaul disabled.\n");
972                 return -ENODEV;
973         }
974 #endif
975 #ifdef CONFIG_X86_IO_APIC
976         if (cpu_has_apic) {
977                 printk(KERN_ERR PFX "APIC detected. Longhaul is currently "
978                                 "broken in this configuration.\n");
979                 return -ENODEV;
980         }
981 #endif
982         switch (c->x86_model) {
983         case 6 ... 9:
984                 return cpufreq_register_driver(&longhaul_driver);
985         case 10:
986                 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
987         default:
988                 ;
989         }
990
991         return -ENODEV;
992 }
993
994
995 static void __exit longhaul_exit(void)
996 {
997         int i;
998
999         for (i = 0; i < numscales; i++) {
1000                 if (mults[i] == maxmult) {
1001                         longhaul_setstate(i);
1002                         break;
1003                 }
1004         }
1005
1006         cpufreq_unregister_driver(&longhaul_driver);
1007         kfree(longhaul_table);
1008 }
1009
1010 /* Even if BIOS is exporting ACPI C3 state, and it is used
1011  * with success when CPU is idle, this state doesn't
1012  * trigger frequency transition in some cases. */
1013 module_param(disable_acpi_c3, int, 0644);
1014 MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
1015 /* Change CPU voltage with frequency. Very usefull to save
1016  * power, but most VIA C3 processors aren't supporting it. */
1017 module_param(scale_voltage, int, 0644);
1018 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
1019 /* Force revision key to 0 for processors which doesn't
1020  * support voltage scaling, but are introducing itself as
1021  * such. */
1022 module_param(revid_errata, int, 0644);
1023 MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID");
1024
1025 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
1026 MODULE_DESCRIPTION("Longhaul driver for VIA Cyrix processors.");
1027 MODULE_LICENSE("GPL");
1028
1029 late_initcall(longhaul_init);
1030 module_exit(longhaul_exit);