x86, clockevents: add C1E aware idle function
[linux-2.6.git] / arch / x86 / kernel / cpu / amd.c
1 #include <linux/init.h>
2 #include <linux/bitops.h>
3 #include <linux/mm.h>
4 #include <asm/io.h>
5 #include <asm/processor.h>
6 #include <asm/apic.h>
7
8 #include <mach_apic.h>
9 #include "cpu.h"
10
11 /*
12  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
13  *      misexecution of code under Linux. Owners of such processors should
14  *      contact AMD for precise details and a CPU swap.
15  *
16  *      See     http://www.multimania.com/poulot/k6bug.html
17  *              http://www.amd.com/K6/k6docs/revgd.html
18  *
19  *      The following test is erm.. interesting. AMD neglected to up
20  *      the chip setting when fixing the bug but they also tweaked some
21  *      performance at the same time..
22  */
23
24 extern void vide(void);
25 __asm__(".align 4\nvide: ret");
26
27 int force_mwait __cpuinitdata;
28
29 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
30 {
31         if (cpuid_eax(0x80000000) >= 0x80000007) {
32                 c->x86_power = cpuid_edx(0x80000007);
33                 if (c->x86_power & (1<<8))
34                         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
35         }
36 }
37
38 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
39 {
40         u32 l, h;
41         int mbytes = num_physpages >> (20-PAGE_SHIFT);
42         int r;
43
44 #ifdef CONFIG_SMP
45         unsigned long long value;
46
47         /*
48          * Disable TLB flush filter by setting HWCR.FFDIS on K8
49          * bit 6 of msr C001_0015
50          *
51          * Errata 63 for SH-B3 steppings
52          * Errata 122 for all steppings (F+ have it disabled by default)
53          */
54         if (c->x86 == 15) {
55                 rdmsrl(MSR_K7_HWCR, value);
56                 value |= 1 << 6;
57                 wrmsrl(MSR_K7_HWCR, value);
58         }
59 #endif
60
61         early_init_amd(c);
62
63         /*
64          *      FIXME: We should handle the K5 here. Set up the write
65          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
66          *      no bus pipeline)
67          */
68
69         /*
70          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
71          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
72          */
73         clear_cpu_cap(c, 0*32+31);
74
75         r = get_model_name(c);
76
77         switch (c->x86) {
78         case 4:
79                 /*
80                  * General Systems BIOSen alias the cpu frequency registers
81                  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
82                  * drivers subsequently pokes it, and changes the CPU speed.
83                  * Workaround : Remove the unneeded alias.
84                  */
85 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
86 #define CBAR_ENB        (0x80000000)
87 #define CBAR_KEY        (0X000000CB)
88                         if (c->x86_model == 9 || c->x86_model == 10) {
89                                 if (inl (CBAR) & CBAR_ENB)
90                                         outl (0 | CBAR_KEY, CBAR);
91                         }
92                         break;
93         case 5:
94                         if (c->x86_model < 6) {
95                                 /* Based on AMD doc 20734R - June 2000 */
96                                 if (c->x86_model == 0) {
97                                         clear_cpu_cap(c, X86_FEATURE_APIC);
98                                         set_cpu_cap(c, X86_FEATURE_PGE);
99                                 }
100                                 break;
101                         }
102
103                         if (c->x86_model == 6 && c->x86_mask == 1) {
104                                 const int K6_BUG_LOOP = 1000000;
105                                 int n;
106                                 void (*f_vide)(void);
107                                 unsigned long d, d2;
108
109                                 printk(KERN_INFO "AMD K6 stepping B detected - ");
110
111                                 /*
112                                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
113                                  * calls at the same time.
114                                  */
115
116                                 n = K6_BUG_LOOP;
117                                 f_vide = vide;
118                                 rdtscl(d);
119                                 while (n--)
120                                         f_vide();
121                                 rdtscl(d2);
122                                 d = d2-d;
123
124                                 if (d > 20*K6_BUG_LOOP)
125                                         printk("system stability may be impaired when more than 32 MB are used.\n");
126                                 else
127                                         printk("probably OK (after B9730xxxx).\n");
128                                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
129                         }
130
131                         /* K6 with old style WHCR */
132                         if (c->x86_model < 8 ||
133                            (c->x86_model == 8 && c->x86_mask < 8)) {
134                                 /* We can only write allocate on the low 508Mb */
135                                 if (mbytes > 508)
136                                         mbytes = 508;
137
138                                 rdmsr(MSR_K6_WHCR, l, h);
139                                 if ((l&0x0000FFFF) == 0) {
140                                         unsigned long flags;
141                                         l = (1<<0)|((mbytes/4)<<1);
142                                         local_irq_save(flags);
143                                         wbinvd();
144                                         wrmsr(MSR_K6_WHCR, l, h);
145                                         local_irq_restore(flags);
146                                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
147                                                 mbytes);
148                                 }
149                                 break;
150                         }
151
152                         if ((c->x86_model == 8 && c->x86_mask > 7) ||
153                              c->x86_model == 9 || c->x86_model == 13) {
154                                 /* The more serious chips .. */
155
156                                 if (mbytes > 4092)
157                                         mbytes = 4092;
158
159                                 rdmsr(MSR_K6_WHCR, l, h);
160                                 if ((l&0xFFFF0000) == 0) {
161                                         unsigned long flags;
162                                         l = ((mbytes>>2)<<22)|(1<<16);
163                                         local_irq_save(flags);
164                                         wbinvd();
165                                         wrmsr(MSR_K6_WHCR, l, h);
166                                         local_irq_restore(flags);
167                                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
168                                                 mbytes);
169                                 }
170
171                                 /*  Set MTRR capability flag if appropriate */
172                                 if (c->x86_model == 13 || c->x86_model == 9 ||
173                                    (c->x86_model == 8 && c->x86_mask >= 8))
174                                         set_cpu_cap(c, X86_FEATURE_K6_MTRR);
175                                 break;
176                         }
177
178                         if (c->x86_model == 10) {
179                                 /* AMD Geode LX is model 10 */
180                                 /* placeholder for any needed mods */
181                                 break;
182                         }
183                         break;
184         case 6: /* An Athlon/Duron */
185
186                         /*
187                          * Bit 15 of Athlon specific MSR 15, needs to be 0
188                          * to enable SSE on Palomino/Morgan/Barton CPU's.
189                          * If the BIOS didn't enable it already, enable it here.
190                          */
191                         if (c->x86_model >= 6 && c->x86_model <= 10) {
192                                 if (!cpu_has(c, X86_FEATURE_XMM)) {
193                                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
194                                         rdmsr(MSR_K7_HWCR, l, h);
195                                         l &= ~0x00008000;
196                                         wrmsr(MSR_K7_HWCR, l, h);
197                                         set_cpu_cap(c, X86_FEATURE_XMM);
198                                 }
199                         }
200
201                         /*
202                          * It's been determined by AMD that Athlons since model 8 stepping 1
203                          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
204                          * As per AMD technical note 27212 0.2
205                          */
206                         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
207                                 rdmsr(MSR_K7_CLK_CTL, l, h);
208                                 if ((l & 0xfff00000) != 0x20000000) {
209                                         printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
210                                                 ((l & 0x000fffff)|0x20000000));
211                                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
212                                 }
213                         }
214                         break;
215         }
216
217         switch (c->x86) {
218         case 15:
219         /* Use K8 tuning for Fam10h and Fam11h */
220         case 0x10:
221         case 0x11:
222                 set_cpu_cap(c, X86_FEATURE_K8);
223                 break;
224         case 6:
225                 set_cpu_cap(c, X86_FEATURE_K7);
226                 break;
227         }
228         if (c->x86 >= 6)
229                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
230
231         display_cacheinfo(c);
232
233         if (cpuid_eax(0x80000000) >= 0x80000008)
234                 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1;
235
236 #ifdef CONFIG_X86_HT
237         /*
238          * On a AMD multi core setup the lower bits of the APIC id
239          * distinguish the cores.
240          */
241         if (c->x86_max_cores > 1) {
242                 int cpu = smp_processor_id();
243                 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf;
244
245                 if (bits == 0) {
246                         while ((1 << bits) < c->x86_max_cores)
247                                 bits++;
248                 }
249                 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1);
250                 c->phys_proc_id >>= bits;
251                 printk(KERN_INFO "CPU %d(%d) -> Core %d\n",
252                        cpu, c->x86_max_cores, c->cpu_core_id);
253         }
254 #endif
255
256         if (cpuid_eax(0x80000000) >= 0x80000006) {
257                 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000))
258                         num_cache_leaves = 4;
259                 else
260                         num_cache_leaves = 3;
261         }
262
263         /* K6s reports MCEs but don't actually have all the MSRs */
264         if (c->x86 < 6)
265                 clear_cpu_cap(c, X86_FEATURE_MCE);
266
267         if (cpu_has_xmm2)
268                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
269
270         if (c->x86 == 0x10)
271                 amd_enable_pci_ext_cfg(c);
272 }
273
274 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
275 {
276         /* AMD errata T13 (order #21922) */
277         if ((c->x86 == 6)) {
278                 if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
279                         size = 64;
280                 if (c->x86_model == 4 &&
281                     (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
282                         size = 256;
283         }
284         return size;
285 }
286
287 static struct cpu_dev amd_cpu_dev __cpuinitdata = {
288         .c_vendor       = "AMD",
289         .c_ident        = { "AuthenticAMD" },
290         .c_models = {
291                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
292                   {
293                           [3] = "486 DX/2",
294                           [7] = "486 DX/2-WB",
295                           [8] = "486 DX/4",
296                           [9] = "486 DX/4-WB",
297                           [14] = "Am5x86-WT",
298                           [15] = "Am5x86-WB"
299                   }
300                 },
301         },
302         .c_early_init   = early_init_amd,
303         .c_init         = init_amd,
304         .c_size_cache   = amd_size_cache,
305 };
306
307 cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev);