9fbf0f7ec7ebec9ad0f1db9b6fd185dccfa6455a
[linux-2.6.git] / arch / x86 / kernel / apic / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h>      /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/uv/uv_hub.h>
63 #include <asm/uv/uv_irq.h>
64
65 #include <asm/apic.h>
66
67 #define __apicdebuginit(type) static type __init
68
69 /*
70  *      Is the SiS APIC rmw bug present ?
71  *      -1 = don't know, 0 = no, 1 = yes
72  */
73 int sis_apic_bug = -1;
74
75 static DEFINE_SPINLOCK(ioapic_lock);
76 static DEFINE_SPINLOCK(vector_lock);
77
78 /*
79  * # of IRQ routing registers
80  */
81 int nr_ioapic_registers[MAX_IO_APICS];
82
83 /* I/O APIC entries */
84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
85 int nr_ioapics;
86
87 /* MP IRQ source entries */
88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
89
90 /* # of MP IRQ source entries */
91 int mp_irq_entries;
92
93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
94 int mp_bus_id_to_type[MAX_MP_BUSSES];
95 #endif
96
97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
98
99 int skip_ioapic_setup;
100
101 void arch_disable_smp_support(void)
102 {
103 #ifdef CONFIG_PCI
104         noioapicquirk = 1;
105         noioapicreroute = -1;
106 #endif
107         skip_ioapic_setup = 1;
108 }
109
110 static int __init parse_noapic(char *str)
111 {
112         /* disable IO-APIC */
113         arch_disable_smp_support();
114         return 0;
115 }
116 early_param("noapic", parse_noapic);
117
118 struct irq_pin_list;
119
120 /*
121  * This is performance-critical, we want to do it O(1)
122  *
123  * the indexing order of this array favors 1:1 mappings
124  * between pins and IRQs.
125  */
126
127 struct irq_pin_list {
128         int apic, pin;
129         struct irq_pin_list *next;
130 };
131
132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
133 {
134         struct irq_pin_list *pin;
135         int node;
136
137         node = cpu_to_node(cpu);
138
139         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
140
141         return pin;
142 }
143
144 struct irq_cfg {
145         struct irq_pin_list *irq_2_pin;
146         cpumask_var_t domain;
147         cpumask_var_t old_domain;
148         unsigned move_cleanup_count;
149         u8 vector;
150         u8 move_in_progress : 1;
151 };
152
153 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
154 #ifdef CONFIG_SPARSE_IRQ
155 static struct irq_cfg irq_cfgx[] = {
156 #else
157 static struct irq_cfg irq_cfgx[NR_IRQS] = {
158 #endif
159         [0]  = { .vector = IRQ0_VECTOR,  },
160         [1]  = { .vector = IRQ1_VECTOR,  },
161         [2]  = { .vector = IRQ2_VECTOR,  },
162         [3]  = { .vector = IRQ3_VECTOR,  },
163         [4]  = { .vector = IRQ4_VECTOR,  },
164         [5]  = { .vector = IRQ5_VECTOR,  },
165         [6]  = { .vector = IRQ6_VECTOR,  },
166         [7]  = { .vector = IRQ7_VECTOR,  },
167         [8]  = { .vector = IRQ8_VECTOR,  },
168         [9]  = { .vector = IRQ9_VECTOR,  },
169         [10] = { .vector = IRQ10_VECTOR, },
170         [11] = { .vector = IRQ11_VECTOR, },
171         [12] = { .vector = IRQ12_VECTOR, },
172         [13] = { .vector = IRQ13_VECTOR, },
173         [14] = { .vector = IRQ14_VECTOR, },
174         [15] = { .vector = IRQ15_VECTOR, },
175 };
176
177 int __init arch_early_irq_init(void)
178 {
179         struct irq_cfg *cfg;
180         struct irq_desc *desc;
181         int count;
182         int i;
183
184         cfg = irq_cfgx;
185         count = ARRAY_SIZE(irq_cfgx);
186
187         for (i = 0; i < count; i++) {
188                 desc = irq_to_desc(i);
189                 desc->chip_data = &cfg[i];
190                 alloc_bootmem_cpumask_var(&cfg[i].domain);
191                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
192                 if (i < NR_IRQS_LEGACY)
193                         cpumask_setall(cfg[i].domain);
194         }
195
196         return 0;
197 }
198
199 #ifdef CONFIG_SPARSE_IRQ
200 static struct irq_cfg *irq_cfg(unsigned int irq)
201 {
202         struct irq_cfg *cfg = NULL;
203         struct irq_desc *desc;
204
205         desc = irq_to_desc(irq);
206         if (desc)
207                 cfg = desc->chip_data;
208
209         return cfg;
210 }
211
212 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
213 {
214         struct irq_cfg *cfg;
215         int node;
216
217         node = cpu_to_node(cpu);
218
219         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
220         if (cfg) {
221                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
222                         kfree(cfg);
223                         cfg = NULL;
224                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
225                                                           GFP_ATOMIC, node)) {
226                         free_cpumask_var(cfg->domain);
227                         kfree(cfg);
228                         cfg = NULL;
229                 } else {
230                         cpumask_clear(cfg->domain);
231                         cpumask_clear(cfg->old_domain);
232                 }
233         }
234
235         return cfg;
236 }
237
238 int arch_init_chip_data(struct irq_desc *desc, int cpu)
239 {
240         struct irq_cfg *cfg;
241
242         cfg = desc->chip_data;
243         if (!cfg) {
244                 desc->chip_data = get_one_free_irq_cfg(cpu);
245                 if (!desc->chip_data) {
246                         printk(KERN_ERR "can not alloc irq_cfg\n");
247                         BUG_ON(1);
248                 }
249         }
250
251         return 0;
252 }
253
254 /* for move_irq_desc */
255 static void
256 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
257 {
258         struct irq_pin_list *old_entry, *head, *tail, *entry;
259
260         cfg->irq_2_pin = NULL;
261         old_entry = old_cfg->irq_2_pin;
262         if (!old_entry)
263                 return;
264
265         entry = get_one_free_irq_2_pin(cpu);
266         if (!entry)
267                 return;
268
269         entry->apic     = old_entry->apic;
270         entry->pin      = old_entry->pin;
271         head            = entry;
272         tail            = entry;
273         old_entry       = old_entry->next;
274         while (old_entry) {
275                 entry = get_one_free_irq_2_pin(cpu);
276                 if (!entry) {
277                         entry = head;
278                         while (entry) {
279                                 head = entry->next;
280                                 kfree(entry);
281                                 entry = head;
282                         }
283                         /* still use the old one */
284                         return;
285                 }
286                 entry->apic     = old_entry->apic;
287                 entry->pin      = old_entry->pin;
288                 tail->next      = entry;
289                 tail            = entry;
290                 old_entry       = old_entry->next;
291         }
292
293         tail->next = NULL;
294         cfg->irq_2_pin = head;
295 }
296
297 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
298 {
299         struct irq_pin_list *entry, *next;
300
301         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
302                 return;
303
304         entry = old_cfg->irq_2_pin;
305
306         while (entry) {
307                 next = entry->next;
308                 kfree(entry);
309                 entry = next;
310         }
311         old_cfg->irq_2_pin = NULL;
312 }
313
314 void arch_init_copy_chip_data(struct irq_desc *old_desc,
315                                  struct irq_desc *desc, int cpu)
316 {
317         struct irq_cfg *cfg;
318         struct irq_cfg *old_cfg;
319
320         cfg = get_one_free_irq_cfg(cpu);
321
322         if (!cfg)
323                 return;
324
325         desc->chip_data = cfg;
326
327         old_cfg = old_desc->chip_data;
328
329         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
330
331         init_copy_irq_2_pin(old_cfg, cfg, cpu);
332 }
333
334 static void free_irq_cfg(struct irq_cfg *old_cfg)
335 {
336         kfree(old_cfg);
337 }
338
339 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
340 {
341         struct irq_cfg *old_cfg, *cfg;
342
343         old_cfg = old_desc->chip_data;
344         cfg = desc->chip_data;
345
346         if (old_cfg == cfg)
347                 return;
348
349         if (old_cfg) {
350                 free_irq_2_pin(old_cfg, cfg);
351                 free_irq_cfg(old_cfg);
352                 old_desc->chip_data = NULL;
353         }
354 }
355 /* end for move_irq_desc */
356
357 #else
358 static struct irq_cfg *irq_cfg(unsigned int irq)
359 {
360         return irq < nr_irqs ? irq_cfgx + irq : NULL;
361 }
362
363 #endif
364
365 struct io_apic {
366         unsigned int index;
367         unsigned int unused[3];
368         unsigned int data;
369         unsigned int unused2[11];
370         unsigned int eoi;
371 };
372
373 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
374 {
375         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
376                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
377 }
378
379 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
380 {
381         struct io_apic __iomem *io_apic = io_apic_base(apic);
382         writel(vector, &io_apic->eoi);
383 }
384
385 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
386 {
387         struct io_apic __iomem *io_apic = io_apic_base(apic);
388         writel(reg, &io_apic->index);
389         return readl(&io_apic->data);
390 }
391
392 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
393 {
394         struct io_apic __iomem *io_apic = io_apic_base(apic);
395         writel(reg, &io_apic->index);
396         writel(value, &io_apic->data);
397 }
398
399 /*
400  * Re-write a value: to be used for read-modify-write
401  * cycles where the read already set up the index register.
402  *
403  * Older SiS APIC requires we rewrite the index register
404  */
405 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
406 {
407         struct io_apic __iomem *io_apic = io_apic_base(apic);
408
409         if (sis_apic_bug)
410                 writel(reg, &io_apic->index);
411         writel(value, &io_apic->data);
412 }
413
414 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
415 {
416         struct irq_pin_list *entry;
417         unsigned long flags;
418
419         spin_lock_irqsave(&ioapic_lock, flags);
420         entry = cfg->irq_2_pin;
421         for (;;) {
422                 unsigned int reg;
423                 int pin;
424
425                 if (!entry)
426                         break;
427                 pin = entry->pin;
428                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
429                 /* Is the remote IRR bit set? */
430                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
431                         spin_unlock_irqrestore(&ioapic_lock, flags);
432                         return true;
433                 }
434                 if (!entry->next)
435                         break;
436                 entry = entry->next;
437         }
438         spin_unlock_irqrestore(&ioapic_lock, flags);
439
440         return false;
441 }
442
443 union entry_union {
444         struct { u32 w1, w2; };
445         struct IO_APIC_route_entry entry;
446 };
447
448 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
449 {
450         union entry_union eu;
451         unsigned long flags;
452         spin_lock_irqsave(&ioapic_lock, flags);
453         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
454         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
455         spin_unlock_irqrestore(&ioapic_lock, flags);
456         return eu.entry;
457 }
458
459 /*
460  * When we write a new IO APIC routing entry, we need to write the high
461  * word first! If the mask bit in the low word is clear, we will enable
462  * the interrupt, and we need to make sure the entry is fully populated
463  * before that happens.
464  */
465 static void
466 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
467 {
468         union entry_union eu;
469         eu.entry = e;
470         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
471         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
472 }
473
474 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
475 {
476         unsigned long flags;
477         spin_lock_irqsave(&ioapic_lock, flags);
478         __ioapic_write_entry(apic, pin, e);
479         spin_unlock_irqrestore(&ioapic_lock, flags);
480 }
481
482 /*
483  * When we mask an IO APIC routing entry, we need to write the low
484  * word first, in order to set the mask bit before we change the
485  * high bits!
486  */
487 static void ioapic_mask_entry(int apic, int pin)
488 {
489         unsigned long flags;
490         union entry_union eu = { .entry.mask = 1 };
491
492         spin_lock_irqsave(&ioapic_lock, flags);
493         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
494         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
495         spin_unlock_irqrestore(&ioapic_lock, flags);
496 }
497
498 #ifdef CONFIG_SMP
499 static void send_cleanup_vector(struct irq_cfg *cfg)
500 {
501         cpumask_var_t cleanup_mask;
502
503         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
504                 unsigned int i;
505                 cfg->move_cleanup_count = 0;
506                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
507                         cfg->move_cleanup_count++;
508                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
509                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
510         } else {
511                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
512                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
513                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
514                 free_cpumask_var(cleanup_mask);
515         }
516         cfg->move_in_progress = 0;
517 }
518
519 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
520 {
521         int apic, pin;
522         struct irq_pin_list *entry;
523         u8 vector = cfg->vector;
524
525         entry = cfg->irq_2_pin;
526         for (;;) {
527                 unsigned int reg;
528
529                 if (!entry)
530                         break;
531
532                 apic = entry->apic;
533                 pin = entry->pin;
534                 /*
535                  * With interrupt-remapping, destination information comes
536                  * from interrupt-remapping table entry.
537                  */
538                 if (!irq_remapped(irq))
539                         io_apic_write(apic, 0x11 + pin*2, dest);
540                 reg = io_apic_read(apic, 0x10 + pin*2);
541                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
542                 reg |= vector;
543                 io_apic_modify(apic, 0x10 + pin*2, reg);
544                 if (!entry->next)
545                         break;
546                 entry = entry->next;
547         }
548 }
549
550 static int
551 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
552
553 /*
554  * Either sets desc->affinity to a valid value, and returns
555  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
556  * leaves desc->affinity untouched.
557  */
558 static unsigned int
559 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
560 {
561         struct irq_cfg *cfg;
562         unsigned int irq;
563
564         if (!cpumask_intersects(mask, cpu_online_mask))
565                 return BAD_APICID;
566
567         irq = desc->irq;
568         cfg = desc->chip_data;
569         if (assign_irq_vector(irq, cfg, mask))
570                 return BAD_APICID;
571
572         cpumask_copy(desc->affinity, mask);
573
574         return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
575 }
576
577 static void
578 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
579 {
580         struct irq_cfg *cfg;
581         unsigned long flags;
582         unsigned int dest;
583         unsigned int irq;
584
585         irq = desc->irq;
586         cfg = desc->chip_data;
587
588         spin_lock_irqsave(&ioapic_lock, flags);
589         dest = set_desc_affinity(desc, mask);
590         if (dest != BAD_APICID) {
591                 /* Only the high 8 bits are valid. */
592                 dest = SET_APIC_LOGICAL_ID(dest);
593                 __target_IO_APIC_irq(irq, dest, cfg);
594         }
595         spin_unlock_irqrestore(&ioapic_lock, flags);
596 }
597
598 static void
599 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
600 {
601         struct irq_desc *desc;
602
603         desc = irq_to_desc(irq);
604
605         set_ioapic_affinity_irq_desc(desc, mask);
606 }
607 #endif /* CONFIG_SMP */
608
609 /*
610  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
611  * shared ISA-space IRQs, so we have to support them. We are super
612  * fast in the common case, and fast for shared ISA-space IRQs.
613  */
614 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
615 {
616         struct irq_pin_list *entry;
617
618         entry = cfg->irq_2_pin;
619         if (!entry) {
620                 entry = get_one_free_irq_2_pin(cpu);
621                 if (!entry) {
622                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
623                                         apic, pin);
624                         return;
625                 }
626                 cfg->irq_2_pin = entry;
627                 entry->apic = apic;
628                 entry->pin = pin;
629                 return;
630         }
631
632         while (entry->next) {
633                 /* not again, please */
634                 if (entry->apic == apic && entry->pin == pin)
635                         return;
636
637                 entry = entry->next;
638         }
639
640         entry->next = get_one_free_irq_2_pin(cpu);
641         entry = entry->next;
642         entry->apic = apic;
643         entry->pin = pin;
644 }
645
646 /*
647  * Reroute an IRQ to a different pin.
648  */
649 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
650                                       int oldapic, int oldpin,
651                                       int newapic, int newpin)
652 {
653         struct irq_pin_list *entry = cfg->irq_2_pin;
654         int replaced = 0;
655
656         while (entry) {
657                 if (entry->apic == oldapic && entry->pin == oldpin) {
658                         entry->apic = newapic;
659                         entry->pin = newpin;
660                         replaced = 1;
661                         /* every one is different, right? */
662                         break;
663                 }
664                 entry = entry->next;
665         }
666
667         /* why? call replace before add? */
668         if (!replaced)
669                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
670 }
671
672 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
673                                 int mask_and, int mask_or,
674                                 void (*final)(struct irq_pin_list *entry))
675 {
676         int pin;
677         struct irq_pin_list *entry;
678
679         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
680                 unsigned int reg;
681                 pin = entry->pin;
682                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
683                 reg &= mask_and;
684                 reg |= mask_or;
685                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
686                 if (final)
687                         final(entry);
688         }
689 }
690
691 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
692 {
693         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
694 }
695
696 #ifdef CONFIG_X86_64
697 static void io_apic_sync(struct irq_pin_list *entry)
698 {
699         /*
700          * Synchronize the IO-APIC and the CPU by doing
701          * a dummy read from the IO-APIC
702          */
703         struct io_apic __iomem *io_apic;
704         io_apic = io_apic_base(entry->apic);
705         readl(&io_apic->data);
706 }
707
708 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
709 {
710         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
711 }
712 #else /* CONFIG_X86_32 */
713 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
714 {
715         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
716 }
717
718 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
719 {
720         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
721                         IO_APIC_REDIR_MASKED, NULL);
722 }
723
724 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
725 {
726         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
727                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
728 }
729 #endif /* CONFIG_X86_32 */
730
731 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
732 {
733         struct irq_cfg *cfg = desc->chip_data;
734         unsigned long flags;
735
736         BUG_ON(!cfg);
737
738         spin_lock_irqsave(&ioapic_lock, flags);
739         __mask_IO_APIC_irq(cfg);
740         spin_unlock_irqrestore(&ioapic_lock, flags);
741 }
742
743 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
744 {
745         struct irq_cfg *cfg = desc->chip_data;
746         unsigned long flags;
747
748         spin_lock_irqsave(&ioapic_lock, flags);
749         __unmask_IO_APIC_irq(cfg);
750         spin_unlock_irqrestore(&ioapic_lock, flags);
751 }
752
753 static void mask_IO_APIC_irq(unsigned int irq)
754 {
755         struct irq_desc *desc = irq_to_desc(irq);
756
757         mask_IO_APIC_irq_desc(desc);
758 }
759 static void unmask_IO_APIC_irq(unsigned int irq)
760 {
761         struct irq_desc *desc = irq_to_desc(irq);
762
763         unmask_IO_APIC_irq_desc(desc);
764 }
765
766 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
767 {
768         struct IO_APIC_route_entry entry;
769
770         /* Check delivery_mode to be sure we're not clearing an SMI pin */
771         entry = ioapic_read_entry(apic, pin);
772         if (entry.delivery_mode == dest_SMI)
773                 return;
774         /*
775          * Disable it in the IO-APIC irq-routing table:
776          */
777         ioapic_mask_entry(apic, pin);
778 }
779
780 static void clear_IO_APIC (void)
781 {
782         int apic, pin;
783
784         for (apic = 0; apic < nr_ioapics; apic++)
785                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
786                         clear_IO_APIC_pin(apic, pin);
787 }
788
789 #ifdef CONFIG_X86_32
790 /*
791  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
792  * specific CPU-side IRQs.
793  */
794
795 #define MAX_PIRQS 8
796 static int pirq_entries[MAX_PIRQS] = {
797         [0 ... MAX_PIRQS - 1] = -1
798 };
799
800 static int __init ioapic_pirq_setup(char *str)
801 {
802         int i, max;
803         int ints[MAX_PIRQS+1];
804
805         get_options(str, ARRAY_SIZE(ints), ints);
806
807         apic_printk(APIC_VERBOSE, KERN_INFO
808                         "PIRQ redirection, working around broken MP-BIOS.\n");
809         max = MAX_PIRQS;
810         if (ints[0] < MAX_PIRQS)
811                 max = ints[0];
812
813         for (i = 0; i < max; i++) {
814                 apic_printk(APIC_VERBOSE, KERN_DEBUG
815                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
816                 /*
817                  * PIRQs are mapped upside down, usually.
818                  */
819                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
820         }
821         return 1;
822 }
823
824 __setup("pirq=", ioapic_pirq_setup);
825 #endif /* CONFIG_X86_32 */
826
827 #ifdef CONFIG_INTR_REMAP
828 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
829 {
830         int apic;
831         struct IO_APIC_route_entry **ioapic_entries;
832
833         ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
834                                 GFP_ATOMIC);
835         if (!ioapic_entries)
836                 return 0;
837
838         for (apic = 0; apic < nr_ioapics; apic++) {
839                 ioapic_entries[apic] =
840                         kzalloc(sizeof(struct IO_APIC_route_entry) *
841                                 nr_ioapic_registers[apic], GFP_ATOMIC);
842                 if (!ioapic_entries[apic])
843                         goto nomem;
844         }
845
846         return ioapic_entries;
847
848 nomem:
849         while (--apic >= 0)
850                 kfree(ioapic_entries[apic]);
851         kfree(ioapic_entries);
852
853         return 0;
854 }
855
856 /*
857  * Saves all the IO-APIC RTE's
858  */
859 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
860 {
861         int apic, pin;
862
863         if (!ioapic_entries)
864                 return -ENOMEM;
865
866         for (apic = 0; apic < nr_ioapics; apic++) {
867                 if (!ioapic_entries[apic])
868                         return -ENOMEM;
869
870                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
871                         ioapic_entries[apic][pin] =
872                                 ioapic_read_entry(apic, pin);
873         }
874
875         return 0;
876 }
877
878 /*
879  * Mask all IO APIC entries.
880  */
881 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
882 {
883         int apic, pin;
884
885         if (!ioapic_entries)
886                 return;
887
888         for (apic = 0; apic < nr_ioapics; apic++) {
889                 if (!ioapic_entries[apic])
890                         break;
891
892                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
893                         struct IO_APIC_route_entry entry;
894
895                         entry = ioapic_entries[apic][pin];
896                         if (!entry.mask) {
897                                 entry.mask = 1;
898                                 ioapic_write_entry(apic, pin, entry);
899                         }
900                 }
901         }
902 }
903
904 /*
905  * Restore IO APIC entries which was saved in ioapic_entries.
906  */
907 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
908 {
909         int apic, pin;
910
911         if (!ioapic_entries)
912                 return -ENOMEM;
913
914         for (apic = 0; apic < nr_ioapics; apic++) {
915                 if (!ioapic_entries[apic])
916                         return -ENOMEM;
917
918                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
919                         ioapic_write_entry(apic, pin,
920                                         ioapic_entries[apic][pin]);
921         }
922         return 0;
923 }
924
925 void reinit_intr_remapped_IO_APIC(int intr_remapping,
926         struct IO_APIC_route_entry **ioapic_entries)
927
928 {
929         /*
930          * for now plain restore of previous settings.
931          * TBD: In the case of OS enabling interrupt-remapping,
932          * IO-APIC RTE's need to be setup to point to interrupt-remapping
933          * table entries. for now, do a plain restore, and wait for
934          * the setup_IO_APIC_irqs() to do proper initialization.
935          */
936         restore_IO_APIC_setup(ioapic_entries);
937 }
938
939 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
940 {
941         int apic;
942
943         for (apic = 0; apic < nr_ioapics; apic++)
944                 kfree(ioapic_entries[apic]);
945
946         kfree(ioapic_entries);
947 }
948 #endif
949
950 /*
951  * Find the IRQ entry number of a certain pin.
952  */
953 static int find_irq_entry(int apic, int pin, int type)
954 {
955         int i;
956
957         for (i = 0; i < mp_irq_entries; i++)
958                 if (mp_irqs[i].irqtype == type &&
959                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
960                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
961                     mp_irqs[i].dstirq == pin)
962                         return i;
963
964         return -1;
965 }
966
967 /*
968  * Find the pin to which IRQ[irq] (ISA) is connected
969  */
970 static int __init find_isa_irq_pin(int irq, int type)
971 {
972         int i;
973
974         for (i = 0; i < mp_irq_entries; i++) {
975                 int lbus = mp_irqs[i].srcbus;
976
977                 if (test_bit(lbus, mp_bus_not_pci) &&
978                     (mp_irqs[i].irqtype == type) &&
979                     (mp_irqs[i].srcbusirq == irq))
980
981                         return mp_irqs[i].dstirq;
982         }
983         return -1;
984 }
985
986 static int __init find_isa_irq_apic(int irq, int type)
987 {
988         int i;
989
990         for (i = 0; i < mp_irq_entries; i++) {
991                 int lbus = mp_irqs[i].srcbus;
992
993                 if (test_bit(lbus, mp_bus_not_pci) &&
994                     (mp_irqs[i].irqtype == type) &&
995                     (mp_irqs[i].srcbusirq == irq))
996                         break;
997         }
998         if (i < mp_irq_entries) {
999                 int apic;
1000                 for(apic = 0; apic < nr_ioapics; apic++) {
1001                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
1002                                 return apic;
1003                 }
1004         }
1005
1006         return -1;
1007 }
1008
1009 /*
1010  * Find a specific PCI IRQ entry.
1011  * Not an __init, possibly needed by modules
1012  */
1013 static int pin_2_irq(int idx, int apic, int pin);
1014
1015 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1016 {
1017         int apic, i, best_guess = -1;
1018
1019         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1020                 bus, slot, pin);
1021         if (test_bit(bus, mp_bus_not_pci)) {
1022                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1023                 return -1;
1024         }
1025         for (i = 0; i < mp_irq_entries; i++) {
1026                 int lbus = mp_irqs[i].srcbus;
1027
1028                 for (apic = 0; apic < nr_ioapics; apic++)
1029                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1030                             mp_irqs[i].dstapic == MP_APIC_ALL)
1031                                 break;
1032
1033                 if (!test_bit(lbus, mp_bus_not_pci) &&
1034                     !mp_irqs[i].irqtype &&
1035                     (bus == lbus) &&
1036                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1037                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1038
1039                         if (!(apic || IO_APIC_IRQ(irq)))
1040                                 continue;
1041
1042                         if (pin == (mp_irqs[i].srcbusirq & 3))
1043                                 return irq;
1044                         /*
1045                          * Use the first all-but-pin matching entry as a
1046                          * best-guess fuzzy result for broken mptables.
1047                          */
1048                         if (best_guess < 0)
1049                                 best_guess = irq;
1050                 }
1051         }
1052         return best_guess;
1053 }
1054
1055 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1056
1057 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1058 /*
1059  * EISA Edge/Level control register, ELCR
1060  */
1061 static int EISA_ELCR(unsigned int irq)
1062 {
1063         if (irq < NR_IRQS_LEGACY) {
1064                 unsigned int port = 0x4d0 + (irq >> 3);
1065                 return (inb(port) >> (irq & 7)) & 1;
1066         }
1067         apic_printk(APIC_VERBOSE, KERN_INFO
1068                         "Broken MPtable reports ISA irq %d\n", irq);
1069         return 0;
1070 }
1071
1072 #endif
1073
1074 /* ISA interrupts are always polarity zero edge triggered,
1075  * when listed as conforming in the MP table. */
1076
1077 #define default_ISA_trigger(idx)        (0)
1078 #define default_ISA_polarity(idx)       (0)
1079
1080 /* EISA interrupts are always polarity zero and can be edge or level
1081  * trigger depending on the ELCR value.  If an interrupt is listed as
1082  * EISA conforming in the MP table, that means its trigger type must
1083  * be read in from the ELCR */
1084
1085 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1086 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1087
1088 /* PCI interrupts are always polarity one level triggered,
1089  * when listed as conforming in the MP table. */
1090
1091 #define default_PCI_trigger(idx)        (1)
1092 #define default_PCI_polarity(idx)       (1)
1093
1094 /* MCA interrupts are always polarity zero level triggered,
1095  * when listed as conforming in the MP table. */
1096
1097 #define default_MCA_trigger(idx)        (1)
1098 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1099
1100 static int MPBIOS_polarity(int idx)
1101 {
1102         int bus = mp_irqs[idx].srcbus;
1103         int polarity;
1104
1105         /*
1106          * Determine IRQ line polarity (high active or low active):
1107          */
1108         switch (mp_irqs[idx].irqflag & 3)
1109         {
1110                 case 0: /* conforms, ie. bus-type dependent polarity */
1111                         if (test_bit(bus, mp_bus_not_pci))
1112                                 polarity = default_ISA_polarity(idx);
1113                         else
1114                                 polarity = default_PCI_polarity(idx);
1115                         break;
1116                 case 1: /* high active */
1117                 {
1118                         polarity = 0;
1119                         break;
1120                 }
1121                 case 2: /* reserved */
1122                 {
1123                         printk(KERN_WARNING "broken BIOS!!\n");
1124                         polarity = 1;
1125                         break;
1126                 }
1127                 case 3: /* low active */
1128                 {
1129                         polarity = 1;
1130                         break;
1131                 }
1132                 default: /* invalid */
1133                 {
1134                         printk(KERN_WARNING "broken BIOS!!\n");
1135                         polarity = 1;
1136                         break;
1137                 }
1138         }
1139         return polarity;
1140 }
1141
1142 static int MPBIOS_trigger(int idx)
1143 {
1144         int bus = mp_irqs[idx].srcbus;
1145         int trigger;
1146
1147         /*
1148          * Determine IRQ trigger mode (edge or level sensitive):
1149          */
1150         switch ((mp_irqs[idx].irqflag>>2) & 3)
1151         {
1152                 case 0: /* conforms, ie. bus-type dependent */
1153                         if (test_bit(bus, mp_bus_not_pci))
1154                                 trigger = default_ISA_trigger(idx);
1155                         else
1156                                 trigger = default_PCI_trigger(idx);
1157 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1158                         switch (mp_bus_id_to_type[bus]) {
1159                                 case MP_BUS_ISA: /* ISA pin */
1160                                 {
1161                                         /* set before the switch */
1162                                         break;
1163                                 }
1164                                 case MP_BUS_EISA: /* EISA pin */
1165                                 {
1166                                         trigger = default_EISA_trigger(idx);
1167                                         break;
1168                                 }
1169                                 case MP_BUS_PCI: /* PCI pin */
1170                                 {
1171                                         /* set before the switch */
1172                                         break;
1173                                 }
1174                                 case MP_BUS_MCA: /* MCA pin */
1175                                 {
1176                                         trigger = default_MCA_trigger(idx);
1177                                         break;
1178                                 }
1179                                 default:
1180                                 {
1181                                         printk(KERN_WARNING "broken BIOS!!\n");
1182                                         trigger = 1;
1183                                         break;
1184                                 }
1185                         }
1186 #endif
1187                         break;
1188                 case 1: /* edge */
1189                 {
1190                         trigger = 0;
1191                         break;
1192                 }
1193                 case 2: /* reserved */
1194                 {
1195                         printk(KERN_WARNING "broken BIOS!!\n");
1196                         trigger = 1;
1197                         break;
1198                 }
1199                 case 3: /* level */
1200                 {
1201                         trigger = 1;
1202                         break;
1203                 }
1204                 default: /* invalid */
1205                 {
1206                         printk(KERN_WARNING "broken BIOS!!\n");
1207                         trigger = 0;
1208                         break;
1209                 }
1210         }
1211         return trigger;
1212 }
1213
1214 static inline int irq_polarity(int idx)
1215 {
1216         return MPBIOS_polarity(idx);
1217 }
1218
1219 static inline int irq_trigger(int idx)
1220 {
1221         return MPBIOS_trigger(idx);
1222 }
1223
1224 int (*ioapic_renumber_irq)(int ioapic, int irq);
1225 static int pin_2_irq(int idx, int apic, int pin)
1226 {
1227         int irq, i;
1228         int bus = mp_irqs[idx].srcbus;
1229
1230         /*
1231          * Debugging check, we are in big trouble if this message pops up!
1232          */
1233         if (mp_irqs[idx].dstirq != pin)
1234                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1235
1236         if (test_bit(bus, mp_bus_not_pci)) {
1237                 irq = mp_irqs[idx].srcbusirq;
1238         } else {
1239                 /*
1240                  * PCI IRQs are mapped in order
1241                  */
1242                 i = irq = 0;
1243                 while (i < apic)
1244                         irq += nr_ioapic_registers[i++];
1245                 irq += pin;
1246                 /*
1247                  * For MPS mode, so far only needed by ES7000 platform
1248                  */
1249                 if (ioapic_renumber_irq)
1250                         irq = ioapic_renumber_irq(apic, irq);
1251         }
1252
1253 #ifdef CONFIG_X86_32
1254         /*
1255          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1256          */
1257         if ((pin >= 16) && (pin <= 23)) {
1258                 if (pirq_entries[pin-16] != -1) {
1259                         if (!pirq_entries[pin-16]) {
1260                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1261                                                 "disabling PIRQ%d\n", pin-16);
1262                         } else {
1263                                 irq = pirq_entries[pin-16];
1264                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1265                                                 "using PIRQ%d -> IRQ %d\n",
1266                                                 pin-16, irq);
1267                         }
1268                 }
1269         }
1270 #endif
1271
1272         return irq;
1273 }
1274
1275 void lock_vector_lock(void)
1276 {
1277         /* Used to the online set of cpus does not change
1278          * during assign_irq_vector.
1279          */
1280         spin_lock(&vector_lock);
1281 }
1282
1283 void unlock_vector_lock(void)
1284 {
1285         spin_unlock(&vector_lock);
1286 }
1287
1288 static int
1289 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1290 {
1291         /*
1292          * NOTE! The local APIC isn't very good at handling
1293          * multiple interrupts at the same interrupt level.
1294          * As the interrupt level is determined by taking the
1295          * vector number and shifting that right by 4, we
1296          * want to spread these out a bit so that they don't
1297          * all fall in the same interrupt level.
1298          *
1299          * Also, we've got to be careful not to trash gate
1300          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1301          */
1302         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1303         unsigned int old_vector;
1304         int cpu, err;
1305         cpumask_var_t tmp_mask;
1306
1307         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1308                 return -EBUSY;
1309
1310         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1311                 return -ENOMEM;
1312
1313         old_vector = cfg->vector;
1314         if (old_vector) {
1315                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1316                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1317                 if (!cpumask_empty(tmp_mask)) {
1318                         free_cpumask_var(tmp_mask);
1319                         return 0;
1320                 }
1321         }
1322
1323         /* Only try and allocate irqs on cpus that are present */
1324         err = -ENOSPC;
1325         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1326                 int new_cpu;
1327                 int vector, offset;
1328
1329                 apic->vector_allocation_domain(cpu, tmp_mask);
1330
1331                 vector = current_vector;
1332                 offset = current_offset;
1333 next:
1334                 vector += 8;
1335                 if (vector >= first_system_vector) {
1336                         /* If out of vectors on large boxen, must share them. */
1337                         offset = (offset + 1) % 8;
1338                         vector = FIRST_DEVICE_VECTOR + offset;
1339                 }
1340                 if (unlikely(current_vector == vector))
1341                         continue;
1342
1343                 if (test_bit(vector, used_vectors))
1344                         goto next;
1345
1346                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1347                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1348                                 goto next;
1349                 /* Found one! */
1350                 current_vector = vector;
1351                 current_offset = offset;
1352                 if (old_vector) {
1353                         cfg->move_in_progress = 1;
1354                         cpumask_copy(cfg->old_domain, cfg->domain);
1355                 }
1356                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1357                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1358                 cfg->vector = vector;
1359                 cpumask_copy(cfg->domain, tmp_mask);
1360                 err = 0;
1361                 break;
1362         }
1363         free_cpumask_var(tmp_mask);
1364         return err;
1365 }
1366
1367 static int
1368 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1369 {
1370         int err;
1371         unsigned long flags;
1372
1373         spin_lock_irqsave(&vector_lock, flags);
1374         err = __assign_irq_vector(irq, cfg, mask);
1375         spin_unlock_irqrestore(&vector_lock, flags);
1376         return err;
1377 }
1378
1379 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1380 {
1381         int cpu, vector;
1382
1383         BUG_ON(!cfg->vector);
1384
1385         vector = cfg->vector;
1386         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1387                 per_cpu(vector_irq, cpu)[vector] = -1;
1388
1389         cfg->vector = 0;
1390         cpumask_clear(cfg->domain);
1391
1392         if (likely(!cfg->move_in_progress))
1393                 return;
1394         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1395                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1396                                                                 vector++) {
1397                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1398                                 continue;
1399                         per_cpu(vector_irq, cpu)[vector] = -1;
1400                         break;
1401                 }
1402         }
1403         cfg->move_in_progress = 0;
1404 }
1405
1406 void __setup_vector_irq(int cpu)
1407 {
1408         /* Initialize vector_irq on a new cpu */
1409         /* This function must be called with vector_lock held */
1410         int irq, vector;
1411         struct irq_cfg *cfg;
1412         struct irq_desc *desc;
1413
1414         /* Mark the inuse vectors */
1415         for_each_irq_desc(irq, desc) {
1416                 cfg = desc->chip_data;
1417                 if (!cpumask_test_cpu(cpu, cfg->domain))
1418                         continue;
1419                 vector = cfg->vector;
1420                 per_cpu(vector_irq, cpu)[vector] = irq;
1421         }
1422         /* Mark the free vectors */
1423         for (vector = 0; vector < NR_VECTORS; ++vector) {
1424                 irq = per_cpu(vector_irq, cpu)[vector];
1425                 if (irq < 0)
1426                         continue;
1427
1428                 cfg = irq_cfg(irq);
1429                 if (!cpumask_test_cpu(cpu, cfg->domain))
1430                         per_cpu(vector_irq, cpu)[vector] = -1;
1431         }
1432 }
1433
1434 static struct irq_chip ioapic_chip;
1435 static struct irq_chip ir_ioapic_chip;
1436
1437 #define IOAPIC_AUTO     -1
1438 #define IOAPIC_EDGE     0
1439 #define IOAPIC_LEVEL    1
1440
1441 #ifdef CONFIG_X86_32
1442 static inline int IO_APIC_irq_trigger(int irq)
1443 {
1444         int apic, idx, pin;
1445
1446         for (apic = 0; apic < nr_ioapics; apic++) {
1447                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1448                         idx = find_irq_entry(apic, pin, mp_INT);
1449                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1450                                 return irq_trigger(idx);
1451                 }
1452         }
1453         /*
1454          * nonexistent IRQs are edge default
1455          */
1456         return 0;
1457 }
1458 #else
1459 static inline int IO_APIC_irq_trigger(int irq)
1460 {
1461         return 1;
1462 }
1463 #endif
1464
1465 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1466 {
1467
1468         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1469             trigger == IOAPIC_LEVEL)
1470                 desc->status |= IRQ_LEVEL;
1471         else
1472                 desc->status &= ~IRQ_LEVEL;
1473
1474         if (irq_remapped(irq)) {
1475                 desc->status |= IRQ_MOVE_PCNTXT;
1476                 if (trigger)
1477                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1478                                                       handle_fasteoi_irq,
1479                                                      "fasteoi");
1480                 else
1481                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1482                                                       handle_edge_irq, "edge");
1483                 return;
1484         }
1485
1486         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1487             trigger == IOAPIC_LEVEL)
1488                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1489                                               handle_fasteoi_irq,
1490                                               "fasteoi");
1491         else
1492                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1493                                               handle_edge_irq, "edge");
1494 }
1495
1496 int setup_ioapic_entry(int apic_id, int irq,
1497                        struct IO_APIC_route_entry *entry,
1498                        unsigned int destination, int trigger,
1499                        int polarity, int vector, int pin)
1500 {
1501         /*
1502          * add it to the IO-APIC irq-routing table:
1503          */
1504         memset(entry,0,sizeof(*entry));
1505
1506         if (intr_remapping_enabled) {
1507                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1508                 struct irte irte;
1509                 struct IR_IO_APIC_route_entry *ir_entry =
1510                         (struct IR_IO_APIC_route_entry *) entry;
1511                 int index;
1512
1513                 if (!iommu)
1514                         panic("No mapping iommu for ioapic %d\n", apic_id);
1515
1516                 index = alloc_irte(iommu, irq, 1);
1517                 if (index < 0)
1518                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1519
1520                 memset(&irte, 0, sizeof(irte));
1521
1522                 irte.present = 1;
1523                 irte.dst_mode = apic->irq_dest_mode;
1524                 /*
1525                  * Trigger mode in the IRTE will always be edge, and the
1526                  * actual level or edge trigger will be setup in the IO-APIC
1527                  * RTE. This will help simplify level triggered irq migration.
1528                  * For more details, see the comments above explainig IO-APIC
1529                  * irq migration in the presence of interrupt-remapping.
1530                  */
1531                 irte.trigger_mode = 0;
1532                 irte.dlvry_mode = apic->irq_delivery_mode;
1533                 irte.vector = vector;
1534                 irte.dest_id = IRTE_DEST(destination);
1535
1536                 modify_irte(irq, &irte);
1537
1538                 ir_entry->index2 = (index >> 15) & 0x1;
1539                 ir_entry->zero = 0;
1540                 ir_entry->format = 1;
1541                 ir_entry->index = (index & 0x7fff);
1542                 /*
1543                  * IO-APIC RTE will be configured with virtual vector.
1544                  * irq handler will do the explicit EOI to the io-apic.
1545                  */
1546                 ir_entry->vector = pin;
1547         } else {
1548                 entry->delivery_mode = apic->irq_delivery_mode;
1549                 entry->dest_mode = apic->irq_dest_mode;
1550                 entry->dest = destination;
1551                 entry->vector = vector;
1552         }
1553
1554         entry->mask = 0;                                /* enable IRQ */
1555         entry->trigger = trigger;
1556         entry->polarity = polarity;
1557
1558         /* Mask level triggered irqs.
1559          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1560          */
1561         if (trigger)
1562                 entry->mask = 1;
1563         return 0;
1564 }
1565
1566 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1567                               int trigger, int polarity)
1568 {
1569         struct irq_cfg *cfg;
1570         struct IO_APIC_route_entry entry;
1571         unsigned int dest;
1572
1573         if (!IO_APIC_IRQ(irq))
1574                 return;
1575
1576         cfg = desc->chip_data;
1577
1578         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1579                 return;
1580
1581         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1582
1583         apic_printk(APIC_VERBOSE,KERN_DEBUG
1584                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1585                     "IRQ %d Mode:%i Active:%i)\n",
1586                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1587                     irq, trigger, polarity);
1588
1589
1590         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1591                                dest, trigger, polarity, cfg->vector, pin)) {
1592                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1593                        mp_ioapics[apic_id].apicid, pin);
1594                 __clear_irq_vector(irq, cfg);
1595                 return;
1596         }
1597
1598         ioapic_register_intr(irq, desc, trigger);
1599         if (irq < NR_IRQS_LEGACY)
1600                 disable_8259A_irq(irq);
1601
1602         ioapic_write_entry(apic_id, pin, entry);
1603 }
1604
1605 static void __init setup_IO_APIC_irqs(void)
1606 {
1607         int apic_id, pin, idx, irq;
1608         int notcon = 0;
1609         struct irq_desc *desc;
1610         struct irq_cfg *cfg;
1611         int cpu = boot_cpu_id;
1612
1613         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1614
1615         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1616                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1617
1618                         idx = find_irq_entry(apic_id, pin, mp_INT);
1619                         if (idx == -1) {
1620                                 if (!notcon) {
1621                                         notcon = 1;
1622                                         apic_printk(APIC_VERBOSE,
1623                                                 KERN_DEBUG " %d-%d",
1624                                                 mp_ioapics[apic_id].apicid, pin);
1625                                 } else
1626                                         apic_printk(APIC_VERBOSE, " %d-%d",
1627                                                 mp_ioapics[apic_id].apicid, pin);
1628                                 continue;
1629                         }
1630                         if (notcon) {
1631                                 apic_printk(APIC_VERBOSE,
1632                                         " (apicid-pin) not connected\n");
1633                                 notcon = 0;
1634                         }
1635
1636                         irq = pin_2_irq(idx, apic_id, pin);
1637
1638                         /*
1639                          * Skip the timer IRQ if there's a quirk handler
1640                          * installed and if it returns 1:
1641                          */
1642                         if (apic->multi_timer_check &&
1643                                         apic->multi_timer_check(apic_id, irq))
1644                                 continue;
1645
1646                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1647                         if (!desc) {
1648                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1649                                 continue;
1650                         }
1651                         cfg = desc->chip_data;
1652                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1653
1654                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1655                                         irq_trigger(idx), irq_polarity(idx));
1656                 }
1657         }
1658
1659         if (notcon)
1660                 apic_printk(APIC_VERBOSE,
1661                         " (apicid-pin) not connected\n");
1662 }
1663
1664 /*
1665  * Set up the timer pin, possibly with the 8259A-master behind.
1666  */
1667 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1668                                         int vector)
1669 {
1670         struct IO_APIC_route_entry entry;
1671
1672         if (intr_remapping_enabled)
1673                 return;
1674
1675         memset(&entry, 0, sizeof(entry));
1676
1677         /*
1678          * We use logical delivery to get the timer IRQ
1679          * to the first CPU.
1680          */
1681         entry.dest_mode = apic->irq_dest_mode;
1682         entry.mask = 0;                 /* don't mask IRQ for edge */
1683         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1684         entry.delivery_mode = apic->irq_delivery_mode;
1685         entry.polarity = 0;
1686         entry.trigger = 0;
1687         entry.vector = vector;
1688
1689         /*
1690          * The timer IRQ doesn't have to know that behind the
1691          * scene we may have a 8259A-master in AEOI mode ...
1692          */
1693         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1694
1695         /*
1696          * Add it to the IO-APIC irq-routing table:
1697          */
1698         ioapic_write_entry(apic_id, pin, entry);
1699 }
1700
1701
1702 __apicdebuginit(void) print_IO_APIC(void)
1703 {
1704         int apic, i;
1705         union IO_APIC_reg_00 reg_00;
1706         union IO_APIC_reg_01 reg_01;
1707         union IO_APIC_reg_02 reg_02;
1708         union IO_APIC_reg_03 reg_03;
1709         unsigned long flags;
1710         struct irq_cfg *cfg;
1711         struct irq_desc *desc;
1712         unsigned int irq;
1713
1714         if (apic_verbosity == APIC_QUIET)
1715                 return;
1716
1717         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1718         for (i = 0; i < nr_ioapics; i++)
1719                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1720                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1721
1722         /*
1723          * We are a bit conservative about what we expect.  We have to
1724          * know about every hardware change ASAP.
1725          */
1726         printk(KERN_INFO "testing the IO APIC.......................\n");
1727
1728         for (apic = 0; apic < nr_ioapics; apic++) {
1729
1730         spin_lock_irqsave(&ioapic_lock, flags);
1731         reg_00.raw = io_apic_read(apic, 0);
1732         reg_01.raw = io_apic_read(apic, 1);
1733         if (reg_01.bits.version >= 0x10)
1734                 reg_02.raw = io_apic_read(apic, 2);
1735         if (reg_01.bits.version >= 0x20)
1736                 reg_03.raw = io_apic_read(apic, 3);
1737         spin_unlock_irqrestore(&ioapic_lock, flags);
1738
1739         printk("\n");
1740         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1741         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1742         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1743         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1744         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1745
1746         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1747         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1748
1749         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1750         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1751
1752         /*
1753          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1754          * but the value of reg_02 is read as the previous read register
1755          * value, so ignore it if reg_02 == reg_01.
1756          */
1757         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1758                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1759                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1760         }
1761
1762         /*
1763          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1764          * or reg_03, but the value of reg_0[23] is read as the previous read
1765          * register value, so ignore it if reg_03 == reg_0[12].
1766          */
1767         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1768             reg_03.raw != reg_01.raw) {
1769                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1770                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1771         }
1772
1773         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1774
1775         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1776                           " Stat Dmod Deli Vect:   \n");
1777
1778         for (i = 0; i <= reg_01.bits.entries; i++) {
1779                 struct IO_APIC_route_entry entry;
1780
1781                 entry = ioapic_read_entry(apic, i);
1782
1783                 printk(KERN_DEBUG " %02x %03X ",
1784                         i,
1785                         entry.dest
1786                 );
1787
1788                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1789                         entry.mask,
1790                         entry.trigger,
1791                         entry.irr,
1792                         entry.polarity,
1793                         entry.delivery_status,
1794                         entry.dest_mode,
1795                         entry.delivery_mode,
1796                         entry.vector
1797                 );
1798         }
1799         }
1800         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1801         for_each_irq_desc(irq, desc) {
1802                 struct irq_pin_list *entry;
1803
1804                 cfg = desc->chip_data;
1805                 entry = cfg->irq_2_pin;
1806                 if (!entry)
1807                         continue;
1808                 printk(KERN_DEBUG "IRQ%d ", irq);
1809                 for (;;) {
1810                         printk("-> %d:%d", entry->apic, entry->pin);
1811                         if (!entry->next)
1812                                 break;
1813                         entry = entry->next;
1814                 }
1815                 printk("\n");
1816         }
1817
1818         printk(KERN_INFO ".................................... done.\n");
1819
1820         return;
1821 }
1822
1823 __apicdebuginit(void) print_APIC_bitfield(int base)
1824 {
1825         unsigned int v;
1826         int i, j;
1827
1828         if (apic_verbosity == APIC_QUIET)
1829                 return;
1830
1831         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1832         for (i = 0; i < 8; i++) {
1833                 v = apic_read(base + i*0x10);
1834                 for (j = 0; j < 32; j++) {
1835                         if (v & (1<<j))
1836                                 printk("1");
1837                         else
1838                                 printk("0");
1839                 }
1840                 printk("\n");
1841         }
1842 }
1843
1844 __apicdebuginit(void) print_local_APIC(void *dummy)
1845 {
1846         unsigned int v, ver, maxlvt;
1847         u64 icr;
1848
1849         if (apic_verbosity == APIC_QUIET)
1850                 return;
1851
1852         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1853                 smp_processor_id(), hard_smp_processor_id());
1854         v = apic_read(APIC_ID);
1855         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1856         v = apic_read(APIC_LVR);
1857         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1858         ver = GET_APIC_VERSION(v);
1859         maxlvt = lapic_get_maxlvt();
1860
1861         v = apic_read(APIC_TASKPRI);
1862         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1863
1864         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1865                 if (!APIC_XAPIC(ver)) {
1866                         v = apic_read(APIC_ARBPRI);
1867                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1868                                v & APIC_ARBPRI_MASK);
1869                 }
1870                 v = apic_read(APIC_PROCPRI);
1871                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1872         }
1873
1874         /*
1875          * Remote read supported only in the 82489DX and local APIC for
1876          * Pentium processors.
1877          */
1878         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1879                 v = apic_read(APIC_RRR);
1880                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1881         }
1882
1883         v = apic_read(APIC_LDR);
1884         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1885         if (!x2apic_enabled()) {
1886                 v = apic_read(APIC_DFR);
1887                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1888         }
1889         v = apic_read(APIC_SPIV);
1890         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1891
1892         printk(KERN_DEBUG "... APIC ISR field:\n");
1893         print_APIC_bitfield(APIC_ISR);
1894         printk(KERN_DEBUG "... APIC TMR field:\n");
1895         print_APIC_bitfield(APIC_TMR);
1896         printk(KERN_DEBUG "... APIC IRR field:\n");
1897         print_APIC_bitfield(APIC_IRR);
1898
1899         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1900                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1901                         apic_write(APIC_ESR, 0);
1902
1903                 v = apic_read(APIC_ESR);
1904                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1905         }
1906
1907         icr = apic_icr_read();
1908         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1909         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1910
1911         v = apic_read(APIC_LVTT);
1912         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1913
1914         if (maxlvt > 3) {                       /* PC is LVT#4. */
1915                 v = apic_read(APIC_LVTPC);
1916                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1917         }
1918         v = apic_read(APIC_LVT0);
1919         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1920         v = apic_read(APIC_LVT1);
1921         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1922
1923         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1924                 v = apic_read(APIC_LVTERR);
1925                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1926         }
1927
1928         v = apic_read(APIC_TMICT);
1929         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1930         v = apic_read(APIC_TMCCT);
1931         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1932         v = apic_read(APIC_TDCR);
1933         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1934         printk("\n");
1935 }
1936
1937 __apicdebuginit(void) print_all_local_APICs(void)
1938 {
1939         int cpu;
1940
1941         preempt_disable();
1942         for_each_online_cpu(cpu)
1943                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1944         preempt_enable();
1945 }
1946
1947 __apicdebuginit(void) print_PIC(void)
1948 {
1949         unsigned int v;
1950         unsigned long flags;
1951
1952         if (apic_verbosity == APIC_QUIET)
1953                 return;
1954
1955         printk(KERN_DEBUG "\nprinting PIC contents\n");
1956
1957         spin_lock_irqsave(&i8259A_lock, flags);
1958
1959         v = inb(0xa1) << 8 | inb(0x21);
1960         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1961
1962         v = inb(0xa0) << 8 | inb(0x20);
1963         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1964
1965         outb(0x0b,0xa0);
1966         outb(0x0b,0x20);
1967         v = inb(0xa0) << 8 | inb(0x20);
1968         outb(0x0a,0xa0);
1969         outb(0x0a,0x20);
1970
1971         spin_unlock_irqrestore(&i8259A_lock, flags);
1972
1973         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1974
1975         v = inb(0x4d1) << 8 | inb(0x4d0);
1976         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1977 }
1978
1979 __apicdebuginit(int) print_all_ICs(void)
1980 {
1981         print_PIC();
1982         print_all_local_APICs();
1983         print_IO_APIC();
1984
1985         return 0;
1986 }
1987
1988 fs_initcall(print_all_ICs);
1989
1990
1991 /* Where if anywhere is the i8259 connect in external int mode */
1992 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1993
1994 void __init enable_IO_APIC(void)
1995 {
1996         union IO_APIC_reg_01 reg_01;
1997         int i8259_apic, i8259_pin;
1998         int apic;
1999         unsigned long flags;
2000
2001         /*
2002          * The number of IO-APIC IRQ registers (== #pins):
2003          */
2004         for (apic = 0; apic < nr_ioapics; apic++) {
2005                 spin_lock_irqsave(&ioapic_lock, flags);
2006                 reg_01.raw = io_apic_read(apic, 1);
2007                 spin_unlock_irqrestore(&ioapic_lock, flags);
2008                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2009         }
2010         for(apic = 0; apic < nr_ioapics; apic++) {
2011                 int pin;
2012                 /* See if any of the pins is in ExtINT mode */
2013                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2014                         struct IO_APIC_route_entry entry;
2015                         entry = ioapic_read_entry(apic, pin);
2016
2017                         /* If the interrupt line is enabled and in ExtInt mode
2018                          * I have found the pin where the i8259 is connected.
2019                          */
2020                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2021                                 ioapic_i8259.apic = apic;
2022                                 ioapic_i8259.pin  = pin;
2023                                 goto found_i8259;
2024                         }
2025                 }
2026         }
2027  found_i8259:
2028         /* Look to see what if the MP table has reported the ExtINT */
2029         /* If we could not find the appropriate pin by looking at the ioapic
2030          * the i8259 probably is not connected the ioapic but give the
2031          * mptable a chance anyway.
2032          */
2033         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2034         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2035         /* Trust the MP table if nothing is setup in the hardware */
2036         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2037                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2038                 ioapic_i8259.pin  = i8259_pin;
2039                 ioapic_i8259.apic = i8259_apic;
2040         }
2041         /* Complain if the MP table and the hardware disagree */
2042         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2043                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2044         {
2045                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2046         }
2047
2048         /*
2049          * Do not trust the IO-APIC being empty at bootup
2050          */
2051         clear_IO_APIC();
2052 }
2053
2054 /*
2055  * Not an __init, needed by the reboot code
2056  */
2057 void disable_IO_APIC(void)
2058 {
2059         /*
2060          * Clear the IO-APIC before rebooting:
2061          */
2062         clear_IO_APIC();
2063
2064         /*
2065          * If the i8259 is routed through an IOAPIC
2066          * Put that IOAPIC in virtual wire mode
2067          * so legacy interrupts can be delivered.
2068          *
2069          * With interrupt-remapping, for now we will use virtual wire A mode,
2070          * as virtual wire B is little complex (need to configure both
2071          * IOAPIC RTE aswell as interrupt-remapping table entry).
2072          * As this gets called during crash dump, keep this simple for now.
2073          */
2074         if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2075                 struct IO_APIC_route_entry entry;
2076
2077                 memset(&entry, 0, sizeof(entry));
2078                 entry.mask            = 0; /* Enabled */
2079                 entry.trigger         = 0; /* Edge */
2080                 entry.irr             = 0;
2081                 entry.polarity        = 0; /* High */
2082                 entry.delivery_status = 0;
2083                 entry.dest_mode       = 0; /* Physical */
2084                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2085                 entry.vector          = 0;
2086                 entry.dest            = read_apic_id();
2087
2088                 /*
2089                  * Add it to the IO-APIC irq-routing table:
2090                  */
2091                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2092         }
2093
2094         /*
2095          * Use virtual wire A mode when interrupt remapping is enabled.
2096          */
2097         disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2098 }
2099
2100 #ifdef CONFIG_X86_32
2101 /*
2102  * function to set the IO-APIC physical IDs based on the
2103  * values stored in the MPC table.
2104  *
2105  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2106  */
2107
2108 static void __init setup_ioapic_ids_from_mpc(void)
2109 {
2110         union IO_APIC_reg_00 reg_00;
2111         physid_mask_t phys_id_present_map;
2112         int apic_id;
2113         int i;
2114         unsigned char old_id;
2115         unsigned long flags;
2116
2117         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2118                 return;
2119
2120         /*
2121          * Don't check I/O APIC IDs for xAPIC systems.  They have
2122          * no meaning without the serial APIC bus.
2123          */
2124         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2125                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2126                 return;
2127         /*
2128          * This is broken; anything with a real cpu count has to
2129          * circumvent this idiocy regardless.
2130          */
2131         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2132
2133         /*
2134          * Set the IOAPIC ID to the value stored in the MPC table.
2135          */
2136         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2137
2138                 /* Read the register 0 value */
2139                 spin_lock_irqsave(&ioapic_lock, flags);
2140                 reg_00.raw = io_apic_read(apic_id, 0);
2141                 spin_unlock_irqrestore(&ioapic_lock, flags);
2142
2143                 old_id = mp_ioapics[apic_id].apicid;
2144
2145                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2146                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2147                                 apic_id, mp_ioapics[apic_id].apicid);
2148                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2149                                 reg_00.bits.ID);
2150                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2151                 }
2152
2153                 /*
2154                  * Sanity check, is the ID really free? Every APIC in a
2155                  * system must have a unique ID or we get lots of nice
2156                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2157                  */
2158                 if (apic->check_apicid_used(phys_id_present_map,
2159                                         mp_ioapics[apic_id].apicid)) {
2160                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2161                                 apic_id, mp_ioapics[apic_id].apicid);
2162                         for (i = 0; i < get_physical_broadcast(); i++)
2163                                 if (!physid_isset(i, phys_id_present_map))
2164                                         break;
2165                         if (i >= get_physical_broadcast())
2166                                 panic("Max APIC ID exceeded!\n");
2167                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2168                                 i);
2169                         physid_set(i, phys_id_present_map);
2170                         mp_ioapics[apic_id].apicid = i;
2171                 } else {
2172                         physid_mask_t tmp;
2173                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2174                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2175                                         "phys_id_present_map\n",
2176                                         mp_ioapics[apic_id].apicid);
2177                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2178                 }
2179
2180
2181                 /*
2182                  * We need to adjust the IRQ routing table
2183                  * if the ID changed.
2184                  */
2185                 if (old_id != mp_ioapics[apic_id].apicid)
2186                         for (i = 0; i < mp_irq_entries; i++)
2187                                 if (mp_irqs[i].dstapic == old_id)
2188                                         mp_irqs[i].dstapic
2189                                                 = mp_ioapics[apic_id].apicid;
2190
2191                 /*
2192                  * Read the right value from the MPC table and
2193                  * write it into the ID register.
2194                  */
2195                 apic_printk(APIC_VERBOSE, KERN_INFO
2196                         "...changing IO-APIC physical APIC ID to %d ...",
2197                         mp_ioapics[apic_id].apicid);
2198
2199                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2200                 spin_lock_irqsave(&ioapic_lock, flags);
2201                 io_apic_write(apic_id, 0, reg_00.raw);
2202                 spin_unlock_irqrestore(&ioapic_lock, flags);
2203
2204                 /*
2205                  * Sanity check
2206                  */
2207                 spin_lock_irqsave(&ioapic_lock, flags);
2208                 reg_00.raw = io_apic_read(apic_id, 0);
2209                 spin_unlock_irqrestore(&ioapic_lock, flags);
2210                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2211                         printk("could not set ID!\n");
2212                 else
2213                         apic_printk(APIC_VERBOSE, " ok.\n");
2214         }
2215 }
2216 #endif
2217
2218 int no_timer_check __initdata;
2219
2220 static int __init notimercheck(char *s)
2221 {
2222         no_timer_check = 1;
2223         return 1;
2224 }
2225 __setup("no_timer_check", notimercheck);
2226
2227 /*
2228  * There is a nasty bug in some older SMP boards, their mptable lies
2229  * about the timer IRQ. We do the following to work around the situation:
2230  *
2231  *      - timer IRQ defaults to IO-APIC IRQ
2232  *      - if this function detects that timer IRQs are defunct, then we fall
2233  *        back to ISA timer IRQs
2234  */
2235 static int __init timer_irq_works(void)
2236 {
2237         unsigned long t1 = jiffies;
2238         unsigned long flags;
2239
2240         if (no_timer_check)
2241                 return 1;
2242
2243         local_save_flags(flags);
2244         local_irq_enable();
2245         /* Let ten ticks pass... */
2246         mdelay((10 * 1000) / HZ);
2247         local_irq_restore(flags);
2248
2249         /*
2250          * Expect a few ticks at least, to be sure some possible
2251          * glue logic does not lock up after one or two first
2252          * ticks in a non-ExtINT mode.  Also the local APIC
2253          * might have cached one ExtINT interrupt.  Finally, at
2254          * least one tick may be lost due to delays.
2255          */
2256
2257         /* jiffies wrap? */
2258         if (time_after(jiffies, t1 + 4))
2259                 return 1;
2260         return 0;
2261 }
2262
2263 /*
2264  * In the SMP+IOAPIC case it might happen that there are an unspecified
2265  * number of pending IRQ events unhandled. These cases are very rare,
2266  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2267  * better to do it this way as thus we do not have to be aware of
2268  * 'pending' interrupts in the IRQ path, except at this point.
2269  */
2270 /*
2271  * Edge triggered needs to resend any interrupt
2272  * that was delayed but this is now handled in the device
2273  * independent code.
2274  */
2275
2276 /*
2277  * Starting up a edge-triggered IO-APIC interrupt is
2278  * nasty - we need to make sure that we get the edge.
2279  * If it is already asserted for some reason, we need
2280  * return 1 to indicate that is was pending.
2281  *
2282  * This is not complete - we should be able to fake
2283  * an edge even if it isn't on the 8259A...
2284  */
2285
2286 static unsigned int startup_ioapic_irq(unsigned int irq)
2287 {
2288         int was_pending = 0;
2289         unsigned long flags;
2290         struct irq_cfg *cfg;
2291
2292         spin_lock_irqsave(&ioapic_lock, flags);
2293         if (irq < NR_IRQS_LEGACY) {
2294                 disable_8259A_irq(irq);
2295                 if (i8259A_irq_pending(irq))
2296                         was_pending = 1;
2297         }
2298         cfg = irq_cfg(irq);
2299         __unmask_IO_APIC_irq(cfg);
2300         spin_unlock_irqrestore(&ioapic_lock, flags);
2301
2302         return was_pending;
2303 }
2304
2305 #ifdef CONFIG_X86_64
2306 static int ioapic_retrigger_irq(unsigned int irq)
2307 {
2308
2309         struct irq_cfg *cfg = irq_cfg(irq);
2310         unsigned long flags;
2311
2312         spin_lock_irqsave(&vector_lock, flags);
2313         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2314         spin_unlock_irqrestore(&vector_lock, flags);
2315
2316         return 1;
2317 }
2318 #else
2319 static int ioapic_retrigger_irq(unsigned int irq)
2320 {
2321         apic->send_IPI_self(irq_cfg(irq)->vector);
2322
2323         return 1;
2324 }
2325 #endif
2326
2327 /*
2328  * Level and edge triggered IO-APIC interrupts need different handling,
2329  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2330  * handled with the level-triggered descriptor, but that one has slightly
2331  * more overhead. Level-triggered interrupts cannot be handled with the
2332  * edge-triggered handler, without risking IRQ storms and other ugly
2333  * races.
2334  */
2335
2336 #ifdef CONFIG_SMP
2337
2338 #ifdef CONFIG_INTR_REMAP
2339
2340 /*
2341  * Migrate the IO-APIC irq in the presence of intr-remapping.
2342  *
2343  * For both level and edge triggered, irq migration is a simple atomic
2344  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2345  *
2346  * For level triggered, we eliminate the io-apic RTE modification (with the
2347  * updated vector information), by using a virtual vector (io-apic pin number).
2348  * Real vector that is used for interrupting cpu will be coming from
2349  * the interrupt-remapping table entry.
2350  */
2351 static void
2352 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2353 {
2354         struct irq_cfg *cfg;
2355         struct irte irte;
2356         unsigned int dest;
2357         unsigned int irq;
2358
2359         if (!cpumask_intersects(mask, cpu_online_mask))
2360                 return;
2361
2362         irq = desc->irq;
2363         if (get_irte(irq, &irte))
2364                 return;
2365
2366         cfg = desc->chip_data;
2367         if (assign_irq_vector(irq, cfg, mask))
2368                 return;
2369
2370         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2371
2372         irte.vector = cfg->vector;
2373         irte.dest_id = IRTE_DEST(dest);
2374
2375         /*
2376          * Modified the IRTE and flushes the Interrupt entry cache.
2377          */
2378         modify_irte(irq, &irte);
2379
2380         if (cfg->move_in_progress)
2381                 send_cleanup_vector(cfg);
2382
2383         cpumask_copy(desc->affinity, mask);
2384 }
2385
2386 /*
2387  * Migrates the IRQ destination in the process context.
2388  */
2389 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2390                                             const struct cpumask *mask)
2391 {
2392         migrate_ioapic_irq_desc(desc, mask);
2393 }
2394 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2395                                        const struct cpumask *mask)
2396 {
2397         struct irq_desc *desc = irq_to_desc(irq);
2398
2399         set_ir_ioapic_affinity_irq_desc(desc, mask);
2400 }
2401 #else
2402 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2403                                                    const struct cpumask *mask)
2404 {
2405 }
2406 #endif
2407
2408 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2409 {
2410         unsigned vector, me;
2411
2412         ack_APIC_irq();
2413         exit_idle();
2414         irq_enter();
2415
2416         me = smp_processor_id();
2417         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2418                 unsigned int irq;
2419                 unsigned int irr;
2420                 struct irq_desc *desc;
2421                 struct irq_cfg *cfg;
2422                 irq = __get_cpu_var(vector_irq)[vector];
2423
2424                 if (irq == -1)
2425                         continue;
2426
2427                 desc = irq_to_desc(irq);
2428                 if (!desc)
2429                         continue;
2430
2431                 cfg = irq_cfg(irq);
2432                 spin_lock(&desc->lock);
2433                 if (!cfg->move_cleanup_count)
2434                         goto unlock;
2435
2436                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2437                         goto unlock;
2438
2439                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2440                 /*
2441                  * Check if the vector that needs to be cleanedup is
2442                  * registered at the cpu's IRR. If so, then this is not
2443                  * the best time to clean it up. Lets clean it up in the
2444                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2445                  * to myself.
2446                  */
2447                 if (irr  & (1 << (vector % 32))) {
2448                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2449                         goto unlock;
2450                 }
2451                 __get_cpu_var(vector_irq)[vector] = -1;
2452                 cfg->move_cleanup_count--;
2453 unlock:
2454                 spin_unlock(&desc->lock);
2455         }
2456
2457         irq_exit();
2458 }
2459
2460 static void irq_complete_move(struct irq_desc **descp)
2461 {
2462         struct irq_desc *desc = *descp;
2463         struct irq_cfg *cfg = desc->chip_data;
2464         unsigned vector, me;
2465
2466         if (likely(!cfg->move_in_progress))
2467                 return;
2468
2469         vector = ~get_irq_regs()->orig_ax;
2470         me = smp_processor_id();
2471
2472         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2473                 send_cleanup_vector(cfg);
2474 }
2475 #else
2476 static inline void irq_complete_move(struct irq_desc **descp) {}
2477 #endif
2478
2479 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2480 {
2481         int apic, pin;
2482         struct irq_pin_list *entry;
2483
2484         entry = cfg->irq_2_pin;
2485         for (;;) {
2486
2487                 if (!entry)
2488                         break;
2489
2490                 apic = entry->apic;
2491                 pin = entry->pin;
2492                 io_apic_eoi(apic, pin);
2493                 entry = entry->next;
2494         }
2495 }
2496
2497 static void
2498 eoi_ioapic_irq(struct irq_desc *desc)
2499 {
2500         struct irq_cfg *cfg;
2501         unsigned long flags;
2502         unsigned int irq;
2503
2504         irq = desc->irq;
2505         cfg = desc->chip_data;
2506
2507         spin_lock_irqsave(&ioapic_lock, flags);
2508         __eoi_ioapic_irq(irq, cfg);
2509         spin_unlock_irqrestore(&ioapic_lock, flags);
2510 }
2511
2512 #ifdef CONFIG_X86_X2APIC
2513 static void ack_x2apic_level(unsigned int irq)
2514 {
2515         struct irq_desc *desc = irq_to_desc(irq);
2516         ack_x2APIC_irq();
2517         eoi_ioapic_irq(desc);
2518 }
2519
2520 static void ack_x2apic_edge(unsigned int irq)
2521 {
2522         ack_x2APIC_irq();
2523 }
2524 #endif
2525
2526 static void ack_apic_edge(unsigned int irq)
2527 {
2528         struct irq_desc *desc = irq_to_desc(irq);
2529
2530         irq_complete_move(&desc);
2531         move_native_irq(irq);
2532         ack_APIC_irq();
2533 }
2534
2535 atomic_t irq_mis_count;
2536
2537 static void ack_apic_level(unsigned int irq)
2538 {
2539         struct irq_desc *desc = irq_to_desc(irq);
2540
2541 #ifdef CONFIG_X86_32
2542         unsigned long v;
2543         int i;
2544 #endif
2545         struct irq_cfg *cfg;
2546         int do_unmask_irq = 0;
2547
2548         irq_complete_move(&desc);
2549 #ifdef CONFIG_GENERIC_PENDING_IRQ
2550         /* If we are moving the irq we need to mask it */
2551         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2552                 do_unmask_irq = 1;
2553                 mask_IO_APIC_irq_desc(desc);
2554         }
2555 #endif
2556
2557 #ifdef CONFIG_X86_32
2558         /*
2559         * It appears there is an erratum which affects at least version 0x11
2560         * of I/O APIC (that's the 82093AA and cores integrated into various
2561         * chipsets).  Under certain conditions a level-triggered interrupt is
2562         * erroneously delivered as edge-triggered one but the respective IRR
2563         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2564         * message but it will never arrive and further interrupts are blocked
2565         * from the source.  The exact reason is so far unknown, but the
2566         * phenomenon was observed when two consecutive interrupt requests
2567         * from a given source get delivered to the same CPU and the source is
2568         * temporarily disabled in between.
2569         *
2570         * A workaround is to simulate an EOI message manually.  We achieve it
2571         * by setting the trigger mode to edge and then to level when the edge
2572         * trigger mode gets detected in the TMR of a local APIC for a
2573         * level-triggered interrupt.  We mask the source for the time of the
2574         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2575         * The idea is from Manfred Spraul.  --macro
2576         */
2577         cfg = desc->chip_data;
2578         i = cfg->vector;
2579
2580         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2581 #endif
2582
2583         /*
2584          * We must acknowledge the irq before we move it or the acknowledge will
2585          * not propagate properly.
2586          */
2587         ack_APIC_irq();
2588
2589         if (irq_remapped(irq))
2590                 eoi_ioapic_irq(desc);
2591
2592         /* Now we can move and renable the irq */
2593         if (unlikely(do_unmask_irq)) {
2594                 /* Only migrate the irq if the ack has been received.
2595                  *
2596                  * On rare occasions the broadcast level triggered ack gets
2597                  * delayed going to ioapics, and if we reprogram the
2598                  * vector while Remote IRR is still set the irq will never
2599                  * fire again.
2600                  *
2601                  * To prevent this scenario we read the Remote IRR bit
2602                  * of the ioapic.  This has two effects.
2603                  * - On any sane system the read of the ioapic will
2604                  *   flush writes (and acks) going to the ioapic from
2605                  *   this cpu.
2606                  * - We get to see if the ACK has actually been delivered.
2607                  *
2608                  * Based on failed experiments of reprogramming the
2609                  * ioapic entry from outside of irq context starting
2610                  * with masking the ioapic entry and then polling until
2611                  * Remote IRR was clear before reprogramming the
2612                  * ioapic I don't trust the Remote IRR bit to be
2613                  * completey accurate.
2614                  *
2615                  * However there appears to be no other way to plug
2616                  * this race, so if the Remote IRR bit is not
2617                  * accurate and is causing problems then it is a hardware bug
2618                  * and you can go talk to the chipset vendor about it.
2619                  */
2620                 cfg = desc->chip_data;
2621                 if (!io_apic_level_ack_pending(cfg))
2622                         move_masked_irq(irq);
2623                 unmask_IO_APIC_irq_desc(desc);
2624         }
2625
2626 #ifdef CONFIG_X86_32
2627         if (!(v & (1 << (i & 0x1f)))) {
2628                 atomic_inc(&irq_mis_count);
2629                 spin_lock(&ioapic_lock);
2630                 __mask_and_edge_IO_APIC_irq(cfg);
2631                 __unmask_and_level_IO_APIC_irq(cfg);
2632                 spin_unlock(&ioapic_lock);
2633         }
2634 #endif
2635 }
2636
2637 #ifdef CONFIG_INTR_REMAP
2638 static void ir_ack_apic_edge(unsigned int irq)
2639 {
2640 #ifdef CONFIG_X86_X2APIC
2641        if (x2apic_enabled())
2642                return ack_x2apic_edge(irq);
2643 #endif
2644        return ack_apic_edge(irq);
2645 }
2646
2647 static void ir_ack_apic_level(unsigned int irq)
2648 {
2649 #ifdef CONFIG_X86_X2APIC
2650        if (x2apic_enabled())
2651                return ack_x2apic_level(irq);
2652 #endif
2653        return ack_apic_level(irq);
2654 }
2655 #endif /* CONFIG_INTR_REMAP */
2656
2657 static struct irq_chip ioapic_chip __read_mostly = {
2658         .name           = "IO-APIC",
2659         .startup        = startup_ioapic_irq,
2660         .mask           = mask_IO_APIC_irq,
2661         .unmask         = unmask_IO_APIC_irq,
2662         .ack            = ack_apic_edge,
2663         .eoi            = ack_apic_level,
2664 #ifdef CONFIG_SMP
2665         .set_affinity   = set_ioapic_affinity_irq,
2666 #endif
2667         .retrigger      = ioapic_retrigger_irq,
2668 };
2669
2670 static struct irq_chip ir_ioapic_chip __read_mostly = {
2671         .name           = "IR-IO-APIC",
2672         .startup        = startup_ioapic_irq,
2673         .mask           = mask_IO_APIC_irq,
2674         .unmask         = unmask_IO_APIC_irq,
2675 #ifdef CONFIG_INTR_REMAP
2676         .ack            = ir_ack_apic_edge,
2677         .eoi            = ir_ack_apic_level,
2678 #ifdef CONFIG_SMP
2679         .set_affinity   = set_ir_ioapic_affinity_irq,
2680 #endif
2681 #endif
2682         .retrigger      = ioapic_retrigger_irq,
2683 };
2684
2685 static inline void init_IO_APIC_traps(void)
2686 {
2687         int irq;
2688         struct irq_desc *desc;
2689         struct irq_cfg *cfg;
2690
2691         /*
2692          * NOTE! The local APIC isn't very good at handling
2693          * multiple interrupts at the same interrupt level.
2694          * As the interrupt level is determined by taking the
2695          * vector number and shifting that right by 4, we
2696          * want to spread these out a bit so that they don't
2697          * all fall in the same interrupt level.
2698          *
2699          * Also, we've got to be careful not to trash gate
2700          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2701          */
2702         for_each_irq_desc(irq, desc) {
2703                 cfg = desc->chip_data;
2704                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2705                         /*
2706                          * Hmm.. We don't have an entry for this,
2707                          * so default to an old-fashioned 8259
2708                          * interrupt if we can..
2709                          */
2710                         if (irq < NR_IRQS_LEGACY)
2711                                 make_8259A_irq(irq);
2712                         else
2713                                 /* Strange. Oh, well.. */
2714                                 desc->chip = &no_irq_chip;
2715                 }
2716         }
2717 }
2718
2719 /*
2720  * The local APIC irq-chip implementation:
2721  */
2722
2723 static void mask_lapic_irq(unsigned int irq)
2724 {
2725         unsigned long v;
2726
2727         v = apic_read(APIC_LVT0);
2728         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2729 }
2730
2731 static void unmask_lapic_irq(unsigned int irq)
2732 {
2733         unsigned long v;
2734
2735         v = apic_read(APIC_LVT0);
2736         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2737 }
2738
2739 static void ack_lapic_irq(unsigned int irq)
2740 {
2741         ack_APIC_irq();
2742 }
2743
2744 static struct irq_chip lapic_chip __read_mostly = {
2745         .name           = "local-APIC",
2746         .mask           = mask_lapic_irq,
2747         .unmask         = unmask_lapic_irq,
2748         .ack            = ack_lapic_irq,
2749 };
2750
2751 static void lapic_register_intr(int irq, struct irq_desc *desc)
2752 {
2753         desc->status &= ~IRQ_LEVEL;
2754         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2755                                       "edge");
2756 }
2757
2758 static void __init setup_nmi(void)
2759 {
2760         /*
2761          * Dirty trick to enable the NMI watchdog ...
2762          * We put the 8259A master into AEOI mode and
2763          * unmask on all local APICs LVT0 as NMI.
2764          *
2765          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2766          * is from Maciej W. Rozycki - so we do not have to EOI from
2767          * the NMI handler or the timer interrupt.
2768          */
2769         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2770
2771         enable_NMI_through_LVT0();
2772
2773         apic_printk(APIC_VERBOSE, " done.\n");
2774 }
2775
2776 /*
2777  * This looks a bit hackish but it's about the only one way of sending
2778  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2779  * not support the ExtINT mode, unfortunately.  We need to send these
2780  * cycles as some i82489DX-based boards have glue logic that keeps the
2781  * 8259A interrupt line asserted until INTA.  --macro
2782  */
2783 static inline void __init unlock_ExtINT_logic(void)
2784 {
2785         int apic, pin, i;
2786         struct IO_APIC_route_entry entry0, entry1;
2787         unsigned char save_control, save_freq_select;
2788
2789         pin  = find_isa_irq_pin(8, mp_INT);
2790         if (pin == -1) {
2791                 WARN_ON_ONCE(1);
2792                 return;
2793         }
2794         apic = find_isa_irq_apic(8, mp_INT);
2795         if (apic == -1) {
2796                 WARN_ON_ONCE(1);
2797                 return;
2798         }
2799
2800         entry0 = ioapic_read_entry(apic, pin);
2801         clear_IO_APIC_pin(apic, pin);
2802
2803         memset(&entry1, 0, sizeof(entry1));
2804
2805         entry1.dest_mode = 0;                   /* physical delivery */
2806         entry1.mask = 0;                        /* unmask IRQ now */
2807         entry1.dest = hard_smp_processor_id();
2808         entry1.delivery_mode = dest_ExtINT;
2809         entry1.polarity = entry0.polarity;
2810         entry1.trigger = 0;
2811         entry1.vector = 0;
2812
2813         ioapic_write_entry(apic, pin, entry1);
2814
2815         save_control = CMOS_READ(RTC_CONTROL);
2816         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2817         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2818                    RTC_FREQ_SELECT);
2819         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2820
2821         i = 100;
2822         while (i-- > 0) {
2823                 mdelay(10);
2824                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2825                         i -= 10;
2826         }
2827
2828         CMOS_WRITE(save_control, RTC_CONTROL);
2829         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2830         clear_IO_APIC_pin(apic, pin);
2831
2832         ioapic_write_entry(apic, pin, entry0);
2833 }
2834
2835 static int disable_timer_pin_1 __initdata;
2836 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2837 static int __init disable_timer_pin_setup(char *arg)
2838 {
2839         disable_timer_pin_1 = 1;
2840         return 0;
2841 }
2842 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2843
2844 int timer_through_8259 __initdata;
2845
2846 /*
2847  * This code may look a bit paranoid, but it's supposed to cooperate with
2848  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2849  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2850  * fanatically on his truly buggy board.
2851  *
2852  * FIXME: really need to revamp this for all platforms.
2853  */
2854 static inline void __init check_timer(void)
2855 {
2856         struct irq_desc *desc = irq_to_desc(0);
2857         struct irq_cfg *cfg = desc->chip_data;
2858         int cpu = boot_cpu_id;
2859         int apic1, pin1, apic2, pin2;
2860         unsigned long flags;
2861         int no_pin1 = 0;
2862
2863         local_irq_save(flags);
2864
2865         /*
2866          * get/set the timer IRQ vector:
2867          */
2868         disable_8259A_irq(0);
2869         assign_irq_vector(0, cfg, apic->target_cpus());
2870
2871         /*
2872          * As IRQ0 is to be enabled in the 8259A, the virtual
2873          * wire has to be disabled in the local APIC.  Also
2874          * timer interrupts need to be acknowledged manually in
2875          * the 8259A for the i82489DX when using the NMI
2876          * watchdog as that APIC treats NMIs as level-triggered.
2877          * The AEOI mode will finish them in the 8259A
2878          * automatically.
2879          */
2880         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2881         init_8259A(1);
2882 #ifdef CONFIG_X86_32
2883         {
2884                 unsigned int ver;
2885
2886                 ver = apic_read(APIC_LVR);
2887                 ver = GET_APIC_VERSION(ver);
2888                 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2889         }
2890 #endif
2891
2892         pin1  = find_isa_irq_pin(0, mp_INT);
2893         apic1 = find_isa_irq_apic(0, mp_INT);
2894         pin2  = ioapic_i8259.pin;
2895         apic2 = ioapic_i8259.apic;
2896
2897         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2898                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2899                     cfg->vector, apic1, pin1, apic2, pin2);
2900
2901         /*
2902          * Some BIOS writers are clueless and report the ExtINTA
2903          * I/O APIC input from the cascaded 8259A as the timer
2904          * interrupt input.  So just in case, if only one pin
2905          * was found above, try it both directly and through the
2906          * 8259A.
2907          */
2908         if (pin1 == -1) {
2909                 if (intr_remapping_enabled)
2910                         panic("BIOS bug: timer not connected to IO-APIC");
2911                 pin1 = pin2;
2912                 apic1 = apic2;
2913                 no_pin1 = 1;
2914         } else if (pin2 == -1) {
2915                 pin2 = pin1;
2916                 apic2 = apic1;
2917         }
2918
2919         if (pin1 != -1) {
2920                 /*
2921                  * Ok, does IRQ0 through the IOAPIC work?
2922                  */
2923                 if (no_pin1) {
2924                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2925                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2926                 } else {
2927                         /* for edge trigger, setup_IO_APIC_irq already
2928                          * leave it unmasked.
2929                          * so only need to unmask if it is level-trigger
2930                          * do we really have level trigger timer?
2931                          */
2932                         int idx;
2933                         idx = find_irq_entry(apic1, pin1, mp_INT);
2934                         if (idx != -1 && irq_trigger(idx))
2935                                 unmask_IO_APIC_irq_desc(desc);
2936                 }
2937                 if (timer_irq_works()) {
2938                         if (nmi_watchdog == NMI_IO_APIC) {
2939                                 setup_nmi();
2940                                 enable_8259A_irq(0);
2941                         }
2942                         if (disable_timer_pin_1 > 0)
2943                                 clear_IO_APIC_pin(0, pin1);
2944                         goto out;
2945                 }
2946                 if (intr_remapping_enabled)
2947                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2948                 local_irq_disable();
2949                 clear_IO_APIC_pin(apic1, pin1);
2950                 if (!no_pin1)
2951                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2952                                     "8254 timer not connected to IO-APIC\n");
2953
2954                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2955                             "(IRQ0) through the 8259A ...\n");
2956                 apic_printk(APIC_QUIET, KERN_INFO
2957                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2958                 /*
2959                  * legacy devices should be connected to IO APIC #0
2960                  */
2961                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2962                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2963                 enable_8259A_irq(0);
2964                 if (timer_irq_works()) {
2965                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2966                         timer_through_8259 = 1;
2967                         if (nmi_watchdog == NMI_IO_APIC) {
2968                                 disable_8259A_irq(0);
2969                                 setup_nmi();
2970                                 enable_8259A_irq(0);
2971                         }
2972                         goto out;
2973                 }
2974                 /*
2975                  * Cleanup, just in case ...
2976                  */
2977                 local_irq_disable();
2978                 disable_8259A_irq(0);
2979                 clear_IO_APIC_pin(apic2, pin2);
2980                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2981         }
2982
2983         if (nmi_watchdog == NMI_IO_APIC) {
2984                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2985                             "through the IO-APIC - disabling NMI Watchdog!\n");
2986                 nmi_watchdog = NMI_NONE;
2987         }
2988 #ifdef CONFIG_X86_32
2989         timer_ack = 0;
2990 #endif
2991
2992         apic_printk(APIC_QUIET, KERN_INFO
2993                     "...trying to set up timer as Virtual Wire IRQ...\n");
2994
2995         lapic_register_intr(0, desc);
2996         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2997         enable_8259A_irq(0);
2998
2999         if (timer_irq_works()) {
3000                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3001                 goto out;
3002         }
3003         local_irq_disable();
3004         disable_8259A_irq(0);
3005         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3006         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3007
3008         apic_printk(APIC_QUIET, KERN_INFO
3009                     "...trying to set up timer as ExtINT IRQ...\n");
3010
3011         init_8259A(0);
3012         make_8259A_irq(0);
3013         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3014
3015         unlock_ExtINT_logic();
3016
3017         if (timer_irq_works()) {
3018                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3019                 goto out;
3020         }
3021         local_irq_disable();
3022         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3023         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3024                 "report.  Then try booting with the 'noapic' option.\n");
3025 out:
3026         local_irq_restore(flags);
3027 }
3028
3029 /*
3030  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3031  * to devices.  However there may be an I/O APIC pin available for
3032  * this interrupt regardless.  The pin may be left unconnected, but
3033  * typically it will be reused as an ExtINT cascade interrupt for
3034  * the master 8259A.  In the MPS case such a pin will normally be
3035  * reported as an ExtINT interrupt in the MP table.  With ACPI
3036  * there is no provision for ExtINT interrupts, and in the absence
3037  * of an override it would be treated as an ordinary ISA I/O APIC
3038  * interrupt, that is edge-triggered and unmasked by default.  We
3039  * used to do this, but it caused problems on some systems because
3040  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3041  * the same ExtINT cascade interrupt to drive the local APIC of the
3042  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3043  * the I/O APIC in all cases now.  No actual device should request
3044  * it anyway.  --macro
3045  */
3046 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3047
3048 void __init setup_IO_APIC(void)
3049 {
3050
3051         /*
3052          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3053          */
3054
3055         io_apic_irqs = ~PIC_IRQS;
3056
3057         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3058         /*
3059          * Set up IO-APIC IRQ routing.
3060          */
3061 #ifdef CONFIG_X86_32
3062         if (!acpi_ioapic)
3063                 setup_ioapic_ids_from_mpc();
3064 #endif
3065         sync_Arb_IDs();
3066         setup_IO_APIC_irqs();
3067         init_IO_APIC_traps();
3068         check_timer();
3069 }
3070
3071 /*
3072  *      Called after all the initialization is done. If we didnt find any
3073  *      APIC bugs then we can allow the modify fast path
3074  */
3075
3076 static int __init io_apic_bug_finalize(void)
3077 {
3078         if (sis_apic_bug == -1)
3079                 sis_apic_bug = 0;
3080         return 0;
3081 }
3082
3083 late_initcall(io_apic_bug_finalize);
3084
3085 struct sysfs_ioapic_data {
3086         struct sys_device dev;
3087         struct IO_APIC_route_entry entry[0];
3088 };
3089 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3090
3091 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3092 {
3093         struct IO_APIC_route_entry *entry;
3094         struct sysfs_ioapic_data *data;
3095         int i;
3096
3097         data = container_of(dev, struct sysfs_ioapic_data, dev);
3098         entry = data->entry;
3099         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3100                 *entry = ioapic_read_entry(dev->id, i);
3101
3102         return 0;
3103 }
3104
3105 static int ioapic_resume(struct sys_device *dev)
3106 {
3107         struct IO_APIC_route_entry *entry;
3108         struct sysfs_ioapic_data *data;
3109         unsigned long flags;
3110         union IO_APIC_reg_00 reg_00;
3111         int i;
3112
3113         data = container_of(dev, struct sysfs_ioapic_data, dev);
3114         entry = data->entry;
3115
3116         spin_lock_irqsave(&ioapic_lock, flags);
3117         reg_00.raw = io_apic_read(dev->id, 0);
3118         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3119                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3120                 io_apic_write(dev->id, 0, reg_00.raw);
3121         }
3122         spin_unlock_irqrestore(&ioapic_lock, flags);
3123         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3124                 ioapic_write_entry(dev->id, i, entry[i]);
3125
3126         return 0;
3127 }
3128
3129 static struct sysdev_class ioapic_sysdev_class = {
3130         .name = "ioapic",
3131         .suspend = ioapic_suspend,
3132         .resume = ioapic_resume,
3133 };
3134
3135 static int __init ioapic_init_sysfs(void)
3136 {
3137         struct sys_device * dev;
3138         int i, size, error;
3139
3140         error = sysdev_class_register(&ioapic_sysdev_class);
3141         if (error)
3142                 return error;
3143
3144         for (i = 0; i < nr_ioapics; i++ ) {
3145                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3146                         * sizeof(struct IO_APIC_route_entry);
3147                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3148                 if (!mp_ioapic_data[i]) {
3149                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3150                         continue;
3151                 }
3152                 dev = &mp_ioapic_data[i]->dev;
3153                 dev->id = i;
3154                 dev->cls = &ioapic_sysdev_class;
3155                 error = sysdev_register(dev);
3156                 if (error) {
3157                         kfree(mp_ioapic_data[i]);
3158                         mp_ioapic_data[i] = NULL;
3159                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3160                         continue;
3161                 }
3162         }
3163
3164         return 0;
3165 }
3166
3167 device_initcall(ioapic_init_sysfs);
3168
3169 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3170 /*
3171  * Dynamic irq allocate and deallocation
3172  */
3173 unsigned int create_irq_nr(unsigned int irq_want)
3174 {
3175         /* Allocate an unused irq */
3176         unsigned int irq;
3177         unsigned int new;
3178         unsigned long flags;
3179         struct irq_cfg *cfg_new = NULL;
3180         int cpu = boot_cpu_id;
3181         struct irq_desc *desc_new = NULL;
3182
3183         irq = 0;
3184         if (irq_want < nr_irqs_gsi)
3185                 irq_want = nr_irqs_gsi;
3186
3187         spin_lock_irqsave(&vector_lock, flags);
3188         for (new = irq_want; new < nr_irqs; new++) {
3189                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3190                 if (!desc_new) {
3191                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3192                         continue;
3193                 }
3194                 cfg_new = desc_new->chip_data;
3195
3196                 if (cfg_new->vector != 0)
3197                         continue;
3198                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3199                         irq = new;
3200                 break;
3201         }
3202         spin_unlock_irqrestore(&vector_lock, flags);
3203
3204         if (irq > 0) {
3205                 dynamic_irq_init(irq);
3206                 /* restore it, in case dynamic_irq_init clear it */
3207                 if (desc_new)
3208                         desc_new->chip_data = cfg_new;
3209         }
3210         return irq;
3211 }
3212
3213 int create_irq(void)
3214 {
3215         unsigned int irq_want;
3216         int irq;
3217
3218         irq_want = nr_irqs_gsi;
3219         irq = create_irq_nr(irq_want);
3220
3221         if (irq == 0)
3222                 irq = -1;
3223
3224         return irq;
3225 }
3226
3227 void destroy_irq(unsigned int irq)
3228 {
3229         unsigned long flags;
3230         struct irq_cfg *cfg;
3231         struct irq_desc *desc;
3232
3233         /* store it, in case dynamic_irq_cleanup clear it */
3234         desc = irq_to_desc(irq);
3235         cfg = desc->chip_data;
3236         dynamic_irq_cleanup(irq);
3237         /* connect back irq_cfg */
3238         if (desc)
3239                 desc->chip_data = cfg;
3240
3241         free_irte(irq);
3242         spin_lock_irqsave(&vector_lock, flags);
3243         __clear_irq_vector(irq, cfg);
3244         spin_unlock_irqrestore(&vector_lock, flags);
3245 }
3246
3247 /*
3248  * MSI message composition
3249  */
3250 #ifdef CONFIG_PCI_MSI
3251 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3252 {
3253         struct irq_cfg *cfg;
3254         int err;
3255         unsigned dest;
3256
3257         if (disable_apic)
3258                 return -ENXIO;
3259
3260         cfg = irq_cfg(irq);
3261         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3262         if (err)
3263                 return err;
3264
3265         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3266
3267         if (irq_remapped(irq)) {
3268                 struct irte irte;
3269                 int ir_index;
3270                 u16 sub_handle;
3271
3272                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3273                 BUG_ON(ir_index == -1);
3274
3275                 memset (&irte, 0, sizeof(irte));
3276
3277                 irte.present = 1;
3278                 irte.dst_mode = apic->irq_dest_mode;
3279                 irte.trigger_mode = 0; /* edge */
3280                 irte.dlvry_mode = apic->irq_delivery_mode;
3281                 irte.vector = cfg->vector;
3282                 irte.dest_id = IRTE_DEST(dest);
3283
3284                 modify_irte(irq, &irte);
3285
3286                 msg->address_hi = MSI_ADDR_BASE_HI;
3287                 msg->data = sub_handle;
3288                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3289                                   MSI_ADDR_IR_SHV |
3290                                   MSI_ADDR_IR_INDEX1(ir_index) |
3291                                   MSI_ADDR_IR_INDEX2(ir_index);
3292         } else {
3293                 if (x2apic_enabled())
3294                         msg->address_hi = MSI_ADDR_BASE_HI |
3295                                           MSI_ADDR_EXT_DEST_ID(dest);
3296                 else
3297                         msg->address_hi = MSI_ADDR_BASE_HI;
3298
3299                 msg->address_lo =
3300                         MSI_ADDR_BASE_LO |
3301                         ((apic->irq_dest_mode == 0) ?
3302                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3303                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3304                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3305                                 MSI_ADDR_REDIRECTION_CPU:
3306                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3307                         MSI_ADDR_DEST_ID(dest);
3308
3309                 msg->data =
3310                         MSI_DATA_TRIGGER_EDGE |
3311                         MSI_DATA_LEVEL_ASSERT |
3312                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3313                                 MSI_DATA_DELIVERY_FIXED:
3314                                 MSI_DATA_DELIVERY_LOWPRI) |
3315                         MSI_DATA_VECTOR(cfg->vector);
3316         }
3317         return err;
3318 }
3319
3320 #ifdef CONFIG_SMP
3321 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3322 {
3323         struct irq_desc *desc = irq_to_desc(irq);
3324         struct irq_cfg *cfg;
3325         struct msi_msg msg;
3326         unsigned int dest;
3327
3328         dest = set_desc_affinity(desc, mask);
3329         if (dest == BAD_APICID)
3330                 return;
3331
3332         cfg = desc->chip_data;
3333
3334         read_msi_msg_desc(desc, &msg);
3335
3336         msg.data &= ~MSI_DATA_VECTOR_MASK;
3337         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3338         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3339         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3340
3341         write_msi_msg_desc(desc, &msg);
3342 }
3343 #ifdef CONFIG_INTR_REMAP
3344 /*
3345  * Migrate the MSI irq to another cpumask. This migration is
3346  * done in the process context using interrupt-remapping hardware.
3347  */
3348 static void
3349 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3350 {
3351         struct irq_desc *desc = irq_to_desc(irq);
3352         struct irq_cfg *cfg = desc->chip_data;
3353         unsigned int dest;
3354         struct irte irte;
3355
3356         if (get_irte(irq, &irte))
3357                 return;
3358
3359         dest = set_desc_affinity(desc, mask);
3360         if (dest == BAD_APICID)
3361                 return;
3362
3363         irte.vector = cfg->vector;
3364         irte.dest_id = IRTE_DEST(dest);
3365
3366         /*
3367          * atomically update the IRTE with the new destination and vector.
3368          */
3369         modify_irte(irq, &irte);
3370
3371         /*
3372          * After this point, all the interrupts will start arriving
3373          * at the new destination. So, time to cleanup the previous
3374          * vector allocation.
3375          */
3376         if (cfg->move_in_progress)
3377                 send_cleanup_vector(cfg);
3378 }
3379
3380 #endif
3381 #endif /* CONFIG_SMP */
3382
3383 /*
3384  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3385  * which implement the MSI or MSI-X Capability Structure.
3386  */
3387 static struct irq_chip msi_chip = {
3388         .name           = "PCI-MSI",
3389         .unmask         = unmask_msi_irq,
3390         .mask           = mask_msi_irq,
3391         .ack            = ack_apic_edge,
3392 #ifdef CONFIG_SMP
3393         .set_affinity   = set_msi_irq_affinity,
3394 #endif
3395         .retrigger      = ioapic_retrigger_irq,
3396 };
3397
3398 static struct irq_chip msi_ir_chip = {
3399         .name           = "IR-PCI-MSI",
3400         .unmask         = unmask_msi_irq,
3401         .mask           = mask_msi_irq,
3402 #ifdef CONFIG_INTR_REMAP
3403         .ack            = ir_ack_apic_edge,
3404 #ifdef CONFIG_SMP
3405         .set_affinity   = ir_set_msi_irq_affinity,
3406 #endif
3407 #endif
3408         .retrigger      = ioapic_retrigger_irq,
3409 };
3410
3411 /*
3412  * Map the PCI dev to the corresponding remapping hardware unit
3413  * and allocate 'nvec' consecutive interrupt-remapping table entries
3414  * in it.
3415  */
3416 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3417 {
3418         struct intel_iommu *iommu;
3419         int index;
3420
3421         iommu = map_dev_to_ir(dev);
3422         if (!iommu) {
3423                 printk(KERN_ERR
3424                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3425                 return -ENOENT;
3426         }
3427
3428         index = alloc_irte(iommu, irq, nvec);
3429         if (index < 0) {
3430                 printk(KERN_ERR
3431                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3432                        pci_name(dev));
3433                 return -ENOSPC;
3434         }
3435         return index;
3436 }
3437
3438 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3439 {
3440         int ret;
3441         struct msi_msg msg;
3442
3443         ret = msi_compose_msg(dev, irq, &msg);
3444         if (ret < 0)
3445                 return ret;
3446
3447         set_irq_msi(irq, msidesc);
3448         write_msi_msg(irq, &msg);
3449
3450         if (irq_remapped(irq)) {
3451                 struct irq_desc *desc = irq_to_desc(irq);
3452                 /*
3453                  * irq migration in process context
3454                  */
3455                 desc->status |= IRQ_MOVE_PCNTXT;
3456                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3457         } else
3458                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3459
3460         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3461
3462         return 0;
3463 }
3464
3465 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3466 {
3467         unsigned int irq;
3468         int ret, sub_handle;
3469         struct msi_desc *msidesc;
3470         unsigned int irq_want;
3471         struct intel_iommu *iommu = NULL;
3472         int index = 0;
3473
3474         /* x86 doesn't support multiple MSI yet */
3475         if (type == PCI_CAP_ID_MSI && nvec > 1)
3476                 return 1;
3477
3478         irq_want = nr_irqs_gsi;
3479         sub_handle = 0;
3480         list_for_each_entry(msidesc, &dev->msi_list, list) {
3481                 irq = create_irq_nr(irq_want);
3482                 if (irq == 0)
3483                         return -1;
3484                 irq_want = irq + 1;
3485                 if (!intr_remapping_enabled)
3486                         goto no_ir;
3487
3488                 if (!sub_handle) {
3489                         /*
3490                          * allocate the consecutive block of IRTE's
3491                          * for 'nvec'
3492                          */
3493                         index = msi_alloc_irte(dev, irq, nvec);
3494                         if (index < 0) {
3495                                 ret = index;
3496                                 goto error;
3497                         }
3498                 } else {
3499                         iommu = map_dev_to_ir(dev);
3500                         if (!iommu) {
3501                                 ret = -ENOENT;
3502                                 goto error;
3503                         }
3504                         /*
3505                          * setup the mapping between the irq and the IRTE
3506                          * base index, the sub_handle pointing to the
3507                          * appropriate interrupt remap table entry.
3508                          */
3509                         set_irte_irq(irq, iommu, index, sub_handle);
3510                 }
3511 no_ir:
3512                 ret = setup_msi_irq(dev, msidesc, irq);
3513                 if (ret < 0)
3514                         goto error;
3515                 sub_handle++;
3516         }
3517         return 0;
3518
3519 error:
3520         destroy_irq(irq);
3521         return ret;
3522 }
3523
3524 void arch_teardown_msi_irq(unsigned int irq)
3525 {
3526         destroy_irq(irq);
3527 }
3528
3529 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3530 #ifdef CONFIG_SMP
3531 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3532 {
3533         struct irq_desc *desc = irq_to_desc(irq);
3534         struct irq_cfg *cfg;
3535         struct msi_msg msg;
3536         unsigned int dest;
3537
3538         dest = set_desc_affinity(desc, mask);
3539         if (dest == BAD_APICID)
3540                 return;
3541
3542         cfg = desc->chip_data;
3543
3544         dmar_msi_read(irq, &msg);
3545
3546         msg.data &= ~MSI_DATA_VECTOR_MASK;
3547         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3548         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3549         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3550
3551         dmar_msi_write(irq, &msg);
3552 }
3553
3554 #endif /* CONFIG_SMP */
3555
3556 struct irq_chip dmar_msi_type = {
3557         .name = "DMAR_MSI",
3558         .unmask = dmar_msi_unmask,
3559         .mask = dmar_msi_mask,
3560         .ack = ack_apic_edge,
3561 #ifdef CONFIG_SMP
3562         .set_affinity = dmar_msi_set_affinity,
3563 #endif
3564         .retrigger = ioapic_retrigger_irq,
3565 };
3566
3567 int arch_setup_dmar_msi(unsigned int irq)
3568 {
3569         int ret;
3570         struct msi_msg msg;
3571
3572         ret = msi_compose_msg(NULL, irq, &msg);
3573         if (ret < 0)
3574                 return ret;
3575         dmar_msi_write(irq, &msg);
3576         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3577                 "edge");
3578         return 0;
3579 }
3580 #endif
3581
3582 #ifdef CONFIG_HPET_TIMER
3583
3584 #ifdef CONFIG_SMP
3585 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3586 {
3587         struct irq_desc *desc = irq_to_desc(irq);
3588         struct irq_cfg *cfg;
3589         struct msi_msg msg;
3590         unsigned int dest;
3591
3592         dest = set_desc_affinity(desc, mask);
3593         if (dest == BAD_APICID)
3594                 return;
3595
3596         cfg = desc->chip_data;
3597
3598         hpet_msi_read(irq, &msg);
3599
3600         msg.data &= ~MSI_DATA_VECTOR_MASK;
3601         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3602         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3603         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3604
3605         hpet_msi_write(irq, &msg);
3606 }
3607
3608 #endif /* CONFIG_SMP */
3609
3610 static struct irq_chip hpet_msi_type = {
3611         .name = "HPET_MSI",
3612         .unmask = hpet_msi_unmask,
3613         .mask = hpet_msi_mask,
3614         .ack = ack_apic_edge,
3615 #ifdef CONFIG_SMP
3616         .set_affinity = hpet_msi_set_affinity,
3617 #endif
3618         .retrigger = ioapic_retrigger_irq,
3619 };
3620
3621 int arch_setup_hpet_msi(unsigned int irq)
3622 {
3623         int ret;
3624         struct msi_msg msg;
3625         struct irq_desc *desc = irq_to_desc(irq);
3626
3627         ret = msi_compose_msg(NULL, irq, &msg);
3628         if (ret < 0)
3629                 return ret;
3630
3631         hpet_msi_write(irq, &msg);
3632         desc->status |= IRQ_MOVE_PCNTXT;
3633         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3634                 "edge");
3635
3636         return 0;
3637 }
3638 #endif
3639
3640 #endif /* CONFIG_PCI_MSI */
3641 /*
3642  * Hypertransport interrupt support
3643  */
3644 #ifdef CONFIG_HT_IRQ
3645
3646 #ifdef CONFIG_SMP
3647
3648 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3649 {
3650         struct ht_irq_msg msg;
3651         fetch_ht_irq_msg(irq, &msg);
3652
3653         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3654         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3655
3656         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3657         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3658
3659         write_ht_irq_msg(irq, &msg);
3660 }
3661
3662 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3663 {
3664         struct irq_desc *desc = irq_to_desc(irq);
3665         struct irq_cfg *cfg;
3666         unsigned int dest;
3667
3668         dest = set_desc_affinity(desc, mask);
3669         if (dest == BAD_APICID)
3670                 return;
3671
3672         cfg = desc->chip_data;
3673
3674         target_ht_irq(irq, dest, cfg->vector);
3675 }
3676
3677 #endif
3678
3679 static struct irq_chip ht_irq_chip = {
3680         .name           = "PCI-HT",
3681         .mask           = mask_ht_irq,
3682         .unmask         = unmask_ht_irq,
3683         .ack            = ack_apic_edge,
3684 #ifdef CONFIG_SMP
3685         .set_affinity   = set_ht_irq_affinity,
3686 #endif
3687         .retrigger      = ioapic_retrigger_irq,
3688 };
3689
3690 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3691 {
3692         struct irq_cfg *cfg;
3693         int err;
3694
3695         if (disable_apic)
3696                 return -ENXIO;
3697
3698         cfg = irq_cfg(irq);
3699         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3700         if (!err) {
3701                 struct ht_irq_msg msg;
3702                 unsigned dest;
3703
3704                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3705                                                     apic->target_cpus());
3706
3707                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3708
3709                 msg.address_lo =
3710                         HT_IRQ_LOW_BASE |
3711                         HT_IRQ_LOW_DEST_ID(dest) |
3712                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3713                         ((apic->irq_dest_mode == 0) ?
3714                                 HT_IRQ_LOW_DM_PHYSICAL :
3715                                 HT_IRQ_LOW_DM_LOGICAL) |
3716                         HT_IRQ_LOW_RQEOI_EDGE |
3717                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3718                                 HT_IRQ_LOW_MT_FIXED :
3719                                 HT_IRQ_LOW_MT_ARBITRATED) |
3720                         HT_IRQ_LOW_IRQ_MASKED;
3721
3722                 write_ht_irq_msg(irq, &msg);
3723
3724                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3725                                               handle_edge_irq, "edge");
3726
3727                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3728         }
3729         return err;
3730 }
3731 #endif /* CONFIG_HT_IRQ */
3732
3733 #ifdef CONFIG_X86_UV
3734 /*
3735  * Re-target the irq to the specified CPU and enable the specified MMR located
3736  * on the specified blade to allow the sending of MSIs to the specified CPU.
3737  */
3738 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3739                        unsigned long mmr_offset)
3740 {
3741         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3742         struct irq_cfg *cfg;
3743         int mmr_pnode;
3744         unsigned long mmr_value;
3745         struct uv_IO_APIC_route_entry *entry;
3746         unsigned long flags;
3747         int err;
3748
3749         cfg = irq_cfg(irq);
3750
3751         err = assign_irq_vector(irq, cfg, eligible_cpu);
3752         if (err != 0)
3753                 return err;
3754
3755         spin_lock_irqsave(&vector_lock, flags);
3756         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3757                                       irq_name);
3758         spin_unlock_irqrestore(&vector_lock, flags);
3759
3760         mmr_value = 0;
3761         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3762         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3763
3764         entry->vector = cfg->vector;
3765         entry->delivery_mode = apic->irq_delivery_mode;
3766         entry->dest_mode = apic->irq_dest_mode;
3767         entry->polarity = 0;
3768         entry->trigger = 0;
3769         entry->mask = 0;
3770         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3771
3772         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3773         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3774
3775         return irq;
3776 }
3777
3778 /*
3779  * Disable the specified MMR located on the specified blade so that MSIs are
3780  * longer allowed to be sent.
3781  */
3782 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3783 {
3784         unsigned long mmr_value;
3785         struct uv_IO_APIC_route_entry *entry;
3786         int mmr_pnode;
3787
3788         mmr_value = 0;
3789         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3790         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3791
3792         entry->mask = 1;
3793
3794         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3795         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3796 }
3797 #endif /* CONFIG_X86_64 */
3798
3799 int __init io_apic_get_redir_entries (int ioapic)
3800 {
3801         union IO_APIC_reg_01    reg_01;
3802         unsigned long flags;
3803
3804         spin_lock_irqsave(&ioapic_lock, flags);
3805         reg_01.raw = io_apic_read(ioapic, 1);
3806         spin_unlock_irqrestore(&ioapic_lock, flags);
3807
3808         return reg_01.bits.entries;
3809 }
3810
3811 void __init probe_nr_irqs_gsi(void)
3812 {
3813         int nr = 0;
3814
3815         nr = acpi_probe_gsi();
3816         if (nr > nr_irqs_gsi) {
3817                 nr_irqs_gsi = nr;
3818         } else {
3819                 /* for acpi=off or acpi is not compiled in */
3820                 int idx;
3821
3822                 nr = 0;
3823                 for (idx = 0; idx < nr_ioapics; idx++)
3824                         nr += io_apic_get_redir_entries(idx) + 1;
3825
3826                 if (nr > nr_irqs_gsi)
3827                         nr_irqs_gsi = nr;
3828         }
3829
3830         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3831 }
3832
3833 #ifdef CONFIG_SPARSE_IRQ
3834 int __init arch_probe_nr_irqs(void)
3835 {
3836         int nr;
3837
3838         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3839                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3840
3841         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3842 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3843         /*
3844          * for MSI and HT dyn irq
3845          */
3846         nr += nr_irqs_gsi * 16;
3847 #endif
3848         if (nr < nr_irqs)
3849                 nr_irqs = nr;
3850
3851         return 0;
3852 }
3853 #endif
3854
3855 /* --------------------------------------------------------------------------
3856                           ACPI-based IOAPIC Configuration
3857    -------------------------------------------------------------------------- */
3858
3859 #ifdef CONFIG_ACPI
3860
3861 #ifdef CONFIG_X86_32
3862 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3863 {
3864         union IO_APIC_reg_00 reg_00;
3865         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3866         physid_mask_t tmp;
3867         unsigned long flags;
3868         int i = 0;
3869
3870         /*
3871          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3872          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3873          * supports up to 16 on one shared APIC bus.
3874          *
3875          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3876          *      advantage of new APIC bus architecture.
3877          */
3878
3879         if (physids_empty(apic_id_map))
3880                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3881
3882         spin_lock_irqsave(&ioapic_lock, flags);
3883         reg_00.raw = io_apic_read(ioapic, 0);
3884         spin_unlock_irqrestore(&ioapic_lock, flags);
3885
3886         if (apic_id >= get_physical_broadcast()) {
3887                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3888                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3889                 apic_id = reg_00.bits.ID;
3890         }
3891
3892         /*
3893          * Every APIC in a system must have a unique ID or we get lots of nice
3894          * 'stuck on smp_invalidate_needed IPI wait' messages.
3895          */
3896         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3897
3898                 for (i = 0; i < get_physical_broadcast(); i++) {
3899                         if (!apic->check_apicid_used(apic_id_map, i))
3900                                 break;
3901                 }
3902
3903                 if (i == get_physical_broadcast())
3904                         panic("Max apic_id exceeded!\n");
3905
3906                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3907                         "trying %d\n", ioapic, apic_id, i);
3908
3909                 apic_id = i;
3910         }
3911
3912         tmp = apic->apicid_to_cpu_present(apic_id);
3913         physids_or(apic_id_map, apic_id_map, tmp);
3914
3915         if (reg_00.bits.ID != apic_id) {
3916                 reg_00.bits.ID = apic_id;
3917
3918                 spin_lock_irqsave(&ioapic_lock, flags);
3919                 io_apic_write(ioapic, 0, reg_00.raw);
3920                 reg_00.raw = io_apic_read(ioapic, 0);
3921                 spin_unlock_irqrestore(&ioapic_lock, flags);
3922
3923                 /* Sanity check */
3924                 if (reg_00.bits.ID != apic_id) {
3925                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3926                         return -1;
3927                 }
3928         }
3929
3930         apic_printk(APIC_VERBOSE, KERN_INFO
3931                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3932
3933         return apic_id;
3934 }
3935
3936 int __init io_apic_get_version(int ioapic)
3937 {
3938         union IO_APIC_reg_01    reg_01;
3939         unsigned long flags;
3940
3941         spin_lock_irqsave(&ioapic_lock, flags);
3942         reg_01.raw = io_apic_read(ioapic, 1);
3943         spin_unlock_irqrestore(&ioapic_lock, flags);
3944
3945         return reg_01.bits.version;
3946 }
3947 #endif
3948
3949 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3950 {
3951         struct irq_desc *desc;
3952         struct irq_cfg *cfg;
3953         int cpu = boot_cpu_id;
3954
3955         if (!IO_APIC_IRQ(irq)) {
3956                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3957                         ioapic);
3958                 return -EINVAL;
3959         }
3960
3961         desc = irq_to_desc_alloc_cpu(irq, cpu);
3962         if (!desc) {
3963                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3964                 return 0;
3965         }
3966
3967         /*
3968          * IRQs < 16 are already in the irq_2_pin[] map
3969          */
3970         if (irq >= NR_IRQS_LEGACY) {
3971                 cfg = desc->chip_data;
3972                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3973         }
3974
3975         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3976
3977         return 0;
3978 }
3979
3980
3981 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3982 {
3983         int i;
3984
3985         if (skip_ioapic_setup)
3986                 return -1;
3987
3988         for (i = 0; i < mp_irq_entries; i++)
3989                 if (mp_irqs[i].irqtype == mp_INT &&
3990                     mp_irqs[i].srcbusirq == bus_irq)
3991                         break;
3992         if (i >= mp_irq_entries)
3993                 return -1;
3994
3995         *trigger = irq_trigger(i);
3996         *polarity = irq_polarity(i);
3997         return 0;
3998 }
3999
4000 #endif /* CONFIG_ACPI */
4001
4002 /*
4003  * This function currently is only a helper for the i386 smp boot process where
4004  * we need to reprogram the ioredtbls to cater for the cpus which have come online
4005  * so mask in all cases should simply be apic->target_cpus()
4006  */
4007 #ifdef CONFIG_SMP
4008 void __init setup_ioapic_dest(void)
4009 {
4010         int pin, ioapic, irq, irq_entry;
4011         struct irq_desc *desc;
4012         struct irq_cfg *cfg;
4013         const struct cpumask *mask;
4014
4015         if (skip_ioapic_setup == 1)
4016                 return;
4017
4018         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4019                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4020                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4021                         if (irq_entry == -1)
4022                                 continue;
4023                         irq = pin_2_irq(irq_entry, ioapic, pin);
4024
4025                         /* setup_IO_APIC_irqs could fail to get vector for some device
4026                          * when you have too many devices, because at that time only boot
4027                          * cpu is online.
4028                          */
4029                         desc = irq_to_desc(irq);
4030                         cfg = desc->chip_data;
4031                         if (!cfg->vector) {
4032                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4033                                                   irq_trigger(irq_entry),
4034                                                   irq_polarity(irq_entry));
4035                                 continue;
4036
4037                         }
4038
4039                         /*
4040                          * Honour affinities which have been set in early boot
4041                          */
4042                         if (desc->status &
4043                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4044                                 mask = desc->affinity;
4045                         else
4046                                 mask = apic->target_cpus();
4047
4048                         if (intr_remapping_enabled)
4049                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4050                         else
4051                                 set_ioapic_affinity_irq_desc(desc, mask);
4052                 }
4053
4054         }
4055 }
4056 #endif
4057
4058 #define IOAPIC_RESOURCE_NAME_SIZE 11
4059
4060 static struct resource *ioapic_resources;
4061
4062 static struct resource * __init ioapic_setup_resources(void)
4063 {
4064         unsigned long n;
4065         struct resource *res;
4066         char *mem;
4067         int i;
4068
4069         if (nr_ioapics <= 0)
4070                 return NULL;
4071
4072         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4073         n *= nr_ioapics;
4074
4075         mem = alloc_bootmem(n);
4076         res = (void *)mem;
4077
4078         if (mem != NULL) {
4079                 mem += sizeof(struct resource) * nr_ioapics;
4080
4081                 for (i = 0; i < nr_ioapics; i++) {
4082                         res[i].name = mem;
4083                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4084                         sprintf(mem,  "IOAPIC %u", i);
4085                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4086                 }
4087         }
4088
4089         ioapic_resources = res;
4090
4091         return res;
4092 }
4093
4094 void __init ioapic_init_mappings(void)
4095 {
4096         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4097         struct resource *ioapic_res;
4098         int i;
4099
4100         ioapic_res = ioapic_setup_resources();
4101         for (i = 0; i < nr_ioapics; i++) {
4102                 if (smp_found_config) {
4103                         ioapic_phys = mp_ioapics[i].apicaddr;
4104 #ifdef CONFIG_X86_32
4105                         if (!ioapic_phys) {
4106                                 printk(KERN_ERR
4107                                        "WARNING: bogus zero IO-APIC "
4108                                        "address found in MPTABLE, "
4109                                        "disabling IO/APIC support!\n");
4110                                 smp_found_config = 0;
4111                                 skip_ioapic_setup = 1;
4112                                 goto fake_ioapic_page;
4113                         }
4114 #endif
4115                 } else {
4116 #ifdef CONFIG_X86_32
4117 fake_ioapic_page:
4118 #endif
4119                         ioapic_phys = (unsigned long)
4120                                 alloc_bootmem_pages(PAGE_SIZE);
4121                         ioapic_phys = __pa(ioapic_phys);
4122                 }
4123                 set_fixmap_nocache(idx, ioapic_phys);
4124                 apic_printk(APIC_VERBOSE,
4125                             "mapped IOAPIC to %08lx (%08lx)\n",
4126                             __fix_to_virt(idx), ioapic_phys);
4127                 idx++;
4128
4129                 if (ioapic_res != NULL) {
4130                         ioapic_res->start = ioapic_phys;
4131                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4132                         ioapic_res++;
4133                 }
4134         }
4135 }
4136
4137 static int __init ioapic_insert_resources(void)
4138 {
4139         int i;
4140         struct resource *r = ioapic_resources;
4141
4142         if (!r) {
4143                 if (nr_ioapics > 0) {
4144                         printk(KERN_ERR
4145                                 "IO APIC resources couldn't be allocated.\n");
4146                         return -1;
4147                 }
4148                 return 0;
4149         }
4150
4151         for (i = 0; i < nr_ioapics; i++) {
4152                 insert_resource(&iomem_resource, r);
4153                 r++;
4154         }
4155
4156         return 0;
4157 }
4158
4159 /* Insert the IO APIC resources after PCI initialization has occured to handle
4160  * IO APICS that are mapped in on a BAR in PCI space. */
4161 late_initcall(ioapic_insert_resources);