1946fac42ab3cb8a406d46509a983163cd347008
[linux-2.6.git] / arch / x86 / kernel / apic / io_apic.c
1 /*
2  *      Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5  *
6  *      Many thanks to Stig Venaas for trying out countless experimental
7  *      patches and reporting/debugging problems patiently!
8  *
9  *      (c) 1999, Multiple IO-APIC support, developed by
10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *      and Ingo Molnar <mingo@redhat.com>
14  *
15  *      Fixes
16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
17  *                                      thanks to Eric Gilmore
18  *                                      and Rolf G. Tews
19  *                                      for testing these extensively
20  *      Paul Diefenbaugh        :       Added full ACPI support
21  */
22
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h>      /* time_after() */
39 #ifdef CONFIG_ACPI
40 #include <acpi/acpi_bus.h>
41 #endif
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
45
46 #include <asm/idle.h>
47 #include <asm/io.h>
48 #include <asm/smp.h>
49 #include <asm/cpu.h>
50 #include <asm/desc.h>
51 #include <asm/proto.h>
52 #include <asm/acpi.h>
53 #include <asm/dma.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
56 #include <asm/nmi.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
61 #include <asm/hpet.h>
62 #include <asm/hw_irq.h>
63 #include <asm/uv/uv_hub.h>
64 #include <asm/uv/uv_irq.h>
65
66 #include <asm/apic.h>
67
68 #define __apicdebuginit(type) static type __init
69
70 /*
71  *      Is the SiS APIC rmw bug present ?
72  *      -1 = don't know, 0 = no, 1 = yes
73  */
74 int sis_apic_bug = -1;
75
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
78
79 /*
80  * # of IRQ routing registers
81  */
82 int nr_ioapic_registers[MAX_IO_APICS];
83
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
86 int nr_ioapics;
87
88 /* MP IRQ source entries */
89 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
90
91 /* # of MP IRQ source entries */
92 int mp_irq_entries;
93
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type[MAX_MP_BUSSES];
96 #endif
97
98 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
99
100 int skip_ioapic_setup;
101
102 void arch_disable_smp_support(void)
103 {
104 #ifdef CONFIG_PCI
105         noioapicquirk = 1;
106         noioapicreroute = -1;
107 #endif
108         skip_ioapic_setup = 1;
109 }
110
111 static int __init parse_noapic(char *str)
112 {
113         /* disable IO-APIC */
114         arch_disable_smp_support();
115         return 0;
116 }
117 early_param("noapic", parse_noapic);
118
119 struct irq_pin_list;
120
121 /*
122  * This is performance-critical, we want to do it O(1)
123  *
124  * the indexing order of this array favors 1:1 mappings
125  * between pins and IRQs.
126  */
127
128 struct irq_pin_list {
129         int apic, pin;
130         struct irq_pin_list *next;
131 };
132
133 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
134 {
135         struct irq_pin_list *pin;
136
137         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
138
139         return pin;
140 }
141
142 struct irq_cfg {
143         struct irq_pin_list *irq_2_pin;
144         cpumask_var_t domain;
145         cpumask_var_t old_domain;
146         unsigned move_cleanup_count;
147         u8 vector;
148         u8 move_in_progress : 1;
149 };
150
151 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
152 #ifdef CONFIG_SPARSE_IRQ
153 static struct irq_cfg irq_cfgx[] = {
154 #else
155 static struct irq_cfg irq_cfgx[NR_IRQS] = {
156 #endif
157         [0]  = { .vector = IRQ0_VECTOR,  },
158         [1]  = { .vector = IRQ1_VECTOR,  },
159         [2]  = { .vector = IRQ2_VECTOR,  },
160         [3]  = { .vector = IRQ3_VECTOR,  },
161         [4]  = { .vector = IRQ4_VECTOR,  },
162         [5]  = { .vector = IRQ5_VECTOR,  },
163         [6]  = { .vector = IRQ6_VECTOR,  },
164         [7]  = { .vector = IRQ7_VECTOR,  },
165         [8]  = { .vector = IRQ8_VECTOR,  },
166         [9]  = { .vector = IRQ9_VECTOR,  },
167         [10] = { .vector = IRQ10_VECTOR, },
168         [11] = { .vector = IRQ11_VECTOR, },
169         [12] = { .vector = IRQ12_VECTOR, },
170         [13] = { .vector = IRQ13_VECTOR, },
171         [14] = { .vector = IRQ14_VECTOR, },
172         [15] = { .vector = IRQ15_VECTOR, },
173 };
174
175 int __init arch_early_irq_init(void)
176 {
177         struct irq_cfg *cfg;
178         struct irq_desc *desc;
179         int count;
180         int i;
181
182         cfg = irq_cfgx;
183         count = ARRAY_SIZE(irq_cfgx);
184
185         for (i = 0; i < count; i++) {
186                 desc = irq_to_desc(i);
187                 desc->chip_data = &cfg[i];
188                 alloc_bootmem_cpumask_var(&cfg[i].domain);
189                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
190                 if (i < NR_IRQS_LEGACY)
191                         cpumask_setall(cfg[i].domain);
192         }
193
194         return 0;
195 }
196
197 #ifdef CONFIG_SPARSE_IRQ
198 static struct irq_cfg *irq_cfg(unsigned int irq)
199 {
200         struct irq_cfg *cfg = NULL;
201         struct irq_desc *desc;
202
203         desc = irq_to_desc(irq);
204         if (desc)
205                 cfg = desc->chip_data;
206
207         return cfg;
208 }
209
210 static struct irq_cfg *get_one_free_irq_cfg(int node)
211 {
212         struct irq_cfg *cfg;
213
214         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
215         if (cfg) {
216                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
217                         kfree(cfg);
218                         cfg = NULL;
219                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
220                                                           GFP_ATOMIC, node)) {
221                         free_cpumask_var(cfg->domain);
222                         kfree(cfg);
223                         cfg = NULL;
224                 } else {
225                         cpumask_clear(cfg->domain);
226                         cpumask_clear(cfg->old_domain);
227                 }
228         }
229
230         return cfg;
231 }
232
233 int arch_init_chip_data(struct irq_desc *desc, int node)
234 {
235         struct irq_cfg *cfg;
236
237         cfg = desc->chip_data;
238         if (!cfg) {
239                 desc->chip_data = get_one_free_irq_cfg(node);
240                 if (!desc->chip_data) {
241                         printk(KERN_ERR "can not alloc irq_cfg\n");
242                         BUG_ON(1);
243                 }
244         }
245
246         return 0;
247 }
248
249 /* for move_irq_desc */
250 static void
251 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
252 {
253         struct irq_pin_list *old_entry, *head, *tail, *entry;
254
255         cfg->irq_2_pin = NULL;
256         old_entry = old_cfg->irq_2_pin;
257         if (!old_entry)
258                 return;
259
260         entry = get_one_free_irq_2_pin(node);
261         if (!entry)
262                 return;
263
264         entry->apic     = old_entry->apic;
265         entry->pin      = old_entry->pin;
266         head            = entry;
267         tail            = entry;
268         old_entry       = old_entry->next;
269         while (old_entry) {
270                 entry = get_one_free_irq_2_pin(node);
271                 if (!entry) {
272                         entry = head;
273                         while (entry) {
274                                 head = entry->next;
275                                 kfree(entry);
276                                 entry = head;
277                         }
278                         /* still use the old one */
279                         return;
280                 }
281                 entry->apic     = old_entry->apic;
282                 entry->pin      = old_entry->pin;
283                 tail->next      = entry;
284                 tail            = entry;
285                 old_entry       = old_entry->next;
286         }
287
288         tail->next = NULL;
289         cfg->irq_2_pin = head;
290 }
291
292 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
293 {
294         struct irq_pin_list *entry, *next;
295
296         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
297                 return;
298
299         entry = old_cfg->irq_2_pin;
300
301         while (entry) {
302                 next = entry->next;
303                 kfree(entry);
304                 entry = next;
305         }
306         old_cfg->irq_2_pin = NULL;
307 }
308
309 void arch_init_copy_chip_data(struct irq_desc *old_desc,
310                                  struct irq_desc *desc, int node)
311 {
312         struct irq_cfg *cfg;
313         struct irq_cfg *old_cfg;
314
315         cfg = get_one_free_irq_cfg(node);
316
317         if (!cfg)
318                 return;
319
320         desc->chip_data = cfg;
321
322         old_cfg = old_desc->chip_data;
323
324         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
325
326         init_copy_irq_2_pin(old_cfg, cfg, node);
327 }
328
329 static void free_irq_cfg(struct irq_cfg *old_cfg)
330 {
331         kfree(old_cfg);
332 }
333
334 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
335 {
336         struct irq_cfg *old_cfg, *cfg;
337
338         old_cfg = old_desc->chip_data;
339         cfg = desc->chip_data;
340
341         if (old_cfg == cfg)
342                 return;
343
344         if (old_cfg) {
345                 free_irq_2_pin(old_cfg, cfg);
346                 free_irq_cfg(old_cfg);
347                 old_desc->chip_data = NULL;
348         }
349 }
350 /* end for move_irq_desc */
351
352 #else
353 static struct irq_cfg *irq_cfg(unsigned int irq)
354 {
355         return irq < nr_irqs ? irq_cfgx + irq : NULL;
356 }
357
358 #endif
359
360 struct io_apic {
361         unsigned int index;
362         unsigned int unused[3];
363         unsigned int data;
364         unsigned int unused2[11];
365         unsigned int eoi;
366 };
367
368 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
369 {
370         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
371                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
372 }
373
374 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
375 {
376         struct io_apic __iomem *io_apic = io_apic_base(apic);
377         writel(vector, &io_apic->eoi);
378 }
379
380 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
381 {
382         struct io_apic __iomem *io_apic = io_apic_base(apic);
383         writel(reg, &io_apic->index);
384         return readl(&io_apic->data);
385 }
386
387 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
388 {
389         struct io_apic __iomem *io_apic = io_apic_base(apic);
390         writel(reg, &io_apic->index);
391         writel(value, &io_apic->data);
392 }
393
394 /*
395  * Re-write a value: to be used for read-modify-write
396  * cycles where the read already set up the index register.
397  *
398  * Older SiS APIC requires we rewrite the index register
399  */
400 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
401 {
402         struct io_apic __iomem *io_apic = io_apic_base(apic);
403
404         if (sis_apic_bug)
405                 writel(reg, &io_apic->index);
406         writel(value, &io_apic->data);
407 }
408
409 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
410 {
411         struct irq_pin_list *entry;
412         unsigned long flags;
413
414         spin_lock_irqsave(&ioapic_lock, flags);
415         entry = cfg->irq_2_pin;
416         for (;;) {
417                 unsigned int reg;
418                 int pin;
419
420                 if (!entry)
421                         break;
422                 pin = entry->pin;
423                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
424                 /* Is the remote IRR bit set? */
425                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
426                         spin_unlock_irqrestore(&ioapic_lock, flags);
427                         return true;
428                 }
429                 if (!entry->next)
430                         break;
431                 entry = entry->next;
432         }
433         spin_unlock_irqrestore(&ioapic_lock, flags);
434
435         return false;
436 }
437
438 union entry_union {
439         struct { u32 w1, w2; };
440         struct IO_APIC_route_entry entry;
441 };
442
443 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
444 {
445         union entry_union eu;
446         unsigned long flags;
447         spin_lock_irqsave(&ioapic_lock, flags);
448         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
449         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
450         spin_unlock_irqrestore(&ioapic_lock, flags);
451         return eu.entry;
452 }
453
454 /*
455  * When we write a new IO APIC routing entry, we need to write the high
456  * word first! If the mask bit in the low word is clear, we will enable
457  * the interrupt, and we need to make sure the entry is fully populated
458  * before that happens.
459  */
460 static void
461 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
462 {
463         union entry_union eu;
464         eu.entry = e;
465         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
466         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
467 }
468
469 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
470 {
471         unsigned long flags;
472         spin_lock_irqsave(&ioapic_lock, flags);
473         __ioapic_write_entry(apic, pin, e);
474         spin_unlock_irqrestore(&ioapic_lock, flags);
475 }
476
477 /*
478  * When we mask an IO APIC routing entry, we need to write the low
479  * word first, in order to set the mask bit before we change the
480  * high bits!
481  */
482 static void ioapic_mask_entry(int apic, int pin)
483 {
484         unsigned long flags;
485         union entry_union eu = { .entry.mask = 1 };
486
487         spin_lock_irqsave(&ioapic_lock, flags);
488         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
489         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
490         spin_unlock_irqrestore(&ioapic_lock, flags);
491 }
492
493 /*
494  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
495  * shared ISA-space IRQs, so we have to support them. We are super
496  * fast in the common case, and fast for shared ISA-space IRQs.
497  */
498 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
499 {
500         struct irq_pin_list *entry;
501
502         entry = cfg->irq_2_pin;
503         if (!entry) {
504                 entry = get_one_free_irq_2_pin(node);
505                 if (!entry) {
506                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
507                                         apic, pin);
508                         return;
509                 }
510                 cfg->irq_2_pin = entry;
511                 entry->apic = apic;
512                 entry->pin = pin;
513                 return;
514         }
515
516         while (entry->next) {
517                 /* not again, please */
518                 if (entry->apic == apic && entry->pin == pin)
519                         return;
520
521                 entry = entry->next;
522         }
523
524         entry->next = get_one_free_irq_2_pin(node);
525         entry = entry->next;
526         entry->apic = apic;
527         entry->pin = pin;
528 }
529
530 /*
531  * Reroute an IRQ to a different pin.
532  */
533 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
534                                       int oldapic, int oldpin,
535                                       int newapic, int newpin)
536 {
537         struct irq_pin_list *entry = cfg->irq_2_pin;
538         int replaced = 0;
539
540         while (entry) {
541                 if (entry->apic == oldapic && entry->pin == oldpin) {
542                         entry->apic = newapic;
543                         entry->pin = newpin;
544                         replaced = 1;
545                         /* every one is different, right? */
546                         break;
547                 }
548                 entry = entry->next;
549         }
550
551         /* why? call replace before add? */
552         if (!replaced)
553                 add_pin_to_irq_node(cfg, node, newapic, newpin);
554 }
555
556 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
557                                 int mask_and, int mask_or,
558                                 void (*final)(struct irq_pin_list *entry))
559 {
560         int pin;
561         struct irq_pin_list *entry;
562
563         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
564                 unsigned int reg;
565                 pin = entry->pin;
566                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
567                 reg &= mask_and;
568                 reg |= mask_or;
569                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
570                 if (final)
571                         final(entry);
572         }
573 }
574
575 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
576 {
577         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
578 }
579
580 #ifdef CONFIG_X86_64
581 static void io_apic_sync(struct irq_pin_list *entry)
582 {
583         /*
584          * Synchronize the IO-APIC and the CPU by doing
585          * a dummy read from the IO-APIC
586          */
587         struct io_apic __iomem *io_apic;
588         io_apic = io_apic_base(entry->apic);
589         readl(&io_apic->data);
590 }
591
592 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
593 {
594         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
595 }
596 #else /* CONFIG_X86_32 */
597 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
598 {
599         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
600 }
601
602 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
603 {
604         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
605                         IO_APIC_REDIR_MASKED, NULL);
606 }
607
608 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
609 {
610         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
611                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
612 }
613 #endif /* CONFIG_X86_32 */
614
615 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
616 {
617         struct irq_cfg *cfg = desc->chip_data;
618         unsigned long flags;
619
620         BUG_ON(!cfg);
621
622         spin_lock_irqsave(&ioapic_lock, flags);
623         __mask_IO_APIC_irq(cfg);
624         spin_unlock_irqrestore(&ioapic_lock, flags);
625 }
626
627 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
628 {
629         struct irq_cfg *cfg = desc->chip_data;
630         unsigned long flags;
631
632         spin_lock_irqsave(&ioapic_lock, flags);
633         __unmask_IO_APIC_irq(cfg);
634         spin_unlock_irqrestore(&ioapic_lock, flags);
635 }
636
637 static void mask_IO_APIC_irq(unsigned int irq)
638 {
639         struct irq_desc *desc = irq_to_desc(irq);
640
641         mask_IO_APIC_irq_desc(desc);
642 }
643 static void unmask_IO_APIC_irq(unsigned int irq)
644 {
645         struct irq_desc *desc = irq_to_desc(irq);
646
647         unmask_IO_APIC_irq_desc(desc);
648 }
649
650 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
651 {
652         struct IO_APIC_route_entry entry;
653
654         /* Check delivery_mode to be sure we're not clearing an SMI pin */
655         entry = ioapic_read_entry(apic, pin);
656         if (entry.delivery_mode == dest_SMI)
657                 return;
658         /*
659          * Disable it in the IO-APIC irq-routing table:
660          */
661         ioapic_mask_entry(apic, pin);
662 }
663
664 static void clear_IO_APIC (void)
665 {
666         int apic, pin;
667
668         for (apic = 0; apic < nr_ioapics; apic++)
669                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
670                         clear_IO_APIC_pin(apic, pin);
671 }
672
673 #ifdef CONFIG_X86_32
674 /*
675  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
676  * specific CPU-side IRQs.
677  */
678
679 #define MAX_PIRQS 8
680 static int pirq_entries[MAX_PIRQS] = {
681         [0 ... MAX_PIRQS - 1] = -1
682 };
683
684 static int __init ioapic_pirq_setup(char *str)
685 {
686         int i, max;
687         int ints[MAX_PIRQS+1];
688
689         get_options(str, ARRAY_SIZE(ints), ints);
690
691         apic_printk(APIC_VERBOSE, KERN_INFO
692                         "PIRQ redirection, working around broken MP-BIOS.\n");
693         max = MAX_PIRQS;
694         if (ints[0] < MAX_PIRQS)
695                 max = ints[0];
696
697         for (i = 0; i < max; i++) {
698                 apic_printk(APIC_VERBOSE, KERN_DEBUG
699                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
700                 /*
701                  * PIRQs are mapped upside down, usually.
702                  */
703                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
704         }
705         return 1;
706 }
707
708 __setup("pirq=", ioapic_pirq_setup);
709 #endif /* CONFIG_X86_32 */
710
711 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
712 {
713         int apic;
714         struct IO_APIC_route_entry **ioapic_entries;
715
716         ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
717                                 GFP_ATOMIC);
718         if (!ioapic_entries)
719                 return 0;
720
721         for (apic = 0; apic < nr_ioapics; apic++) {
722                 ioapic_entries[apic] =
723                         kzalloc(sizeof(struct IO_APIC_route_entry) *
724                                 nr_ioapic_registers[apic], GFP_ATOMIC);
725                 if (!ioapic_entries[apic])
726                         goto nomem;
727         }
728
729         return ioapic_entries;
730
731 nomem:
732         while (--apic >= 0)
733                 kfree(ioapic_entries[apic]);
734         kfree(ioapic_entries);
735
736         return 0;
737 }
738
739 /*
740  * Saves all the IO-APIC RTE's
741  */
742 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
743 {
744         int apic, pin;
745
746         if (!ioapic_entries)
747                 return -ENOMEM;
748
749         for (apic = 0; apic < nr_ioapics; apic++) {
750                 if (!ioapic_entries[apic])
751                         return -ENOMEM;
752
753                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
754                         ioapic_entries[apic][pin] =
755                                 ioapic_read_entry(apic, pin);
756         }
757
758         return 0;
759 }
760
761 /*
762  * Mask all IO APIC entries.
763  */
764 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
765 {
766         int apic, pin;
767
768         if (!ioapic_entries)
769                 return;
770
771         for (apic = 0; apic < nr_ioapics; apic++) {
772                 if (!ioapic_entries[apic])
773                         break;
774
775                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
776                         struct IO_APIC_route_entry entry;
777
778                         entry = ioapic_entries[apic][pin];
779                         if (!entry.mask) {
780                                 entry.mask = 1;
781                                 ioapic_write_entry(apic, pin, entry);
782                         }
783                 }
784         }
785 }
786
787 /*
788  * Restore IO APIC entries which was saved in ioapic_entries.
789  */
790 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
791 {
792         int apic, pin;
793
794         if (!ioapic_entries)
795                 return -ENOMEM;
796
797         for (apic = 0; apic < nr_ioapics; apic++) {
798                 if (!ioapic_entries[apic])
799                         return -ENOMEM;
800
801                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
802                         ioapic_write_entry(apic, pin,
803                                         ioapic_entries[apic][pin]);
804         }
805         return 0;
806 }
807
808 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
809 {
810         int apic;
811
812         for (apic = 0; apic < nr_ioapics; apic++)
813                 kfree(ioapic_entries[apic]);
814
815         kfree(ioapic_entries);
816 }
817
818 /*
819  * Find the IRQ entry number of a certain pin.
820  */
821 static int find_irq_entry(int apic, int pin, int type)
822 {
823         int i;
824
825         for (i = 0; i < mp_irq_entries; i++)
826                 if (mp_irqs[i].irqtype == type &&
827                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
828                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
829                     mp_irqs[i].dstirq == pin)
830                         return i;
831
832         return -1;
833 }
834
835 /*
836  * Find the pin to which IRQ[irq] (ISA) is connected
837  */
838 static int __init find_isa_irq_pin(int irq, int type)
839 {
840         int i;
841
842         for (i = 0; i < mp_irq_entries; i++) {
843                 int lbus = mp_irqs[i].srcbus;
844
845                 if (test_bit(lbus, mp_bus_not_pci) &&
846                     (mp_irqs[i].irqtype == type) &&
847                     (mp_irqs[i].srcbusirq == irq))
848
849                         return mp_irqs[i].dstirq;
850         }
851         return -1;
852 }
853
854 static int __init find_isa_irq_apic(int irq, int type)
855 {
856         int i;
857
858         for (i = 0; i < mp_irq_entries; i++) {
859                 int lbus = mp_irqs[i].srcbus;
860
861                 if (test_bit(lbus, mp_bus_not_pci) &&
862                     (mp_irqs[i].irqtype == type) &&
863                     (mp_irqs[i].srcbusirq == irq))
864                         break;
865         }
866         if (i < mp_irq_entries) {
867                 int apic;
868                 for(apic = 0; apic < nr_ioapics; apic++) {
869                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
870                                 return apic;
871                 }
872         }
873
874         return -1;
875 }
876
877 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
878 /*
879  * EISA Edge/Level control register, ELCR
880  */
881 static int EISA_ELCR(unsigned int irq)
882 {
883         if (irq < NR_IRQS_LEGACY) {
884                 unsigned int port = 0x4d0 + (irq >> 3);
885                 return (inb(port) >> (irq & 7)) & 1;
886         }
887         apic_printk(APIC_VERBOSE, KERN_INFO
888                         "Broken MPtable reports ISA irq %d\n", irq);
889         return 0;
890 }
891
892 #endif
893
894 /* ISA interrupts are always polarity zero edge triggered,
895  * when listed as conforming in the MP table. */
896
897 #define default_ISA_trigger(idx)        (0)
898 #define default_ISA_polarity(idx)       (0)
899
900 /* EISA interrupts are always polarity zero and can be edge or level
901  * trigger depending on the ELCR value.  If an interrupt is listed as
902  * EISA conforming in the MP table, that means its trigger type must
903  * be read in from the ELCR */
904
905 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
906 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
907
908 /* PCI interrupts are always polarity one level triggered,
909  * when listed as conforming in the MP table. */
910
911 #define default_PCI_trigger(idx)        (1)
912 #define default_PCI_polarity(idx)       (1)
913
914 /* MCA interrupts are always polarity zero level triggered,
915  * when listed as conforming in the MP table. */
916
917 #define default_MCA_trigger(idx)        (1)
918 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
919
920 static int MPBIOS_polarity(int idx)
921 {
922         int bus = mp_irqs[idx].srcbus;
923         int polarity;
924
925         /*
926          * Determine IRQ line polarity (high active or low active):
927          */
928         switch (mp_irqs[idx].irqflag & 3)
929         {
930                 case 0: /* conforms, ie. bus-type dependent polarity */
931                         if (test_bit(bus, mp_bus_not_pci))
932                                 polarity = default_ISA_polarity(idx);
933                         else
934                                 polarity = default_PCI_polarity(idx);
935                         break;
936                 case 1: /* high active */
937                 {
938                         polarity = 0;
939                         break;
940                 }
941                 case 2: /* reserved */
942                 {
943                         printk(KERN_WARNING "broken BIOS!!\n");
944                         polarity = 1;
945                         break;
946                 }
947                 case 3: /* low active */
948                 {
949                         polarity = 1;
950                         break;
951                 }
952                 default: /* invalid */
953                 {
954                         printk(KERN_WARNING "broken BIOS!!\n");
955                         polarity = 1;
956                         break;
957                 }
958         }
959         return polarity;
960 }
961
962 static int MPBIOS_trigger(int idx)
963 {
964         int bus = mp_irqs[idx].srcbus;
965         int trigger;
966
967         /*
968          * Determine IRQ trigger mode (edge or level sensitive):
969          */
970         switch ((mp_irqs[idx].irqflag>>2) & 3)
971         {
972                 case 0: /* conforms, ie. bus-type dependent */
973                         if (test_bit(bus, mp_bus_not_pci))
974                                 trigger = default_ISA_trigger(idx);
975                         else
976                                 trigger = default_PCI_trigger(idx);
977 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
978                         switch (mp_bus_id_to_type[bus]) {
979                                 case MP_BUS_ISA: /* ISA pin */
980                                 {
981                                         /* set before the switch */
982                                         break;
983                                 }
984                                 case MP_BUS_EISA: /* EISA pin */
985                                 {
986                                         trigger = default_EISA_trigger(idx);
987                                         break;
988                                 }
989                                 case MP_BUS_PCI: /* PCI pin */
990                                 {
991                                         /* set before the switch */
992                                         break;
993                                 }
994                                 case MP_BUS_MCA: /* MCA pin */
995                                 {
996                                         trigger = default_MCA_trigger(idx);
997                                         break;
998                                 }
999                                 default:
1000                                 {
1001                                         printk(KERN_WARNING "broken BIOS!!\n");
1002                                         trigger = 1;
1003                                         break;
1004                                 }
1005                         }
1006 #endif
1007                         break;
1008                 case 1: /* edge */
1009                 {
1010                         trigger = 0;
1011                         break;
1012                 }
1013                 case 2: /* reserved */
1014                 {
1015                         printk(KERN_WARNING "broken BIOS!!\n");
1016                         trigger = 1;
1017                         break;
1018                 }
1019                 case 3: /* level */
1020                 {
1021                         trigger = 1;
1022                         break;
1023                 }
1024                 default: /* invalid */
1025                 {
1026                         printk(KERN_WARNING "broken BIOS!!\n");
1027                         trigger = 0;
1028                         break;
1029                 }
1030         }
1031         return trigger;
1032 }
1033
1034 static inline int irq_polarity(int idx)
1035 {
1036         return MPBIOS_polarity(idx);
1037 }
1038
1039 static inline int irq_trigger(int idx)
1040 {
1041         return MPBIOS_trigger(idx);
1042 }
1043
1044 int (*ioapic_renumber_irq)(int ioapic, int irq);
1045 static int pin_2_irq(int idx, int apic, int pin)
1046 {
1047         int irq, i;
1048         int bus = mp_irqs[idx].srcbus;
1049
1050         /*
1051          * Debugging check, we are in big trouble if this message pops up!
1052          */
1053         if (mp_irqs[idx].dstirq != pin)
1054                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1055
1056         if (test_bit(bus, mp_bus_not_pci)) {
1057                 irq = mp_irqs[idx].srcbusirq;
1058         } else {
1059                 /*
1060                  * PCI IRQs are mapped in order
1061                  */
1062                 i = irq = 0;
1063                 while (i < apic)
1064                         irq += nr_ioapic_registers[i++];
1065                 irq += pin;
1066                 /*
1067                  * For MPS mode, so far only needed by ES7000 platform
1068                  */
1069                 if (ioapic_renumber_irq)
1070                         irq = ioapic_renumber_irq(apic, irq);
1071         }
1072
1073 #ifdef CONFIG_X86_32
1074         /*
1075          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1076          */
1077         if ((pin >= 16) && (pin <= 23)) {
1078                 if (pirq_entries[pin-16] != -1) {
1079                         if (!pirq_entries[pin-16]) {
1080                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1081                                                 "disabling PIRQ%d\n", pin-16);
1082                         } else {
1083                                 irq = pirq_entries[pin-16];
1084                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1085                                                 "using PIRQ%d -> IRQ %d\n",
1086                                                 pin-16, irq);
1087                         }
1088                 }
1089         }
1090 #endif
1091
1092         return irq;
1093 }
1094
1095 /*
1096  * Find a specific PCI IRQ entry.
1097  * Not an __init, possibly needed by modules
1098  */
1099 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1100                                 struct io_apic_irq_attr *irq_attr)
1101 {
1102         int apic, i, best_guess = -1;
1103
1104         apic_printk(APIC_DEBUG,
1105                     "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1106                     bus, slot, pin);
1107         if (test_bit(bus, mp_bus_not_pci)) {
1108                 apic_printk(APIC_VERBOSE,
1109                             "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1110                 return -1;
1111         }
1112         for (i = 0; i < mp_irq_entries; i++) {
1113                 int lbus = mp_irqs[i].srcbus;
1114
1115                 for (apic = 0; apic < nr_ioapics; apic++)
1116                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1117                             mp_irqs[i].dstapic == MP_APIC_ALL)
1118                                 break;
1119
1120                 if (!test_bit(lbus, mp_bus_not_pci) &&
1121                     !mp_irqs[i].irqtype &&
1122                     (bus == lbus) &&
1123                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1124                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1125
1126                         if (!(apic || IO_APIC_IRQ(irq)))
1127                                 continue;
1128
1129                         if (pin == (mp_irqs[i].srcbusirq & 3)) {
1130                                 set_io_apic_irq_attr(irq_attr, apic,
1131                                                      mp_irqs[i].dstirq,
1132                                                      irq_trigger(i),
1133                                                      irq_polarity(i));
1134                                 return irq;
1135                         }
1136                         /*
1137                          * Use the first all-but-pin matching entry as a
1138                          * best-guess fuzzy result for broken mptables.
1139                          */
1140                         if (best_guess < 0) {
1141                                 set_io_apic_irq_attr(irq_attr, apic,
1142                                                      mp_irqs[i].dstirq,
1143                                                      irq_trigger(i),
1144                                                      irq_polarity(i));
1145                                 best_guess = irq;
1146                         }
1147                 }
1148         }
1149         return best_guess;
1150 }
1151 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1152
1153 void lock_vector_lock(void)
1154 {
1155         /* Used to the online set of cpus does not change
1156          * during assign_irq_vector.
1157          */
1158         spin_lock(&vector_lock);
1159 }
1160
1161 void unlock_vector_lock(void)
1162 {
1163         spin_unlock(&vector_lock);
1164 }
1165
1166 static int
1167 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1168 {
1169         /*
1170          * NOTE! The local APIC isn't very good at handling
1171          * multiple interrupts at the same interrupt level.
1172          * As the interrupt level is determined by taking the
1173          * vector number and shifting that right by 4, we
1174          * want to spread these out a bit so that they don't
1175          * all fall in the same interrupt level.
1176          *
1177          * Also, we've got to be careful not to trash gate
1178          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1179          */
1180         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1181         unsigned int old_vector;
1182         int cpu, err;
1183         cpumask_var_t tmp_mask;
1184
1185         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1186                 return -EBUSY;
1187
1188         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1189                 return -ENOMEM;
1190
1191         old_vector = cfg->vector;
1192         if (old_vector) {
1193                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1194                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1195                 if (!cpumask_empty(tmp_mask)) {
1196                         free_cpumask_var(tmp_mask);
1197                         return 0;
1198                 }
1199         }
1200
1201         /* Only try and allocate irqs on cpus that are present */
1202         err = -ENOSPC;
1203         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1204                 int new_cpu;
1205                 int vector, offset;
1206
1207                 apic->vector_allocation_domain(cpu, tmp_mask);
1208
1209                 vector = current_vector;
1210                 offset = current_offset;
1211 next:
1212                 vector += 8;
1213                 if (vector >= first_system_vector) {
1214                         /* If out of vectors on large boxen, must share them. */
1215                         offset = (offset + 1) % 8;
1216                         vector = FIRST_DEVICE_VECTOR + offset;
1217                 }
1218                 if (unlikely(current_vector == vector))
1219                         continue;
1220
1221                 if (test_bit(vector, used_vectors))
1222                         goto next;
1223
1224                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1225                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1226                                 goto next;
1227                 /* Found one! */
1228                 current_vector = vector;
1229                 current_offset = offset;
1230                 if (old_vector) {
1231                         cfg->move_in_progress = 1;
1232                         cpumask_copy(cfg->old_domain, cfg->domain);
1233                 }
1234                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1235                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1236                 cfg->vector = vector;
1237                 cpumask_copy(cfg->domain, tmp_mask);
1238                 err = 0;
1239                 break;
1240         }
1241         free_cpumask_var(tmp_mask);
1242         return err;
1243 }
1244
1245 static int
1246 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1247 {
1248         int err;
1249         unsigned long flags;
1250
1251         spin_lock_irqsave(&vector_lock, flags);
1252         err = __assign_irq_vector(irq, cfg, mask);
1253         spin_unlock_irqrestore(&vector_lock, flags);
1254         return err;
1255 }
1256
1257 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1258 {
1259         int cpu, vector;
1260
1261         BUG_ON(!cfg->vector);
1262
1263         vector = cfg->vector;
1264         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1265                 per_cpu(vector_irq, cpu)[vector] = -1;
1266
1267         cfg->vector = 0;
1268         cpumask_clear(cfg->domain);
1269
1270         if (likely(!cfg->move_in_progress))
1271                 return;
1272         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1273                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1274                                                                 vector++) {
1275                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1276                                 continue;
1277                         per_cpu(vector_irq, cpu)[vector] = -1;
1278                         break;
1279                 }
1280         }
1281         cfg->move_in_progress = 0;
1282 }
1283
1284 void __setup_vector_irq(int cpu)
1285 {
1286         /* Initialize vector_irq on a new cpu */
1287         /* This function must be called with vector_lock held */
1288         int irq, vector;
1289         struct irq_cfg *cfg;
1290         struct irq_desc *desc;
1291
1292         /* Mark the inuse vectors */
1293         for_each_irq_desc(irq, desc) {
1294                 cfg = desc->chip_data;
1295                 if (!cpumask_test_cpu(cpu, cfg->domain))
1296                         continue;
1297                 vector = cfg->vector;
1298                 per_cpu(vector_irq, cpu)[vector] = irq;
1299         }
1300         /* Mark the free vectors */
1301         for (vector = 0; vector < NR_VECTORS; ++vector) {
1302                 irq = per_cpu(vector_irq, cpu)[vector];
1303                 if (irq < 0)
1304                         continue;
1305
1306                 cfg = irq_cfg(irq);
1307                 if (!cpumask_test_cpu(cpu, cfg->domain))
1308                         per_cpu(vector_irq, cpu)[vector] = -1;
1309         }
1310 }
1311
1312 static struct irq_chip ioapic_chip;
1313 static struct irq_chip ir_ioapic_chip;
1314
1315 #define IOAPIC_AUTO     -1
1316 #define IOAPIC_EDGE     0
1317 #define IOAPIC_LEVEL    1
1318
1319 #ifdef CONFIG_X86_32
1320 static inline int IO_APIC_irq_trigger(int irq)
1321 {
1322         int apic, idx, pin;
1323
1324         for (apic = 0; apic < nr_ioapics; apic++) {
1325                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1326                         idx = find_irq_entry(apic, pin, mp_INT);
1327                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1328                                 return irq_trigger(idx);
1329                 }
1330         }
1331         /*
1332          * nonexistent IRQs are edge default
1333          */
1334         return 0;
1335 }
1336 #else
1337 static inline int IO_APIC_irq_trigger(int irq)
1338 {
1339         return 1;
1340 }
1341 #endif
1342
1343 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1344 {
1345
1346         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1347             trigger == IOAPIC_LEVEL)
1348                 desc->status |= IRQ_LEVEL;
1349         else
1350                 desc->status &= ~IRQ_LEVEL;
1351
1352         if (irq_remapped(irq)) {
1353                 desc->status |= IRQ_MOVE_PCNTXT;
1354                 if (trigger)
1355                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1356                                                       handle_fasteoi_irq,
1357                                                      "fasteoi");
1358                 else
1359                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1360                                                       handle_edge_irq, "edge");
1361                 return;
1362         }
1363
1364         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1365             trigger == IOAPIC_LEVEL)
1366                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1367                                               handle_fasteoi_irq,
1368                                               "fasteoi");
1369         else
1370                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1371                                               handle_edge_irq, "edge");
1372 }
1373
1374 int setup_ioapic_entry(int apic_id, int irq,
1375                        struct IO_APIC_route_entry *entry,
1376                        unsigned int destination, int trigger,
1377                        int polarity, int vector, int pin)
1378 {
1379         /*
1380          * add it to the IO-APIC irq-routing table:
1381          */
1382         memset(entry,0,sizeof(*entry));
1383
1384         if (intr_remapping_enabled) {
1385                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1386                 struct irte irte;
1387                 struct IR_IO_APIC_route_entry *ir_entry =
1388                         (struct IR_IO_APIC_route_entry *) entry;
1389                 int index;
1390
1391                 if (!iommu)
1392                         panic("No mapping iommu for ioapic %d\n", apic_id);
1393
1394                 index = alloc_irte(iommu, irq, 1);
1395                 if (index < 0)
1396                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1397
1398                 memset(&irte, 0, sizeof(irte));
1399
1400                 irte.present = 1;
1401                 irte.dst_mode = apic->irq_dest_mode;
1402                 /*
1403                  * Trigger mode in the IRTE will always be edge, and the
1404                  * actual level or edge trigger will be setup in the IO-APIC
1405                  * RTE. This will help simplify level triggered irq migration.
1406                  * For more details, see the comments above explainig IO-APIC
1407                  * irq migration in the presence of interrupt-remapping.
1408                  */
1409                 irte.trigger_mode = 0;
1410                 irte.dlvry_mode = apic->irq_delivery_mode;
1411                 irte.vector = vector;
1412                 irte.dest_id = IRTE_DEST(destination);
1413
1414                 modify_irte(irq, &irte);
1415
1416                 ir_entry->index2 = (index >> 15) & 0x1;
1417                 ir_entry->zero = 0;
1418                 ir_entry->format = 1;
1419                 ir_entry->index = (index & 0x7fff);
1420                 /*
1421                  * IO-APIC RTE will be configured with virtual vector.
1422                  * irq handler will do the explicit EOI to the io-apic.
1423                  */
1424                 ir_entry->vector = pin;
1425         } else {
1426                 entry->delivery_mode = apic->irq_delivery_mode;
1427                 entry->dest_mode = apic->irq_dest_mode;
1428                 entry->dest = destination;
1429                 entry->vector = vector;
1430         }
1431
1432         entry->mask = 0;                                /* enable IRQ */
1433         entry->trigger = trigger;
1434         entry->polarity = polarity;
1435
1436         /* Mask level triggered irqs.
1437          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1438          */
1439         if (trigger)
1440                 entry->mask = 1;
1441         return 0;
1442 }
1443
1444 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1445                               int trigger, int polarity)
1446 {
1447         struct irq_cfg *cfg;
1448         struct IO_APIC_route_entry entry;
1449         unsigned int dest;
1450
1451         if (!IO_APIC_IRQ(irq))
1452                 return;
1453
1454         cfg = desc->chip_data;
1455
1456         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1457                 return;
1458
1459         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1460
1461         apic_printk(APIC_VERBOSE,KERN_DEBUG
1462                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1463                     "IRQ %d Mode:%i Active:%i)\n",
1464                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1465                     irq, trigger, polarity);
1466
1467
1468         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1469                                dest, trigger, polarity, cfg->vector, pin)) {
1470                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1471                        mp_ioapics[apic_id].apicid, pin);
1472                 __clear_irq_vector(irq, cfg);
1473                 return;
1474         }
1475
1476         ioapic_register_intr(irq, desc, trigger);
1477         if (irq < NR_IRQS_LEGACY)
1478                 disable_8259A_irq(irq);
1479
1480         ioapic_write_entry(apic_id, pin, entry);
1481 }
1482
1483 static struct {
1484         DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1485 } mp_ioapic_routing[MAX_IO_APICS];
1486
1487 static void __init setup_IO_APIC_irqs(void)
1488 {
1489         int apic_id = 0, pin, idx, irq;
1490         int notcon = 0;
1491         struct irq_desc *desc;
1492         struct irq_cfg *cfg;
1493         int node = cpu_to_node(boot_cpu_id);
1494
1495         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1496
1497 #ifdef CONFIG_ACPI
1498         if (!acpi_disabled && acpi_ioapic) {
1499                 apic_id = mp_find_ioapic(0);
1500                 if (apic_id < 0)
1501                         apic_id = 0;
1502         }
1503 #endif
1504
1505         for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1506                 idx = find_irq_entry(apic_id, pin, mp_INT);
1507                 if (idx == -1) {
1508                         if (!notcon) {
1509                                 notcon = 1;
1510                                 apic_printk(APIC_VERBOSE,
1511                                         KERN_DEBUG " %d-%d",
1512                                         mp_ioapics[apic_id].apicid, pin);
1513                         } else
1514                                 apic_printk(APIC_VERBOSE, " %d-%d",
1515                                         mp_ioapics[apic_id].apicid, pin);
1516                         continue;
1517                 }
1518                 if (notcon) {
1519                         apic_printk(APIC_VERBOSE,
1520                                 " (apicid-pin) not connected\n");
1521                         notcon = 0;
1522                 }
1523
1524                 irq = pin_2_irq(idx, apic_id, pin);
1525
1526                 /*
1527                  * Skip the timer IRQ if there's a quirk handler
1528                  * installed and if it returns 1:
1529                  */
1530                 if (apic->multi_timer_check &&
1531                                 apic->multi_timer_check(apic_id, irq))
1532                         continue;
1533
1534                 desc = irq_to_desc_alloc_node(irq, node);
1535                 if (!desc) {
1536                         printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1537                         continue;
1538                 }
1539                 cfg = desc->chip_data;
1540                 add_pin_to_irq_node(cfg, node, apic_id, pin);
1541                 /*
1542                  * don't mark it in pin_programmed, so later acpi could
1543                  * set it correctly when irq < 16
1544                  */
1545                 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1546                                 irq_trigger(idx), irq_polarity(idx));
1547         }
1548
1549         if (notcon)
1550                 apic_printk(APIC_VERBOSE,
1551                         " (apicid-pin) not connected\n");
1552 }
1553
1554 /*
1555  * Set up the timer pin, possibly with the 8259A-master behind.
1556  */
1557 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1558                                         int vector)
1559 {
1560         struct IO_APIC_route_entry entry;
1561
1562         if (intr_remapping_enabled)
1563                 return;
1564
1565         memset(&entry, 0, sizeof(entry));
1566
1567         /*
1568          * We use logical delivery to get the timer IRQ
1569          * to the first CPU.
1570          */
1571         entry.dest_mode = apic->irq_dest_mode;
1572         entry.mask = 0;                 /* don't mask IRQ for edge */
1573         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1574         entry.delivery_mode = apic->irq_delivery_mode;
1575         entry.polarity = 0;
1576         entry.trigger = 0;
1577         entry.vector = vector;
1578
1579         /*
1580          * The timer IRQ doesn't have to know that behind the
1581          * scene we may have a 8259A-master in AEOI mode ...
1582          */
1583         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1584
1585         /*
1586          * Add it to the IO-APIC irq-routing table:
1587          */
1588         ioapic_write_entry(apic_id, pin, entry);
1589 }
1590
1591
1592 __apicdebuginit(void) print_IO_APIC(void)
1593 {
1594         int apic, i;
1595         union IO_APIC_reg_00 reg_00;
1596         union IO_APIC_reg_01 reg_01;
1597         union IO_APIC_reg_02 reg_02;
1598         union IO_APIC_reg_03 reg_03;
1599         unsigned long flags;
1600         struct irq_cfg *cfg;
1601         struct irq_desc *desc;
1602         unsigned int irq;
1603
1604         if (apic_verbosity == APIC_QUIET)
1605                 return;
1606
1607         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1608         for (i = 0; i < nr_ioapics; i++)
1609                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1610                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1611
1612         /*
1613          * We are a bit conservative about what we expect.  We have to
1614          * know about every hardware change ASAP.
1615          */
1616         printk(KERN_INFO "testing the IO APIC.......................\n");
1617
1618         for (apic = 0; apic < nr_ioapics; apic++) {
1619
1620         spin_lock_irqsave(&ioapic_lock, flags);
1621         reg_00.raw = io_apic_read(apic, 0);
1622         reg_01.raw = io_apic_read(apic, 1);
1623         if (reg_01.bits.version >= 0x10)
1624                 reg_02.raw = io_apic_read(apic, 2);
1625         if (reg_01.bits.version >= 0x20)
1626                 reg_03.raw = io_apic_read(apic, 3);
1627         spin_unlock_irqrestore(&ioapic_lock, flags);
1628
1629         printk("\n");
1630         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1631         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1632         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1633         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1634         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1635
1636         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1637         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1638
1639         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1640         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1641
1642         /*
1643          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1644          * but the value of reg_02 is read as the previous read register
1645          * value, so ignore it if reg_02 == reg_01.
1646          */
1647         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1648                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1649                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1650         }
1651
1652         /*
1653          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1654          * or reg_03, but the value of reg_0[23] is read as the previous read
1655          * register value, so ignore it if reg_03 == reg_0[12].
1656          */
1657         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1658             reg_03.raw != reg_01.raw) {
1659                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1660                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1661         }
1662
1663         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1664
1665         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1666                           " Stat Dmod Deli Vect:   \n");
1667
1668         for (i = 0; i <= reg_01.bits.entries; i++) {
1669                 struct IO_APIC_route_entry entry;
1670
1671                 entry = ioapic_read_entry(apic, i);
1672
1673                 printk(KERN_DEBUG " %02x %03X ",
1674                         i,
1675                         entry.dest
1676                 );
1677
1678                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1679                         entry.mask,
1680                         entry.trigger,
1681                         entry.irr,
1682                         entry.polarity,
1683                         entry.delivery_status,
1684                         entry.dest_mode,
1685                         entry.delivery_mode,
1686                         entry.vector
1687                 );
1688         }
1689         }
1690         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1691         for_each_irq_desc(irq, desc) {
1692                 struct irq_pin_list *entry;
1693
1694                 cfg = desc->chip_data;
1695                 entry = cfg->irq_2_pin;
1696                 if (!entry)
1697                         continue;
1698                 printk(KERN_DEBUG "IRQ%d ", irq);
1699                 for (;;) {
1700                         printk("-> %d:%d", entry->apic, entry->pin);
1701                         if (!entry->next)
1702                                 break;
1703                         entry = entry->next;
1704                 }
1705                 printk("\n");
1706         }
1707
1708         printk(KERN_INFO ".................................... done.\n");
1709
1710         return;
1711 }
1712
1713 __apicdebuginit(void) print_APIC_bitfield(int base)
1714 {
1715         unsigned int v;
1716         int i, j;
1717
1718         if (apic_verbosity == APIC_QUIET)
1719                 return;
1720
1721         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1722         for (i = 0; i < 8; i++) {
1723                 v = apic_read(base + i*0x10);
1724                 for (j = 0; j < 32; j++) {
1725                         if (v & (1<<j))
1726                                 printk("1");
1727                         else
1728                                 printk("0");
1729                 }
1730                 printk("\n");
1731         }
1732 }
1733
1734 __apicdebuginit(void) print_local_APIC(void *dummy)
1735 {
1736         unsigned int i, v, ver, maxlvt;
1737         u64 icr;
1738
1739         if (apic_verbosity == APIC_QUIET)
1740                 return;
1741
1742         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1743                 smp_processor_id(), hard_smp_processor_id());
1744         v = apic_read(APIC_ID);
1745         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1746         v = apic_read(APIC_LVR);
1747         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1748         ver = GET_APIC_VERSION(v);
1749         maxlvt = lapic_get_maxlvt();
1750
1751         v = apic_read(APIC_TASKPRI);
1752         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1753
1754         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1755                 if (!APIC_XAPIC(ver)) {
1756                         v = apic_read(APIC_ARBPRI);
1757                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1758                                v & APIC_ARBPRI_MASK);
1759                 }
1760                 v = apic_read(APIC_PROCPRI);
1761                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1762         }
1763
1764         /*
1765          * Remote read supported only in the 82489DX and local APIC for
1766          * Pentium processors.
1767          */
1768         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1769                 v = apic_read(APIC_RRR);
1770                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1771         }
1772
1773         v = apic_read(APIC_LDR);
1774         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1775         if (!x2apic_enabled()) {
1776                 v = apic_read(APIC_DFR);
1777                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1778         }
1779         v = apic_read(APIC_SPIV);
1780         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1781
1782         printk(KERN_DEBUG "... APIC ISR field:\n");
1783         print_APIC_bitfield(APIC_ISR);
1784         printk(KERN_DEBUG "... APIC TMR field:\n");
1785         print_APIC_bitfield(APIC_TMR);
1786         printk(KERN_DEBUG "... APIC IRR field:\n");
1787         print_APIC_bitfield(APIC_IRR);
1788
1789         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1790                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1791                         apic_write(APIC_ESR, 0);
1792
1793                 v = apic_read(APIC_ESR);
1794                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1795         }
1796
1797         icr = apic_icr_read();
1798         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1799         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1800
1801         v = apic_read(APIC_LVTT);
1802         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1803
1804         if (maxlvt > 3) {                       /* PC is LVT#4. */
1805                 v = apic_read(APIC_LVTPC);
1806                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1807         }
1808         v = apic_read(APIC_LVT0);
1809         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1810         v = apic_read(APIC_LVT1);
1811         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1812
1813         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1814                 v = apic_read(APIC_LVTERR);
1815                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1816         }
1817
1818         v = apic_read(APIC_TMICT);
1819         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1820         v = apic_read(APIC_TMCCT);
1821         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1822         v = apic_read(APIC_TDCR);
1823         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1824
1825         if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1826                 v = apic_read(APIC_EFEAT);
1827                 maxlvt = (v >> 16) & 0xff;
1828                 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1829                 v = apic_read(APIC_ECTRL);
1830                 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1831                 for (i = 0; i < maxlvt; i++) {
1832                         v = apic_read(APIC_EILVTn(i));
1833                         printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1834                 }
1835         }
1836         printk("\n");
1837 }
1838
1839 __apicdebuginit(void) print_all_local_APICs(void)
1840 {
1841         int cpu;
1842
1843         preempt_disable();
1844         for_each_online_cpu(cpu)
1845                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1846         preempt_enable();
1847 }
1848
1849 __apicdebuginit(void) print_PIC(void)
1850 {
1851         unsigned int v;
1852         unsigned long flags;
1853
1854         if (apic_verbosity == APIC_QUIET)
1855                 return;
1856
1857         printk(KERN_DEBUG "\nprinting PIC contents\n");
1858
1859         spin_lock_irqsave(&i8259A_lock, flags);
1860
1861         v = inb(0xa1) << 8 | inb(0x21);
1862         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1863
1864         v = inb(0xa0) << 8 | inb(0x20);
1865         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1866
1867         outb(0x0b,0xa0);
1868         outb(0x0b,0x20);
1869         v = inb(0xa0) << 8 | inb(0x20);
1870         outb(0x0a,0xa0);
1871         outb(0x0a,0x20);
1872
1873         spin_unlock_irqrestore(&i8259A_lock, flags);
1874
1875         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1876
1877         v = inb(0x4d1) << 8 | inb(0x4d0);
1878         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1879 }
1880
1881 __apicdebuginit(int) print_all_ICs(void)
1882 {
1883         print_PIC();
1884
1885         /* don't print out if apic is not there */
1886         if (!cpu_has_apic || disable_apic)
1887                 return 0;
1888
1889         print_all_local_APICs();
1890         print_IO_APIC();
1891
1892         return 0;
1893 }
1894
1895 fs_initcall(print_all_ICs);
1896
1897
1898 /* Where if anywhere is the i8259 connect in external int mode */
1899 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1900
1901 void __init enable_IO_APIC(void)
1902 {
1903         union IO_APIC_reg_01 reg_01;
1904         int i8259_apic, i8259_pin;
1905         int apic;
1906         unsigned long flags;
1907
1908         /*
1909          * The number of IO-APIC IRQ registers (== #pins):
1910          */
1911         for (apic = 0; apic < nr_ioapics; apic++) {
1912                 spin_lock_irqsave(&ioapic_lock, flags);
1913                 reg_01.raw = io_apic_read(apic, 1);
1914                 spin_unlock_irqrestore(&ioapic_lock, flags);
1915                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1916         }
1917         for(apic = 0; apic < nr_ioapics; apic++) {
1918                 int pin;
1919                 /* See if any of the pins is in ExtINT mode */
1920                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1921                         struct IO_APIC_route_entry entry;
1922                         entry = ioapic_read_entry(apic, pin);
1923
1924                         /* If the interrupt line is enabled and in ExtInt mode
1925                          * I have found the pin where the i8259 is connected.
1926                          */
1927                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1928                                 ioapic_i8259.apic = apic;
1929                                 ioapic_i8259.pin  = pin;
1930                                 goto found_i8259;
1931                         }
1932                 }
1933         }
1934  found_i8259:
1935         /* Look to see what if the MP table has reported the ExtINT */
1936         /* If we could not find the appropriate pin by looking at the ioapic
1937          * the i8259 probably is not connected the ioapic but give the
1938          * mptable a chance anyway.
1939          */
1940         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1941         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1942         /* Trust the MP table if nothing is setup in the hardware */
1943         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1944                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1945                 ioapic_i8259.pin  = i8259_pin;
1946                 ioapic_i8259.apic = i8259_apic;
1947         }
1948         /* Complain if the MP table and the hardware disagree */
1949         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1950                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1951         {
1952                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1953         }
1954
1955         /*
1956          * Do not trust the IO-APIC being empty at bootup
1957          */
1958         clear_IO_APIC();
1959 }
1960
1961 /*
1962  * Not an __init, needed by the reboot code
1963  */
1964 void disable_IO_APIC(void)
1965 {
1966         /*
1967          * Clear the IO-APIC before rebooting:
1968          */
1969         clear_IO_APIC();
1970
1971         /*
1972          * If the i8259 is routed through an IOAPIC
1973          * Put that IOAPIC in virtual wire mode
1974          * so legacy interrupts can be delivered.
1975          *
1976          * With interrupt-remapping, for now we will use virtual wire A mode,
1977          * as virtual wire B is little complex (need to configure both
1978          * IOAPIC RTE aswell as interrupt-remapping table entry).
1979          * As this gets called during crash dump, keep this simple for now.
1980          */
1981         if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1982                 struct IO_APIC_route_entry entry;
1983
1984                 memset(&entry, 0, sizeof(entry));
1985                 entry.mask            = 0; /* Enabled */
1986                 entry.trigger         = 0; /* Edge */
1987                 entry.irr             = 0;
1988                 entry.polarity        = 0; /* High */
1989                 entry.delivery_status = 0;
1990                 entry.dest_mode       = 0; /* Physical */
1991                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
1992                 entry.vector          = 0;
1993                 entry.dest            = read_apic_id();
1994
1995                 /*
1996                  * Add it to the IO-APIC irq-routing table:
1997                  */
1998                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1999         }
2000
2001         /*
2002          * Use virtual wire A mode when interrupt remapping is enabled.
2003          */
2004         disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2005 }
2006
2007 #ifdef CONFIG_X86_32
2008 /*
2009  * function to set the IO-APIC physical IDs based on the
2010  * values stored in the MPC table.
2011  *
2012  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2013  */
2014
2015 static void __init setup_ioapic_ids_from_mpc(void)
2016 {
2017         union IO_APIC_reg_00 reg_00;
2018         physid_mask_t phys_id_present_map;
2019         int apic_id;
2020         int i;
2021         unsigned char old_id;
2022         unsigned long flags;
2023
2024         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2025                 return;
2026
2027         /*
2028          * Don't check I/O APIC IDs for xAPIC systems.  They have
2029          * no meaning without the serial APIC bus.
2030          */
2031         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2032                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2033                 return;
2034         /*
2035          * This is broken; anything with a real cpu count has to
2036          * circumvent this idiocy regardless.
2037          */
2038         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2039
2040         /*
2041          * Set the IOAPIC ID to the value stored in the MPC table.
2042          */
2043         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2044
2045                 /* Read the register 0 value */
2046                 spin_lock_irqsave(&ioapic_lock, flags);
2047                 reg_00.raw = io_apic_read(apic_id, 0);
2048                 spin_unlock_irqrestore(&ioapic_lock, flags);
2049
2050                 old_id = mp_ioapics[apic_id].apicid;
2051
2052                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2053                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2054                                 apic_id, mp_ioapics[apic_id].apicid);
2055                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2056                                 reg_00.bits.ID);
2057                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2058                 }
2059
2060                 /*
2061                  * Sanity check, is the ID really free? Every APIC in a
2062                  * system must have a unique ID or we get lots of nice
2063                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2064                  */
2065                 if (apic->check_apicid_used(phys_id_present_map,
2066                                         mp_ioapics[apic_id].apicid)) {
2067                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2068                                 apic_id, mp_ioapics[apic_id].apicid);
2069                         for (i = 0; i < get_physical_broadcast(); i++)
2070                                 if (!physid_isset(i, phys_id_present_map))
2071                                         break;
2072                         if (i >= get_physical_broadcast())
2073                                 panic("Max APIC ID exceeded!\n");
2074                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2075                                 i);
2076                         physid_set(i, phys_id_present_map);
2077                         mp_ioapics[apic_id].apicid = i;
2078                 } else {
2079                         physid_mask_t tmp;
2080                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2081                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2082                                         "phys_id_present_map\n",
2083                                         mp_ioapics[apic_id].apicid);
2084                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2085                 }
2086
2087
2088                 /*
2089                  * We need to adjust the IRQ routing table
2090                  * if the ID changed.
2091                  */
2092                 if (old_id != mp_ioapics[apic_id].apicid)
2093                         for (i = 0; i < mp_irq_entries; i++)
2094                                 if (mp_irqs[i].dstapic == old_id)
2095                                         mp_irqs[i].dstapic
2096                                                 = mp_ioapics[apic_id].apicid;
2097
2098                 /*
2099                  * Read the right value from the MPC table and
2100                  * write it into the ID register.
2101                  */
2102                 apic_printk(APIC_VERBOSE, KERN_INFO
2103                         "...changing IO-APIC physical APIC ID to %d ...",
2104                         mp_ioapics[apic_id].apicid);
2105
2106                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2107                 spin_lock_irqsave(&ioapic_lock, flags);
2108                 io_apic_write(apic_id, 0, reg_00.raw);
2109                 spin_unlock_irqrestore(&ioapic_lock, flags);
2110
2111                 /*
2112                  * Sanity check
2113                  */
2114                 spin_lock_irqsave(&ioapic_lock, flags);
2115                 reg_00.raw = io_apic_read(apic_id, 0);
2116                 spin_unlock_irqrestore(&ioapic_lock, flags);
2117                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2118                         printk("could not set ID!\n");
2119                 else
2120                         apic_printk(APIC_VERBOSE, " ok.\n");
2121         }
2122 }
2123 #endif
2124
2125 int no_timer_check __initdata;
2126
2127 static int __init notimercheck(char *s)
2128 {
2129         no_timer_check = 1;
2130         return 1;
2131 }
2132 __setup("no_timer_check", notimercheck);
2133
2134 /*
2135  * There is a nasty bug in some older SMP boards, their mptable lies
2136  * about the timer IRQ. We do the following to work around the situation:
2137  *
2138  *      - timer IRQ defaults to IO-APIC IRQ
2139  *      - if this function detects that timer IRQs are defunct, then we fall
2140  *        back to ISA timer IRQs
2141  */
2142 static int __init timer_irq_works(void)
2143 {
2144         unsigned long t1 = jiffies;
2145         unsigned long flags;
2146
2147         if (no_timer_check)
2148                 return 1;
2149
2150         local_save_flags(flags);
2151         local_irq_enable();
2152         /* Let ten ticks pass... */
2153         mdelay((10 * 1000) / HZ);
2154         local_irq_restore(flags);
2155
2156         /*
2157          * Expect a few ticks at least, to be sure some possible
2158          * glue logic does not lock up after one or two first
2159          * ticks in a non-ExtINT mode.  Also the local APIC
2160          * might have cached one ExtINT interrupt.  Finally, at
2161          * least one tick may be lost due to delays.
2162          */
2163
2164         /* jiffies wrap? */
2165         if (time_after(jiffies, t1 + 4))
2166                 return 1;
2167         return 0;
2168 }
2169
2170 /*
2171  * In the SMP+IOAPIC case it might happen that there are an unspecified
2172  * number of pending IRQ events unhandled. These cases are very rare,
2173  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2174  * better to do it this way as thus we do not have to be aware of
2175  * 'pending' interrupts in the IRQ path, except at this point.
2176  */
2177 /*
2178  * Edge triggered needs to resend any interrupt
2179  * that was delayed but this is now handled in the device
2180  * independent code.
2181  */
2182
2183 /*
2184  * Starting up a edge-triggered IO-APIC interrupt is
2185  * nasty - we need to make sure that we get the edge.
2186  * If it is already asserted for some reason, we need
2187  * return 1 to indicate that is was pending.
2188  *
2189  * This is not complete - we should be able to fake
2190  * an edge even if it isn't on the 8259A...
2191  */
2192
2193 static unsigned int startup_ioapic_irq(unsigned int irq)
2194 {
2195         int was_pending = 0;
2196         unsigned long flags;
2197         struct irq_cfg *cfg;
2198
2199         spin_lock_irqsave(&ioapic_lock, flags);
2200         if (irq < NR_IRQS_LEGACY) {
2201                 disable_8259A_irq(irq);
2202                 if (i8259A_irq_pending(irq))
2203                         was_pending = 1;
2204         }
2205         cfg = irq_cfg(irq);
2206         __unmask_IO_APIC_irq(cfg);
2207         spin_unlock_irqrestore(&ioapic_lock, flags);
2208
2209         return was_pending;
2210 }
2211
2212 #ifdef CONFIG_X86_64
2213 static int ioapic_retrigger_irq(unsigned int irq)
2214 {
2215
2216         struct irq_cfg *cfg = irq_cfg(irq);
2217         unsigned long flags;
2218
2219         spin_lock_irqsave(&vector_lock, flags);
2220         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2221         spin_unlock_irqrestore(&vector_lock, flags);
2222
2223         return 1;
2224 }
2225 #else
2226 static int ioapic_retrigger_irq(unsigned int irq)
2227 {
2228         apic->send_IPI_self(irq_cfg(irq)->vector);
2229
2230         return 1;
2231 }
2232 #endif
2233
2234 /*
2235  * Level and edge triggered IO-APIC interrupts need different handling,
2236  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2237  * handled with the level-triggered descriptor, but that one has slightly
2238  * more overhead. Level-triggered interrupts cannot be handled with the
2239  * edge-triggered handler, without risking IRQ storms and other ugly
2240  * races.
2241  */
2242
2243 #ifdef CONFIG_SMP
2244 static void send_cleanup_vector(struct irq_cfg *cfg)
2245 {
2246         cpumask_var_t cleanup_mask;
2247
2248         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2249                 unsigned int i;
2250                 cfg->move_cleanup_count = 0;
2251                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2252                         cfg->move_cleanup_count++;
2253                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2254                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2255         } else {
2256                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2257                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
2258                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2259                 free_cpumask_var(cleanup_mask);
2260         }
2261         cfg->move_in_progress = 0;
2262 }
2263
2264 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2265 {
2266         int apic, pin;
2267         struct irq_pin_list *entry;
2268         u8 vector = cfg->vector;
2269
2270         entry = cfg->irq_2_pin;
2271         for (;;) {
2272                 unsigned int reg;
2273
2274                 if (!entry)
2275                         break;
2276
2277                 apic = entry->apic;
2278                 pin = entry->pin;
2279                 /*
2280                  * With interrupt-remapping, destination information comes
2281                  * from interrupt-remapping table entry.
2282                  */
2283                 if (!irq_remapped(irq))
2284                         io_apic_write(apic, 0x11 + pin*2, dest);
2285                 reg = io_apic_read(apic, 0x10 + pin*2);
2286                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2287                 reg |= vector;
2288                 io_apic_modify(apic, 0x10 + pin*2, reg);
2289                 if (!entry->next)
2290                         break;
2291                 entry = entry->next;
2292         }
2293 }
2294
2295 static int
2296 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
2297
2298 /*
2299  * Either sets desc->affinity to a valid value, and returns
2300  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
2301  * leaves desc->affinity untouched.
2302  */
2303 static unsigned int
2304 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
2305 {
2306         struct irq_cfg *cfg;
2307         unsigned int irq;
2308
2309         if (!cpumask_intersects(mask, cpu_online_mask))
2310                 return BAD_APICID;
2311
2312         irq = desc->irq;
2313         cfg = desc->chip_data;
2314         if (assign_irq_vector(irq, cfg, mask))
2315                 return BAD_APICID;
2316
2317         cpumask_copy(desc->affinity, mask);
2318
2319         return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2320 }
2321
2322 static int
2323 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2324 {
2325         struct irq_cfg *cfg;
2326         unsigned long flags;
2327         unsigned int dest;
2328         unsigned int irq;
2329         int ret = -1;
2330
2331         irq = desc->irq;
2332         cfg = desc->chip_data;
2333
2334         spin_lock_irqsave(&ioapic_lock, flags);
2335         dest = set_desc_affinity(desc, mask);
2336         if (dest != BAD_APICID) {
2337                 /* Only the high 8 bits are valid. */
2338                 dest = SET_APIC_LOGICAL_ID(dest);
2339                 __target_IO_APIC_irq(irq, dest, cfg);
2340                 ret = 0;
2341         }
2342         spin_unlock_irqrestore(&ioapic_lock, flags);
2343
2344         return ret;
2345 }
2346
2347 static int
2348 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2349 {
2350         struct irq_desc *desc;
2351
2352         desc = irq_to_desc(irq);
2353
2354         return set_ioapic_affinity_irq_desc(desc, mask);
2355 }
2356
2357 #ifdef CONFIG_INTR_REMAP
2358
2359 /*
2360  * Migrate the IO-APIC irq in the presence of intr-remapping.
2361  *
2362  * For both level and edge triggered, irq migration is a simple atomic
2363  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2364  *
2365  * For level triggered, we eliminate the io-apic RTE modification (with the
2366  * updated vector information), by using a virtual vector (io-apic pin number).
2367  * Real vector that is used for interrupting cpu will be coming from
2368  * the interrupt-remapping table entry.
2369  */
2370 static int
2371 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2372 {
2373         struct irq_cfg *cfg;
2374         struct irte irte;
2375         unsigned int dest;
2376         unsigned int irq;
2377         int ret = -1;
2378
2379         if (!cpumask_intersects(mask, cpu_online_mask))
2380                 return ret;
2381
2382         irq = desc->irq;
2383         if (get_irte(irq, &irte))
2384                 return ret;
2385
2386         cfg = desc->chip_data;
2387         if (assign_irq_vector(irq, cfg, mask))
2388                 return ret;
2389
2390         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2391
2392         irte.vector = cfg->vector;
2393         irte.dest_id = IRTE_DEST(dest);
2394
2395         /*
2396          * Modified the IRTE and flushes the Interrupt entry cache.
2397          */
2398         modify_irte(irq, &irte);
2399
2400         if (cfg->move_in_progress)
2401                 send_cleanup_vector(cfg);
2402
2403         cpumask_copy(desc->affinity, mask);
2404
2405         return 0;
2406 }
2407
2408 /*
2409  * Migrates the IRQ destination in the process context.
2410  */
2411 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2412                                             const struct cpumask *mask)
2413 {
2414         return migrate_ioapic_irq_desc(desc, mask);
2415 }
2416 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2417                                        const struct cpumask *mask)
2418 {
2419         struct irq_desc *desc = irq_to_desc(irq);
2420
2421         return set_ir_ioapic_affinity_irq_desc(desc, mask);
2422 }
2423 #else
2424 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2425                                                    const struct cpumask *mask)
2426 {
2427         return 0;
2428 }
2429 #endif
2430
2431 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2432 {
2433         unsigned vector, me;
2434
2435         ack_APIC_irq();
2436         exit_idle();
2437         irq_enter();
2438
2439         me = smp_processor_id();
2440         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2441                 unsigned int irq;
2442                 unsigned int irr;
2443                 struct irq_desc *desc;
2444                 struct irq_cfg *cfg;
2445                 irq = __get_cpu_var(vector_irq)[vector];
2446
2447                 if (irq == -1)
2448                         continue;
2449
2450                 desc = irq_to_desc(irq);
2451                 if (!desc)
2452                         continue;
2453
2454                 cfg = irq_cfg(irq);
2455                 spin_lock(&desc->lock);
2456                 if (!cfg->move_cleanup_count)
2457                         goto unlock;
2458
2459                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2460                         goto unlock;
2461
2462                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2463                 /*
2464                  * Check if the vector that needs to be cleanedup is
2465                  * registered at the cpu's IRR. If so, then this is not
2466                  * the best time to clean it up. Lets clean it up in the
2467                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2468                  * to myself.
2469                  */
2470                 if (irr  & (1 << (vector % 32))) {
2471                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2472                         goto unlock;
2473                 }
2474                 __get_cpu_var(vector_irq)[vector] = -1;
2475                 cfg->move_cleanup_count--;
2476 unlock:
2477                 spin_unlock(&desc->lock);
2478         }
2479
2480         irq_exit();
2481 }
2482
2483 static void irq_complete_move(struct irq_desc **descp)
2484 {
2485         struct irq_desc *desc = *descp;
2486         struct irq_cfg *cfg = desc->chip_data;
2487         unsigned vector, me;
2488
2489         if (likely(!cfg->move_in_progress))
2490                 return;
2491
2492         vector = ~get_irq_regs()->orig_ax;
2493         me = smp_processor_id();
2494
2495         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2496                 send_cleanup_vector(cfg);
2497 }
2498 #else
2499 static inline void irq_complete_move(struct irq_desc **descp) {}
2500 #endif
2501
2502 static void ack_apic_edge(unsigned int irq)
2503 {
2504         struct irq_desc *desc = irq_to_desc(irq);
2505
2506         irq_complete_move(&desc);
2507         move_native_irq(irq);
2508         ack_APIC_irq();
2509 }
2510
2511 atomic_t irq_mis_count;
2512
2513 static void ack_apic_level(unsigned int irq)
2514 {
2515         struct irq_desc *desc = irq_to_desc(irq);
2516
2517 #ifdef CONFIG_X86_32
2518         unsigned long v;
2519         int i;
2520 #endif
2521         struct irq_cfg *cfg;
2522         int do_unmask_irq = 0;
2523
2524         irq_complete_move(&desc);
2525 #ifdef CONFIG_GENERIC_PENDING_IRQ
2526         /* If we are moving the irq we need to mask it */
2527         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2528                 do_unmask_irq = 1;
2529                 mask_IO_APIC_irq_desc(desc);
2530         }
2531 #endif
2532
2533 #ifdef CONFIG_X86_32
2534         /*
2535         * It appears there is an erratum which affects at least version 0x11
2536         * of I/O APIC (that's the 82093AA and cores integrated into various
2537         * chipsets).  Under certain conditions a level-triggered interrupt is
2538         * erroneously delivered as edge-triggered one but the respective IRR
2539         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2540         * message but it will never arrive and further interrupts are blocked
2541         * from the source.  The exact reason is so far unknown, but the
2542         * phenomenon was observed when two consecutive interrupt requests
2543         * from a given source get delivered to the same CPU and the source is
2544         * temporarily disabled in between.
2545         *
2546         * A workaround is to simulate an EOI message manually.  We achieve it
2547         * by setting the trigger mode to edge and then to level when the edge
2548         * trigger mode gets detected in the TMR of a local APIC for a
2549         * level-triggered interrupt.  We mask the source for the time of the
2550         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2551         * The idea is from Manfred Spraul.  --macro
2552         */
2553         cfg = desc->chip_data;
2554         i = cfg->vector;
2555
2556         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2557 #endif
2558
2559         /*
2560          * We must acknowledge the irq before we move it or the acknowledge will
2561          * not propagate properly.
2562          */
2563         ack_APIC_irq();
2564
2565         /* Now we can move and renable the irq */
2566         if (unlikely(do_unmask_irq)) {
2567                 /* Only migrate the irq if the ack has been received.
2568                  *
2569                  * On rare occasions the broadcast level triggered ack gets
2570                  * delayed going to ioapics, and if we reprogram the
2571                  * vector while Remote IRR is still set the irq will never
2572                  * fire again.
2573                  *
2574                  * To prevent this scenario we read the Remote IRR bit
2575                  * of the ioapic.  This has two effects.
2576                  * - On any sane system the read of the ioapic will
2577                  *   flush writes (and acks) going to the ioapic from
2578                  *   this cpu.
2579                  * - We get to see if the ACK has actually been delivered.
2580                  *
2581                  * Based on failed experiments of reprogramming the
2582                  * ioapic entry from outside of irq context starting
2583                  * with masking the ioapic entry and then polling until
2584                  * Remote IRR was clear before reprogramming the
2585                  * ioapic I don't trust the Remote IRR bit to be
2586                  * completey accurate.
2587                  *
2588                  * However there appears to be no other way to plug
2589                  * this race, so if the Remote IRR bit is not
2590                  * accurate and is causing problems then it is a hardware bug
2591                  * and you can go talk to the chipset vendor about it.
2592                  */
2593                 cfg = desc->chip_data;
2594                 if (!io_apic_level_ack_pending(cfg))
2595                         move_masked_irq(irq);
2596                 unmask_IO_APIC_irq_desc(desc);
2597         }
2598
2599 #ifdef CONFIG_X86_32
2600         if (!(v & (1 << (i & 0x1f)))) {
2601                 atomic_inc(&irq_mis_count);
2602                 spin_lock(&ioapic_lock);
2603                 __mask_and_edge_IO_APIC_irq(cfg);
2604                 __unmask_and_level_IO_APIC_irq(cfg);
2605                 spin_unlock(&ioapic_lock);
2606         }
2607 #endif
2608 }
2609
2610 #ifdef CONFIG_INTR_REMAP
2611 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2612 {
2613         int apic, pin;
2614         struct irq_pin_list *entry;
2615
2616         entry = cfg->irq_2_pin;
2617         for (;;) {
2618
2619                 if (!entry)
2620                         break;
2621
2622                 apic = entry->apic;
2623                 pin = entry->pin;
2624                 io_apic_eoi(apic, pin);
2625                 entry = entry->next;
2626         }
2627 }
2628
2629 static void
2630 eoi_ioapic_irq(struct irq_desc *desc)
2631 {
2632         struct irq_cfg *cfg;
2633         unsigned long flags;
2634         unsigned int irq;
2635
2636         irq = desc->irq;
2637         cfg = desc->chip_data;
2638
2639         spin_lock_irqsave(&ioapic_lock, flags);
2640         __eoi_ioapic_irq(irq, cfg);
2641         spin_unlock_irqrestore(&ioapic_lock, flags);
2642 }
2643
2644 static void ir_ack_apic_edge(unsigned int irq)
2645 {
2646         ack_APIC_irq();
2647 }
2648
2649 static void ir_ack_apic_level(unsigned int irq)
2650 {
2651         struct irq_desc *desc = irq_to_desc(irq);
2652
2653         ack_APIC_irq();
2654         eoi_ioapic_irq(desc);
2655 }
2656 #endif /* CONFIG_INTR_REMAP */
2657
2658 static struct irq_chip ioapic_chip __read_mostly = {
2659         .name           = "IO-APIC",
2660         .startup        = startup_ioapic_irq,
2661         .mask           = mask_IO_APIC_irq,
2662         .unmask         = unmask_IO_APIC_irq,
2663         .ack            = ack_apic_edge,
2664         .eoi            = ack_apic_level,
2665 #ifdef CONFIG_SMP
2666         .set_affinity   = set_ioapic_affinity_irq,
2667 #endif
2668         .retrigger      = ioapic_retrigger_irq,
2669 };
2670
2671 static struct irq_chip ir_ioapic_chip __read_mostly = {
2672         .name           = "IR-IO-APIC",
2673         .startup        = startup_ioapic_irq,
2674         .mask           = mask_IO_APIC_irq,
2675         .unmask         = unmask_IO_APIC_irq,
2676 #ifdef CONFIG_INTR_REMAP
2677         .ack            = ir_ack_apic_edge,
2678         .eoi            = ir_ack_apic_level,
2679 #ifdef CONFIG_SMP
2680         .set_affinity   = set_ir_ioapic_affinity_irq,
2681 #endif
2682 #endif
2683         .retrigger      = ioapic_retrigger_irq,
2684 };
2685
2686 static inline void init_IO_APIC_traps(void)
2687 {
2688         int irq;
2689         struct irq_desc *desc;
2690         struct irq_cfg *cfg;
2691
2692         /*
2693          * NOTE! The local APIC isn't very good at handling
2694          * multiple interrupts at the same interrupt level.
2695          * As the interrupt level is determined by taking the
2696          * vector number and shifting that right by 4, we
2697          * want to spread these out a bit so that they don't
2698          * all fall in the same interrupt level.
2699          *
2700          * Also, we've got to be careful not to trash gate
2701          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2702          */
2703         for_each_irq_desc(irq, desc) {
2704                 cfg = desc->chip_data;
2705                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2706                         /*
2707                          * Hmm.. We don't have an entry for this,
2708                          * so default to an old-fashioned 8259
2709                          * interrupt if we can..
2710                          */
2711                         if (irq < NR_IRQS_LEGACY)
2712                                 make_8259A_irq(irq);
2713                         else
2714                                 /* Strange. Oh, well.. */
2715                                 desc->chip = &no_irq_chip;
2716                 }
2717         }
2718 }
2719
2720 /*
2721  * The local APIC irq-chip implementation:
2722  */
2723
2724 static void mask_lapic_irq(unsigned int irq)
2725 {
2726         unsigned long v;
2727
2728         v = apic_read(APIC_LVT0);
2729         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2730 }
2731
2732 static void unmask_lapic_irq(unsigned int irq)
2733 {
2734         unsigned long v;
2735
2736         v = apic_read(APIC_LVT0);
2737         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2738 }
2739
2740 static void ack_lapic_irq(unsigned int irq)
2741 {
2742         ack_APIC_irq();
2743 }
2744
2745 static struct irq_chip lapic_chip __read_mostly = {
2746         .name           = "local-APIC",
2747         .mask           = mask_lapic_irq,
2748         .unmask         = unmask_lapic_irq,
2749         .ack            = ack_lapic_irq,
2750 };
2751
2752 static void lapic_register_intr(int irq, struct irq_desc *desc)
2753 {
2754         desc->status &= ~IRQ_LEVEL;
2755         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2756                                       "edge");
2757 }
2758
2759 static void __init setup_nmi(void)
2760 {
2761         /*
2762          * Dirty trick to enable the NMI watchdog ...
2763          * We put the 8259A master into AEOI mode and
2764          * unmask on all local APICs LVT0 as NMI.
2765          *
2766          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2767          * is from Maciej W. Rozycki - so we do not have to EOI from
2768          * the NMI handler or the timer interrupt.
2769          */
2770         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2771
2772         enable_NMI_through_LVT0();
2773
2774         apic_printk(APIC_VERBOSE, " done.\n");
2775 }
2776
2777 /*
2778  * This looks a bit hackish but it's about the only one way of sending
2779  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2780  * not support the ExtINT mode, unfortunately.  We need to send these
2781  * cycles as some i82489DX-based boards have glue logic that keeps the
2782  * 8259A interrupt line asserted until INTA.  --macro
2783  */
2784 static inline void __init unlock_ExtINT_logic(void)
2785 {
2786         int apic, pin, i;
2787         struct IO_APIC_route_entry entry0, entry1;
2788         unsigned char save_control, save_freq_select;
2789
2790         pin  = find_isa_irq_pin(8, mp_INT);
2791         if (pin == -1) {
2792                 WARN_ON_ONCE(1);
2793                 return;
2794         }
2795         apic = find_isa_irq_apic(8, mp_INT);
2796         if (apic == -1) {
2797                 WARN_ON_ONCE(1);
2798                 return;
2799         }
2800
2801         entry0 = ioapic_read_entry(apic, pin);
2802         clear_IO_APIC_pin(apic, pin);
2803
2804         memset(&entry1, 0, sizeof(entry1));
2805
2806         entry1.dest_mode = 0;                   /* physical delivery */
2807         entry1.mask = 0;                        /* unmask IRQ now */
2808         entry1.dest = hard_smp_processor_id();
2809         entry1.delivery_mode = dest_ExtINT;
2810         entry1.polarity = entry0.polarity;
2811         entry1.trigger = 0;
2812         entry1.vector = 0;
2813
2814         ioapic_write_entry(apic, pin, entry1);
2815
2816         save_control = CMOS_READ(RTC_CONTROL);
2817         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2818         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2819                    RTC_FREQ_SELECT);
2820         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2821
2822         i = 100;
2823         while (i-- > 0) {
2824                 mdelay(10);
2825                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2826                         i -= 10;
2827         }
2828
2829         CMOS_WRITE(save_control, RTC_CONTROL);
2830         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2831         clear_IO_APIC_pin(apic, pin);
2832
2833         ioapic_write_entry(apic, pin, entry0);
2834 }
2835
2836 static int disable_timer_pin_1 __initdata;
2837 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2838 static int __init disable_timer_pin_setup(char *arg)
2839 {
2840         disable_timer_pin_1 = 1;
2841         return 0;
2842 }
2843 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2844
2845 int timer_through_8259 __initdata;
2846
2847 /*
2848  * This code may look a bit paranoid, but it's supposed to cooperate with
2849  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2850  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2851  * fanatically on his truly buggy board.
2852  *
2853  * FIXME: really need to revamp this for all platforms.
2854  */
2855 static inline void __init check_timer(void)
2856 {
2857         struct irq_desc *desc = irq_to_desc(0);
2858         struct irq_cfg *cfg = desc->chip_data;
2859         int node = cpu_to_node(boot_cpu_id);
2860         int apic1, pin1, apic2, pin2;
2861         unsigned long flags;
2862         int no_pin1 = 0;
2863
2864         local_irq_save(flags);
2865
2866         /*
2867          * get/set the timer IRQ vector:
2868          */
2869         disable_8259A_irq(0);
2870         assign_irq_vector(0, cfg, apic->target_cpus());
2871
2872         /*
2873          * As IRQ0 is to be enabled in the 8259A, the virtual
2874          * wire has to be disabled in the local APIC.  Also
2875          * timer interrupts need to be acknowledged manually in
2876          * the 8259A for the i82489DX when using the NMI
2877          * watchdog as that APIC treats NMIs as level-triggered.
2878          * The AEOI mode will finish them in the 8259A
2879          * automatically.
2880          */
2881         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2882         init_8259A(1);
2883 #ifdef CONFIG_X86_32
2884         {
2885                 unsigned int ver;
2886
2887                 ver = apic_read(APIC_LVR);
2888                 ver = GET_APIC_VERSION(ver);
2889                 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2890         }
2891 #endif
2892
2893         pin1  = find_isa_irq_pin(0, mp_INT);
2894         apic1 = find_isa_irq_apic(0, mp_INT);
2895         pin2  = ioapic_i8259.pin;
2896         apic2 = ioapic_i8259.apic;
2897
2898         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2899                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2900                     cfg->vector, apic1, pin1, apic2, pin2);
2901
2902         /*
2903          * Some BIOS writers are clueless and report the ExtINTA
2904          * I/O APIC input from the cascaded 8259A as the timer
2905          * interrupt input.  So just in case, if only one pin
2906          * was found above, try it both directly and through the
2907          * 8259A.
2908          */
2909         if (pin1 == -1) {
2910                 if (intr_remapping_enabled)
2911                         panic("BIOS bug: timer not connected to IO-APIC");
2912                 pin1 = pin2;
2913                 apic1 = apic2;
2914                 no_pin1 = 1;
2915         } else if (pin2 == -1) {
2916                 pin2 = pin1;
2917                 apic2 = apic1;
2918         }
2919
2920         if (pin1 != -1) {
2921                 /*
2922                  * Ok, does IRQ0 through the IOAPIC work?
2923                  */
2924                 if (no_pin1) {
2925                         add_pin_to_irq_node(cfg, node, apic1, pin1);
2926                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2927                 } else {
2928                         /* for edge trigger, setup_IO_APIC_irq already
2929                          * leave it unmasked.
2930                          * so only need to unmask if it is level-trigger
2931                          * do we really have level trigger timer?
2932                          */
2933                         int idx;
2934                         idx = find_irq_entry(apic1, pin1, mp_INT);
2935                         if (idx != -1 && irq_trigger(idx))
2936                                 unmask_IO_APIC_irq_desc(desc);
2937                 }
2938                 if (timer_irq_works()) {
2939                         if (nmi_watchdog == NMI_IO_APIC) {
2940                                 setup_nmi();
2941                                 enable_8259A_irq(0);
2942                         }
2943                         if (disable_timer_pin_1 > 0)
2944                                 clear_IO_APIC_pin(0, pin1);
2945                         goto out;
2946                 }
2947                 if (intr_remapping_enabled)
2948                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2949                 local_irq_disable();
2950                 clear_IO_APIC_pin(apic1, pin1);
2951                 if (!no_pin1)
2952                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2953                                     "8254 timer not connected to IO-APIC\n");
2954
2955                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2956                             "(IRQ0) through the 8259A ...\n");
2957                 apic_printk(APIC_QUIET, KERN_INFO
2958                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2959                 /*
2960                  * legacy devices should be connected to IO APIC #0
2961                  */
2962                 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2963                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2964                 enable_8259A_irq(0);
2965                 if (timer_irq_works()) {
2966                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2967                         timer_through_8259 = 1;
2968                         if (nmi_watchdog == NMI_IO_APIC) {
2969                                 disable_8259A_irq(0);
2970                                 setup_nmi();
2971                                 enable_8259A_irq(0);
2972                         }
2973                         goto out;
2974                 }
2975                 /*
2976                  * Cleanup, just in case ...
2977                  */
2978                 local_irq_disable();
2979                 disable_8259A_irq(0);
2980                 clear_IO_APIC_pin(apic2, pin2);
2981                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2982         }
2983
2984         if (nmi_watchdog == NMI_IO_APIC) {
2985                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2986                             "through the IO-APIC - disabling NMI Watchdog!\n");
2987                 nmi_watchdog = NMI_NONE;
2988         }
2989 #ifdef CONFIG_X86_32
2990         timer_ack = 0;
2991 #endif
2992
2993         apic_printk(APIC_QUIET, KERN_INFO
2994                     "...trying to set up timer as Virtual Wire IRQ...\n");
2995
2996         lapic_register_intr(0, desc);
2997         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2998         enable_8259A_irq(0);
2999
3000         if (timer_irq_works()) {
3001                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3002                 goto out;
3003         }
3004         local_irq_disable();
3005         disable_8259A_irq(0);
3006         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3007         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3008
3009         apic_printk(APIC_QUIET, KERN_INFO
3010                     "...trying to set up timer as ExtINT IRQ...\n");
3011
3012         init_8259A(0);
3013         make_8259A_irq(0);
3014         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3015
3016         unlock_ExtINT_logic();
3017
3018         if (timer_irq_works()) {
3019                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3020                 goto out;
3021         }
3022         local_irq_disable();
3023         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3024         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3025                 "report.  Then try booting with the 'noapic' option.\n");
3026 out:
3027         local_irq_restore(flags);
3028 }
3029
3030 /*
3031  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3032  * to devices.  However there may be an I/O APIC pin available for
3033  * this interrupt regardless.  The pin may be left unconnected, but
3034  * typically it will be reused as an ExtINT cascade interrupt for
3035  * the master 8259A.  In the MPS case such a pin will normally be
3036  * reported as an ExtINT interrupt in the MP table.  With ACPI
3037  * there is no provision for ExtINT interrupts, and in the absence
3038  * of an override it would be treated as an ordinary ISA I/O APIC
3039  * interrupt, that is edge-triggered and unmasked by default.  We
3040  * used to do this, but it caused problems on some systems because
3041  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3042  * the same ExtINT cascade interrupt to drive the local APIC of the
3043  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3044  * the I/O APIC in all cases now.  No actual device should request
3045  * it anyway.  --macro
3046  */
3047 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3048
3049 void __init setup_IO_APIC(void)
3050 {
3051
3052         /*
3053          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3054          */
3055
3056         io_apic_irqs = ~PIC_IRQS;
3057
3058         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3059         /*
3060          * Set up IO-APIC IRQ routing.
3061          */
3062 #ifdef CONFIG_X86_32
3063         if (!acpi_ioapic)
3064                 setup_ioapic_ids_from_mpc();
3065 #endif
3066         sync_Arb_IDs();
3067         setup_IO_APIC_irqs();
3068         init_IO_APIC_traps();
3069         check_timer();
3070 }
3071
3072 /*
3073  *      Called after all the initialization is done. If we didnt find any
3074  *      APIC bugs then we can allow the modify fast path
3075  */
3076
3077 static int __init io_apic_bug_finalize(void)
3078 {
3079         if (sis_apic_bug == -1)
3080                 sis_apic_bug = 0;
3081         return 0;
3082 }
3083
3084 late_initcall(io_apic_bug_finalize);
3085
3086 struct sysfs_ioapic_data {
3087         struct sys_device dev;
3088         struct IO_APIC_route_entry entry[0];
3089 };
3090 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3091
3092 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3093 {
3094         struct IO_APIC_route_entry *entry;
3095         struct sysfs_ioapic_data *data;
3096         int i;
3097
3098         data = container_of(dev, struct sysfs_ioapic_data, dev);
3099         entry = data->entry;
3100         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3101                 *entry = ioapic_read_entry(dev->id, i);
3102
3103         return 0;
3104 }
3105
3106 static int ioapic_resume(struct sys_device *dev)
3107 {
3108         struct IO_APIC_route_entry *entry;
3109         struct sysfs_ioapic_data *data;
3110         unsigned long flags;
3111         union IO_APIC_reg_00 reg_00;
3112         int i;
3113
3114         data = container_of(dev, struct sysfs_ioapic_data, dev);
3115         entry = data->entry;
3116
3117         spin_lock_irqsave(&ioapic_lock, flags);
3118         reg_00.raw = io_apic_read(dev->id, 0);
3119         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3120                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3121                 io_apic_write(dev->id, 0, reg_00.raw);
3122         }
3123         spin_unlock_irqrestore(&ioapic_lock, flags);
3124         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3125                 ioapic_write_entry(dev->id, i, entry[i]);
3126
3127         return 0;
3128 }
3129
3130 static struct sysdev_class ioapic_sysdev_class = {
3131         .name = "ioapic",
3132         .suspend = ioapic_suspend,
3133         .resume = ioapic_resume,
3134 };
3135
3136 static int __init ioapic_init_sysfs(void)
3137 {
3138         struct sys_device * dev;
3139         int i, size, error;
3140
3141         error = sysdev_class_register(&ioapic_sysdev_class);
3142         if (error)
3143                 return error;
3144
3145         for (i = 0; i < nr_ioapics; i++ ) {
3146                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3147                         * sizeof(struct IO_APIC_route_entry);
3148                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3149                 if (!mp_ioapic_data[i]) {
3150                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3151                         continue;
3152                 }
3153                 dev = &mp_ioapic_data[i]->dev;
3154                 dev->id = i;
3155                 dev->cls = &ioapic_sysdev_class;
3156                 error = sysdev_register(dev);
3157                 if (error) {
3158                         kfree(mp_ioapic_data[i]);
3159                         mp_ioapic_data[i] = NULL;
3160                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3161                         continue;
3162                 }
3163         }
3164
3165         return 0;
3166 }
3167
3168 device_initcall(ioapic_init_sysfs);
3169
3170 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3171 /*
3172  * Dynamic irq allocate and deallocation
3173  */
3174 unsigned int create_irq_nr(unsigned int irq_want, int node)
3175 {
3176         /* Allocate an unused irq */
3177         unsigned int irq;
3178         unsigned int new;
3179         unsigned long flags;
3180         struct irq_cfg *cfg_new = NULL;
3181         struct irq_desc *desc_new = NULL;
3182
3183         irq = 0;
3184         if (irq_want < nr_irqs_gsi)
3185                 irq_want = nr_irqs_gsi;
3186
3187         spin_lock_irqsave(&vector_lock, flags);
3188         for (new = irq_want; new < nr_irqs; new++) {
3189                 desc_new = irq_to_desc_alloc_node(new, node);
3190                 if (!desc_new) {
3191                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3192                         continue;
3193                 }
3194                 cfg_new = desc_new->chip_data;
3195
3196                 if (cfg_new->vector != 0)
3197                         continue;
3198
3199                 desc_new = move_irq_desc(desc_new, node);
3200
3201                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3202                         irq = new;
3203                 break;
3204         }
3205         spin_unlock_irqrestore(&vector_lock, flags);
3206
3207         if (irq > 0) {
3208                 dynamic_irq_init(irq);
3209                 /* restore it, in case dynamic_irq_init clear it */
3210                 if (desc_new)
3211                         desc_new->chip_data = cfg_new;
3212         }
3213         return irq;
3214 }
3215
3216 int create_irq(void)
3217 {
3218         int node = cpu_to_node(boot_cpu_id);
3219         unsigned int irq_want;
3220         int irq;
3221
3222         irq_want = nr_irqs_gsi;
3223         irq = create_irq_nr(irq_want, node);
3224
3225         if (irq == 0)
3226                 irq = -1;
3227
3228         return irq;
3229 }
3230
3231 void destroy_irq(unsigned int irq)
3232 {
3233         unsigned long flags;
3234         struct irq_cfg *cfg;
3235         struct irq_desc *desc;
3236
3237         /* store it, in case dynamic_irq_cleanup clear it */
3238         desc = irq_to_desc(irq);
3239         cfg = desc->chip_data;
3240         dynamic_irq_cleanup(irq);
3241         /* connect back irq_cfg */
3242         if (desc)
3243                 desc->chip_data = cfg;
3244
3245         free_irte(irq);
3246         spin_lock_irqsave(&vector_lock, flags);
3247         __clear_irq_vector(irq, cfg);
3248         spin_unlock_irqrestore(&vector_lock, flags);
3249 }
3250
3251 /*
3252  * MSI message composition
3253  */
3254 #ifdef CONFIG_PCI_MSI
3255 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3256 {
3257         struct irq_cfg *cfg;
3258         int err;
3259         unsigned dest;
3260
3261         if (disable_apic)
3262                 return -ENXIO;
3263
3264         cfg = irq_cfg(irq);
3265         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3266         if (err)
3267                 return err;
3268
3269         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3270
3271         if (irq_remapped(irq)) {
3272                 struct irte irte;
3273                 int ir_index;
3274                 u16 sub_handle;
3275
3276                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3277                 BUG_ON(ir_index == -1);
3278
3279                 memset (&irte, 0, sizeof(irte));
3280
3281                 irte.present = 1;
3282                 irte.dst_mode = apic->irq_dest_mode;
3283                 irte.trigger_mode = 0; /* edge */
3284                 irte.dlvry_mode = apic->irq_delivery_mode;
3285                 irte.vector = cfg->vector;
3286                 irte.dest_id = IRTE_DEST(dest);
3287
3288                 modify_irte(irq, &irte);
3289
3290                 msg->address_hi = MSI_ADDR_BASE_HI;
3291                 msg->data = sub_handle;
3292                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3293                                   MSI_ADDR_IR_SHV |
3294                                   MSI_ADDR_IR_INDEX1(ir_index) |
3295                                   MSI_ADDR_IR_INDEX2(ir_index);
3296         } else {
3297                 if (x2apic_enabled())
3298                         msg->address_hi = MSI_ADDR_BASE_HI |
3299                                           MSI_ADDR_EXT_DEST_ID(dest);
3300                 else
3301                         msg->address_hi = MSI_ADDR_BASE_HI;
3302
3303                 msg->address_lo =
3304                         MSI_ADDR_BASE_LO |
3305                         ((apic->irq_dest_mode == 0) ?
3306                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3307                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3308                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3309                                 MSI_ADDR_REDIRECTION_CPU:
3310                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3311                         MSI_ADDR_DEST_ID(dest);
3312
3313                 msg->data =
3314                         MSI_DATA_TRIGGER_EDGE |
3315                         MSI_DATA_LEVEL_ASSERT |
3316                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3317                                 MSI_DATA_DELIVERY_FIXED:
3318                                 MSI_DATA_DELIVERY_LOWPRI) |
3319                         MSI_DATA_VECTOR(cfg->vector);
3320         }
3321         return err;
3322 }
3323
3324 #ifdef CONFIG_SMP
3325 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3326 {
3327         struct irq_desc *desc = irq_to_desc(irq);
3328         struct irq_cfg *cfg;
3329         struct msi_msg msg;
3330         unsigned int dest;
3331
3332         dest = set_desc_affinity(desc, mask);
3333         if (dest == BAD_APICID)
3334                 return -1;
3335
3336         cfg = desc->chip_data;
3337
3338         read_msi_msg_desc(desc, &msg);
3339
3340         msg.data &= ~MSI_DATA_VECTOR_MASK;
3341         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3342         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3343         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3344
3345         write_msi_msg_desc(desc, &msg);
3346
3347         return 0;
3348 }
3349 #ifdef CONFIG_INTR_REMAP
3350 /*
3351  * Migrate the MSI irq to another cpumask. This migration is
3352  * done in the process context using interrupt-remapping hardware.
3353  */
3354 static int
3355 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3356 {
3357         struct irq_desc *desc = irq_to_desc(irq);
3358         struct irq_cfg *cfg = desc->chip_data;
3359         unsigned int dest;
3360         struct irte irte;
3361
3362         if (get_irte(irq, &irte))
3363                 return -1;
3364
3365         dest = set_desc_affinity(desc, mask);
3366         if (dest == BAD_APICID)
3367                 return -1;
3368
3369         irte.vector = cfg->vector;
3370         irte.dest_id = IRTE_DEST(dest);
3371
3372         /*
3373          * atomically update the IRTE with the new destination and vector.
3374          */
3375         modify_irte(irq, &irte);
3376
3377         /*
3378          * After this point, all the interrupts will start arriving
3379          * at the new destination. So, time to cleanup the previous
3380          * vector allocation.
3381          */
3382         if (cfg->move_in_progress)
3383                 send_cleanup_vector(cfg);
3384
3385         return 0;
3386 }
3387
3388 #endif
3389 #endif /* CONFIG_SMP */
3390
3391 /*
3392  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3393  * which implement the MSI or MSI-X Capability Structure.
3394  */
3395 static struct irq_chip msi_chip = {
3396         .name           = "PCI-MSI",
3397         .unmask         = unmask_msi_irq,
3398         .mask           = mask_msi_irq,
3399         .ack            = ack_apic_edge,
3400 #ifdef CONFIG_SMP
3401         .set_affinity   = set_msi_irq_affinity,
3402 #endif
3403         .retrigger      = ioapic_retrigger_irq,
3404 };
3405
3406 static struct irq_chip msi_ir_chip = {
3407         .name           = "IR-PCI-MSI",
3408         .unmask         = unmask_msi_irq,
3409         .mask           = mask_msi_irq,
3410 #ifdef CONFIG_INTR_REMAP
3411         .ack            = ir_ack_apic_edge,
3412 #ifdef CONFIG_SMP
3413         .set_affinity   = ir_set_msi_irq_affinity,
3414 #endif
3415 #endif
3416         .retrigger      = ioapic_retrigger_irq,
3417 };
3418
3419 /*
3420  * Map the PCI dev to the corresponding remapping hardware unit
3421  * and allocate 'nvec' consecutive interrupt-remapping table entries
3422  * in it.
3423  */
3424 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3425 {
3426         struct intel_iommu *iommu;
3427         int index;
3428
3429         iommu = map_dev_to_ir(dev);
3430         if (!iommu) {
3431                 printk(KERN_ERR
3432                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3433                 return -ENOENT;
3434         }
3435
3436         index = alloc_irte(iommu, irq, nvec);
3437         if (index < 0) {
3438                 printk(KERN_ERR
3439                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3440                        pci_name(dev));
3441                 return -ENOSPC;
3442         }
3443         return index;
3444 }
3445
3446 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3447 {
3448         int ret;
3449         struct msi_msg msg;
3450
3451         ret = msi_compose_msg(dev, irq, &msg);
3452         if (ret < 0)
3453                 return ret;
3454
3455         set_irq_msi(irq, msidesc);
3456         write_msi_msg(irq, &msg);
3457
3458         if (irq_remapped(irq)) {
3459                 struct irq_desc *desc = irq_to_desc(irq);
3460                 /*
3461                  * irq migration in process context
3462                  */
3463                 desc->status |= IRQ_MOVE_PCNTXT;
3464                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3465         } else
3466                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3467
3468         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3469
3470         return 0;
3471 }
3472
3473 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3474 {
3475         unsigned int irq;
3476         int ret, sub_handle;
3477         struct msi_desc *msidesc;
3478         unsigned int irq_want;
3479         struct intel_iommu *iommu = NULL;
3480         int index = 0;
3481         int node;
3482
3483         /* x86 doesn't support multiple MSI yet */
3484         if (type == PCI_CAP_ID_MSI && nvec > 1)
3485                 return 1;
3486
3487         node = dev_to_node(&dev->dev);
3488         irq_want = nr_irqs_gsi;
3489         sub_handle = 0;
3490         list_for_each_entry(msidesc, &dev->msi_list, list) {
3491                 irq = create_irq_nr(irq_want, node);
3492                 if (irq == 0)
3493                         return -1;
3494                 irq_want = irq + 1;
3495                 if (!intr_remapping_enabled)
3496                         goto no_ir;
3497
3498                 if (!sub_handle) {
3499                         /*
3500                          * allocate the consecutive block of IRTE's
3501                          * for 'nvec'
3502                          */
3503                         index = msi_alloc_irte(dev, irq, nvec);
3504                         if (index < 0) {
3505                                 ret = index;
3506                                 goto error;
3507                         }
3508                 } else {
3509                         iommu = map_dev_to_ir(dev);
3510                         if (!iommu) {
3511                                 ret = -ENOENT;
3512                                 goto error;
3513                         }
3514                         /*
3515                          * setup the mapping between the irq and the IRTE
3516                          * base index, the sub_handle pointing to the
3517                          * appropriate interrupt remap table entry.
3518                          */
3519                         set_irte_irq(irq, iommu, index, sub_handle);
3520                 }
3521 no_ir:
3522                 ret = setup_msi_irq(dev, msidesc, irq);
3523                 if (ret < 0)
3524                         goto error;
3525                 sub_handle++;
3526         }
3527         return 0;
3528
3529 error:
3530         destroy_irq(irq);
3531         return ret;
3532 }
3533
3534 void arch_teardown_msi_irq(unsigned int irq)
3535 {
3536         destroy_irq(irq);
3537 }
3538
3539 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3540 #ifdef CONFIG_SMP
3541 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3542 {
3543         struct irq_desc *desc = irq_to_desc(irq);
3544         struct irq_cfg *cfg;
3545         struct msi_msg msg;
3546         unsigned int dest;
3547
3548         dest = set_desc_affinity(desc, mask);
3549         if (dest == BAD_APICID)
3550                 return -1;
3551
3552         cfg = desc->chip_data;
3553
3554         dmar_msi_read(irq, &msg);
3555
3556         msg.data &= ~MSI_DATA_VECTOR_MASK;
3557         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3558         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3559         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3560
3561         dmar_msi_write(irq, &msg);
3562
3563         return 0;
3564 }
3565
3566 #endif /* CONFIG_SMP */
3567
3568 struct irq_chip dmar_msi_type = {
3569         .name = "DMAR_MSI",
3570         .unmask = dmar_msi_unmask,
3571         .mask = dmar_msi_mask,
3572         .ack = ack_apic_edge,
3573 #ifdef CONFIG_SMP
3574         .set_affinity = dmar_msi_set_affinity,
3575 #endif
3576         .retrigger = ioapic_retrigger_irq,
3577 };
3578
3579 int arch_setup_dmar_msi(unsigned int irq)
3580 {
3581         int ret;
3582         struct msi_msg msg;
3583
3584         ret = msi_compose_msg(NULL, irq, &msg);
3585         if (ret < 0)
3586                 return ret;
3587         dmar_msi_write(irq, &msg);
3588         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3589                 "edge");
3590         return 0;
3591 }
3592 #endif
3593
3594 #ifdef CONFIG_HPET_TIMER
3595
3596 #ifdef CONFIG_SMP
3597 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3598 {
3599         struct irq_desc *desc = irq_to_desc(irq);
3600         struct irq_cfg *cfg;
3601         struct msi_msg msg;
3602         unsigned int dest;
3603
3604         dest = set_desc_affinity(desc, mask);
3605         if (dest == BAD_APICID)
3606                 return -1;
3607
3608         cfg = desc->chip_data;
3609
3610         hpet_msi_read(irq, &msg);
3611
3612         msg.data &= ~MSI_DATA_VECTOR_MASK;
3613         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3614         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3615         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3616
3617         hpet_msi_write(irq, &msg);
3618
3619         return 0;
3620 }
3621
3622 #endif /* CONFIG_SMP */
3623
3624 static struct irq_chip hpet_msi_type = {
3625         .name = "HPET_MSI",
3626         .unmask = hpet_msi_unmask,
3627         .mask = hpet_msi_mask,
3628         .ack = ack_apic_edge,
3629 #ifdef CONFIG_SMP
3630         .set_affinity = hpet_msi_set_affinity,
3631 #endif
3632         .retrigger = ioapic_retrigger_irq,
3633 };
3634
3635 int arch_setup_hpet_msi(unsigned int irq)
3636 {
3637         int ret;
3638         struct msi_msg msg;
3639         struct irq_desc *desc = irq_to_desc(irq);
3640
3641         ret = msi_compose_msg(NULL, irq, &msg);
3642         if (ret < 0)
3643                 return ret;
3644
3645         hpet_msi_write(irq, &msg);
3646         desc->status |= IRQ_MOVE_PCNTXT;
3647         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3648                 "edge");
3649
3650         return 0;
3651 }
3652 #endif
3653
3654 #endif /* CONFIG_PCI_MSI */
3655 /*
3656  * Hypertransport interrupt support
3657  */
3658 #ifdef CONFIG_HT_IRQ
3659
3660 #ifdef CONFIG_SMP
3661
3662 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3663 {
3664         struct ht_irq_msg msg;
3665         fetch_ht_irq_msg(irq, &msg);
3666
3667         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3668         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3669
3670         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3671         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3672
3673         write_ht_irq_msg(irq, &msg);
3674 }
3675
3676 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3677 {
3678         struct irq_desc *desc = irq_to_desc(irq);
3679         struct irq_cfg *cfg;
3680         unsigned int dest;
3681
3682         dest = set_desc_affinity(desc, mask);
3683         if (dest == BAD_APICID)
3684                 return -1;
3685
3686         cfg = desc->chip_data;
3687
3688         target_ht_irq(irq, dest, cfg->vector);
3689
3690         return 0;
3691 }
3692
3693 #endif
3694
3695 static struct irq_chip ht_irq_chip = {
3696         .name           = "PCI-HT",
3697         .mask           = mask_ht_irq,
3698         .unmask         = unmask_ht_irq,
3699         .ack            = ack_apic_edge,
3700 #ifdef CONFIG_SMP
3701         .set_affinity   = set_ht_irq_affinity,
3702 #endif
3703         .retrigger      = ioapic_retrigger_irq,
3704 };
3705
3706 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3707 {
3708         struct irq_cfg *cfg;
3709         int err;
3710
3711         if (disable_apic)
3712                 return -ENXIO;
3713
3714         cfg = irq_cfg(irq);
3715         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3716         if (!err) {
3717                 struct ht_irq_msg msg;
3718                 unsigned dest;
3719
3720                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3721                                                     apic->target_cpus());
3722
3723                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3724
3725                 msg.address_lo =
3726                         HT_IRQ_LOW_BASE |
3727                         HT_IRQ_LOW_DEST_ID(dest) |
3728                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3729                         ((apic->irq_dest_mode == 0) ?
3730                                 HT_IRQ_LOW_DM_PHYSICAL :
3731                                 HT_IRQ_LOW_DM_LOGICAL) |
3732                         HT_IRQ_LOW_RQEOI_EDGE |
3733                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3734                                 HT_IRQ_LOW_MT_FIXED :
3735                                 HT_IRQ_LOW_MT_ARBITRATED) |
3736                         HT_IRQ_LOW_IRQ_MASKED;
3737
3738                 write_ht_irq_msg(irq, &msg);
3739
3740                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3741                                               handle_edge_irq, "edge");
3742
3743                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3744         }
3745         return err;
3746 }
3747 #endif /* CONFIG_HT_IRQ */
3748
3749 #ifdef CONFIG_X86_UV
3750 /*
3751  * Re-target the irq to the specified CPU and enable the specified MMR located
3752  * on the specified blade to allow the sending of MSIs to the specified CPU.
3753  */
3754 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3755                        unsigned long mmr_offset)
3756 {
3757         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3758         struct irq_cfg *cfg;
3759         int mmr_pnode;
3760         unsigned long mmr_value;
3761         struct uv_IO_APIC_route_entry *entry;
3762         unsigned long flags;
3763         int err;
3764
3765         BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3766
3767         cfg = irq_cfg(irq);
3768
3769         err = assign_irq_vector(irq, cfg, eligible_cpu);
3770         if (err != 0)
3771                 return err;
3772
3773         spin_lock_irqsave(&vector_lock, flags);
3774         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3775                                       irq_name);
3776         spin_unlock_irqrestore(&vector_lock, flags);
3777
3778         mmr_value = 0;
3779         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3780         entry->vector           = cfg->vector;
3781         entry->delivery_mode    = apic->irq_delivery_mode;
3782         entry->dest_mode        = apic->irq_dest_mode;
3783         entry->polarity         = 0;
3784         entry->trigger          = 0;
3785         entry->mask             = 0;
3786         entry->dest             = apic->cpu_mask_to_apicid(eligible_cpu);
3787
3788         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3789         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3790
3791         return irq;
3792 }
3793
3794 /*
3795  * Disable the specified MMR located on the specified blade so that MSIs are
3796  * longer allowed to be sent.
3797  */
3798 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3799 {
3800         unsigned long mmr_value;
3801         struct uv_IO_APIC_route_entry *entry;
3802         int mmr_pnode;
3803
3804         BUILD_BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3805
3806         mmr_value = 0;
3807         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3808         entry->mask = 1;
3809
3810         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3811         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3812 }
3813 #endif /* CONFIG_X86_64 */
3814
3815 int __init io_apic_get_redir_entries (int ioapic)
3816 {
3817         union IO_APIC_reg_01    reg_01;
3818         unsigned long flags;
3819
3820         spin_lock_irqsave(&ioapic_lock, flags);
3821         reg_01.raw = io_apic_read(ioapic, 1);
3822         spin_unlock_irqrestore(&ioapic_lock, flags);
3823
3824         return reg_01.bits.entries;
3825 }
3826
3827 void __init probe_nr_irqs_gsi(void)
3828 {
3829         int nr = 0;
3830
3831         nr = acpi_probe_gsi();
3832         if (nr > nr_irqs_gsi) {
3833                 nr_irqs_gsi = nr;
3834         } else {
3835                 /* for acpi=off or acpi is not compiled in */
3836                 int idx;
3837
3838                 nr = 0;
3839                 for (idx = 0; idx < nr_ioapics; idx++)
3840                         nr += io_apic_get_redir_entries(idx) + 1;
3841
3842                 if (nr > nr_irqs_gsi)
3843                         nr_irqs_gsi = nr;
3844         }
3845
3846         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3847 }
3848
3849 #ifdef CONFIG_SPARSE_IRQ
3850 int __init arch_probe_nr_irqs(void)
3851 {
3852         int nr;
3853
3854         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3855                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3856
3857         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3858 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3859         /*
3860          * for MSI and HT dyn irq
3861          */
3862         nr += nr_irqs_gsi * 16;
3863 #endif
3864         if (nr < nr_irqs)
3865                 nr_irqs = nr;
3866
3867         return 0;
3868 }
3869 #endif
3870
3871 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3872                                 struct io_apic_irq_attr *irq_attr)
3873 {
3874         struct irq_desc *desc;
3875         struct irq_cfg *cfg;
3876         int node;
3877         int ioapic, pin;
3878         int trigger, polarity;
3879
3880         ioapic = irq_attr->ioapic;
3881         if (!IO_APIC_IRQ(irq)) {
3882                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3883                         ioapic);
3884                 return -EINVAL;
3885         }
3886
3887         if (dev)
3888                 node = dev_to_node(dev);
3889         else
3890                 node = cpu_to_node(boot_cpu_id);
3891
3892         desc = irq_to_desc_alloc_node(irq, node);
3893         if (!desc) {
3894                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3895                 return 0;
3896         }
3897
3898         pin = irq_attr->ioapic_pin;
3899         trigger = irq_attr->trigger;
3900         polarity = irq_attr->polarity;
3901
3902         /*
3903          * IRQs < 16 are already in the irq_2_pin[] map
3904          */
3905         if (irq >= NR_IRQS_LEGACY) {
3906                 cfg = desc->chip_data;
3907                 add_pin_to_irq_node(cfg, node, ioapic, pin);
3908         }
3909
3910         setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3911
3912         return 0;
3913 }
3914
3915 int io_apic_set_pci_routing(struct device *dev, int irq,
3916                                 struct io_apic_irq_attr *irq_attr)
3917 {
3918         int ioapic, pin;
3919         /*
3920          * Avoid pin reprogramming.  PRTs typically include entries
3921          * with redundant pin->gsi mappings (but unique PCI devices);
3922          * we only program the IOAPIC on the first.
3923          */
3924         ioapic = irq_attr->ioapic;
3925         pin = irq_attr->ioapic_pin;
3926         if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3927                 pr_debug("Pin %d-%d already programmed\n",
3928                          mp_ioapics[ioapic].apicid, pin);
3929                 return 0;
3930         }
3931         set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3932
3933         return __io_apic_set_pci_routing(dev, irq, irq_attr);
3934 }
3935
3936 /* --------------------------------------------------------------------------
3937                           ACPI-based IOAPIC Configuration
3938    -------------------------------------------------------------------------- */
3939
3940 #ifdef CONFIG_ACPI
3941
3942 #ifdef CONFIG_X86_32
3943 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3944 {
3945         union IO_APIC_reg_00 reg_00;
3946         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3947         physid_mask_t tmp;
3948         unsigned long flags;
3949         int i = 0;
3950
3951         /*
3952          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3953          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3954          * supports up to 16 on one shared APIC bus.
3955          *
3956          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3957          *      advantage of new APIC bus architecture.
3958          */
3959
3960         if (physids_empty(apic_id_map))
3961                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3962
3963         spin_lock_irqsave(&ioapic_lock, flags);
3964         reg_00.raw = io_apic_read(ioapic, 0);
3965         spin_unlock_irqrestore(&ioapic_lock, flags);
3966
3967         if (apic_id >= get_physical_broadcast()) {
3968                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3969                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3970                 apic_id = reg_00.bits.ID;
3971         }
3972
3973         /*
3974          * Every APIC in a system must have a unique ID or we get lots of nice
3975          * 'stuck on smp_invalidate_needed IPI wait' messages.
3976          */
3977         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3978
3979                 for (i = 0; i < get_physical_broadcast(); i++) {
3980                         if (!apic->check_apicid_used(apic_id_map, i))
3981                                 break;
3982                 }
3983
3984                 if (i == get_physical_broadcast())
3985                         panic("Max apic_id exceeded!\n");
3986
3987                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3988                         "trying %d\n", ioapic, apic_id, i);
3989
3990                 apic_id = i;
3991         }
3992
3993         tmp = apic->apicid_to_cpu_present(apic_id);
3994         physids_or(apic_id_map, apic_id_map, tmp);
3995
3996         if (reg_00.bits.ID != apic_id) {
3997                 reg_00.bits.ID = apic_id;
3998
3999                 spin_lock_irqsave(&ioapic_lock, flags);
4000                 io_apic_write(ioapic, 0, reg_00.raw);
4001                 reg_00.raw = io_apic_read(ioapic, 0);
4002                 spin_unlock_irqrestore(&ioapic_lock, flags);
4003
4004                 /* Sanity check */
4005                 if (reg_00.bits.ID != apic_id) {
4006                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4007                         return -1;
4008                 }
4009         }
4010
4011         apic_printk(APIC_VERBOSE, KERN_INFO
4012                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4013
4014         return apic_id;
4015 }
4016 #endif
4017
4018 int __init io_apic_get_version(int ioapic)
4019 {
4020         union IO_APIC_reg_01    reg_01;
4021         unsigned long flags;
4022
4023         spin_lock_irqsave(&ioapic_lock, flags);
4024         reg_01.raw = io_apic_read(ioapic, 1);
4025         spin_unlock_irqrestore(&ioapic_lock, flags);
4026
4027         return reg_01.bits.version;
4028 }
4029
4030 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4031 {
4032         int i;
4033
4034         if (skip_ioapic_setup)
4035                 return -1;
4036
4037         for (i = 0; i < mp_irq_entries; i++)
4038                 if (mp_irqs[i].irqtype == mp_INT &&
4039                     mp_irqs[i].srcbusirq == bus_irq)
4040                         break;
4041         if (i >= mp_irq_entries)
4042                 return -1;
4043
4044         *trigger = irq_trigger(i);
4045         *polarity = irq_polarity(i);
4046         return 0;
4047 }
4048
4049 #endif /* CONFIG_ACPI */
4050
4051 /*
4052  * This function currently is only a helper for the i386 smp boot process where
4053  * we need to reprogram the ioredtbls to cater for the cpus which have come online
4054  * so mask in all cases should simply be apic->target_cpus()
4055  */
4056 #ifdef CONFIG_SMP
4057 void __init setup_ioapic_dest(void)
4058 {
4059         int pin, ioapic = 0, irq, irq_entry;
4060         struct irq_desc *desc;
4061         const struct cpumask *mask;
4062
4063         if (skip_ioapic_setup == 1)
4064                 return;
4065
4066 #ifdef CONFIG_ACPI
4067         if (!acpi_disabled && acpi_ioapic) {
4068                 ioapic = mp_find_ioapic(0);
4069                 if (ioapic < 0)
4070                         ioapic = 0;
4071         }
4072 #endif
4073
4074         for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4075                 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4076                 if (irq_entry == -1)
4077                         continue;
4078                 irq = pin_2_irq(irq_entry, ioapic, pin);
4079
4080                 desc = irq_to_desc(irq);
4081
4082                 /*
4083                  * Honour affinities which have been set in early boot
4084                  */
4085                 if (desc->status &
4086                     (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4087                         mask = desc->affinity;
4088                 else
4089                         mask = apic->target_cpus();
4090
4091                 if (intr_remapping_enabled)
4092                         set_ir_ioapic_affinity_irq_desc(desc, mask);
4093                 else
4094                         set_ioapic_affinity_irq_desc(desc, mask);
4095         }
4096
4097 }
4098 #endif
4099
4100 #define IOAPIC_RESOURCE_NAME_SIZE 11
4101
4102 static struct resource *ioapic_resources;
4103
4104 static struct resource * __init ioapic_setup_resources(void)
4105 {
4106         unsigned long n;
4107         struct resource *res;
4108         char *mem;
4109         int i;
4110
4111         if (nr_ioapics <= 0)
4112                 return NULL;
4113
4114         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4115         n *= nr_ioapics;
4116
4117         mem = alloc_bootmem(n);
4118         res = (void *)mem;
4119
4120         if (mem != NULL) {
4121                 mem += sizeof(struct resource) * nr_ioapics;
4122
4123                 for (i = 0; i < nr_ioapics; i++) {
4124                         res[i].name = mem;
4125                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4126                         sprintf(mem,  "IOAPIC %u", i);
4127                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4128                 }
4129         }
4130
4131         ioapic_resources = res;
4132
4133         return res;
4134 }
4135
4136 void __init ioapic_init_mappings(void)
4137 {
4138         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4139         struct resource *ioapic_res;
4140         int i;
4141
4142         ioapic_res = ioapic_setup_resources();
4143         for (i = 0; i < nr_ioapics; i++) {
4144                 if (smp_found_config) {
4145                         ioapic_phys = mp_ioapics[i].apicaddr;
4146 #ifdef CONFIG_X86_32
4147                         if (!ioapic_phys) {
4148                                 printk(KERN_ERR
4149                                        "WARNING: bogus zero IO-APIC "
4150                                        "address found in MPTABLE, "
4151                                        "disabling IO/APIC support!\n");
4152                                 smp_found_config = 0;
4153                                 skip_ioapic_setup = 1;
4154                                 goto fake_ioapic_page;
4155                         }
4156 #endif
4157                 } else {
4158 #ifdef CONFIG_X86_32
4159 fake_ioapic_page:
4160 #endif
4161                         ioapic_phys = (unsigned long)
4162                                 alloc_bootmem_pages(PAGE_SIZE);
4163                         ioapic_phys = __pa(ioapic_phys);
4164                 }
4165                 set_fixmap_nocache(idx, ioapic_phys);
4166                 apic_printk(APIC_VERBOSE,
4167                             "mapped IOAPIC to %08lx (%08lx)\n",
4168                             __fix_to_virt(idx), ioapic_phys);
4169                 idx++;
4170
4171                 if (ioapic_res != NULL) {
4172                         ioapic_res->start = ioapic_phys;
4173                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4174                         ioapic_res++;
4175                 }
4176         }
4177 }
4178
4179 static int __init ioapic_insert_resources(void)
4180 {
4181         int i;
4182         struct resource *r = ioapic_resources;
4183
4184         if (!r) {
4185                 if (nr_ioapics > 0) {
4186                         printk(KERN_ERR
4187                                 "IO APIC resources couldn't be allocated.\n");
4188                         return -1;
4189                 }
4190                 return 0;
4191         }
4192
4193         for (i = 0; i < nr_ioapics; i++) {
4194                 insert_resource(&iomem_resource, r);
4195                 r++;
4196         }
4197
4198         return 0;
4199 }
4200
4201 /* Insert the IO APIC resources after PCI initialization has occured to handle
4202  * IO APICS that are mapped in on a BAR in PCI space. */
4203 late_initcall(ioapic_insert_resources);