2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
44 #ifdef CONFIG_IOMMU_API
45 static struct iommu_ops amd_iommu_ops;
49 * general struct to manage commands send to an IOMMU
55 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
56 struct unity_map_entry *e);
57 static struct dma_ops_domain *find_protection_domain(u16 devid);
58 static u64* alloc_pte(struct protection_domain *dom,
59 unsigned long address, u64
60 **pte_page, gfp_t gfp);
61 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
62 unsigned long start_page,
64 static u64 *fetch_pte(struct protection_domain *domain,
65 unsigned long address);
67 #ifndef BUS_NOTIFY_UNBOUND_DRIVER
68 #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005
71 #ifdef CONFIG_AMD_IOMMU_STATS
74 * Initialization code for statistics collection
77 DECLARE_STATS_COUNTER(compl_wait);
78 DECLARE_STATS_COUNTER(cnt_map_single);
79 DECLARE_STATS_COUNTER(cnt_unmap_single);
80 DECLARE_STATS_COUNTER(cnt_map_sg);
81 DECLARE_STATS_COUNTER(cnt_unmap_sg);
82 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
83 DECLARE_STATS_COUNTER(cnt_free_coherent);
84 DECLARE_STATS_COUNTER(cross_page);
85 DECLARE_STATS_COUNTER(domain_flush_single);
86 DECLARE_STATS_COUNTER(domain_flush_all);
87 DECLARE_STATS_COUNTER(alloced_io_mem);
88 DECLARE_STATS_COUNTER(total_map_requests);
90 static struct dentry *stats_dir;
91 static struct dentry *de_isolate;
92 static struct dentry *de_fflush;
94 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
96 if (stats_dir == NULL)
99 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
103 static void amd_iommu_stats_init(void)
105 stats_dir = debugfs_create_dir("amd-iommu", NULL);
106 if (stats_dir == NULL)
109 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
110 (u32 *)&amd_iommu_isolate);
112 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
113 (u32 *)&amd_iommu_unmap_flush);
115 amd_iommu_stats_add(&compl_wait);
116 amd_iommu_stats_add(&cnt_map_single);
117 amd_iommu_stats_add(&cnt_unmap_single);
118 amd_iommu_stats_add(&cnt_map_sg);
119 amd_iommu_stats_add(&cnt_unmap_sg);
120 amd_iommu_stats_add(&cnt_alloc_coherent);
121 amd_iommu_stats_add(&cnt_free_coherent);
122 amd_iommu_stats_add(&cross_page);
123 amd_iommu_stats_add(&domain_flush_single);
124 amd_iommu_stats_add(&domain_flush_all);
125 amd_iommu_stats_add(&alloced_io_mem);
126 amd_iommu_stats_add(&total_map_requests);
131 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
132 static int iommu_has_npcache(struct amd_iommu *iommu)
134 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
137 /****************************************************************************
139 * Interrupt handling functions
141 ****************************************************************************/
143 static void iommu_print_event(void *__evt)
146 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
147 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
148 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
149 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
150 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
152 printk(KERN_ERR "AMD IOMMU: Event logged [");
155 case EVENT_TYPE_ILL_DEV:
156 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
157 "address=0x%016llx flags=0x%04x]\n",
158 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
161 case EVENT_TYPE_IO_FAULT:
162 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
163 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
164 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
165 domid, address, flags);
167 case EVENT_TYPE_DEV_TAB_ERR:
168 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
169 "address=0x%016llx flags=0x%04x]\n",
170 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
173 case EVENT_TYPE_PAGE_TAB_ERR:
174 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
175 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
176 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
177 domid, address, flags);
179 case EVENT_TYPE_ILL_CMD:
180 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
182 case EVENT_TYPE_CMD_HARD_ERR:
183 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
184 "flags=0x%04x]\n", address, flags);
186 case EVENT_TYPE_IOTLB_INV_TO:
187 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
188 "address=0x%016llx]\n",
189 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
192 case EVENT_TYPE_INV_DEV_REQ:
193 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
194 "address=0x%016llx flags=0x%04x]\n",
195 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
199 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
203 static void iommu_poll_events(struct amd_iommu *iommu)
208 spin_lock_irqsave(&iommu->lock, flags);
210 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
211 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
213 while (head != tail) {
214 iommu_print_event(iommu->evt_buf + head);
215 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
218 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
220 spin_unlock_irqrestore(&iommu->lock, flags);
223 irqreturn_t amd_iommu_int_handler(int irq, void *data)
225 struct amd_iommu *iommu;
227 for_each_iommu(iommu)
228 iommu_poll_events(iommu);
233 /****************************************************************************
235 * IOMMU command queuing functions
237 ****************************************************************************/
240 * Writes the command to the IOMMUs command buffer and informs the
241 * hardware about the new command. Must be called with iommu->lock held.
243 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
248 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
249 target = iommu->cmd_buf + tail;
250 memcpy_toio(target, cmd, sizeof(*cmd));
251 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
252 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
255 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
261 * General queuing function for commands. Takes iommu->lock and calls
262 * __iommu_queue_command().
264 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
269 spin_lock_irqsave(&iommu->lock, flags);
270 ret = __iommu_queue_command(iommu, cmd);
272 iommu->need_sync = true;
273 spin_unlock_irqrestore(&iommu->lock, flags);
279 * This function waits until an IOMMU has completed a completion
282 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
288 INC_STATS_COUNTER(compl_wait);
290 while (!ready && (i < EXIT_LOOP_COUNT)) {
292 /* wait for the bit to become one */
293 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
294 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
297 /* set bit back to zero */
298 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
299 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
301 if (unlikely(i == EXIT_LOOP_COUNT))
302 panic("AMD IOMMU: Completion wait loop failed\n");
306 * This function queues a completion wait command into the command
309 static int __iommu_completion_wait(struct amd_iommu *iommu)
311 struct iommu_cmd cmd;
313 memset(&cmd, 0, sizeof(cmd));
314 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
315 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
317 return __iommu_queue_command(iommu, &cmd);
321 * This function is called whenever we need to ensure that the IOMMU has
322 * completed execution of all commands we sent. It sends a
323 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
324 * us about that by writing a value to a physical address we pass with
327 static int iommu_completion_wait(struct amd_iommu *iommu)
332 spin_lock_irqsave(&iommu->lock, flags);
334 if (!iommu->need_sync)
337 ret = __iommu_completion_wait(iommu);
339 iommu->need_sync = false;
344 __iommu_wait_for_completion(iommu);
347 spin_unlock_irqrestore(&iommu->lock, flags);
353 * Command send function for invalidating a device table entry
355 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
357 struct iommu_cmd cmd;
360 BUG_ON(iommu == NULL);
362 memset(&cmd, 0, sizeof(cmd));
363 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
366 ret = iommu_queue_command(iommu, &cmd);
371 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
372 u16 domid, int pde, int s)
374 memset(cmd, 0, sizeof(*cmd));
375 address &= PAGE_MASK;
376 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
377 cmd->data[1] |= domid;
378 cmd->data[2] = lower_32_bits(address);
379 cmd->data[3] = upper_32_bits(address);
380 if (s) /* size bit - we flush more than one 4kb page */
381 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
382 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
383 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
387 * Generic command send function for invalidaing TLB entries
389 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
390 u64 address, u16 domid, int pde, int s)
392 struct iommu_cmd cmd;
395 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
397 ret = iommu_queue_command(iommu, &cmd);
403 * TLB invalidation function which is called from the mapping functions.
404 * It invalidates a single PTE if the range to flush is within a single
405 * page. Otherwise it flushes the whole TLB of the IOMMU.
407 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
408 u64 address, size_t size)
411 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
413 address &= PAGE_MASK;
417 * If we have to flush more than one page, flush all
418 * TLB entries for this domain
420 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
424 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
429 /* Flush the whole IO/TLB for a given protection domain */
430 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
432 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
434 INC_STATS_COUNTER(domain_flush_single);
436 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
439 /* Flush the whole IO/TLB for a given protection domain - including PDE */
440 static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
442 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
444 INC_STATS_COUNTER(domain_flush_single);
446 iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1);
450 * This function is used to flush the IO/TLB for a given protection domain
451 * on every IOMMU in the system
453 static void iommu_flush_domain(u16 domid)
456 struct amd_iommu *iommu;
457 struct iommu_cmd cmd;
459 INC_STATS_COUNTER(domain_flush_all);
461 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
464 for_each_iommu(iommu) {
465 spin_lock_irqsave(&iommu->lock, flags);
466 __iommu_queue_command(iommu, &cmd);
467 __iommu_completion_wait(iommu);
468 __iommu_wait_for_completion(iommu);
469 spin_unlock_irqrestore(&iommu->lock, flags);
473 void amd_iommu_flush_all_domains(void)
477 for (i = 1; i < MAX_DOMAIN_ID; ++i) {
478 if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
480 iommu_flush_domain(i);
484 static void flush_devices_by_domain(struct protection_domain *domain)
486 struct amd_iommu *iommu;
489 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
490 if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
491 (amd_iommu_pd_table[i] != domain))
494 iommu = amd_iommu_rlookup_table[i];
498 iommu_queue_inv_dev_entry(iommu, i);
499 iommu_completion_wait(iommu);
503 void amd_iommu_flush_all_devices(void)
505 flush_devices_by_domain(NULL);
508 /****************************************************************************
510 * The functions below are used the create the page table mappings for
511 * unity mapped regions.
513 ****************************************************************************/
516 * Generic mapping functions. It maps a physical address into a DMA
517 * address space. It allocates the page table pages if necessary.
518 * In the future it can be extended to a generic mapping function
519 * supporting all features of AMD IOMMU page tables like level skipping
520 * and full 64 bit address spaces.
522 static int iommu_map_page(struct protection_domain *dom,
523 unsigned long bus_addr,
524 unsigned long phys_addr,
529 bus_addr = PAGE_ALIGN(bus_addr);
530 phys_addr = PAGE_ALIGN(phys_addr);
532 /* only support 512GB address spaces for now */
533 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
536 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
538 if (IOMMU_PTE_PRESENT(*pte))
541 __pte = phys_addr | IOMMU_PTE_P;
542 if (prot & IOMMU_PROT_IR)
543 __pte |= IOMMU_PTE_IR;
544 if (prot & IOMMU_PROT_IW)
545 __pte |= IOMMU_PTE_IW;
552 static void iommu_unmap_page(struct protection_domain *dom,
553 unsigned long bus_addr)
555 u64 *pte = fetch_pte(dom, bus_addr);
562 * This function checks if a specific unity mapping entry is needed for
563 * this specific IOMMU.
565 static int iommu_for_unity_map(struct amd_iommu *iommu,
566 struct unity_map_entry *entry)
570 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
571 bdf = amd_iommu_alias_table[i];
572 if (amd_iommu_rlookup_table[bdf] == iommu)
580 * Init the unity mappings for a specific IOMMU in the system
582 * Basically iterates over all unity mapping entries and applies them to
583 * the default domain DMA of that IOMMU if necessary.
585 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
587 struct unity_map_entry *entry;
590 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
591 if (!iommu_for_unity_map(iommu, entry))
593 ret = dma_ops_unity_map(iommu->default_dom, entry);
602 * This function actually applies the mapping to the page table of the
605 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
606 struct unity_map_entry *e)
611 for (addr = e->address_start; addr < e->address_end;
613 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
617 * if unity mapping is in aperture range mark the page
618 * as allocated in the aperture
620 if (addr < dma_dom->aperture_size)
621 __set_bit(addr >> PAGE_SHIFT,
622 dma_dom->aperture[0]->bitmap);
629 * Inits the unity mappings required for a specific device
631 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
634 struct unity_map_entry *e;
637 list_for_each_entry(e, &amd_iommu_unity_map, list) {
638 if (!(devid >= e->devid_start && devid <= e->devid_end))
640 ret = dma_ops_unity_map(dma_dom, e);
648 /****************************************************************************
650 * The next functions belong to the address allocator for the dma_ops
651 * interface functions. They work like the allocators in the other IOMMU
652 * drivers. Its basically a bitmap which marks the allocated pages in
653 * the aperture. Maybe it could be enhanced in the future to a more
654 * efficient allocator.
656 ****************************************************************************/
659 * The address allocator core functions.
661 * called with domain->lock held
665 * This function checks if there is a PTE for a given dma address. If
666 * there is one, it returns the pointer to it.
668 static u64 *fetch_pte(struct protection_domain *domain,
669 unsigned long address)
674 level = domain->mode - 1;
675 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
678 if (!IOMMU_PTE_PRESENT(*pte))
683 pte = IOMMU_PTE_PAGE(*pte);
684 pte = &pte[PM_LEVEL_INDEX(level, address)];
691 * This function is used to add a new aperture range to an existing
692 * aperture in case of dma_ops domain allocation or address allocation
695 static int alloc_new_range(struct amd_iommu *iommu,
696 struct dma_ops_domain *dma_dom,
697 bool populate, gfp_t gfp)
699 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
702 #ifdef CONFIG_IOMMU_STRESS
706 if (index >= APERTURE_MAX_RANGES)
709 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
710 if (!dma_dom->aperture[index])
713 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
714 if (!dma_dom->aperture[index]->bitmap)
717 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
720 unsigned long address = dma_dom->aperture_size;
721 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
724 for (i = 0; i < num_ptes; ++i) {
725 pte = alloc_pte(&dma_dom->domain, address,
730 dma_dom->aperture[index]->pte_pages[i] = pte_page;
732 address += APERTURE_RANGE_SIZE / 64;
736 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
738 /* Intialize the exclusion range if necessary */
739 if (iommu->exclusion_start &&
740 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
741 iommu->exclusion_start < dma_dom->aperture_size) {
742 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
743 int pages = iommu_num_pages(iommu->exclusion_start,
744 iommu->exclusion_length,
746 dma_ops_reserve_addresses(dma_dom, startpage, pages);
750 * Check for areas already mapped as present in the new aperture
751 * range and mark those pages as reserved in the allocator. Such
752 * mappings may already exist as a result of requested unity
753 * mappings for devices.
755 for (i = dma_dom->aperture[index]->offset;
756 i < dma_dom->aperture_size;
758 u64 *pte = fetch_pte(&dma_dom->domain, i);
759 if (!pte || !IOMMU_PTE_PRESENT(*pte))
762 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
768 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
770 kfree(dma_dom->aperture[index]);
771 dma_dom->aperture[index] = NULL;
776 static unsigned long dma_ops_area_alloc(struct device *dev,
777 struct dma_ops_domain *dom,
779 unsigned long align_mask,
783 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
784 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
785 int i = start >> APERTURE_RANGE_SHIFT;
786 unsigned long boundary_size;
787 unsigned long address = -1;
790 next_bit >>= PAGE_SHIFT;
792 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
793 PAGE_SIZE) >> PAGE_SHIFT;
795 for (;i < max_index; ++i) {
796 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
798 if (dom->aperture[i]->offset >= dma_mask)
801 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
802 dma_mask >> PAGE_SHIFT);
804 address = iommu_area_alloc(dom->aperture[i]->bitmap,
805 limit, next_bit, pages, 0,
806 boundary_size, align_mask);
808 address = dom->aperture[i]->offset +
809 (address << PAGE_SHIFT);
810 dom->next_address = address + (pages << PAGE_SHIFT);
820 static unsigned long dma_ops_alloc_addresses(struct device *dev,
821 struct dma_ops_domain *dom,
823 unsigned long align_mask,
826 unsigned long address;
828 #ifdef CONFIG_IOMMU_STRESS
829 dom->next_address = 0;
830 dom->need_flush = true;
833 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
834 dma_mask, dom->next_address);
837 dom->next_address = 0;
838 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
840 dom->need_flush = true;
843 if (unlikely(address == -1))
844 address = bad_dma_address;
846 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
852 * The address free function.
854 * called with domain->lock held
856 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
857 unsigned long address,
860 unsigned i = address >> APERTURE_RANGE_SHIFT;
861 struct aperture_range *range = dom->aperture[i];
863 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
865 #ifdef CONFIG_IOMMU_STRESS
870 if (address >= dom->next_address)
871 dom->need_flush = true;
873 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
875 iommu_area_free(range->bitmap, address, pages);
879 /****************************************************************************
881 * The next functions belong to the domain allocation. A domain is
882 * allocated for every IOMMU as the default domain. If device isolation
883 * is enabled, every device get its own domain. The most important thing
884 * about domains is the page table mapping the DMA address space they
887 ****************************************************************************/
889 static u16 domain_id_alloc(void)
894 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
895 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
897 if (id > 0 && id < MAX_DOMAIN_ID)
898 __set_bit(id, amd_iommu_pd_alloc_bitmap);
901 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
906 static void domain_id_free(int id)
910 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
911 if (id > 0 && id < MAX_DOMAIN_ID)
912 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
913 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
917 * Used to reserve address ranges in the aperture (e.g. for exclusion
920 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
921 unsigned long start_page,
924 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
926 if (start_page + pages > last_page)
927 pages = last_page - start_page;
929 for (i = start_page; i < start_page + pages; ++i) {
930 int index = i / APERTURE_RANGE_PAGES;
931 int page = i % APERTURE_RANGE_PAGES;
932 __set_bit(page, dom->aperture[index]->bitmap);
936 static void free_pagetable(struct protection_domain *domain)
941 p1 = domain->pt_root;
946 for (i = 0; i < 512; ++i) {
947 if (!IOMMU_PTE_PRESENT(p1[i]))
950 p2 = IOMMU_PTE_PAGE(p1[i]);
951 for (j = 0; j < 512; ++j) {
952 if (!IOMMU_PTE_PRESENT(p2[j]))
954 p3 = IOMMU_PTE_PAGE(p2[j]);
955 free_page((unsigned long)p3);
958 free_page((unsigned long)p2);
961 free_page((unsigned long)p1);
963 domain->pt_root = NULL;
967 * Free a domain, only used if something went wrong in the
968 * allocation path and we need to free an already allocated page table
970 static void dma_ops_domain_free(struct dma_ops_domain *dom)
977 free_pagetable(&dom->domain);
979 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
980 if (!dom->aperture[i])
982 free_page((unsigned long)dom->aperture[i]->bitmap);
983 kfree(dom->aperture[i]);
990 * Allocates a new protection domain usable for the dma_ops functions.
991 * It also intializes the page table and the address allocator data
992 * structures required for the dma_ops interface
994 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
996 struct dma_ops_domain *dma_dom;
998 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1002 spin_lock_init(&dma_dom->domain.lock);
1004 dma_dom->domain.id = domain_id_alloc();
1005 if (dma_dom->domain.id == 0)
1007 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1008 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1009 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1010 dma_dom->domain.priv = dma_dom;
1011 if (!dma_dom->domain.pt_root)
1014 dma_dom->need_flush = false;
1015 dma_dom->target_dev = 0xffff;
1017 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
1021 * mark the first page as allocated so we never return 0 as
1022 * a valid dma-address. So we can use 0 as error value
1024 dma_dom->aperture[0]->bitmap[0] = 1;
1025 dma_dom->next_address = 0;
1031 dma_ops_domain_free(dma_dom);
1037 * little helper function to check whether a given protection domain is a
1040 static bool dma_ops_domain(struct protection_domain *domain)
1042 return domain->flags & PD_DMA_OPS_MASK;
1046 * Find out the protection domain structure for a given PCI device. This
1047 * will give us the pointer to the page table root for example.
1049 static struct protection_domain *domain_for_device(u16 devid)
1051 struct protection_domain *dom;
1052 unsigned long flags;
1054 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1055 dom = amd_iommu_pd_table[devid];
1056 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1062 * If a device is not yet associated with a domain, this function does
1063 * assigns it visible for the hardware
1065 static void attach_device(struct amd_iommu *iommu,
1066 struct protection_domain *domain,
1069 unsigned long flags;
1070 u64 pte_root = virt_to_phys(domain->pt_root);
1072 domain->dev_cnt += 1;
1074 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1075 << DEV_ENTRY_MODE_SHIFT;
1076 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1078 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1079 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1080 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1081 amd_iommu_dev_table[devid].data[2] = domain->id;
1083 amd_iommu_pd_table[devid] = domain;
1084 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1087 * We might boot into a crash-kernel here. The crashed kernel
1088 * left the caches in the IOMMU dirty. So we have to flush
1089 * here to evict all dirty stuff.
1091 iommu_queue_inv_dev_entry(iommu, devid);
1092 iommu_flush_tlb_pde(iommu, domain->id);
1096 * Removes a device from a protection domain (unlocked)
1098 static void __detach_device(struct protection_domain *domain, u16 devid)
1102 spin_lock(&domain->lock);
1104 /* remove domain from the lookup table */
1105 amd_iommu_pd_table[devid] = NULL;
1107 /* remove entry from the device table seen by the hardware */
1108 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1109 amd_iommu_dev_table[devid].data[1] = 0;
1110 amd_iommu_dev_table[devid].data[2] = 0;
1112 /* decrease reference counter */
1113 domain->dev_cnt -= 1;
1116 spin_unlock(&domain->lock);
1120 * Removes a device from a protection domain (with devtable_lock held)
1122 static void detach_device(struct protection_domain *domain, u16 devid)
1124 unsigned long flags;
1126 /* lock device table */
1127 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1128 __detach_device(domain, devid);
1129 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1132 static int device_change_notifier(struct notifier_block *nb,
1133 unsigned long action, void *data)
1135 struct device *dev = data;
1136 struct pci_dev *pdev = to_pci_dev(dev);
1137 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1138 struct protection_domain *domain;
1139 struct dma_ops_domain *dma_domain;
1140 struct amd_iommu *iommu;
1141 unsigned long flags;
1143 if (devid > amd_iommu_last_bdf)
1146 devid = amd_iommu_alias_table[devid];
1148 iommu = amd_iommu_rlookup_table[devid];
1152 domain = domain_for_device(devid);
1154 if (domain && !dma_ops_domain(domain))
1155 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1156 "to a non-dma-ops domain\n", dev_name(dev));
1159 case BUS_NOTIFY_UNBOUND_DRIVER:
1162 detach_device(domain, devid);
1164 case BUS_NOTIFY_ADD_DEVICE:
1165 /* allocate a protection domain if a device is added */
1166 dma_domain = find_protection_domain(devid);
1169 dma_domain = dma_ops_domain_alloc(iommu);
1172 dma_domain->target_dev = devid;
1174 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1175 list_add_tail(&dma_domain->list, &iommu_pd_list);
1176 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1183 iommu_queue_inv_dev_entry(iommu, devid);
1184 iommu_completion_wait(iommu);
1190 static struct notifier_block device_nb = {
1191 .notifier_call = device_change_notifier,
1194 /*****************************************************************************
1196 * The next functions belong to the dma_ops mapping/unmapping code.
1198 *****************************************************************************/
1201 * This function checks if the driver got a valid device from the caller to
1202 * avoid dereferencing invalid pointers.
1204 static bool check_device(struct device *dev)
1206 if (!dev || !dev->dma_mask)
1213 * In this function the list of preallocated protection domains is traversed to
1214 * find the domain for a specific device
1216 static struct dma_ops_domain *find_protection_domain(u16 devid)
1218 struct dma_ops_domain *entry, *ret = NULL;
1219 unsigned long flags;
1221 if (list_empty(&iommu_pd_list))
1224 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1226 list_for_each_entry(entry, &iommu_pd_list, list) {
1227 if (entry->target_dev == devid) {
1233 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1239 * In the dma_ops path we only have the struct device. This function
1240 * finds the corresponding IOMMU, the protection domain and the
1241 * requestor id for a given device.
1242 * If the device is not yet associated with a domain this is also done
1245 static int get_device_resources(struct device *dev,
1246 struct amd_iommu **iommu,
1247 struct protection_domain **domain,
1250 struct dma_ops_domain *dma_dom;
1251 struct pci_dev *pcidev;
1258 if (dev->bus != &pci_bus_type)
1261 pcidev = to_pci_dev(dev);
1262 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1264 /* device not translated by any IOMMU in the system? */
1265 if (_bdf > amd_iommu_last_bdf)
1268 *bdf = amd_iommu_alias_table[_bdf];
1270 *iommu = amd_iommu_rlookup_table[*bdf];
1273 *domain = domain_for_device(*bdf);
1274 if (*domain == NULL) {
1275 dma_dom = find_protection_domain(*bdf);
1277 dma_dom = (*iommu)->default_dom;
1278 *domain = &dma_dom->domain;
1279 attach_device(*iommu, *domain, *bdf);
1280 DUMP_printk("Using protection domain %d for device %s\n",
1281 (*domain)->id, dev_name(dev));
1284 if (domain_for_device(_bdf) == NULL)
1285 attach_device(*iommu, *domain, _bdf);
1291 * If the pte_page is not yet allocated this function is called
1293 static u64* alloc_pte(struct protection_domain *dom,
1294 unsigned long address, u64 **pte_page, gfp_t gfp)
1298 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1300 if (!IOMMU_PTE_PRESENT(*pte)) {
1301 page = (u64 *)get_zeroed_page(gfp);
1304 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1307 pte = IOMMU_PTE_PAGE(*pte);
1308 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1310 if (!IOMMU_PTE_PRESENT(*pte)) {
1311 page = (u64 *)get_zeroed_page(gfp);
1314 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1317 pte = IOMMU_PTE_PAGE(*pte);
1322 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1328 * This function fetches the PTE for a given address in the aperture
1330 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1331 unsigned long address)
1333 struct aperture_range *aperture;
1334 u64 *pte, *pte_page;
1336 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1340 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1342 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1343 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1345 pte += IOMMU_PTE_L0_INDEX(address);
1351 * This is the generic map function. It maps one 4kb page at paddr to
1352 * the given address in the DMA address space for the domain.
1354 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1355 struct dma_ops_domain *dom,
1356 unsigned long address,
1362 WARN_ON(address > dom->aperture_size);
1366 pte = dma_ops_get_pte(dom, address);
1368 return bad_dma_address;
1370 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1372 if (direction == DMA_TO_DEVICE)
1373 __pte |= IOMMU_PTE_IR;
1374 else if (direction == DMA_FROM_DEVICE)
1375 __pte |= IOMMU_PTE_IW;
1376 else if (direction == DMA_BIDIRECTIONAL)
1377 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1383 return (dma_addr_t)address;
1387 * The generic unmapping function for on page in the DMA address space.
1389 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1390 struct dma_ops_domain *dom,
1391 unsigned long address)
1393 struct aperture_range *aperture;
1396 if (address >= dom->aperture_size)
1399 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1403 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1407 pte += IOMMU_PTE_L0_INDEX(address);
1415 * This function contains common code for mapping of a physically
1416 * contiguous memory region into DMA address space. It is used by all
1417 * mapping functions provided with this IOMMU driver.
1418 * Must be called with the domain lock held.
1420 static dma_addr_t __map_single(struct device *dev,
1421 struct amd_iommu *iommu,
1422 struct dma_ops_domain *dma_dom,
1429 dma_addr_t offset = paddr & ~PAGE_MASK;
1430 dma_addr_t address, start, ret;
1432 unsigned long align_mask = 0;
1435 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1438 INC_STATS_COUNTER(total_map_requests);
1441 INC_STATS_COUNTER(cross_page);
1444 align_mask = (1UL << get_order(size)) - 1;
1447 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1449 if (unlikely(address == bad_dma_address)) {
1451 * setting next_address here will let the address
1452 * allocator only scan the new allocated range in the
1453 * first run. This is a small optimization.
1455 dma_dom->next_address = dma_dom->aperture_size;
1457 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1461 * aperture was sucessfully enlarged by 128 MB, try
1468 for (i = 0; i < pages; ++i) {
1469 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1470 if (ret == bad_dma_address)
1478 ADD_STATS_COUNTER(alloced_io_mem, size);
1480 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1481 iommu_flush_tlb(iommu, dma_dom->domain.id);
1482 dma_dom->need_flush = false;
1483 } else if (unlikely(iommu_has_npcache(iommu)))
1484 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1491 for (--i; i >= 0; --i) {
1493 dma_ops_domain_unmap(iommu, dma_dom, start);
1496 dma_ops_free_addresses(dma_dom, address, pages);
1498 return bad_dma_address;
1502 * Does the reverse of the __map_single function. Must be called with
1503 * the domain lock held too
1505 static void __unmap_single(struct amd_iommu *iommu,
1506 struct dma_ops_domain *dma_dom,
1507 dma_addr_t dma_addr,
1511 dma_addr_t i, start;
1514 if ((dma_addr == bad_dma_address) ||
1515 (dma_addr + size > dma_dom->aperture_size))
1518 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1519 dma_addr &= PAGE_MASK;
1522 for (i = 0; i < pages; ++i) {
1523 dma_ops_domain_unmap(iommu, dma_dom, start);
1527 SUB_STATS_COUNTER(alloced_io_mem, size);
1529 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1531 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1532 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1533 dma_dom->need_flush = false;
1538 * The exported map_single function for dma_ops.
1540 static dma_addr_t map_page(struct device *dev, struct page *page,
1541 unsigned long offset, size_t size,
1542 enum dma_data_direction dir,
1543 struct dma_attrs *attrs)
1545 unsigned long flags;
1546 struct amd_iommu *iommu;
1547 struct protection_domain *domain;
1551 phys_addr_t paddr = page_to_phys(page) + offset;
1553 INC_STATS_COUNTER(cnt_map_single);
1555 if (!check_device(dev))
1556 return bad_dma_address;
1558 dma_mask = *dev->dma_mask;
1560 get_device_resources(dev, &iommu, &domain, &devid);
1562 if (iommu == NULL || domain == NULL)
1563 /* device not handled by any AMD IOMMU */
1564 return (dma_addr_t)paddr;
1566 if (!dma_ops_domain(domain))
1567 return bad_dma_address;
1569 spin_lock_irqsave(&domain->lock, flags);
1570 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1572 if (addr == bad_dma_address)
1575 iommu_completion_wait(iommu);
1578 spin_unlock_irqrestore(&domain->lock, flags);
1584 * The exported unmap_single function for dma_ops.
1586 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1587 enum dma_data_direction dir, struct dma_attrs *attrs)
1589 unsigned long flags;
1590 struct amd_iommu *iommu;
1591 struct protection_domain *domain;
1594 INC_STATS_COUNTER(cnt_unmap_single);
1596 if (!check_device(dev) ||
1597 !get_device_resources(dev, &iommu, &domain, &devid))
1598 /* device not handled by any AMD IOMMU */
1601 if (!dma_ops_domain(domain))
1604 spin_lock_irqsave(&domain->lock, flags);
1606 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1608 iommu_completion_wait(iommu);
1610 spin_unlock_irqrestore(&domain->lock, flags);
1614 * This is a special map_sg function which is used if we should map a
1615 * device which is not handled by an AMD IOMMU in the system.
1617 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1618 int nelems, int dir)
1620 struct scatterlist *s;
1623 for_each_sg(sglist, s, nelems, i) {
1624 s->dma_address = (dma_addr_t)sg_phys(s);
1625 s->dma_length = s->length;
1632 * The exported map_sg function for dma_ops (handles scatter-gather
1635 static int map_sg(struct device *dev, struct scatterlist *sglist,
1636 int nelems, enum dma_data_direction dir,
1637 struct dma_attrs *attrs)
1639 unsigned long flags;
1640 struct amd_iommu *iommu;
1641 struct protection_domain *domain;
1644 struct scatterlist *s;
1646 int mapped_elems = 0;
1649 INC_STATS_COUNTER(cnt_map_sg);
1651 if (!check_device(dev))
1654 dma_mask = *dev->dma_mask;
1656 get_device_resources(dev, &iommu, &domain, &devid);
1658 if (!iommu || !domain)
1659 return map_sg_no_iommu(dev, sglist, nelems, dir);
1661 if (!dma_ops_domain(domain))
1664 spin_lock_irqsave(&domain->lock, flags);
1666 for_each_sg(sglist, s, nelems, i) {
1669 s->dma_address = __map_single(dev, iommu, domain->priv,
1670 paddr, s->length, dir, false,
1673 if (s->dma_address) {
1674 s->dma_length = s->length;
1680 iommu_completion_wait(iommu);
1683 spin_unlock_irqrestore(&domain->lock, flags);
1685 return mapped_elems;
1687 for_each_sg(sglist, s, mapped_elems, i) {
1689 __unmap_single(iommu, domain->priv, s->dma_address,
1690 s->dma_length, dir);
1691 s->dma_address = s->dma_length = 0;
1700 * The exported map_sg function for dma_ops (handles scatter-gather
1703 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1704 int nelems, enum dma_data_direction dir,
1705 struct dma_attrs *attrs)
1707 unsigned long flags;
1708 struct amd_iommu *iommu;
1709 struct protection_domain *domain;
1710 struct scatterlist *s;
1714 INC_STATS_COUNTER(cnt_unmap_sg);
1716 if (!check_device(dev) ||
1717 !get_device_resources(dev, &iommu, &domain, &devid))
1720 if (!dma_ops_domain(domain))
1723 spin_lock_irqsave(&domain->lock, flags);
1725 for_each_sg(sglist, s, nelems, i) {
1726 __unmap_single(iommu, domain->priv, s->dma_address,
1727 s->dma_length, dir);
1728 s->dma_address = s->dma_length = 0;
1731 iommu_completion_wait(iommu);
1733 spin_unlock_irqrestore(&domain->lock, flags);
1737 * The exported alloc_coherent function for dma_ops.
1739 static void *alloc_coherent(struct device *dev, size_t size,
1740 dma_addr_t *dma_addr, gfp_t flag)
1742 unsigned long flags;
1744 struct amd_iommu *iommu;
1745 struct protection_domain *domain;
1748 u64 dma_mask = dev->coherent_dma_mask;
1750 INC_STATS_COUNTER(cnt_alloc_coherent);
1752 if (!check_device(dev))
1755 if (!get_device_resources(dev, &iommu, &domain, &devid))
1756 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1759 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1763 paddr = virt_to_phys(virt_addr);
1765 if (!iommu || !domain) {
1766 *dma_addr = (dma_addr_t)paddr;
1770 if (!dma_ops_domain(domain))
1774 dma_mask = *dev->dma_mask;
1776 spin_lock_irqsave(&domain->lock, flags);
1778 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1779 size, DMA_BIDIRECTIONAL, true, dma_mask);
1781 if (*dma_addr == bad_dma_address) {
1782 spin_unlock_irqrestore(&domain->lock, flags);
1786 iommu_completion_wait(iommu);
1788 spin_unlock_irqrestore(&domain->lock, flags);
1794 free_pages((unsigned long)virt_addr, get_order(size));
1800 * The exported free_coherent function for dma_ops.
1802 static void free_coherent(struct device *dev, size_t size,
1803 void *virt_addr, dma_addr_t dma_addr)
1805 unsigned long flags;
1806 struct amd_iommu *iommu;
1807 struct protection_domain *domain;
1810 INC_STATS_COUNTER(cnt_free_coherent);
1812 if (!check_device(dev))
1815 get_device_resources(dev, &iommu, &domain, &devid);
1817 if (!iommu || !domain)
1820 if (!dma_ops_domain(domain))
1823 spin_lock_irqsave(&domain->lock, flags);
1825 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1827 iommu_completion_wait(iommu);
1829 spin_unlock_irqrestore(&domain->lock, flags);
1832 free_pages((unsigned long)virt_addr, get_order(size));
1836 * This function is called by the DMA layer to find out if we can handle a
1837 * particular device. It is part of the dma_ops.
1839 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1842 struct pci_dev *pcidev;
1844 /* No device or no PCI device */
1845 if (!dev || dev->bus != &pci_bus_type)
1848 pcidev = to_pci_dev(dev);
1850 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1852 /* Out of our scope? */
1853 if (bdf > amd_iommu_last_bdf)
1860 * The function for pre-allocating protection domains.
1862 * If the driver core informs the DMA layer if a driver grabs a device
1863 * we don't need to preallocate the protection domains anymore.
1864 * For now we have to.
1866 static void prealloc_protection_domains(void)
1868 struct pci_dev *dev = NULL;
1869 struct dma_ops_domain *dma_dom;
1870 struct amd_iommu *iommu;
1873 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1874 devid = calc_devid(dev->bus->number, dev->devfn);
1875 if (devid > amd_iommu_last_bdf)
1877 devid = amd_iommu_alias_table[devid];
1878 if (domain_for_device(devid))
1880 iommu = amd_iommu_rlookup_table[devid];
1883 dma_dom = dma_ops_domain_alloc(iommu);
1886 init_unity_mappings_for_device(dma_dom, devid);
1887 dma_dom->target_dev = devid;
1889 list_add_tail(&dma_dom->list, &iommu_pd_list);
1893 static struct dma_map_ops amd_iommu_dma_ops = {
1894 .alloc_coherent = alloc_coherent,
1895 .free_coherent = free_coherent,
1896 .map_page = map_page,
1897 .unmap_page = unmap_page,
1899 .unmap_sg = unmap_sg,
1900 .dma_supported = amd_iommu_dma_supported,
1904 * The function which clues the AMD IOMMU driver into dma_ops.
1906 int __init amd_iommu_init_dma_ops(void)
1908 struct amd_iommu *iommu;
1912 * first allocate a default protection domain for every IOMMU we
1913 * found in the system. Devices not assigned to any other
1914 * protection domain will be assigned to the default one.
1916 for_each_iommu(iommu) {
1917 iommu->default_dom = dma_ops_domain_alloc(iommu);
1918 if (iommu->default_dom == NULL)
1920 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1921 ret = iommu_init_unity_mappings(iommu);
1927 * If device isolation is enabled, pre-allocate the protection
1928 * domains for each device.
1930 if (amd_iommu_isolate)
1931 prealloc_protection_domains();
1935 bad_dma_address = 0;
1936 #ifdef CONFIG_GART_IOMMU
1937 gart_iommu_aperture_disabled = 1;
1938 gart_iommu_aperture = 0;
1941 /* Make the driver finally visible to the drivers */
1942 dma_ops = &amd_iommu_dma_ops;
1944 register_iommu(&amd_iommu_ops);
1946 bus_register_notifier(&pci_bus_type, &device_nb);
1948 amd_iommu_stats_init();
1954 for_each_iommu(iommu) {
1955 if (iommu->default_dom)
1956 dma_ops_domain_free(iommu->default_dom);
1962 /*****************************************************************************
1964 * The following functions belong to the exported interface of AMD IOMMU
1966 * This interface allows access to lower level functions of the IOMMU
1967 * like protection domain handling and assignement of devices to domains
1968 * which is not possible with the dma_ops interface.
1970 *****************************************************************************/
1972 static void cleanup_domain(struct protection_domain *domain)
1974 unsigned long flags;
1977 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1979 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1980 if (amd_iommu_pd_table[devid] == domain)
1981 __detach_device(domain, devid);
1983 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1986 static int amd_iommu_domain_init(struct iommu_domain *dom)
1988 struct protection_domain *domain;
1990 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1994 spin_lock_init(&domain->lock);
1995 domain->mode = PAGE_MODE_3_LEVEL;
1996 domain->id = domain_id_alloc();
1999 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2000 if (!domain->pt_root)
2013 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2015 struct protection_domain *domain = dom->priv;
2020 if (domain->dev_cnt > 0)
2021 cleanup_domain(domain);
2023 BUG_ON(domain->dev_cnt != 0);
2025 free_pagetable(domain);
2027 domain_id_free(domain->id);
2034 static void amd_iommu_detach_device(struct iommu_domain *dom,
2037 struct protection_domain *domain = dom->priv;
2038 struct amd_iommu *iommu;
2039 struct pci_dev *pdev;
2042 if (dev->bus != &pci_bus_type)
2045 pdev = to_pci_dev(dev);
2047 devid = calc_devid(pdev->bus->number, pdev->devfn);
2050 detach_device(domain, devid);
2052 iommu = amd_iommu_rlookup_table[devid];
2056 iommu_queue_inv_dev_entry(iommu, devid);
2057 iommu_completion_wait(iommu);
2060 static int amd_iommu_attach_device(struct iommu_domain *dom,
2063 struct protection_domain *domain = dom->priv;
2064 struct protection_domain *old_domain;
2065 struct amd_iommu *iommu;
2066 struct pci_dev *pdev;
2069 if (dev->bus != &pci_bus_type)
2072 pdev = to_pci_dev(dev);
2074 devid = calc_devid(pdev->bus->number, pdev->devfn);
2076 if (devid >= amd_iommu_last_bdf ||
2077 devid != amd_iommu_alias_table[devid])
2080 iommu = amd_iommu_rlookup_table[devid];
2084 old_domain = domain_for_device(devid);
2086 detach_device(old_domain, devid);
2088 attach_device(iommu, domain, devid);
2090 iommu_completion_wait(iommu);
2095 static int amd_iommu_map_range(struct iommu_domain *dom,
2096 unsigned long iova, phys_addr_t paddr,
2097 size_t size, int iommu_prot)
2099 struct protection_domain *domain = dom->priv;
2100 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2104 if (iommu_prot & IOMMU_READ)
2105 prot |= IOMMU_PROT_IR;
2106 if (iommu_prot & IOMMU_WRITE)
2107 prot |= IOMMU_PROT_IW;
2112 for (i = 0; i < npages; ++i) {
2113 ret = iommu_map_page(domain, iova, paddr, prot);
2124 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2125 unsigned long iova, size_t size)
2128 struct protection_domain *domain = dom->priv;
2129 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2133 for (i = 0; i < npages; ++i) {
2134 iommu_unmap_page(domain, iova);
2138 iommu_flush_domain(domain->id);
2141 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2144 struct protection_domain *domain = dom->priv;
2145 unsigned long offset = iova & ~PAGE_MASK;
2149 pte = fetch_pte(domain, iova);
2151 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2154 paddr = *pte & IOMMU_PAGE_MASK;
2160 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2166 static struct iommu_ops amd_iommu_ops = {
2167 .domain_init = amd_iommu_domain_init,
2168 .domain_destroy = amd_iommu_domain_destroy,
2169 .attach_dev = amd_iommu_attach_device,
2170 .detach_dev = amd_iommu_detach_device,
2171 .map = amd_iommu_map_range,
2172 .unmap = amd_iommu_unmap_range,
2173 .iova_to_phys = amd_iommu_iova_to_phys,
2174 .domain_has_cap = amd_iommu_domain_has_cap,