[SPARC64]: Make cpu_present_map available earlier.
[linux-2.6.git] / arch / sparc64 / kernel / smp.c
1 /* smp.c: Sparc64 SMP support.
2  *
3  * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
4  */
5
6 #include <linux/module.h>
7 #include <linux/kernel.h>
8 #include <linux/sched.h>
9 #include <linux/mm.h>
10 #include <linux/pagemap.h>
11 #include <linux/threads.h>
12 #include <linux/smp.h>
13 #include <linux/smp_lock.h>
14 #include <linux/interrupt.h>
15 #include <linux/kernel_stat.h>
16 #include <linux/delay.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/fs.h>
20 #include <linux/seq_file.h>
21 #include <linux/cache.h>
22 #include <linux/jiffies.h>
23 #include <linux/profile.h>
24 #include <linux/bootmem.h>
25
26 #include <asm/head.h>
27 #include <asm/ptrace.h>
28 #include <asm/atomic.h>
29 #include <asm/tlbflush.h>
30 #include <asm/mmu_context.h>
31 #include <asm/cpudata.h>
32
33 #include <asm/irq.h>
34 #include <asm/page.h>
35 #include <asm/pgtable.h>
36 #include <asm/oplib.h>
37 #include <asm/uaccess.h>
38 #include <asm/timer.h>
39 #include <asm/starfire.h>
40 #include <asm/tlb.h>
41
42 extern void calibrate_delay(void);
43
44 /* Please don't make this stuff initdata!!!  --DaveM */
45 static unsigned char boot_cpu_id;
46
47 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
48 cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE;
49 static cpumask_t smp_commenced_mask;
50 static cpumask_t cpu_callout_map;
51
52 void smp_info(struct seq_file *m)
53 {
54         int i;
55         
56         seq_printf(m, "State:\n");
57         for (i = 0; i < NR_CPUS; i++) {
58                 if (cpu_online(i))
59                         seq_printf(m,
60                                    "CPU%d:\t\tonline\n", i);
61         }
62 }
63
64 void smp_bogo(struct seq_file *m)
65 {
66         int i;
67         
68         for (i = 0; i < NR_CPUS; i++)
69                 if (cpu_online(i))
70                         seq_printf(m,
71                                    "Cpu%dBogo\t: %lu.%02lu\n"
72                                    "Cpu%dClkTck\t: %016lx\n",
73                                    i, cpu_data(i).udelay_val / (500000/HZ),
74                                    (cpu_data(i).udelay_val / (5000/HZ)) % 100,
75                                    i, cpu_data(i).clock_tick);
76 }
77
78 void __init smp_store_cpu_info(int id)
79 {
80         int cpu_node;
81
82         /* multiplier and counter set by
83            smp_setup_percpu_timer()  */
84         cpu_data(id).udelay_val                 = loops_per_jiffy;
85
86         cpu_find_by_mid(id, &cpu_node);
87         cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
88                                                      "clock-frequency", 0);
89
90         cpu_data(id).pgcache_size               = 0;
91         cpu_data(id).pte_cache[0]               = NULL;
92         cpu_data(id).pte_cache[1]               = NULL;
93         cpu_data(id).pgd_cache                  = NULL;
94         cpu_data(id).idle_volume                = 1;
95
96         cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size",
97                                                       16 * 1024);
98         cpu_data(id).dcache_line_size =
99                 prom_getintdefault(cpu_node, "dcache-line-size", 32);
100         cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size",
101                                                       16 * 1024);
102         cpu_data(id).icache_line_size =
103                 prom_getintdefault(cpu_node, "icache-line-size", 32);
104         cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size",
105                                                       4 * 1024 * 1024);
106         cpu_data(id).ecache_line_size =
107                 prom_getintdefault(cpu_node, "ecache-line-size", 64);
108         printk("CPU[%d]: Caches "
109                "D[sz(%d):line_sz(%d)] "
110                "I[sz(%d):line_sz(%d)] "
111                "E[sz(%d):line_sz(%d)]\n",
112                id,
113                cpu_data(id).dcache_size, cpu_data(id).dcache_line_size,
114                cpu_data(id).icache_size, cpu_data(id).icache_line_size,
115                cpu_data(id).ecache_size, cpu_data(id).ecache_line_size);
116 }
117
118 static void smp_setup_percpu_timer(void);
119
120 static volatile unsigned long callin_flag = 0;
121
122 extern void inherit_locked_prom_mappings(int save_p);
123
124 static inline void cpu_setup_percpu_base(unsigned long cpu_id)
125 {
126         __asm__ __volatile__("mov       %0, %%g5\n\t"
127                              "stxa      %0, [%1] %2\n\t"
128                              "membar    #Sync"
129                              : /* no outputs */
130                              : "r" (__per_cpu_offset(cpu_id)),
131                                "r" (TSB_REG), "i" (ASI_IMMU));
132 }
133
134 void __init smp_callin(void)
135 {
136         int cpuid = hard_smp_processor_id();
137
138         inherit_locked_prom_mappings(0);
139
140         __flush_tlb_all();
141
142         cpu_setup_percpu_base(cpuid);
143
144         smp_setup_percpu_timer();
145
146         if (cheetah_pcache_forced_on)
147                 cheetah_enable_pcache();
148
149         local_irq_enable();
150
151         calibrate_delay();
152         smp_store_cpu_info(cpuid);
153         callin_flag = 1;
154         __asm__ __volatile__("membar #Sync\n\t"
155                              "flush  %%g6" : : : "memory");
156
157         /* Clear this or we will die instantly when we
158          * schedule back to this idler...
159          */
160         current_thread_info()->new_child = 0;
161
162         /* Attach to the address space of init_task. */
163         atomic_inc(&init_mm.mm_count);
164         current->active_mm = &init_mm;
165
166         while (!cpu_isset(cpuid, smp_commenced_mask))
167                 rmb();
168
169         cpu_set(cpuid, cpu_online_map);
170
171         /* idle thread is expected to have preempt disabled */
172         preempt_disable();
173 }
174
175 void cpu_panic(void)
176 {
177         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
178         panic("SMP bolixed\n");
179 }
180
181 static unsigned long current_tick_offset __read_mostly;
182
183 /* This tick register synchronization scheme is taken entirely from
184  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
185  *
186  * The only change I've made is to rework it so that the master
187  * initiates the synchonization instead of the slave. -DaveM
188  */
189
190 #define MASTER  0
191 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
192
193 #define NUM_ROUNDS      64      /* magic value */
194 #define NUM_ITERS       5       /* likewise */
195
196 static DEFINE_SPINLOCK(itc_sync_lock);
197 static unsigned long go[SLAVE + 1];
198
199 #define DEBUG_TICK_SYNC 0
200
201 static inline long get_delta (long *rt, long *master)
202 {
203         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
204         unsigned long tcenter, t0, t1, tm;
205         unsigned long i;
206
207         for (i = 0; i < NUM_ITERS; i++) {
208                 t0 = tick_ops->get_tick();
209                 go[MASTER] = 1;
210                 membar_storeload();
211                 while (!(tm = go[SLAVE]))
212                         rmb();
213                 go[SLAVE] = 0;
214                 wmb();
215                 t1 = tick_ops->get_tick();
216
217                 if (t1 - t0 < best_t1 - best_t0)
218                         best_t0 = t0, best_t1 = t1, best_tm = tm;
219         }
220
221         *rt = best_t1 - best_t0;
222         *master = best_tm - best_t0;
223
224         /* average best_t0 and best_t1 without overflow: */
225         tcenter = (best_t0/2 + best_t1/2);
226         if (best_t0 % 2 + best_t1 % 2 == 2)
227                 tcenter++;
228         return tcenter - best_tm;
229 }
230
231 void smp_synchronize_tick_client(void)
232 {
233         long i, delta, adj, adjust_latency = 0, done = 0;
234         unsigned long flags, rt, master_time_stamp, bound;
235 #if DEBUG_TICK_SYNC
236         struct {
237                 long rt;        /* roundtrip time */
238                 long master;    /* master's timestamp */
239                 long diff;      /* difference between midpoint and master's timestamp */
240                 long lat;       /* estimate of itc adjustment latency */
241         } t[NUM_ROUNDS];
242 #endif
243
244         go[MASTER] = 1;
245
246         while (go[MASTER])
247                 rmb();
248
249         local_irq_save(flags);
250         {
251                 for (i = 0; i < NUM_ROUNDS; i++) {
252                         delta = get_delta(&rt, &master_time_stamp);
253                         if (delta == 0) {
254                                 done = 1;       /* let's lock on to this... */
255                                 bound = rt;
256                         }
257
258                         if (!done) {
259                                 if (i > 0) {
260                                         adjust_latency += -delta;
261                                         adj = -delta + adjust_latency/4;
262                                 } else
263                                         adj = -delta;
264
265                                 tick_ops->add_tick(adj, current_tick_offset);
266                         }
267 #if DEBUG_TICK_SYNC
268                         t[i].rt = rt;
269                         t[i].master = master_time_stamp;
270                         t[i].diff = delta;
271                         t[i].lat = adjust_latency/4;
272 #endif
273                 }
274         }
275         local_irq_restore(flags);
276
277 #if DEBUG_TICK_SYNC
278         for (i = 0; i < NUM_ROUNDS; i++)
279                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
280                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
281 #endif
282
283         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
284                "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
285 }
286
287 static void smp_start_sync_tick_client(int cpu);
288
289 static void smp_synchronize_one_tick(int cpu)
290 {
291         unsigned long flags, i;
292
293         go[MASTER] = 0;
294
295         smp_start_sync_tick_client(cpu);
296
297         /* wait for client to be ready */
298         while (!go[MASTER])
299                 rmb();
300
301         /* now let the client proceed into his loop */
302         go[MASTER] = 0;
303         membar_storeload();
304
305         spin_lock_irqsave(&itc_sync_lock, flags);
306         {
307                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
308                         while (!go[MASTER])
309                                 rmb();
310                         go[MASTER] = 0;
311                         wmb();
312                         go[SLAVE] = tick_ops->get_tick();
313                         membar_storeload();
314                 }
315         }
316         spin_unlock_irqrestore(&itc_sync_lock, flags);
317 }
318
319 extern unsigned long sparc64_cpu_startup;
320
321 /* The OBP cpu startup callback truncates the 3rd arg cookie to
322  * 32-bits (I think) so to be safe we have it read the pointer
323  * contained here so we work on >4GB machines. -DaveM
324  */
325 static struct thread_info *cpu_new_thread = NULL;
326
327 static int __devinit smp_boot_one_cpu(unsigned int cpu)
328 {
329         unsigned long entry =
330                 (unsigned long)(&sparc64_cpu_startup);
331         unsigned long cookie =
332                 (unsigned long)(&cpu_new_thread);
333         struct task_struct *p;
334         int timeout, ret, cpu_node;
335
336         p = fork_idle(cpu);
337         callin_flag = 0;
338         cpu_new_thread = task_thread_info(p);
339         cpu_set(cpu, cpu_callout_map);
340
341         cpu_find_by_mid(cpu, &cpu_node);
342         prom_startcpu(cpu_node, entry, cookie);
343
344         for (timeout = 0; timeout < 5000000; timeout++) {
345                 if (callin_flag)
346                         break;
347                 udelay(100);
348         }
349         if (callin_flag) {
350                 ret = 0;
351         } else {
352                 printk("Processor %d is stuck.\n", cpu);
353                 cpu_clear(cpu, cpu_callout_map);
354                 ret = -ENODEV;
355         }
356         cpu_new_thread = NULL;
357
358         return ret;
359 }
360
361 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
362 {
363         u64 result, target;
364         int stuck, tmp;
365
366         if (this_is_starfire) {
367                 /* map to real upaid */
368                 cpu = (((cpu & 0x3c) << 1) |
369                         ((cpu & 0x40) >> 4) |
370                         (cpu & 0x3));
371         }
372
373         target = (cpu << 14) | 0x70;
374 again:
375         /* Ok, this is the real Spitfire Errata #54.
376          * One must read back from a UDB internal register
377          * after writes to the UDB interrupt dispatch, but
378          * before the membar Sync for that write.
379          * So we use the high UDB control register (ASI 0x7f,
380          * ADDR 0x20) for the dummy read. -DaveM
381          */
382         tmp = 0x40;
383         __asm__ __volatile__(
384         "wrpr   %1, %2, %%pstate\n\t"
385         "stxa   %4, [%0] %3\n\t"
386         "stxa   %5, [%0+%8] %3\n\t"
387         "add    %0, %8, %0\n\t"
388         "stxa   %6, [%0+%8] %3\n\t"
389         "membar #Sync\n\t"
390         "stxa   %%g0, [%7] %3\n\t"
391         "membar #Sync\n\t"
392         "mov    0x20, %%g1\n\t"
393         "ldxa   [%%g1] 0x7f, %%g0\n\t"
394         "membar #Sync"
395         : "=r" (tmp)
396         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
397           "r" (data0), "r" (data1), "r" (data2), "r" (target),
398           "r" (0x10), "0" (tmp)
399         : "g1");
400
401         /* NOTE: PSTATE_IE is still clear. */
402         stuck = 100000;
403         do {
404                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
405                         : "=r" (result)
406                         : "i" (ASI_INTR_DISPATCH_STAT));
407                 if (result == 0) {
408                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
409                                              : : "r" (pstate));
410                         return;
411                 }
412                 stuck -= 1;
413                 if (stuck == 0)
414                         break;
415         } while (result & 0x1);
416         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
417                              : : "r" (pstate));
418         if (stuck == 0) {
419                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
420                        smp_processor_id(), result);
421         } else {
422                 udelay(2);
423                 goto again;
424         }
425 }
426
427 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
428 {
429         u64 pstate;
430         int i;
431
432         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
433         for_each_cpu_mask(i, mask)
434                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
435 }
436
437 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
438  * packet, but we have no use for that.  However we do take advantage of
439  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
440  */
441 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
442 {
443         u64 pstate, ver;
444         int nack_busy_id, is_jalapeno;
445
446         if (cpus_empty(mask))
447                 return;
448
449         /* Unfortunately, someone at Sun had the brilliant idea to make the
450          * busy/nack fields hard-coded by ITID number for this Ultra-III
451          * derivative processor.
452          */
453         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
454         is_jalapeno = ((ver >> 32) == 0x003e0016);
455
456         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
457
458 retry:
459         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
460                              : : "r" (pstate), "i" (PSTATE_IE));
461
462         /* Setup the dispatch data registers. */
463         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
464                              "stxa      %1, [%4] %6\n\t"
465                              "stxa      %2, [%5] %6\n\t"
466                              "membar    #Sync\n\t"
467                              : /* no outputs */
468                              : "r" (data0), "r" (data1), "r" (data2),
469                                "r" (0x40), "r" (0x50), "r" (0x60),
470                                "i" (ASI_INTR_W));
471
472         nack_busy_id = 0;
473         {
474                 int i;
475
476                 for_each_cpu_mask(i, mask) {
477                         u64 target = (i << 14) | 0x70;
478
479                         if (!is_jalapeno)
480                                 target |= (nack_busy_id << 24);
481                         __asm__ __volatile__(
482                                 "stxa   %%g0, [%0] %1\n\t"
483                                 "membar #Sync\n\t"
484                                 : /* no outputs */
485                                 : "r" (target), "i" (ASI_INTR_W));
486                         nack_busy_id++;
487                 }
488         }
489
490         /* Now, poll for completion. */
491         {
492                 u64 dispatch_stat;
493                 long stuck;
494
495                 stuck = 100000 * nack_busy_id;
496                 do {
497                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
498                                              : "=r" (dispatch_stat)
499                                              : "i" (ASI_INTR_DISPATCH_STAT));
500                         if (dispatch_stat == 0UL) {
501                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
502                                                      : : "r" (pstate));
503                                 return;
504                         }
505                         if (!--stuck)
506                                 break;
507                 } while (dispatch_stat & 0x5555555555555555UL);
508
509                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
510                                      : : "r" (pstate));
511
512                 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
513                         /* Busy bits will not clear, continue instead
514                          * of freezing up on this cpu.
515                          */
516                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
517                                smp_processor_id(), dispatch_stat);
518                 } else {
519                         int i, this_busy_nack = 0;
520
521                         /* Delay some random time with interrupts enabled
522                          * to prevent deadlock.
523                          */
524                         udelay(2 * nack_busy_id);
525
526                         /* Clear out the mask bits for cpus which did not
527                          * NACK us.
528                          */
529                         for_each_cpu_mask(i, mask) {
530                                 u64 check_mask;
531
532                                 if (is_jalapeno)
533                                         check_mask = (0x2UL << (2*i));
534                                 else
535                                         check_mask = (0x2UL <<
536                                                       this_busy_nack);
537                                 if ((dispatch_stat & check_mask) == 0)
538                                         cpu_clear(i, mask);
539                                 this_busy_nack += 2;
540                         }
541
542                         goto retry;
543                 }
544         }
545 }
546
547 /* Send cross call to all processors mentioned in MASK
548  * except self.
549  */
550 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
551 {
552         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
553         int this_cpu = get_cpu();
554
555         cpus_and(mask, mask, cpu_online_map);
556         cpu_clear(this_cpu, mask);
557
558         if (tlb_type == spitfire)
559                 spitfire_xcall_deliver(data0, data1, data2, mask);
560         else
561                 cheetah_xcall_deliver(data0, data1, data2, mask);
562         /* NOTE: Caller runs local copy on master. */
563
564         put_cpu();
565 }
566
567 extern unsigned long xcall_sync_tick;
568
569 static void smp_start_sync_tick_client(int cpu)
570 {
571         cpumask_t mask = cpumask_of_cpu(cpu);
572
573         smp_cross_call_masked(&xcall_sync_tick,
574                               0, 0, 0, mask);
575 }
576
577 /* Send cross call to all processors except self. */
578 #define smp_cross_call(func, ctx, data1, data2) \
579         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
580
581 struct call_data_struct {
582         void (*func) (void *info);
583         void *info;
584         atomic_t finished;
585         int wait;
586 };
587
588 static DEFINE_SPINLOCK(call_lock);
589 static struct call_data_struct *call_data;
590
591 extern unsigned long xcall_call_function;
592
593 /*
594  * You must not call this function with disabled interrupts or from a
595  * hardware interrupt handler or from a bottom half handler.
596  */
597 int smp_call_function(void (*func)(void *info), void *info,
598                       int nonatomic, int wait)
599 {
600         struct call_data_struct data;
601         int cpus = num_online_cpus() - 1;
602         long timeout;
603
604         if (!cpus)
605                 return 0;
606
607         /* Can deadlock when called with interrupts disabled */
608         WARN_ON(irqs_disabled());
609
610         data.func = func;
611         data.info = info;
612         atomic_set(&data.finished, 0);
613         data.wait = wait;
614
615         spin_lock(&call_lock);
616
617         call_data = &data;
618
619         smp_cross_call(&xcall_call_function, 0, 0, 0);
620
621         /* 
622          * Wait for other cpus to complete function or at
623          * least snap the call data.
624          */
625         timeout = 1000000;
626         while (atomic_read(&data.finished) != cpus) {
627                 if (--timeout <= 0)
628                         goto out_timeout;
629                 barrier();
630                 udelay(1);
631         }
632
633         spin_unlock(&call_lock);
634
635         return 0;
636
637 out_timeout:
638         spin_unlock(&call_lock);
639         printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
640                (long) num_online_cpus() - 1L,
641                (long) atomic_read(&data.finished));
642         return 0;
643 }
644
645 void smp_call_function_client(int irq, struct pt_regs *regs)
646 {
647         void (*func) (void *info) = call_data->func;
648         void *info = call_data->info;
649
650         clear_softint(1 << irq);
651         if (call_data->wait) {
652                 /* let initiator proceed only after completion */
653                 func(info);
654                 atomic_inc(&call_data->finished);
655         } else {
656                 /* let initiator proceed after getting data */
657                 atomic_inc(&call_data->finished);
658                 func(info);
659         }
660 }
661
662 extern unsigned long xcall_flush_tlb_mm;
663 extern unsigned long xcall_flush_tlb_pending;
664 extern unsigned long xcall_flush_tlb_kernel_range;
665 extern unsigned long xcall_flush_tlb_all_spitfire;
666 extern unsigned long xcall_flush_tlb_all_cheetah;
667 extern unsigned long xcall_report_regs;
668 extern unsigned long xcall_receive_signal;
669
670 #ifdef DCACHE_ALIASING_POSSIBLE
671 extern unsigned long xcall_flush_dcache_page_cheetah;
672 #endif
673 extern unsigned long xcall_flush_dcache_page_spitfire;
674
675 #ifdef CONFIG_DEBUG_DCFLUSH
676 extern atomic_t dcpage_flushes;
677 extern atomic_t dcpage_flushes_xcall;
678 #endif
679
680 static __inline__ void __local_flush_dcache_page(struct page *page)
681 {
682 #ifdef DCACHE_ALIASING_POSSIBLE
683         __flush_dcache_page(page_address(page),
684                             ((tlb_type == spitfire) &&
685                              page_mapping(page) != NULL));
686 #else
687         if (page_mapping(page) != NULL &&
688             tlb_type == spitfire)
689                 __flush_icache_page(__pa(page_address(page)));
690 #endif
691 }
692
693 void smp_flush_dcache_page_impl(struct page *page, int cpu)
694 {
695         cpumask_t mask = cpumask_of_cpu(cpu);
696         int this_cpu = get_cpu();
697
698 #ifdef CONFIG_DEBUG_DCFLUSH
699         atomic_inc(&dcpage_flushes);
700 #endif
701         if (cpu == this_cpu) {
702                 __local_flush_dcache_page(page);
703         } else if (cpu_online(cpu)) {
704                 void *pg_addr = page_address(page);
705                 u64 data0;
706
707                 if (tlb_type == spitfire) {
708                         data0 =
709                                 ((u64)&xcall_flush_dcache_page_spitfire);
710                         if (page_mapping(page) != NULL)
711                                 data0 |= ((u64)1 << 32);
712                         spitfire_xcall_deliver(data0,
713                                                __pa(pg_addr),
714                                                (u64) pg_addr,
715                                                mask);
716                 } else {
717 #ifdef DCACHE_ALIASING_POSSIBLE
718                         data0 =
719                                 ((u64)&xcall_flush_dcache_page_cheetah);
720                         cheetah_xcall_deliver(data0,
721                                               __pa(pg_addr),
722                                               0, mask);
723 #endif
724                 }
725 #ifdef CONFIG_DEBUG_DCFLUSH
726                 atomic_inc(&dcpage_flushes_xcall);
727 #endif
728         }
729
730         put_cpu();
731 }
732
733 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
734 {
735         void *pg_addr = page_address(page);
736         cpumask_t mask = cpu_online_map;
737         u64 data0;
738         int this_cpu = get_cpu();
739
740         cpu_clear(this_cpu, mask);
741
742 #ifdef CONFIG_DEBUG_DCFLUSH
743         atomic_inc(&dcpage_flushes);
744 #endif
745         if (cpus_empty(mask))
746                 goto flush_self;
747         if (tlb_type == spitfire) {
748                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
749                 if (page_mapping(page) != NULL)
750                         data0 |= ((u64)1 << 32);
751                 spitfire_xcall_deliver(data0,
752                                        __pa(pg_addr),
753                                        (u64) pg_addr,
754                                        mask);
755         } else {
756 #ifdef DCACHE_ALIASING_POSSIBLE
757                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
758                 cheetah_xcall_deliver(data0,
759                                       __pa(pg_addr),
760                                       0, mask);
761 #endif
762         }
763 #ifdef CONFIG_DEBUG_DCFLUSH
764         atomic_inc(&dcpage_flushes_xcall);
765 #endif
766  flush_self:
767         __local_flush_dcache_page(page);
768
769         put_cpu();
770 }
771
772 void smp_receive_signal(int cpu)
773 {
774         cpumask_t mask = cpumask_of_cpu(cpu);
775
776         if (cpu_online(cpu)) {
777                 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
778
779                 if (tlb_type == spitfire)
780                         spitfire_xcall_deliver(data0, 0, 0, mask);
781                 else
782                         cheetah_xcall_deliver(data0, 0, 0, mask);
783         }
784 }
785
786 void smp_receive_signal_client(int irq, struct pt_regs *regs)
787 {
788         /* Just return, rtrap takes care of the rest. */
789         clear_softint(1 << irq);
790 }
791
792 void smp_report_regs(void)
793 {
794         smp_cross_call(&xcall_report_regs, 0, 0, 0);
795 }
796
797 void smp_flush_tlb_all(void)
798 {
799         if (tlb_type == spitfire)
800                 smp_cross_call(&xcall_flush_tlb_all_spitfire, 0, 0, 0);
801         else
802                 smp_cross_call(&xcall_flush_tlb_all_cheetah, 0, 0, 0);
803         __flush_tlb_all();
804 }
805
806 /* We know that the window frames of the user have been flushed
807  * to the stack before we get here because all callers of us
808  * are flush_tlb_*() routines, and these run after flush_cache_*()
809  * which performs the flushw.
810  *
811  * The SMP TLB coherency scheme we use works as follows:
812  *
813  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
814  *    space has (potentially) executed on, this is the heuristic
815  *    we use to avoid doing cross calls.
816  *
817  *    Also, for flushing from kswapd and also for clones, we
818  *    use cpu_vm_mask as the list of cpus to make run the TLB.
819  *
820  * 2) TLB context numbers are shared globally across all processors
821  *    in the system, this allows us to play several games to avoid
822  *    cross calls.
823  *
824  *    One invariant is that when a cpu switches to a process, and
825  *    that processes tsk->active_mm->cpu_vm_mask does not have the
826  *    current cpu's bit set, that tlb context is flushed locally.
827  *
828  *    If the address space is non-shared (ie. mm->count == 1) we avoid
829  *    cross calls when we want to flush the currently running process's
830  *    tlb state.  This is done by clearing all cpu bits except the current
831  *    processor's in current->active_mm->cpu_vm_mask and performing the
832  *    flush locally only.  This will force any subsequent cpus which run
833  *    this task to flush the context from the local tlb if the process
834  *    migrates to another cpu (again).
835  *
836  * 3) For shared address spaces (threads) and swapping we bite the
837  *    bullet for most cases and perform the cross call (but only to
838  *    the cpus listed in cpu_vm_mask).
839  *
840  *    The performance gain from "optimizing" away the cross call for threads is
841  *    questionable (in theory the big win for threads is the massive sharing of
842  *    address space state across processors).
843  */
844
845 /* This currently is only used by the hugetlb arch pre-fault
846  * hook on UltraSPARC-III+ and later when changing the pagesize
847  * bits of the context register for an address space.
848  */
849 void smp_flush_tlb_mm(struct mm_struct *mm)
850 {
851         u32 ctx = CTX_HWBITS(mm->context);
852         int cpu = get_cpu();
853
854         if (atomic_read(&mm->mm_users) == 1) {
855                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
856                 goto local_flush_and_out;
857         }
858
859         smp_cross_call_masked(&xcall_flush_tlb_mm,
860                               ctx, 0, 0,
861                               mm->cpu_vm_mask);
862
863 local_flush_and_out:
864         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
865
866         put_cpu();
867 }
868
869 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
870 {
871         u32 ctx = CTX_HWBITS(mm->context);
872         int cpu = get_cpu();
873
874         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
875                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
876         else
877                 smp_cross_call_masked(&xcall_flush_tlb_pending,
878                                       ctx, nr, (unsigned long) vaddrs,
879                                       mm->cpu_vm_mask);
880
881         __flush_tlb_pending(ctx, nr, vaddrs);
882
883         put_cpu();
884 }
885
886 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
887 {
888         start &= PAGE_MASK;
889         end    = PAGE_ALIGN(end);
890         if (start != end) {
891                 smp_cross_call(&xcall_flush_tlb_kernel_range,
892                                0, start, end);
893
894                 __flush_tlb_kernel_range(start, end);
895         }
896 }
897
898 /* CPU capture. */
899 /* #define CAPTURE_DEBUG */
900 extern unsigned long xcall_capture;
901
902 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
903 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
904 static unsigned long penguins_are_doing_time;
905
906 void smp_capture(void)
907 {
908         int result = atomic_add_ret(1, &smp_capture_depth);
909
910         if (result == 1) {
911                 int ncpus = num_online_cpus();
912
913 #ifdef CAPTURE_DEBUG
914                 printk("CPU[%d]: Sending penguins to jail...",
915                        smp_processor_id());
916 #endif
917                 penguins_are_doing_time = 1;
918                 membar_storestore_loadstore();
919                 atomic_inc(&smp_capture_registry);
920                 smp_cross_call(&xcall_capture, 0, 0, 0);
921                 while (atomic_read(&smp_capture_registry) != ncpus)
922                         rmb();
923 #ifdef CAPTURE_DEBUG
924                 printk("done\n");
925 #endif
926         }
927 }
928
929 void smp_release(void)
930 {
931         if (atomic_dec_and_test(&smp_capture_depth)) {
932 #ifdef CAPTURE_DEBUG
933                 printk("CPU[%d]: Giving pardon to "
934                        "imprisoned penguins\n",
935                        smp_processor_id());
936 #endif
937                 penguins_are_doing_time = 0;
938                 membar_storeload_storestore();
939                 atomic_dec(&smp_capture_registry);
940         }
941 }
942
943 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
944  * can service tlb flush xcalls...
945  */
946 extern void prom_world(int);
947 extern void save_alternate_globals(unsigned long *);
948 extern void restore_alternate_globals(unsigned long *);
949 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
950 {
951         unsigned long global_save[24];
952
953         clear_softint(1 << irq);
954
955         preempt_disable();
956
957         __asm__ __volatile__("flushw");
958         save_alternate_globals(global_save);
959         prom_world(1);
960         atomic_inc(&smp_capture_registry);
961         membar_storeload_storestore();
962         while (penguins_are_doing_time)
963                 rmb();
964         restore_alternate_globals(global_save);
965         atomic_dec(&smp_capture_registry);
966         prom_world(0);
967
968         preempt_enable();
969 }
970
971 #define prof_multiplier(__cpu)          cpu_data(__cpu).multiplier
972 #define prof_counter(__cpu)             cpu_data(__cpu).counter
973
974 void smp_percpu_timer_interrupt(struct pt_regs *regs)
975 {
976         unsigned long compare, tick, pstate;
977         int cpu = smp_processor_id();
978         int user = user_mode(regs);
979
980         /*
981          * Check for level 14 softint.
982          */
983         {
984                 unsigned long tick_mask = tick_ops->softint_mask;
985
986                 if (!(get_softint() & tick_mask)) {
987                         extern void handler_irq(int, struct pt_regs *);
988
989                         handler_irq(14, regs);
990                         return;
991                 }
992                 clear_softint(tick_mask);
993         }
994
995         do {
996                 profile_tick(CPU_PROFILING, regs);
997                 if (!--prof_counter(cpu)) {
998                         irq_enter();
999
1000                         if (cpu == boot_cpu_id) {
1001                                 kstat_this_cpu.irqs[0]++;
1002                                 timer_tick_interrupt(regs);
1003                         }
1004
1005                         update_process_times(user);
1006
1007                         irq_exit();
1008
1009                         prof_counter(cpu) = prof_multiplier(cpu);
1010                 }
1011
1012                 /* Guarantee that the following sequences execute
1013                  * uninterrupted.
1014                  */
1015                 __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1016                                      "wrpr      %0, %1, %%pstate"
1017                                      : "=r" (pstate)
1018                                      : "i" (PSTATE_IE));
1019
1020                 compare = tick_ops->add_compare(current_tick_offset);
1021                 tick = tick_ops->get_tick();
1022
1023                 /* Restore PSTATE_IE. */
1024                 __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1025                                      : /* no outputs */
1026                                      : "r" (pstate));
1027         } while (time_after_eq(tick, compare));
1028 }
1029
1030 static void __init smp_setup_percpu_timer(void)
1031 {
1032         int cpu = smp_processor_id();
1033         unsigned long pstate;
1034
1035         prof_counter(cpu) = prof_multiplier(cpu) = 1;
1036
1037         /* Guarantee that the following sequences execute
1038          * uninterrupted.
1039          */
1040         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
1041                              "wrpr      %0, %1, %%pstate"
1042                              : "=r" (pstate)
1043                              : "i" (PSTATE_IE));
1044
1045         tick_ops->init_tick(current_tick_offset);
1046
1047         /* Restore PSTATE_IE. */
1048         __asm__ __volatile__("wrpr      %0, 0x0, %%pstate"
1049                              : /* no outputs */
1050                              : "r" (pstate));
1051 }
1052
1053 void __init smp_tick_init(void)
1054 {
1055         boot_cpu_id = hard_smp_processor_id();
1056         current_tick_offset = timer_tick_offset;
1057
1058         cpu_set(boot_cpu_id, cpu_online_map);
1059         prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1060 }
1061
1062 /* /proc/profile writes can call this, don't __init it please. */
1063 static DEFINE_SPINLOCK(prof_setup_lock);
1064
1065 int setup_profiling_timer(unsigned int multiplier)
1066 {
1067         unsigned long flags;
1068         int i;
1069
1070         if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1071                 return -EINVAL;
1072
1073         spin_lock_irqsave(&prof_setup_lock, flags);
1074         for (i = 0; i < NR_CPUS; i++)
1075                 prof_multiplier(i) = multiplier;
1076         current_tick_offset = (timer_tick_offset / multiplier);
1077         spin_unlock_irqrestore(&prof_setup_lock, flags);
1078
1079         return 0;
1080 }
1081
1082 /* Constrain the number of cpus to max_cpus.  */
1083 void __init smp_prepare_cpus(unsigned int max_cpus)
1084 {
1085         if (num_possible_cpus() > max_cpus) {
1086                 int instance, mid;
1087
1088                 instance = 0;
1089                 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1090                         if (mid != boot_cpu_id) {
1091                                 cpu_clear(mid, phys_cpu_present_map);
1092                                 if (num_possible_cpus() <= max_cpus)
1093                                         break;
1094                         }
1095                         instance++;
1096                 }
1097         }
1098
1099         smp_store_cpu_info(boot_cpu_id);
1100 }
1101
1102 /* Set this up early so that things like the scheduler can init
1103  * properly.  We use the same cpu mask for both the present and
1104  * possible cpu map.
1105  */
1106 void __init smp_setup_cpu_possible_map(void)
1107 {
1108         int instance, mid;
1109
1110         instance = 0;
1111         while (!cpu_find_by_instance(instance, NULL, &mid)) {
1112                 if (mid < NR_CPUS)
1113                         cpu_set(mid, phys_cpu_present_map);
1114                 instance++;
1115         }
1116 }
1117
1118 void __devinit smp_prepare_boot_cpu(void)
1119 {
1120         if (hard_smp_processor_id() >= NR_CPUS) {
1121                 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1122                 prom_halt();
1123         }
1124
1125         current_thread_info()->cpu = hard_smp_processor_id();
1126
1127         cpu_set(smp_processor_id(), cpu_online_map);
1128         cpu_set(smp_processor_id(), phys_cpu_present_map);
1129 }
1130
1131 int __devinit __cpu_up(unsigned int cpu)
1132 {
1133         int ret = smp_boot_one_cpu(cpu);
1134
1135         if (!ret) {
1136                 cpu_set(cpu, smp_commenced_mask);
1137                 while (!cpu_isset(cpu, cpu_online_map))
1138                         mb();
1139                 if (!cpu_isset(cpu, cpu_online_map)) {
1140                         ret = -ENODEV;
1141                 } else {
1142                         smp_synchronize_one_tick(cpu);
1143                 }
1144         }
1145         return ret;
1146 }
1147
1148 void __init smp_cpus_done(unsigned int max_cpus)
1149 {
1150         unsigned long bogosum = 0;
1151         int i;
1152
1153         for (i = 0; i < NR_CPUS; i++) {
1154                 if (cpu_online(i))
1155                         bogosum += cpu_data(i).udelay_val;
1156         }
1157         printk("Total of %ld processors activated "
1158                "(%lu.%02lu BogoMIPS).\n",
1159                (long) num_online_cpus(),
1160                bogosum/(500000/HZ),
1161                (bogosum/(5000/HZ))%100);
1162 }
1163
1164 void smp_send_reschedule(int cpu)
1165 {
1166         smp_receive_signal(cpu);
1167 }
1168
1169 /* This is a nop because we capture all other cpus
1170  * anyways when making the PROM active.
1171  */
1172 void smp_send_stop(void)
1173 {
1174 }
1175
1176 unsigned long __per_cpu_base __read_mostly;
1177 unsigned long __per_cpu_shift __read_mostly;
1178
1179 EXPORT_SYMBOL(__per_cpu_base);
1180 EXPORT_SYMBOL(__per_cpu_shift);
1181
1182 void __init setup_per_cpu_areas(void)
1183 {
1184         unsigned long goal, size, i;
1185         char *ptr;
1186         /* Created by linker magic */
1187         extern char __per_cpu_start[], __per_cpu_end[];
1188
1189         /* Copy section for each CPU (we discard the original) */
1190         goal = ALIGN(__per_cpu_end - __per_cpu_start, PAGE_SIZE);
1191
1192 #ifdef CONFIG_MODULES
1193         if (goal < PERCPU_ENOUGH_ROOM)
1194                 goal = PERCPU_ENOUGH_ROOM;
1195 #endif
1196         __per_cpu_shift = 0;
1197         for (size = 1UL; size < goal; size <<= 1UL)
1198                 __per_cpu_shift++;
1199
1200         /* Make sure the resulting __per_cpu_base value
1201          * will fit in the 43-bit sign extended IMMU
1202          * TSB register.
1203          */
1204         ptr = __alloc_bootmem(size * NR_CPUS, PAGE_SIZE,
1205                               (unsigned long) __per_cpu_start);
1206
1207         __per_cpu_base = ptr - __per_cpu_start;
1208
1209         if ((__per_cpu_shift < PAGE_SHIFT) ||
1210             (__per_cpu_base & ~PAGE_MASK) ||
1211             (__per_cpu_base != (((long) __per_cpu_base << 20) >> 20))) {
1212                 prom_printf("PER_CPU: Invalid layout, "
1213                             "ptr[%p] shift[%lx] base[%lx]\n",
1214                             ptr, __per_cpu_shift, __per_cpu_base);
1215                 prom_halt();
1216         }
1217
1218         for (i = 0; i < NR_CPUS; i++, ptr += size)
1219                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1220
1221         /* Finally, load in the boot cpu's base value.
1222          * We abuse the IMMU TSB register for trap handler
1223          * entry and exit loading of %g5.  That is why it
1224          * has to be page aligned.
1225          */
1226         cpu_setup_percpu_base(hard_smp_processor_id());
1227 }