[SPARC64]: Generic sun4v_build_irq().
[linux-2.6.git] / arch / sparc64 / kernel / irq.c
1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2  * irq.c: UltraSparc IRQ handling/init/registry.
3  *
4  * Copyright (C) 1997  David S. Miller  (davem@caip.rutgers.edu)
5  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
6  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
7  */
8
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
16 #include <linux/mm.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
24 #include <linux/bootmem.h>
25
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
30 #include <asm/irq.h>
31 #include <asm/io.h>
32 #include <asm/sbus.h>
33 #include <asm/iommu.h>
34 #include <asm/upa.h>
35 #include <asm/oplib.h>
36 #include <asm/timer.h>
37 #include <asm/smp.h>
38 #include <asm/starfire.h>
39 #include <asm/uaccess.h>
40 #include <asm/cache.h>
41 #include <asm/cpudata.h>
42 #include <asm/auxio.h>
43 #include <asm/head.h>
44
45 #ifdef CONFIG_SMP
46 static void distribute_irqs(void);
47 #endif
48
49 /* UPA nodes send interrupt packet to UltraSparc with first data reg
50  * value low 5 (7 on Starfire) bits holding the IRQ identifier being
51  * delivered.  We must translate this into a non-vector IRQ so we can
52  * set the softint on this cpu.
53  *
54  * To make processing these packets efficient and race free we use
55  * an array of irq buckets below.  The interrupt vector handler in
56  * entry.S feeds incoming packets into per-cpu pil-indexed lists.
57  * The IVEC handler does not need to act atomically, the PIL dispatch
58  * code uses CAS to get an atomic snapshot of the list and clear it
59  * at the same time.
60  */
61
62 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
63
64 /* This has to be in the main kernel image, it cannot be
65  * turned into per-cpu data.  The reason is that the main
66  * kernel image is locked into the TLB and this structure
67  * is accessed from the vectored interrupt trap handler.  If
68  * access to this structure takes a TLB miss it could cause
69  * the 5-level sparc v9 trap stack to overflow.
70  */
71 struct irq_work_struct {
72         unsigned int    irq_worklists[16];
73 };
74 struct irq_work_struct __irq_work[NR_CPUS];
75 #define irq_work(__cpu, __pil)  &(__irq_work[(__cpu)].irq_worklists[(__pil)])
76
77 static struct irqaction *irq_action[NR_IRQS+1];
78
79 /* This only synchronizes entities which modify IRQ handler
80  * state and some selected user-level spots that want to
81  * read things in the table.  IRQ handler processing orders
82  * its' accesses such that no locking is needed.
83  */
84 static DEFINE_SPINLOCK(irq_action_lock);
85
86 static void register_irq_proc (unsigned int irq);
87
88 /*
89  * Upper 2b of irqaction->flags holds the ino.
90  * irqaction->mask holds the smp affinity information.
91  */
92 #define put_ino_in_irqaction(action, irq) \
93         action->flags &= 0xffffffffffffUL; \
94         if (__bucket(irq) == &pil0_dummy_bucket) \
95                 action->flags |= 0xdeadUL << 48;  \
96         else \
97                 action->flags |= __irq_ino(irq) << 48;
98 #define get_ino_in_irqaction(action)    (action->flags >> 48)
99
100 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
101 #define get_smpaff_in_irqaction(action)         ((action)->mask)
102
103 int show_interrupts(struct seq_file *p, void *v)
104 {
105         unsigned long flags;
106         int i = *(loff_t *) v;
107         struct irqaction *action;
108 #ifdef CONFIG_SMP
109         int j;
110 #endif
111
112         spin_lock_irqsave(&irq_action_lock, flags);
113         if (i <= NR_IRQS) {
114                 if (!(action = *(i + irq_action)))
115                         goto out_unlock;
116                 seq_printf(p, "%3d: ", i);
117 #ifndef CONFIG_SMP
118                 seq_printf(p, "%10u ", kstat_irqs(i));
119 #else
120                 for (j = 0; j < NR_CPUS; j++) {
121                         if (!cpu_online(j))
122                                 continue;
123                         seq_printf(p, "%10u ",
124                                    kstat_cpu(j).irqs[i]);
125                 }
126 #endif
127                 seq_printf(p, " %s:%lx", action->name,
128                            get_ino_in_irqaction(action));
129                 for (action = action->next; action; action = action->next) {
130                         seq_printf(p, ", %s:%lx", action->name,
131                                    get_ino_in_irqaction(action));
132                 }
133                 seq_putc(p, '\n');
134         }
135 out_unlock:
136         spin_unlock_irqrestore(&irq_action_lock, flags);
137
138         return 0;
139 }
140
141 /* Now these are always passed a true fully specified sun4u INO. */
142 void enable_irq(unsigned int irq)
143 {
144         struct ino_bucket *bucket = __bucket(irq);
145         unsigned long imap;
146         unsigned long tid;
147
148         imap = bucket->imap;
149         if (imap == 0UL)
150                 return;
151
152         preempt_disable();
153
154         if (tlb_type == hypervisor) {
155                 /* XXX SUN4V: implement me... XXX */
156         } else {
157                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
158                         unsigned long ver;
159
160                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
161                         if ((ver >> 32) == __JALAPENO_ID ||
162                             (ver >> 32) == __SERRANO_ID) {
163                                 /* We set it to our JBUS ID. */
164                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
165                                                      : "=r" (tid)
166                                                      : "i" (ASI_JBUS_CONFIG));
167                                 tid = ((tid & (0x1fUL<<17)) << 9);
168                                 tid &= IMAP_TID_JBUS;
169                         } else {
170                                 /* We set it to our Safari AID. */
171                                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
172                                                      : "=r" (tid)
173                                                      : "i"(ASI_SAFARI_CONFIG));
174                                 tid = ((tid & (0x3ffUL<<17)) << 9);
175                                 tid &= IMAP_AID_SAFARI;
176                         }
177                 } else if (this_is_starfire == 0) {
178                         /* We set it to our UPA MID. */
179                         __asm__ __volatile__("ldxa [%%g0] %1, %0"
180                                              : "=r" (tid)
181                                              : "i" (ASI_UPA_CONFIG));
182                         tid = ((tid & UPA_CONFIG_MID) << 9);
183                         tid &= IMAP_TID_UPA;
184                 } else {
185                         tid = (starfire_translate(imap,
186                                                   smp_processor_id()) << 26);
187                         tid &= IMAP_TID_UPA;
188                 }
189
190                 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
191                  * of this SYSIO's preconfigured IGN in the SYSIO Control
192                  * Register, the hardware just mirrors that value here.
193                  * However for Graphics and UPA Slave devices the full
194                  * IMAP_INR field can be set by the programmer here.
195                  *
196                  * Things like FFB can now be handled via the new IRQ
197                  * mechanism.
198                  */
199                 upa_writel(tid | IMAP_VALID, imap);
200         }
201
202         preempt_enable();
203 }
204
205 /* This now gets passed true ino's as well. */
206 void disable_irq(unsigned int irq)
207 {
208         struct ino_bucket *bucket = __bucket(irq);
209         unsigned long imap;
210
211         imap = bucket->imap;
212         if (imap != 0UL) {
213                 u32 tmp;
214
215                 /* NOTE: We do not want to futz with the IRQ clear registers
216                  *       and move the state to IDLE, the SCSI code does call
217                  *       disable_irq() to assure atomicity in the queue cmd
218                  *       SCSI adapter driver code.  Thus we'd lose interrupts.
219                  */
220                 tmp = upa_readl(imap);
221                 tmp &= ~IMAP_VALID;
222                 upa_writel(tmp, imap);
223         }
224 }
225
226 /* The timer is the one "weird" interrupt which is generated by
227  * the CPU %tick register and not by some normal vectored interrupt
228  * source.  To handle this special case, we use this dummy INO bucket.
229  */
230 static struct irq_desc pil0_dummy_desc;
231 static struct ino_bucket pil0_dummy_bucket = {
232         .irq_info       =       &pil0_dummy_desc,
233 };
234
235 static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup,
236                             unsigned long iclr, unsigned long imap,
237                             struct ino_bucket *bucket)
238 {
239         prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
240                     "(%d:%d:%016lx:%016lx), halting...\n",
241                     ino, bucket->pil, bucket->iclr, bucket->imap,
242                     pil, inofixup, iclr, imap);
243         prom_halt();
244 }
245
246 unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap)
247 {
248         struct ino_bucket *bucket;
249         int ino;
250
251         if (pil == 0) {
252                 if (iclr != 0UL || imap != 0UL) {
253                         prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
254                                     iclr, imap);
255                         prom_halt();
256                 }
257                 return __irq(&pil0_dummy_bucket);
258         }
259
260         /* RULE: Both must be specified in all other cases. */
261         if (iclr == 0UL || imap == 0UL) {
262                 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
263                             pil, inofixup, iclr, imap);
264                 prom_halt();
265         }
266         
267         ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
268         if (ino > NUM_IVECS) {
269                 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
270                             ino, pil, inofixup, iclr, imap);
271                 prom_halt();
272         }
273
274         bucket = &ivector_table[ino];
275         if (bucket->flags & IBF_ACTIVE)
276                 build_irq_error("IRQ: Trying to build active INO bucket.\n",
277                                 ino, pil, inofixup, iclr, imap, bucket);
278
279         if (bucket->irq_info) {
280                 if (bucket->imap != imap || bucket->iclr != iclr)
281                         build_irq_error("IRQ: Trying to reinit INO bucket.\n",
282                                         ino, pil, inofixup, iclr, imap, bucket);
283
284                 goto out;
285         }
286
287         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
288         if (!bucket->irq_info) {
289                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
290                 prom_halt();
291         }
292         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
293
294         /* Ok, looks good, set it up.  Don't touch the irq_chain or
295          * the pending flag.
296          */
297         bucket->imap  = imap;
298         bucket->iclr  = iclr;
299         bucket->pil   = pil;
300         bucket->flags = 0;
301
302 out:
303         return __irq(bucket);
304 }
305
306 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags)
307 {
308         struct ino_bucket *bucket;
309         unsigned long sysino;
310
311         sysino = sun4v_devino_to_sysino(devhandle, devino);
312
313         printk(KERN_INFO "sun4v_irq: Mapping ( devh[%08x] devino[%08x] ) "
314                "--> sysino[%016lx]\n", devhandle, devino, sysino);
315
316         bucket = &ivector_table[sysino];
317
318         /* Catch accidental accesses to these things.  IMAP/ICLR handling
319          * is done by hypervisor calls on sun4v platforms, not by direct
320          * register accesses.
321          */
322         bucket->imap = ~0UL;
323         bucket->iclr = ~0UL;
324
325         bucket->pil = pil;
326         bucket->flags = flags;
327
328         bucket->irq_info = kmalloc(sizeof(struct irq_desc), GFP_ATOMIC);
329         if (!bucket->irq_info) {
330                 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
331                 prom_halt();
332         }
333         memset(bucket->irq_info, 0, sizeof(struct irq_desc));
334
335         return __irq(bucket);
336 }
337
338 static void atomic_bucket_insert(struct ino_bucket *bucket)
339 {
340         unsigned long pstate;
341         unsigned int *ent;
342
343         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
344         __asm__ __volatile__("wrpr %0, %1, %%pstate"
345                              : : "r" (pstate), "i" (PSTATE_IE));
346         ent = irq_work(smp_processor_id(), bucket->pil);
347         bucket->irq_chain = *ent;
348         *ent = __irq(bucket);
349         __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
350 }
351
352 static int check_irq_sharing(int pil, unsigned long irqflags)
353 {
354         struct irqaction *action, *tmp;
355
356         action = *(irq_action + pil);
357         if (action) {
358                 if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) {
359                         for (tmp = action; tmp->next; tmp = tmp->next)
360                                 ;
361                 } else {
362                         return -EBUSY;
363                 }
364         }
365         return 0;
366 }
367
368 static void append_irq_action(int pil, struct irqaction *action)
369 {
370         struct irqaction **pp = irq_action + pil;
371
372         while (*pp)
373                 pp = &((*pp)->next);
374         *pp = action;
375 }
376
377 static struct irqaction *get_action_slot(struct ino_bucket *bucket)
378 {
379         struct irq_desc *desc = bucket->irq_info;
380         int max_irq, i;
381
382         max_irq = 1;
383         if (bucket->flags & IBF_PCI)
384                 max_irq = MAX_IRQ_DESC_ACTION;
385         for (i = 0; i < max_irq; i++) {
386                 struct irqaction *p = &desc->action[i];
387                 u32 mask = (1 << i);
388
389                 if (desc->action_active_mask & mask)
390                         continue;
391
392                 desc->action_active_mask |= mask;
393                 return p;
394         }
395         return NULL;
396 }
397
398 int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
399                 unsigned long irqflags, const char *name, void *dev_id)
400 {
401         struct irqaction *action;
402         struct ino_bucket *bucket = __bucket(irq);
403         unsigned long flags;
404         int pending = 0;
405
406         if (unlikely(!handler))
407                 return -EINVAL;
408
409         if (unlikely(!bucket->irq_info))
410                 return -ENODEV;
411
412         if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) {
413                 /*
414                  * This function might sleep, we want to call it first,
415                  * outside of the atomic block. In SA_STATIC_ALLOC case,
416                  * random driver's kmalloc will fail, but it is safe.
417                  * If already initialized, random driver will not reinit.
418                  * Yes, this might clear the entropy pool if the wrong
419                  * driver is attempted to be loaded, without actually
420                  * installing a new handler, but is this really a problem,
421                  * only the sysadmin is able to do this.
422                  */
423                 rand_initialize_irq(irq);
424         }
425
426         spin_lock_irqsave(&irq_action_lock, flags);
427
428         if (check_irq_sharing(bucket->pil, irqflags)) {
429                 spin_unlock_irqrestore(&irq_action_lock, flags);
430                 return -EBUSY;
431         }
432
433         action = get_action_slot(bucket);
434         if (!action) { 
435                 spin_unlock_irqrestore(&irq_action_lock, flags);
436                 return -ENOMEM;
437         }
438
439         bucket->flags |= IBF_ACTIVE;
440         pending = 0;
441         if (bucket != &pil0_dummy_bucket) {
442                 pending = bucket->pending;
443                 if (pending)
444                         bucket->pending = 0;
445         }
446
447         action->handler = handler;
448         action->flags = irqflags;
449         action->name = name;
450         action->next = NULL;
451         action->dev_id = dev_id;
452         put_ino_in_irqaction(action, irq);
453         put_smpaff_in_irqaction(action, CPU_MASK_NONE);
454
455         append_irq_action(bucket->pil, action);
456
457         enable_irq(irq);
458
459         /* We ate the IVEC already, this makes sure it does not get lost. */
460         if (pending) {
461                 atomic_bucket_insert(bucket);
462                 set_softint(1 << bucket->pil);
463         }
464
465         spin_unlock_irqrestore(&irq_action_lock, flags);
466
467         if (bucket != &pil0_dummy_bucket)
468                 register_irq_proc(__irq_ino(irq));
469
470 #ifdef CONFIG_SMP
471         distribute_irqs();
472 #endif
473         return 0;
474 }
475
476 EXPORT_SYMBOL(request_irq);
477
478 static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id)
479 {
480         struct ino_bucket *bucket = __bucket(irq);
481         struct irqaction *action, **pp;
482
483         pp = irq_action + bucket->pil;
484         action = *pp;
485         if (unlikely(!action))
486                 return NULL;
487
488         if (unlikely(!action->handler)) {
489                 printk("Freeing free IRQ %d\n", bucket->pil);
490                 return NULL;
491         }
492
493         while (action && action->dev_id != dev_id) {
494                 pp = &action->next;
495                 action = *pp;
496         }
497
498         if (likely(action))
499                 *pp = action->next;
500
501         return action;
502 }
503
504 void free_irq(unsigned int irq, void *dev_id)
505 {
506         struct irqaction *action;
507         struct ino_bucket *bucket;
508         unsigned long flags;
509
510         spin_lock_irqsave(&irq_action_lock, flags);
511
512         action = unlink_irq_action(irq, dev_id);
513
514         spin_unlock_irqrestore(&irq_action_lock, flags);
515
516         if (unlikely(!action))
517                 return;
518
519         synchronize_irq(irq);
520
521         spin_lock_irqsave(&irq_action_lock, flags);
522
523         bucket = __bucket(irq);
524         if (bucket != &pil0_dummy_bucket) {
525                 struct irq_desc *desc = bucket->irq_info;
526                 unsigned long imap = bucket->imap;
527                 int ent, i;
528
529                 for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
530                         struct irqaction *p = &desc->action[i];
531
532                         if (p == action) {
533                                 desc->action_active_mask &= ~(1 << i);
534                                 break;
535                         }
536                 }
537
538                 if (!desc->action_active_mask) {
539                         /* This unique interrupt source is now inactive. */
540                         bucket->flags &= ~IBF_ACTIVE;
541
542                         /* See if any other buckets share this bucket's IMAP
543                          * and are still active.
544                          */
545                         for (ent = 0; ent < NUM_IVECS; ent++) {
546                                 struct ino_bucket *bp = &ivector_table[ent];
547                                 if (bp != bucket        &&
548                                     bp->imap == imap    &&
549                                     (bp->flags & IBF_ACTIVE) != 0)
550                                         break;
551                         }
552
553                         /* Only disable when no other sub-irq levels of
554                          * the same IMAP are active.
555                          */
556                         if (ent == NUM_IVECS)
557                                 disable_irq(irq);
558                 }
559         }
560
561         spin_unlock_irqrestore(&irq_action_lock, flags);
562 }
563
564 EXPORT_SYMBOL(free_irq);
565
566 #ifdef CONFIG_SMP
567 void synchronize_irq(unsigned int irq)
568 {
569         struct ino_bucket *bucket = __bucket(irq);
570
571 #if 0
572         /* The following is how I wish I could implement this.
573          * Unfortunately the ICLR registers are read-only, you can
574          * only write ICLR_foo values to them.  To get the current
575          * IRQ status you would need to get at the IRQ diag registers
576          * in the PCI/SBUS controller and the layout of those vary
577          * from one controller to the next, sigh... -DaveM
578          */
579         unsigned long iclr = bucket->iclr;
580
581         while (1) {
582                 u32 tmp = upa_readl(iclr);
583                 
584                 if (tmp == ICLR_TRANSMIT ||
585                     tmp == ICLR_PENDING) {
586                         cpu_relax();
587                         continue;
588                 }
589                 break;
590         }
591 #else
592         /* So we have to do this with a INPROGRESS bit just like x86.  */
593         while (bucket->flags & IBF_INPROGRESS)
594                 cpu_relax();
595 #endif
596 }
597 #endif /* CONFIG_SMP */
598
599 static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs)
600 {
601         struct irq_desc *desc = bp->irq_info;
602         unsigned char flags = bp->flags;
603         u32 action_mask, i;
604         int random;
605
606         bp->flags |= IBF_INPROGRESS;
607
608         if (unlikely(!(flags & IBF_ACTIVE))) {
609                 bp->pending = 1;
610                 goto out;
611         }
612
613         if (desc->pre_handler)
614                 desc->pre_handler(bp,
615                                   desc->pre_handler_arg1,
616                                   desc->pre_handler_arg2);
617
618         action_mask = desc->action_active_mask;
619         random = 0;
620         for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) {
621                 struct irqaction *p = &desc->action[i];
622                 u32 mask = (1 << i);
623
624                 if (!(action_mask & mask))
625                         continue;
626
627                 action_mask &= ~mask;
628
629                 if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED)
630                         random |= p->flags;
631
632                 if (!action_mask)
633                         break;
634         }
635         if (bp->pil != 0) {
636                 upa_writel(ICLR_IDLE, bp->iclr);
637                 /* Test and add entropy */
638                 if (random & SA_SAMPLE_RANDOM)
639                         add_interrupt_randomness(irq);
640         }
641 out:
642         bp->flags &= ~IBF_INPROGRESS;
643 }
644
645 void handler_irq(int irq, struct pt_regs *regs)
646 {
647         struct ino_bucket *bp;
648         int cpu = smp_processor_id();
649
650 #ifndef CONFIG_SMP
651         /*
652          * Check for TICK_INT on level 14 softint.
653          */
654         {
655                 unsigned long clr_mask = 1 << irq;
656                 unsigned long tick_mask = tick_ops->softint_mask;
657
658                 if ((irq == 14) && (get_softint() & tick_mask)) {
659                         irq = 0;
660                         clr_mask = tick_mask;
661                 }
662                 clear_softint(clr_mask);
663         }
664 #else
665         clear_softint(1 << irq);
666 #endif
667
668         irq_enter();
669         kstat_this_cpu.irqs[irq]++;
670
671         /* Sliiiick... */
672 #ifndef CONFIG_SMP
673         bp = ((irq != 0) ?
674               __bucket(xchg32(irq_work(cpu, irq), 0)) :
675               &pil0_dummy_bucket);
676 #else
677         bp = __bucket(xchg32(irq_work(cpu, irq), 0));
678 #endif
679         while (bp) {
680                 struct ino_bucket *nbp = __bucket(bp->irq_chain);
681
682                 bp->irq_chain = 0;
683                 process_bucket(irq, bp, regs);
684                 bp = nbp;
685         }
686         irq_exit();
687 }
688
689 #ifdef CONFIG_BLK_DEV_FD
690 extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);;
691
692 /* XXX No easy way to include asm/floppy.h XXX */
693 extern unsigned char *pdma_vaddr;
694 extern unsigned long pdma_size;
695 extern volatile int doing_pdma;
696 extern unsigned long fdc_status;
697
698 irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs)
699 {
700         if (likely(doing_pdma)) {
701                 void __iomem *stat = (void __iomem *) fdc_status;
702                 unsigned char *vaddr = pdma_vaddr;
703                 unsigned long size = pdma_size;
704                 u8 val;
705
706                 while (size) {
707                         val = readb(stat);
708                         if (unlikely(!(val & 0x80))) {
709                                 pdma_vaddr = vaddr;
710                                 pdma_size = size;
711                                 return IRQ_HANDLED;
712                         }
713                         if (unlikely(!(val & 0x20))) {
714                                 pdma_vaddr = vaddr;
715                                 pdma_size = size;
716                                 doing_pdma = 0;
717                                 goto main_interrupt;
718                         }
719                         if (val & 0x40) {
720                                 /* read */
721                                 *vaddr++ = readb(stat + 1);
722                         } else {
723                                 unsigned char data = *vaddr++;
724
725                                 /* write */
726                                 writeb(data, stat + 1);
727                         }
728                         size--;
729                 }
730
731                 pdma_vaddr = vaddr;
732                 pdma_size = size;
733
734                 /* Send Terminal Count pulse to floppy controller. */
735                 val = readb(auxio_register);
736                 val |= AUXIO_AUX1_FTCNT;
737                 writeb(val, auxio_register);
738                 val &= ~AUXIO_AUX1_FTCNT;
739                 writeb(val, auxio_register);
740
741                 doing_pdma = 0;
742         }
743
744 main_interrupt:
745         return floppy_interrupt(irq, dev_cookie, regs);
746 }
747 EXPORT_SYMBOL(sparc_floppy_irq);
748 #endif
749
750 /* We really don't need these at all on the Sparc.  We only have
751  * stubs here because they are exported to modules.
752  */
753 unsigned long probe_irq_on(void)
754 {
755         return 0;
756 }
757
758 EXPORT_SYMBOL(probe_irq_on);
759
760 int probe_irq_off(unsigned long mask)
761 {
762         return 0;
763 }
764
765 EXPORT_SYMBOL(probe_irq_off);
766
767 #ifdef CONFIG_SMP
768 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
769 {
770         struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table;
771         unsigned long imap = bucket->imap;
772         unsigned int tid;
773
774         while (!cpu_online(goal_cpu)) {
775                 if (++goal_cpu >= NR_CPUS)
776                         goal_cpu = 0;
777         }
778
779         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
780                 tid = goal_cpu << 26;
781                 tid &= IMAP_AID_SAFARI;
782         } else if (this_is_starfire == 0) {
783                 tid = goal_cpu << 26;
784                 tid &= IMAP_TID_UPA;
785         } else {
786                 tid = (starfire_translate(imap, goal_cpu) << 26);
787                 tid &= IMAP_TID_UPA;
788         }
789         upa_writel(tid | IMAP_VALID, imap);
790
791         do {
792                 if (++goal_cpu >= NR_CPUS)
793                         goal_cpu = 0;
794         } while (!cpu_online(goal_cpu));
795
796         return goal_cpu;
797 }
798
799 /* Called from request_irq. */
800 static void distribute_irqs(void)
801 {
802         unsigned long flags;
803         int cpu, level;
804
805         spin_lock_irqsave(&irq_action_lock, flags);
806         cpu = 0;
807
808         /*
809          * Skip the timer at [0], and very rare error/power intrs at [15].
810          * Also level [12], it causes problems on Ex000 systems.
811          */
812         for (level = 1; level < NR_IRQS; level++) {
813                 struct irqaction *p = irq_action[level];
814
815                 if (level == 12)
816                         continue;
817
818                 while(p) {
819                         cpu = retarget_one_irq(p, cpu);
820                         p = p->next;
821                 }
822         }
823         spin_unlock_irqrestore(&irq_action_lock, flags);
824 }
825 #endif
826
827 struct sun5_timer {
828         u64     count0;
829         u64     limit0;
830         u64     count1;
831         u64     limit1;
832 };
833
834 static struct sun5_timer *prom_timers;
835 static u64 prom_limit0, prom_limit1;
836
837 static void map_prom_timers(void)
838 {
839         unsigned int addr[3];
840         int tnode, err;
841
842         /* PROM timer node hangs out in the top level of device siblings... */
843         tnode = prom_finddevice("/counter-timer");
844
845         /* Assume if node is not present, PROM uses different tick mechanism
846          * which we should not care about.
847          */
848         if (tnode == 0 || tnode == -1) {
849                 prom_timers = (struct sun5_timer *) 0;
850                 return;
851         }
852
853         /* If PROM is really using this, it must be mapped by him. */
854         err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr));
855         if (err == -1) {
856                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
857                 prom_timers = (struct sun5_timer *) 0;
858                 return;
859         }
860         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
861 }
862
863 static void kill_prom_timer(void)
864 {
865         if (!prom_timers)
866                 return;
867
868         /* Save them away for later. */
869         prom_limit0 = prom_timers->limit0;
870         prom_limit1 = prom_timers->limit1;
871
872         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
873          * We turn both off here just to be paranoid.
874          */
875         prom_timers->limit0 = 0;
876         prom_timers->limit1 = 0;
877
878         /* Wheee, eat the interrupt packet too... */
879         __asm__ __volatile__(
880 "       mov     0x40, %%g2\n"
881 "       ldxa    [%%g0] %0, %%g1\n"
882 "       ldxa    [%%g2] %1, %%g1\n"
883 "       stxa    %%g0, [%%g0] %0\n"
884 "       membar  #Sync\n"
885         : /* no outputs */
886         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
887         : "g1", "g2");
888 }
889
890 void init_irqwork_curcpu(void)
891 {
892         int cpu = hard_smp_processor_id();
893
894         memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct));
895 }
896
897 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type)
898 {
899         register unsigned long func __asm__("%o5");
900         register unsigned long arg0 __asm__("%o0");
901         register unsigned long arg1 __asm__("%o1");
902         register unsigned long arg2 __asm__("%o2");
903
904         func = HV_FAST_CPU_QCONF;
905         arg0 = type;
906         arg1 = paddr;
907         arg2 = 128; /* XXX Implied by Niagara queue offsets. XXX */
908         __asm__ __volatile__("ta        %8"
909                              : "=&r" (func), "=&r" (arg0),
910                                "=&r" (arg1), "=&r" (arg2)
911                              : "0" (func), "1" (arg0),
912                                "2" (arg1), "3" (arg2),
913                                "i" (HV_FAST_TRAP));
914
915         if (arg0 != HV_EOK) {
916                 prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n",
917                             type, func);
918                 prom_halt();
919         }
920 }
921
922 static void __cpuinit sun4v_register_mondo_queues(int this_cpu)
923 {
924         struct trap_per_cpu *tb = &trap_block[this_cpu];
925
926         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO);
927         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO);
928         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR);
929         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR);
930 }
931
932 static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem)
933 {
934         void *page;
935
936         if (use_bootmem)
937                 page = alloc_bootmem_low_pages(PAGE_SIZE);
938         else
939                 page = (void *) get_zeroed_page(GFP_ATOMIC);
940
941         if (!page) {
942                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
943                 prom_halt();
944         }
945
946         *pa_ptr = __pa(page);
947 }
948
949 static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem)
950 {
951         void *page;
952
953         if (use_bootmem)
954                 page = alloc_bootmem_low_pages(PAGE_SIZE);
955         else
956                 page = (void *) get_zeroed_page(GFP_ATOMIC);
957
958         if (!page) {
959                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
960                 prom_halt();
961         }
962
963         *pa_ptr = __pa(page);
964 }
965
966 static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem)
967 {
968 #ifdef CONFIG_SMP
969         void *page;
970
971         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
972
973         if (use_bootmem)
974                 page = alloc_bootmem_low_pages(PAGE_SIZE);
975         else
976                 page = (void *) get_zeroed_page(GFP_ATOMIC);
977
978         if (!page) {
979                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
980                 prom_halt();
981         }
982
983         tb->cpu_mondo_block_pa = __pa(page);
984         tb->cpu_list_pa = __pa(page + 64);
985 #endif
986 }
987
988 /* Allocate and register the mondo and error queues for this cpu.  */
989 void __cpuinit sun4v_init_mondo_queues(int use_bootmem)
990 {
991         int cpu = hard_smp_processor_id();
992         struct trap_per_cpu *tb = &trap_block[cpu];
993
994         alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem);
995         alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem);
996         alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem);
997         alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem);
998         alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem);
999         alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem);
1000
1001         init_cpu_send_mondo_info(tb, use_bootmem);
1002
1003         sun4v_register_mondo_queues(cpu);
1004 }
1005
1006 /* Only invoked on boot processor. */
1007 void __init init_IRQ(void)
1008 {
1009         map_prom_timers();
1010         kill_prom_timer();
1011         memset(&ivector_table[0], 0, sizeof(ivector_table));
1012
1013         if (tlb_type == hypervisor)
1014                 sun4v_init_mondo_queues(1);
1015
1016         /* We need to clear any IRQ's pending in the soft interrupt
1017          * registers, a spurious one could be left around from the
1018          * PROM timer which we just disabled.
1019          */
1020         clear_softint(get_softint());
1021
1022         /* Now that ivector table is initialized, it is safe
1023          * to receive IRQ vector traps.  We will normally take
1024          * one or two right now, in case some device PROM used
1025          * to boot us wants to speak to us.  We just ignore them.
1026          */
1027         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1028                              "or        %%g1, %0, %%g1\n\t"
1029                              "wrpr      %%g1, 0x0, %%pstate"
1030                              : /* No outputs */
1031                              : "i" (PSTATE_IE)
1032                              : "g1");
1033 }
1034
1035 static struct proc_dir_entry * root_irq_dir;
1036 static struct proc_dir_entry * irq_dir [NUM_IVECS];
1037
1038 #ifdef CONFIG_SMP
1039
1040 static int irq_affinity_read_proc (char *page, char **start, off_t off,
1041                         int count, int *eof, void *data)
1042 {
1043         struct ino_bucket *bp = ivector_table + (long)data;
1044         struct irq_desc *desc = bp->irq_info;
1045         struct irqaction *ap = desc->action;
1046         cpumask_t mask;
1047         int len;
1048
1049         mask = get_smpaff_in_irqaction(ap);
1050         if (cpus_empty(mask))
1051                 mask = cpu_online_map;
1052
1053         len = cpumask_scnprintf(page, count, mask);
1054         if (count - len < 2)
1055                 return -EINVAL;
1056         len += sprintf(page + len, "\n");
1057         return len;
1058 }
1059
1060 static inline void set_intr_affinity(int irq, cpumask_t hw_aff)
1061 {
1062         struct ino_bucket *bp = ivector_table + irq;
1063         struct irq_desc *desc = bp->irq_info;
1064         struct irqaction *ap = desc->action;
1065
1066         /* Users specify affinity in terms of hw cpu ids.
1067          * As soon as we do this, handler_irq() might see and take action.
1068          */
1069         put_smpaff_in_irqaction(ap, hw_aff);
1070
1071         /* Migration is simply done by the next cpu to service this
1072          * interrupt.
1073          */
1074 }
1075
1076 static int irq_affinity_write_proc (struct file *file, const char __user *buffer,
1077                                         unsigned long count, void *data)
1078 {
1079         int irq = (long) data, full_count = count, err;
1080         cpumask_t new_value;
1081
1082         err = cpumask_parse(buffer, count, new_value);
1083
1084         /*
1085          * Do not allow disabling IRQs completely - it's a too easy
1086          * way to make the system unusable accidentally :-) At least
1087          * one online CPU still has to be targeted.
1088          */
1089         cpus_and(new_value, new_value, cpu_online_map);
1090         if (cpus_empty(new_value))
1091                 return -EINVAL;
1092
1093         set_intr_affinity(irq, new_value);
1094
1095         return full_count;
1096 }
1097
1098 #endif
1099
1100 #define MAX_NAMELEN 10
1101
1102 static void register_irq_proc (unsigned int irq)
1103 {
1104         char name [MAX_NAMELEN];
1105
1106         if (!root_irq_dir || irq_dir[irq])
1107                 return;
1108
1109         memset(name, 0, MAX_NAMELEN);
1110         sprintf(name, "%x", irq);
1111
1112         /* create /proc/irq/1234 */
1113         irq_dir[irq] = proc_mkdir(name, root_irq_dir);
1114
1115 #ifdef CONFIG_SMP
1116         /* XXX SMP affinity not supported on starfire yet. */
1117         if (this_is_starfire == 0) {
1118                 struct proc_dir_entry *entry;
1119
1120                 /* create /proc/irq/1234/smp_affinity */
1121                 entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]);
1122
1123                 if (entry) {
1124                         entry->nlink = 1;
1125                         entry->data = (void *)(long)irq;
1126                         entry->read_proc = irq_affinity_read_proc;
1127                         entry->write_proc = irq_affinity_write_proc;
1128                 }
1129         }
1130 #endif
1131 }
1132
1133 void init_irq_proc (void)
1134 {
1135         /* create /proc/irq */
1136         root_irq_dir = proc_mkdir("irq", NULL);
1137 }
1138