c77c7ef5d5d4d51de8ac6dfe58a74c8336f83d14
[linux-2.6.git] / arch / sparc / mm / init_64.c
1 /*
2  *  arch/sparc64/mm/init.c
3  *
4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6  */
7  
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
14 #include <linux/mm.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/percpu.h>
27 #include <linux/lmb.h>
28 #include <linux/mmzone.h>
29
30 #include <asm/head.h>
31 #include <asm/system.h>
32 #include <asm/page.h>
33 #include <asm/pgalloc.h>
34 #include <asm/pgtable.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <asm/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/irq.h>
52
53 #include "init_64.h"
54
55 unsigned long kern_linear_pte_xor[2] __read_mostly;
56
57 /* A bitmap, one bit for every 256MB of physical memory.  If the bit
58  * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
59  * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60  */
61 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62
63 #ifndef CONFIG_DEBUG_PAGEALLOC
64 /* A special kernel TSB for 4MB and 256MB linear mappings.
65  * Space is allocated for this right after the trap table
66  * in arch/sparc64/kernel/head.S
67  */
68 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 #endif
70
71 #define MAX_BANKS       32
72
73 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
74 static int pavail_ents __initdata;
75
76 static int cmp_p64(const void *a, const void *b)
77 {
78         const struct linux_prom64_registers *x = a, *y = b;
79
80         if (x->phys_addr > y->phys_addr)
81                 return 1;
82         if (x->phys_addr < y->phys_addr)
83                 return -1;
84         return 0;
85 }
86
87 static void __init read_obp_memory(const char *property,
88                                    struct linux_prom64_registers *regs,
89                                    int *num_ents)
90 {
91         int node = prom_finddevice("/memory");
92         int prop_size = prom_getproplen(node, property);
93         int ents, ret, i;
94
95         ents = prop_size / sizeof(struct linux_prom64_registers);
96         if (ents > MAX_BANKS) {
97                 prom_printf("The machine has more %s property entries than "
98                             "this kernel can support (%d).\n",
99                             property, MAX_BANKS);
100                 prom_halt();
101         }
102
103         ret = prom_getproperty(node, property, (char *) regs, prop_size);
104         if (ret == -1) {
105                 prom_printf("Couldn't get %s property from /memory.\n");
106                 prom_halt();
107         }
108
109         /* Sanitize what we got from the firmware, by page aligning
110          * everything.
111          */
112         for (i = 0; i < ents; i++) {
113                 unsigned long base, size;
114
115                 base = regs[i].phys_addr;
116                 size = regs[i].reg_size;
117
118                 size &= PAGE_MASK;
119                 if (base & ~PAGE_MASK) {
120                         unsigned long new_base = PAGE_ALIGN(base);
121
122                         size -= new_base - base;
123                         if ((long) size < 0L)
124                                 size = 0UL;
125                         base = new_base;
126                 }
127                 if (size == 0UL) {
128                         /* If it is empty, simply get rid of it.
129                          * This simplifies the logic of the other
130                          * functions that process these arrays.
131                          */
132                         memmove(&regs[i], &regs[i + 1],
133                                 (ents - i - 1) * sizeof(regs[0]));
134                         i--;
135                         ents--;
136                         continue;
137                 }
138                 regs[i].phys_addr = base;
139                 regs[i].reg_size = size;
140         }
141
142         *num_ents = ents;
143
144         sort(regs, ents, sizeof(struct linux_prom64_registers),
145              cmp_p64, NULL);
146 }
147
148 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
149
150 /* Kernel physical address base and size in bytes.  */
151 unsigned long kern_base __read_mostly;
152 unsigned long kern_size __read_mostly;
153
154 /* Initial ramdisk setup */
155 extern unsigned long sparc_ramdisk_image64;
156 extern unsigned int sparc_ramdisk_image;
157 extern unsigned int sparc_ramdisk_size;
158
159 struct page *mem_map_zero __read_mostly;
160 EXPORT_SYMBOL(mem_map_zero);
161
162 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
163
164 unsigned long sparc64_kern_pri_context __read_mostly;
165 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
166 unsigned long sparc64_kern_sec_context __read_mostly;
167
168 int num_kernel_image_mappings;
169
170 #ifdef CONFIG_DEBUG_DCFLUSH
171 atomic_t dcpage_flushes = ATOMIC_INIT(0);
172 #ifdef CONFIG_SMP
173 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
174 #endif
175 #endif
176
177 inline void flush_dcache_page_impl(struct page *page)
178 {
179         BUG_ON(tlb_type == hypervisor);
180 #ifdef CONFIG_DEBUG_DCFLUSH
181         atomic_inc(&dcpage_flushes);
182 #endif
183
184 #ifdef DCACHE_ALIASING_POSSIBLE
185         __flush_dcache_page(page_address(page),
186                             ((tlb_type == spitfire) &&
187                              page_mapping(page) != NULL));
188 #else
189         if (page_mapping(page) != NULL &&
190             tlb_type == spitfire)
191                 __flush_icache_page(__pa(page_address(page)));
192 #endif
193 }
194
195 #define PG_dcache_dirty         PG_arch_1
196 #define PG_dcache_cpu_shift     32UL
197 #define PG_dcache_cpu_mask      \
198         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
199
200 #define dcache_dirty_cpu(page) \
201         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
202
203 static inline void set_dcache_dirty(struct page *page, int this_cpu)
204 {
205         unsigned long mask = this_cpu;
206         unsigned long non_cpu_bits;
207
208         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
209         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
210
211         __asm__ __volatile__("1:\n\t"
212                              "ldx       [%2], %%g7\n\t"
213                              "and       %%g7, %1, %%g1\n\t"
214                              "or        %%g1, %0, %%g1\n\t"
215                              "casx      [%2], %%g7, %%g1\n\t"
216                              "cmp       %%g7, %%g1\n\t"
217                              "bne,pn    %%xcc, 1b\n\t"
218                              " nop"
219                              : /* no outputs */
220                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
221                              : "g1", "g7");
222 }
223
224 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
225 {
226         unsigned long mask = (1UL << PG_dcache_dirty);
227
228         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
229                              "1:\n\t"
230                              "ldx       [%2], %%g7\n\t"
231                              "srlx      %%g7, %4, %%g1\n\t"
232                              "and       %%g1, %3, %%g1\n\t"
233                              "cmp       %%g1, %0\n\t"
234                              "bne,pn    %%icc, 2f\n\t"
235                              " andn     %%g7, %1, %%g1\n\t"
236                              "casx      [%2], %%g7, %%g1\n\t"
237                              "cmp       %%g7, %%g1\n\t"
238                              "bne,pn    %%xcc, 1b\n\t"
239                              " nop\n"
240                              "2:"
241                              : /* no outputs */
242                              : "r" (cpu), "r" (mask), "r" (&page->flags),
243                                "i" (PG_dcache_cpu_mask),
244                                "i" (PG_dcache_cpu_shift)
245                              : "g1", "g7");
246 }
247
248 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
249 {
250         unsigned long tsb_addr = (unsigned long) ent;
251
252         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
253                 tsb_addr = __pa(tsb_addr);
254
255         __tsb_insert(tsb_addr, tag, pte);
256 }
257
258 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
259 unsigned long _PAGE_SZBITS __read_mostly;
260
261 static void flush_dcache(unsigned long pfn)
262 {
263         struct page *page;
264
265         page = pfn_to_page(pfn);
266         if (page && page_mapping(page)) {
267                 unsigned long pg_flags;
268
269                 pg_flags = page->flags;
270                 if (pg_flags & (1UL << PG_dcache_dirty)) {
271                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
272                                    PG_dcache_cpu_mask);
273                         int this_cpu = get_cpu();
274
275                         /* This is just to optimize away some function calls
276                          * in the SMP case.
277                          */
278                         if (cpu == this_cpu)
279                                 flush_dcache_page_impl(page);
280                         else
281                                 smp_flush_dcache_page_impl(page, cpu);
282
283                         clear_dcache_dirty_cpu(page, cpu);
284
285                         put_cpu();
286                 }
287         }
288 }
289
290 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
291 {
292         struct mm_struct *mm;
293         struct tsb *tsb;
294         unsigned long tag, flags;
295         unsigned long tsb_index, tsb_hash_shift;
296
297         if (tlb_type != hypervisor) {
298                 unsigned long pfn = pte_pfn(pte);
299
300                 if (pfn_valid(pfn))
301                         flush_dcache(pfn);
302         }
303
304         mm = vma->vm_mm;
305
306         tsb_index = MM_TSB_BASE;
307         tsb_hash_shift = PAGE_SHIFT;
308
309         spin_lock_irqsave(&mm->context.lock, flags);
310
311 #ifdef CONFIG_HUGETLB_PAGE
312         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
313                 if ((tlb_type == hypervisor &&
314                      (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
315                     (tlb_type != hypervisor &&
316                      (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
317                         tsb_index = MM_TSB_HUGE;
318                         tsb_hash_shift = HPAGE_SHIFT;
319                 }
320         }
321 #endif
322
323         tsb = mm->context.tsb_block[tsb_index].tsb;
324         tsb += ((address >> tsb_hash_shift) &
325                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
326         tag = (address >> 22UL);
327         tsb_insert(tsb, tag, pte_val(pte));
328
329         spin_unlock_irqrestore(&mm->context.lock, flags);
330 }
331
332 void flush_dcache_page(struct page *page)
333 {
334         struct address_space *mapping;
335         int this_cpu;
336
337         if (tlb_type == hypervisor)
338                 return;
339
340         /* Do not bother with the expensive D-cache flush if it
341          * is merely the zero page.  The 'bigcore' testcase in GDB
342          * causes this case to run millions of times.
343          */
344         if (page == ZERO_PAGE(0))
345                 return;
346
347         this_cpu = get_cpu();
348
349         mapping = page_mapping(page);
350         if (mapping && !mapping_mapped(mapping)) {
351                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
352                 if (dirty) {
353                         int dirty_cpu = dcache_dirty_cpu(page);
354
355                         if (dirty_cpu == this_cpu)
356                                 goto out;
357                         smp_flush_dcache_page_impl(page, dirty_cpu);
358                 }
359                 set_dcache_dirty(page, this_cpu);
360         } else {
361                 /* We could delay the flush for the !page_mapping
362                  * case too.  But that case is for exec env/arg
363                  * pages and those are %99 certainly going to get
364                  * faulted into the tlb (and thus flushed) anyways.
365                  */
366                 flush_dcache_page_impl(page);
367         }
368
369 out:
370         put_cpu();
371 }
372
373 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
374 {
375         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
376         if (tlb_type == spitfire) {
377                 unsigned long kaddr;
378
379                 /* This code only runs on Spitfire cpus so this is
380                  * why we can assume _PAGE_PADDR_4U.
381                  */
382                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
383                         unsigned long paddr, mask = _PAGE_PADDR_4U;
384
385                         if (kaddr >= PAGE_OFFSET)
386                                 paddr = kaddr & mask;
387                         else {
388                                 pgd_t *pgdp = pgd_offset_k(kaddr);
389                                 pud_t *pudp = pud_offset(pgdp, kaddr);
390                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
391                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
392
393                                 paddr = pte_val(*ptep) & mask;
394                         }
395                         __flush_icache_page(paddr);
396                 }
397         }
398 }
399
400 void mmu_info(struct seq_file *m)
401 {
402         if (tlb_type == cheetah)
403                 seq_printf(m, "MMU Type\t: Cheetah\n");
404         else if (tlb_type == cheetah_plus)
405                 seq_printf(m, "MMU Type\t: Cheetah+\n");
406         else if (tlb_type == spitfire)
407                 seq_printf(m, "MMU Type\t: Spitfire\n");
408         else if (tlb_type == hypervisor)
409                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
410         else
411                 seq_printf(m, "MMU Type\t: ???\n");
412
413 #ifdef CONFIG_DEBUG_DCFLUSH
414         seq_printf(m, "DCPageFlushes\t: %d\n",
415                    atomic_read(&dcpage_flushes));
416 #ifdef CONFIG_SMP
417         seq_printf(m, "DCPageFlushesXC\t: %d\n",
418                    atomic_read(&dcpage_flushes_xcall));
419 #endif /* CONFIG_SMP */
420 #endif /* CONFIG_DEBUG_DCFLUSH */
421 }
422
423 struct linux_prom_translation prom_trans[512] __read_mostly;
424 unsigned int prom_trans_ents __read_mostly;
425
426 unsigned long kern_locked_tte_data;
427
428 /* The obp translations are saved based on 8k pagesize, since obp can
429  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
430  * HI_OBP_ADDRESS range are handled in ktlb.S.
431  */
432 static inline int in_obp_range(unsigned long vaddr)
433 {
434         return (vaddr >= LOW_OBP_ADDRESS &&
435                 vaddr < HI_OBP_ADDRESS);
436 }
437
438 static int cmp_ptrans(const void *a, const void *b)
439 {
440         const struct linux_prom_translation *x = a, *y = b;
441
442         if (x->virt > y->virt)
443                 return 1;
444         if (x->virt < y->virt)
445                 return -1;
446         return 0;
447 }
448
449 /* Read OBP translations property into 'prom_trans[]'.  */
450 static void __init read_obp_translations(void)
451 {
452         int n, node, ents, first, last, i;
453
454         node = prom_finddevice("/virtual-memory");
455         n = prom_getproplen(node, "translations");
456         if (unlikely(n == 0 || n == -1)) {
457                 prom_printf("prom_mappings: Couldn't get size.\n");
458                 prom_halt();
459         }
460         if (unlikely(n > sizeof(prom_trans))) {
461                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
462                 prom_halt();
463         }
464
465         if ((n = prom_getproperty(node, "translations",
466                                   (char *)&prom_trans[0],
467                                   sizeof(prom_trans))) == -1) {
468                 prom_printf("prom_mappings: Couldn't get property.\n");
469                 prom_halt();
470         }
471
472         n = n / sizeof(struct linux_prom_translation);
473
474         ents = n;
475
476         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
477              cmp_ptrans, NULL);
478
479         /* Now kick out all the non-OBP entries.  */
480         for (i = 0; i < ents; i++) {
481                 if (in_obp_range(prom_trans[i].virt))
482                         break;
483         }
484         first = i;
485         for (; i < ents; i++) {
486                 if (!in_obp_range(prom_trans[i].virt))
487                         break;
488         }
489         last = i;
490
491         for (i = 0; i < (last - first); i++) {
492                 struct linux_prom_translation *src = &prom_trans[i + first];
493                 struct linux_prom_translation *dest = &prom_trans[i];
494
495                 *dest = *src;
496         }
497         for (; i < ents; i++) {
498                 struct linux_prom_translation *dest = &prom_trans[i];
499                 dest->virt = dest->size = dest->data = 0x0UL;
500         }
501
502         prom_trans_ents = last - first;
503
504         if (tlb_type == spitfire) {
505                 /* Clear diag TTE bits. */
506                 for (i = 0; i < prom_trans_ents; i++)
507                         prom_trans[i].data &= ~0x0003fe0000000000UL;
508         }
509 }
510
511 static void __init hypervisor_tlb_lock(unsigned long vaddr,
512                                        unsigned long pte,
513                                        unsigned long mmu)
514 {
515         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
516
517         if (ret != 0) {
518                 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
519                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
520                 prom_halt();
521         }
522 }
523
524 static unsigned long kern_large_tte(unsigned long paddr);
525
526 static void __init remap_kernel(void)
527 {
528         unsigned long phys_page, tte_vaddr, tte_data;
529         int i, tlb_ent = sparc64_highest_locked_tlbent();
530
531         tte_vaddr = (unsigned long) KERNBASE;
532         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
533         tte_data = kern_large_tte(phys_page);
534
535         kern_locked_tte_data = tte_data;
536
537         /* Now lock us into the TLBs via Hypervisor or OBP. */
538         if (tlb_type == hypervisor) {
539                 for (i = 0; i < num_kernel_image_mappings; i++) {
540                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
541                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
542                         tte_vaddr += 0x400000;
543                         tte_data += 0x400000;
544                 }
545         } else {
546                 for (i = 0; i < num_kernel_image_mappings; i++) {
547                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
548                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
549                         tte_vaddr += 0x400000;
550                         tte_data += 0x400000;
551                 }
552                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
553         }
554         if (tlb_type == cheetah_plus) {
555                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
556                                             CTX_CHEETAH_PLUS_NUC);
557                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
558                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
559         }
560 }
561
562
563 static void __init inherit_prom_mappings(void)
564 {
565         /* Now fixup OBP's idea about where we really are mapped. */
566         printk("Remapping the kernel... ");
567         remap_kernel();
568         printk("done.\n");
569 }
570
571 void prom_world(int enter)
572 {
573         if (!enter)
574                 set_fs((mm_segment_t) { get_thread_current_ds() });
575
576         __asm__ __volatile__("flushw");
577 }
578
579 void __flush_dcache_range(unsigned long start, unsigned long end)
580 {
581         unsigned long va;
582
583         if (tlb_type == spitfire) {
584                 int n = 0;
585
586                 for (va = start; va < end; va += 32) {
587                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
588                         if (++n >= 512)
589                                 break;
590                 }
591         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
592                 start = __pa(start);
593                 end = __pa(end);
594                 for (va = start; va < end; va += 32)
595                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
596                                              "membar #Sync"
597                                              : /* no outputs */
598                                              : "r" (va),
599                                                "i" (ASI_DCACHE_INVALIDATE));
600         }
601 }
602
603 /* get_new_mmu_context() uses "cache + 1".  */
604 DEFINE_SPINLOCK(ctx_alloc_lock);
605 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
606 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
607 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
608 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
609
610 /* Caller does TLB context flushing on local CPU if necessary.
611  * The caller also ensures that CTX_VALID(mm->context) is false.
612  *
613  * We must be careful about boundary cases so that we never
614  * let the user have CTX 0 (nucleus) or we ever use a CTX
615  * version of zero (and thus NO_CONTEXT would not be caught
616  * by version mis-match tests in mmu_context.h).
617  *
618  * Always invoked with interrupts disabled.
619  */
620 void get_new_mmu_context(struct mm_struct *mm)
621 {
622         unsigned long ctx, new_ctx;
623         unsigned long orig_pgsz_bits;
624         unsigned long flags;
625         int new_version;
626
627         spin_lock_irqsave(&ctx_alloc_lock, flags);
628         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
629         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
630         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
631         new_version = 0;
632         if (new_ctx >= (1 << CTX_NR_BITS)) {
633                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
634                 if (new_ctx >= ctx) {
635                         int i;
636                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
637                                 CTX_FIRST_VERSION;
638                         if (new_ctx == 1)
639                                 new_ctx = CTX_FIRST_VERSION;
640
641                         /* Don't call memset, for 16 entries that's just
642                          * plain silly...
643                          */
644                         mmu_context_bmap[0] = 3;
645                         mmu_context_bmap[1] = 0;
646                         mmu_context_bmap[2] = 0;
647                         mmu_context_bmap[3] = 0;
648                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
649                                 mmu_context_bmap[i + 0] = 0;
650                                 mmu_context_bmap[i + 1] = 0;
651                                 mmu_context_bmap[i + 2] = 0;
652                                 mmu_context_bmap[i + 3] = 0;
653                         }
654                         new_version = 1;
655                         goto out;
656                 }
657         }
658         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
659         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
660 out:
661         tlb_context_cache = new_ctx;
662         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
663         spin_unlock_irqrestore(&ctx_alloc_lock, flags);
664
665         if (unlikely(new_version))
666                 smp_new_mmu_context_version();
667 }
668
669 static int numa_enabled = 1;
670 static int numa_debug;
671
672 static int __init early_numa(char *p)
673 {
674         if (!p)
675                 return 0;
676
677         if (strstr(p, "off"))
678                 numa_enabled = 0;
679
680         if (strstr(p, "debug"))
681                 numa_debug = 1;
682
683         return 0;
684 }
685 early_param("numa", early_numa);
686
687 #define numadbg(f, a...) \
688 do {    if (numa_debug) \
689                 printk(KERN_INFO f, ## a); \
690 } while (0)
691
692 static void __init find_ramdisk(unsigned long phys_base)
693 {
694 #ifdef CONFIG_BLK_DEV_INITRD
695         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
696                 unsigned long ramdisk_image;
697
698                 /* Older versions of the bootloader only supported a
699                  * 32-bit physical address for the ramdisk image
700                  * location, stored at sparc_ramdisk_image.  Newer
701                  * SILO versions set sparc_ramdisk_image to zero and
702                  * provide a full 64-bit physical address at
703                  * sparc_ramdisk_image64.
704                  */
705                 ramdisk_image = sparc_ramdisk_image;
706                 if (!ramdisk_image)
707                         ramdisk_image = sparc_ramdisk_image64;
708
709                 /* Another bootloader quirk.  The bootloader normalizes
710                  * the physical address to KERNBASE, so we have to
711                  * factor that back out and add in the lowest valid
712                  * physical page address to get the true physical address.
713                  */
714                 ramdisk_image -= KERNBASE;
715                 ramdisk_image += phys_base;
716
717                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
718                         ramdisk_image, sparc_ramdisk_size);
719
720                 initrd_start = ramdisk_image;
721                 initrd_end = ramdisk_image + sparc_ramdisk_size;
722
723                 lmb_reserve(initrd_start, sparc_ramdisk_size);
724
725                 initrd_start += PAGE_OFFSET;
726                 initrd_end += PAGE_OFFSET;
727         }
728 #endif
729 }
730
731 struct node_mem_mask {
732         unsigned long mask;
733         unsigned long val;
734         unsigned long bootmem_paddr;
735 };
736 static struct node_mem_mask node_masks[MAX_NUMNODES];
737 static int num_node_masks;
738
739 int numa_cpu_lookup_table[NR_CPUS];
740 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
741
742 #ifdef CONFIG_NEED_MULTIPLE_NODES
743
744 struct mdesc_mblock {
745         u64     base;
746         u64     size;
747         u64     offset; /* RA-to-PA */
748 };
749 static struct mdesc_mblock *mblocks;
750 static int num_mblocks;
751
752 static unsigned long ra_to_pa(unsigned long addr)
753 {
754         int i;
755
756         for (i = 0; i < num_mblocks; i++) {
757                 struct mdesc_mblock *m = &mblocks[i];
758
759                 if (addr >= m->base &&
760                     addr < (m->base + m->size)) {
761                         addr += m->offset;
762                         break;
763                 }
764         }
765         return addr;
766 }
767
768 static int find_node(unsigned long addr)
769 {
770         int i;
771
772         addr = ra_to_pa(addr);
773         for (i = 0; i < num_node_masks; i++) {
774                 struct node_mem_mask *p = &node_masks[i];
775
776                 if ((addr & p->mask) == p->val)
777                         return i;
778         }
779         return -1;
780 }
781
782 static unsigned long long nid_range(unsigned long long start,
783                                     unsigned long long end, int *nid)
784 {
785         *nid = find_node(start);
786         start += PAGE_SIZE;
787         while (start < end) {
788                 int n = find_node(start);
789
790                 if (n != *nid)
791                         break;
792                 start += PAGE_SIZE;
793         }
794
795         if (start > end)
796                 start = end;
797
798         return start;
799 }
800 #else
801 static unsigned long long nid_range(unsigned long long start,
802                                     unsigned long long end, int *nid)
803 {
804         *nid = 0;
805         return end;
806 }
807 #endif
808
809 /* This must be invoked after performing all of the necessary
810  * add_active_range() calls for 'nid'.  We need to be able to get
811  * correct data from get_pfn_range_for_nid().
812  */
813 static void __init allocate_node_data(int nid)
814 {
815         unsigned long paddr, num_pages, start_pfn, end_pfn;
816         struct pglist_data *p;
817
818 #ifdef CONFIG_NEED_MULTIPLE_NODES
819         paddr = lmb_alloc_nid(sizeof(struct pglist_data),
820                               SMP_CACHE_BYTES, nid, nid_range);
821         if (!paddr) {
822                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
823                 prom_halt();
824         }
825         NODE_DATA(nid) = __va(paddr);
826         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
827
828         NODE_DATA(nid)->bdata = &bootmem_node_data[nid];
829 #endif
830
831         p = NODE_DATA(nid);
832
833         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
834         p->node_start_pfn = start_pfn;
835         p->node_spanned_pages = end_pfn - start_pfn;
836
837         if (p->node_spanned_pages) {
838                 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
839
840                 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
841                                       nid_range);
842                 if (!paddr) {
843                         prom_printf("Cannot allocate bootmap for nid[%d]\n",
844                                   nid);
845                         prom_halt();
846                 }
847                 node_masks[nid].bootmem_paddr = paddr;
848         }
849 }
850
851 static void init_node_masks_nonnuma(void)
852 {
853         int i;
854
855         numadbg("Initializing tables for non-numa.\n");
856
857         node_masks[0].mask = node_masks[0].val = 0;
858         num_node_masks = 1;
859
860         for (i = 0; i < NR_CPUS; i++)
861                 numa_cpu_lookup_table[i] = 0;
862
863         numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
864 }
865
866 #ifdef CONFIG_NEED_MULTIPLE_NODES
867 struct pglist_data *node_data[MAX_NUMNODES];
868
869 EXPORT_SYMBOL(numa_cpu_lookup_table);
870 EXPORT_SYMBOL(numa_cpumask_lookup_table);
871 EXPORT_SYMBOL(node_data);
872
873 struct mdesc_mlgroup {
874         u64     node;
875         u64     latency;
876         u64     match;
877         u64     mask;
878 };
879 static struct mdesc_mlgroup *mlgroups;
880 static int num_mlgroups;
881
882 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
883                                    u32 cfg_handle)
884 {
885         u64 arc;
886
887         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
888                 u64 target = mdesc_arc_target(md, arc);
889                 const u64 *val;
890
891                 val = mdesc_get_property(md, target,
892                                          "cfg-handle", NULL);
893                 if (val && *val == cfg_handle)
894                         return 0;
895         }
896         return -ENODEV;
897 }
898
899 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
900                                     u32 cfg_handle)
901 {
902         u64 arc, candidate, best_latency = ~(u64)0;
903
904         candidate = MDESC_NODE_NULL;
905         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
906                 u64 target = mdesc_arc_target(md, arc);
907                 const char *name = mdesc_node_name(md, target);
908                 const u64 *val;
909
910                 if (strcmp(name, "pio-latency-group"))
911                         continue;
912
913                 val = mdesc_get_property(md, target, "latency", NULL);
914                 if (!val)
915                         continue;
916
917                 if (*val < best_latency) {
918                         candidate = target;
919                         best_latency = *val;
920                 }
921         }
922
923         if (candidate == MDESC_NODE_NULL)
924                 return -ENODEV;
925
926         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
927 }
928
929 int of_node_to_nid(struct device_node *dp)
930 {
931         const struct linux_prom64_registers *regs;
932         struct mdesc_handle *md;
933         u32 cfg_handle;
934         int count, nid;
935         u64 grp;
936
937         /* This is the right thing to do on currently supported
938          * SUN4U NUMA platforms as well, as the PCI controller does
939          * not sit behind any particular memory controller.
940          */
941         if (!mlgroups)
942                 return -1;
943
944         regs = of_get_property(dp, "reg", NULL);
945         if (!regs)
946                 return -1;
947
948         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
949
950         md = mdesc_grab();
951
952         count = 0;
953         nid = -1;
954         mdesc_for_each_node_by_name(md, grp, "group") {
955                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
956                         nid = count;
957                         break;
958                 }
959                 count++;
960         }
961
962         mdesc_release(md);
963
964         return nid;
965 }
966
967 static void add_node_ranges(void)
968 {
969         int i;
970
971         for (i = 0; i < lmb.memory.cnt; i++) {
972                 unsigned long size = lmb_size_bytes(&lmb.memory, i);
973                 unsigned long start, end;
974
975                 start = lmb.memory.region[i].base;
976                 end = start + size;
977                 while (start < end) {
978                         unsigned long this_end;
979                         int nid;
980
981                         this_end = nid_range(start, end, &nid);
982
983                         numadbg("Adding active range nid[%d] "
984                                 "start[%lx] end[%lx]\n",
985                                 nid, start, this_end);
986
987                         add_active_range(nid,
988                                          start >> PAGE_SHIFT,
989                                          this_end >> PAGE_SHIFT);
990
991                         start = this_end;
992                 }
993         }
994 }
995
996 static int __init grab_mlgroups(struct mdesc_handle *md)
997 {
998         unsigned long paddr;
999         int count = 0;
1000         u64 node;
1001
1002         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1003                 count++;
1004         if (!count)
1005                 return -ENOENT;
1006
1007         paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1008                           SMP_CACHE_BYTES);
1009         if (!paddr)
1010                 return -ENOMEM;
1011
1012         mlgroups = __va(paddr);
1013         num_mlgroups = count;
1014
1015         count = 0;
1016         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1017                 struct mdesc_mlgroup *m = &mlgroups[count++];
1018                 const u64 *val;
1019
1020                 m->node = node;
1021
1022                 val = mdesc_get_property(md, node, "latency", NULL);
1023                 m->latency = *val;
1024                 val = mdesc_get_property(md, node, "address-match", NULL);
1025                 m->match = *val;
1026                 val = mdesc_get_property(md, node, "address-mask", NULL);
1027                 m->mask = *val;
1028
1029                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1030                         "match[%llx] mask[%llx]\n",
1031                         count - 1, m->node, m->latency, m->match, m->mask);
1032         }
1033
1034         return 0;
1035 }
1036
1037 static int __init grab_mblocks(struct mdesc_handle *md)
1038 {
1039         unsigned long paddr;
1040         int count = 0;
1041         u64 node;
1042
1043         mdesc_for_each_node_by_name(md, node, "mblock")
1044                 count++;
1045         if (!count)
1046                 return -ENOENT;
1047
1048         paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1049                           SMP_CACHE_BYTES);
1050         if (!paddr)
1051                 return -ENOMEM;
1052
1053         mblocks = __va(paddr);
1054         num_mblocks = count;
1055
1056         count = 0;
1057         mdesc_for_each_node_by_name(md, node, "mblock") {
1058                 struct mdesc_mblock *m = &mblocks[count++];
1059                 const u64 *val;
1060
1061                 val = mdesc_get_property(md, node, "base", NULL);
1062                 m->base = *val;
1063                 val = mdesc_get_property(md, node, "size", NULL);
1064                 m->size = *val;
1065                 val = mdesc_get_property(md, node,
1066                                          "address-congruence-offset", NULL);
1067                 m->offset = *val;
1068
1069                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1070                         count - 1, m->base, m->size, m->offset);
1071         }
1072
1073         return 0;
1074 }
1075
1076 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1077                                                u64 grp, cpumask_t *mask)
1078 {
1079         u64 arc;
1080
1081         cpus_clear(*mask);
1082
1083         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1084                 u64 target = mdesc_arc_target(md, arc);
1085                 const char *name = mdesc_node_name(md, target);
1086                 const u64 *id;
1087
1088                 if (strcmp(name, "cpu"))
1089                         continue;
1090                 id = mdesc_get_property(md, target, "id", NULL);
1091                 if (*id < NR_CPUS)
1092                         cpu_set(*id, *mask);
1093         }
1094 }
1095
1096 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1097 {
1098         int i;
1099
1100         for (i = 0; i < num_mlgroups; i++) {
1101                 struct mdesc_mlgroup *m = &mlgroups[i];
1102                 if (m->node == node)
1103                         return m;
1104         }
1105         return NULL;
1106 }
1107
1108 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1109                                       int index)
1110 {
1111         struct mdesc_mlgroup *candidate = NULL;
1112         u64 arc, best_latency = ~(u64)0;
1113         struct node_mem_mask *n;
1114
1115         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1116                 u64 target = mdesc_arc_target(md, arc);
1117                 struct mdesc_mlgroup *m = find_mlgroup(target);
1118                 if (!m)
1119                         continue;
1120                 if (m->latency < best_latency) {
1121                         candidate = m;
1122                         best_latency = m->latency;
1123                 }
1124         }
1125         if (!candidate)
1126                 return -ENOENT;
1127
1128         if (num_node_masks != index) {
1129                 printk(KERN_ERR "Inconsistent NUMA state, "
1130                        "index[%d] != num_node_masks[%d]\n",
1131                        index, num_node_masks);
1132                 return -EINVAL;
1133         }
1134
1135         n = &node_masks[num_node_masks++];
1136
1137         n->mask = candidate->mask;
1138         n->val = candidate->match;
1139
1140         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1141                 index, n->mask, n->val, candidate->latency);
1142
1143         return 0;
1144 }
1145
1146 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1147                                          int index)
1148 {
1149         cpumask_t mask;
1150         int cpu;
1151
1152         numa_parse_mdesc_group_cpus(md, grp, &mask);
1153
1154         for_each_cpu_mask(cpu, mask)
1155                 numa_cpu_lookup_table[cpu] = index;
1156         numa_cpumask_lookup_table[index] = mask;
1157
1158         if (numa_debug) {
1159                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1160                 for_each_cpu_mask(cpu, mask)
1161                         printk("%d ", cpu);
1162                 printk("]\n");
1163         }
1164
1165         return numa_attach_mlgroup(md, grp, index);
1166 }
1167
1168 static int __init numa_parse_mdesc(void)
1169 {
1170         struct mdesc_handle *md = mdesc_grab();
1171         int i, err, count;
1172         u64 node;
1173
1174         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1175         if (node == MDESC_NODE_NULL) {
1176                 mdesc_release(md);
1177                 return -ENOENT;
1178         }
1179
1180         err = grab_mblocks(md);
1181         if (err < 0)
1182                 goto out;
1183
1184         err = grab_mlgroups(md);
1185         if (err < 0)
1186                 goto out;
1187
1188         count = 0;
1189         mdesc_for_each_node_by_name(md, node, "group") {
1190                 err = numa_parse_mdesc_group(md, node, count);
1191                 if (err < 0)
1192                         break;
1193                 count++;
1194         }
1195
1196         add_node_ranges();
1197
1198         for (i = 0; i < num_node_masks; i++) {
1199                 allocate_node_data(i);
1200                 node_set_online(i);
1201         }
1202
1203         err = 0;
1204 out:
1205         mdesc_release(md);
1206         return err;
1207 }
1208
1209 static int __init numa_parse_jbus(void)
1210 {
1211         unsigned long cpu, index;
1212
1213         /* NUMA node id is encoded in bits 36 and higher, and there is
1214          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1215          */
1216         index = 0;
1217         for_each_present_cpu(cpu) {
1218                 numa_cpu_lookup_table[cpu] = index;
1219                 numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu);
1220                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1221                 node_masks[index].val = cpu << 36UL;
1222
1223                 index++;
1224         }
1225         num_node_masks = index;
1226
1227         add_node_ranges();
1228
1229         for (index = 0; index < num_node_masks; index++) {
1230                 allocate_node_data(index);
1231                 node_set_online(index);
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int __init numa_parse_sun4u(void)
1238 {
1239         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1240                 unsigned long ver;
1241
1242                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1243                 if ((ver >> 32UL) == __JALAPENO_ID ||
1244                     (ver >> 32UL) == __SERRANO_ID)
1245                         return numa_parse_jbus();
1246         }
1247         return -1;
1248 }
1249
1250 static int __init bootmem_init_numa(void)
1251 {
1252         int err = -1;
1253
1254         numadbg("bootmem_init_numa()\n");
1255
1256         if (numa_enabled) {
1257                 if (tlb_type == hypervisor)
1258                         err = numa_parse_mdesc();
1259                 else
1260                         err = numa_parse_sun4u();
1261         }
1262         return err;
1263 }
1264
1265 #else
1266
1267 static int bootmem_init_numa(void)
1268 {
1269         return -1;
1270 }
1271
1272 #endif
1273
1274 static void __init bootmem_init_nonnuma(void)
1275 {
1276         unsigned long top_of_ram = lmb_end_of_DRAM();
1277         unsigned long total_ram = lmb_phys_mem_size();
1278         unsigned int i;
1279
1280         numadbg("bootmem_init_nonnuma()\n");
1281
1282         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1283                top_of_ram, total_ram);
1284         printk(KERN_INFO "Memory hole size: %ldMB\n",
1285                (top_of_ram - total_ram) >> 20);
1286
1287         init_node_masks_nonnuma();
1288
1289         for (i = 0; i < lmb.memory.cnt; i++) {
1290                 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1291                 unsigned long start_pfn, end_pfn;
1292
1293                 if (!size)
1294                         continue;
1295
1296                 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1297                 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1298                 add_active_range(0, start_pfn, end_pfn);
1299         }
1300
1301         allocate_node_data(0);
1302
1303         node_set_online(0);
1304 }
1305
1306 static void __init reserve_range_in_node(int nid, unsigned long start,
1307                                          unsigned long end)
1308 {
1309         numadbg("    reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1310                 nid, start, end);
1311         while (start < end) {
1312                 unsigned long this_end;
1313                 int n;
1314
1315                 this_end = nid_range(start, end, &n);
1316                 if (n == nid) {
1317                         numadbg("      MATCH reserving range [%lx:%lx]\n",
1318                                 start, this_end);
1319                         reserve_bootmem_node(NODE_DATA(nid), start,
1320                                              (this_end - start), BOOTMEM_DEFAULT);
1321                 } else
1322                         numadbg("      NO MATCH, advancing start to %lx\n",
1323                                 this_end);
1324
1325                 start = this_end;
1326         }
1327 }
1328
1329 static void __init trim_reserved_in_node(int nid)
1330 {
1331         int i;
1332
1333         numadbg("  trim_reserved_in_node(%d)\n", nid);
1334
1335         for (i = 0; i < lmb.reserved.cnt; i++) {
1336                 unsigned long start = lmb.reserved.region[i].base;
1337                 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1338                 unsigned long end = start + size;
1339
1340                 reserve_range_in_node(nid, start, end);
1341         }
1342 }
1343
1344 static void __init bootmem_init_one_node(int nid)
1345 {
1346         struct pglist_data *p;
1347
1348         numadbg("bootmem_init_one_node(%d)\n", nid);
1349
1350         p = NODE_DATA(nid);
1351
1352         if (p->node_spanned_pages) {
1353                 unsigned long paddr = node_masks[nid].bootmem_paddr;
1354                 unsigned long end_pfn;
1355
1356                 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1357
1358                 numadbg("  init_bootmem_node(%d, %lx, %lx, %lx)\n",
1359                         nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1360
1361                 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1362                                   p->node_start_pfn, end_pfn);
1363
1364                 numadbg("  free_bootmem_with_active_regions(%d, %lx)\n",
1365                         nid, end_pfn);
1366                 free_bootmem_with_active_regions(nid, end_pfn);
1367
1368                 trim_reserved_in_node(nid);
1369
1370                 numadbg("  sparse_memory_present_with_active_regions(%d)\n",
1371                         nid);
1372                 sparse_memory_present_with_active_regions(nid);
1373         }
1374 }
1375
1376 static unsigned long __init bootmem_init(unsigned long phys_base)
1377 {
1378         unsigned long end_pfn;
1379         int nid;
1380
1381         end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1382         max_pfn = max_low_pfn = end_pfn;
1383         min_low_pfn = (phys_base >> PAGE_SHIFT);
1384
1385         if (bootmem_init_numa() < 0)
1386                 bootmem_init_nonnuma();
1387
1388         /* XXX cpu notifier XXX */
1389
1390         for_each_online_node(nid)
1391                 bootmem_init_one_node(nid);
1392
1393         sparse_init();
1394
1395         return end_pfn;
1396 }
1397
1398 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1399 static int pall_ents __initdata;
1400
1401 #ifdef CONFIG_DEBUG_PAGEALLOC
1402 static unsigned long __ref kernel_map_range(unsigned long pstart,
1403                                             unsigned long pend, pgprot_t prot)
1404 {
1405         unsigned long vstart = PAGE_OFFSET + pstart;
1406         unsigned long vend = PAGE_OFFSET + pend;
1407         unsigned long alloc_bytes = 0UL;
1408
1409         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1410                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1411                             vstart, vend);
1412                 prom_halt();
1413         }
1414
1415         while (vstart < vend) {
1416                 unsigned long this_end, paddr = __pa(vstart);
1417                 pgd_t *pgd = pgd_offset_k(vstart);
1418                 pud_t *pud;
1419                 pmd_t *pmd;
1420                 pte_t *pte;
1421
1422                 pud = pud_offset(pgd, vstart);
1423                 if (pud_none(*pud)) {
1424                         pmd_t *new;
1425
1426                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1427                         alloc_bytes += PAGE_SIZE;
1428                         pud_populate(&init_mm, pud, new);
1429                 }
1430
1431                 pmd = pmd_offset(pud, vstart);
1432                 if (!pmd_present(*pmd)) {
1433                         pte_t *new;
1434
1435                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1436                         alloc_bytes += PAGE_SIZE;
1437                         pmd_populate_kernel(&init_mm, pmd, new);
1438                 }
1439
1440                 pte = pte_offset_kernel(pmd, vstart);
1441                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1442                 if (this_end > vend)
1443                         this_end = vend;
1444
1445                 while (vstart < this_end) {
1446                         pte_val(*pte) = (paddr | pgprot_val(prot));
1447
1448                         vstart += PAGE_SIZE;
1449                         paddr += PAGE_SIZE;
1450                         pte++;
1451                 }
1452         }
1453
1454         return alloc_bytes;
1455 }
1456
1457 extern unsigned int kvmap_linear_patch[1];
1458 #endif /* CONFIG_DEBUG_PAGEALLOC */
1459
1460 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1461 {
1462         const unsigned long shift_256MB = 28;
1463         const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1464         const unsigned long size_256MB = (1UL << shift_256MB);
1465
1466         while (start < end) {
1467                 long remains;
1468
1469                 remains = end - start;
1470                 if (remains < size_256MB)
1471                         break;
1472
1473                 if (start & mask_256MB) {
1474                         start = (start + size_256MB) & ~mask_256MB;
1475                         continue;
1476                 }
1477
1478                 while (remains >= size_256MB) {
1479                         unsigned long index = start >> shift_256MB;
1480
1481                         __set_bit(index, kpte_linear_bitmap);
1482
1483                         start += size_256MB;
1484                         remains -= size_256MB;
1485                 }
1486         }
1487 }
1488
1489 static void __init init_kpte_bitmap(void)
1490 {
1491         unsigned long i;
1492
1493         for (i = 0; i < pall_ents; i++) {
1494                 unsigned long phys_start, phys_end;
1495
1496                 phys_start = pall[i].phys_addr;
1497                 phys_end = phys_start + pall[i].reg_size;
1498
1499                 mark_kpte_bitmap(phys_start, phys_end);
1500         }
1501 }
1502
1503 static void __init kernel_physical_mapping_init(void)
1504 {
1505 #ifdef CONFIG_DEBUG_PAGEALLOC
1506         unsigned long i, mem_alloced = 0UL;
1507
1508         for (i = 0; i < pall_ents; i++) {
1509                 unsigned long phys_start, phys_end;
1510
1511                 phys_start = pall[i].phys_addr;
1512                 phys_end = phys_start + pall[i].reg_size;
1513
1514                 mem_alloced += kernel_map_range(phys_start, phys_end,
1515                                                 PAGE_KERNEL);
1516         }
1517
1518         printk("Allocated %ld bytes for kernel page tables.\n",
1519                mem_alloced);
1520
1521         kvmap_linear_patch[0] = 0x01000000; /* nop */
1522         flushi(&kvmap_linear_patch[0]);
1523
1524         __flush_tlb_all();
1525 #endif
1526 }
1527
1528 #ifdef CONFIG_DEBUG_PAGEALLOC
1529 void kernel_map_pages(struct page *page, int numpages, int enable)
1530 {
1531         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1532         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1533
1534         kernel_map_range(phys_start, phys_end,
1535                          (enable ? PAGE_KERNEL : __pgprot(0)));
1536
1537         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1538                                PAGE_OFFSET + phys_end);
1539
1540         /* we should perform an IPI and flush all tlbs,
1541          * but that can deadlock->flush only current cpu.
1542          */
1543         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1544                                  PAGE_OFFSET + phys_end);
1545 }
1546 #endif
1547
1548 unsigned long __init find_ecache_flush_span(unsigned long size)
1549 {
1550         int i;
1551
1552         for (i = 0; i < pavail_ents; i++) {
1553                 if (pavail[i].reg_size >= size)
1554                         return pavail[i].phys_addr;
1555         }
1556
1557         return ~0UL;
1558 }
1559
1560 static void __init tsb_phys_patch(void)
1561 {
1562         struct tsb_ldquad_phys_patch_entry *pquad;
1563         struct tsb_phys_patch_entry *p;
1564
1565         pquad = &__tsb_ldquad_phys_patch;
1566         while (pquad < &__tsb_ldquad_phys_patch_end) {
1567                 unsigned long addr = pquad->addr;
1568
1569                 if (tlb_type == hypervisor)
1570                         *(unsigned int *) addr = pquad->sun4v_insn;
1571                 else
1572                         *(unsigned int *) addr = pquad->sun4u_insn;
1573                 wmb();
1574                 __asm__ __volatile__("flush     %0"
1575                                      : /* no outputs */
1576                                      : "r" (addr));
1577
1578                 pquad++;
1579         }
1580
1581         p = &__tsb_phys_patch;
1582         while (p < &__tsb_phys_patch_end) {
1583                 unsigned long addr = p->addr;
1584
1585                 *(unsigned int *) addr = p->insn;
1586                 wmb();
1587                 __asm__ __volatile__("flush     %0"
1588                                      : /* no outputs */
1589                                      : "r" (addr));
1590
1591                 p++;
1592         }
1593 }
1594
1595 /* Don't mark as init, we give this to the Hypervisor.  */
1596 #ifndef CONFIG_DEBUG_PAGEALLOC
1597 #define NUM_KTSB_DESCR  2
1598 #else
1599 #define NUM_KTSB_DESCR  1
1600 #endif
1601 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1602 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1603
1604 static void __init sun4v_ktsb_init(void)
1605 {
1606         unsigned long ktsb_pa;
1607
1608         /* First KTSB for PAGE_SIZE mappings.  */
1609         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1610
1611         switch (PAGE_SIZE) {
1612         case 8 * 1024:
1613         default:
1614                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1615                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1616                 break;
1617
1618         case 64 * 1024:
1619                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1620                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1621                 break;
1622
1623         case 512 * 1024:
1624                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1625                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1626                 break;
1627
1628         case 4 * 1024 * 1024:
1629                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1630                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1631                 break;
1632         };
1633
1634         ktsb_descr[0].assoc = 1;
1635         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1636         ktsb_descr[0].ctx_idx = 0;
1637         ktsb_descr[0].tsb_base = ktsb_pa;
1638         ktsb_descr[0].resv = 0;
1639
1640 #ifndef CONFIG_DEBUG_PAGEALLOC
1641         /* Second KTSB for 4MB/256MB mappings.  */
1642         ktsb_pa = (kern_base +
1643                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1644
1645         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1646         ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1647                                    HV_PGSZ_MASK_256MB);
1648         ktsb_descr[1].assoc = 1;
1649         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1650         ktsb_descr[1].ctx_idx = 0;
1651         ktsb_descr[1].tsb_base = ktsb_pa;
1652         ktsb_descr[1].resv = 0;
1653 #endif
1654 }
1655
1656 void __cpuinit sun4v_ktsb_register(void)
1657 {
1658         unsigned long pa, ret;
1659
1660         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1661
1662         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1663         if (ret != 0) {
1664                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1665                             "errors with %lx\n", pa, ret);
1666                 prom_halt();
1667         }
1668 }
1669
1670 /* paging_init() sets up the page tables */
1671
1672 static unsigned long last_valid_pfn;
1673 pgd_t swapper_pg_dir[2048];
1674
1675 static void sun4u_pgprot_init(void);
1676 static void sun4v_pgprot_init(void);
1677
1678 /* Dummy function */
1679 void __init setup_per_cpu_areas(void)
1680 {
1681 }
1682
1683 void __init paging_init(void)
1684 {
1685         unsigned long end_pfn, shift, phys_base;
1686         unsigned long real_end, i;
1687
1688         /* These build time checkes make sure that the dcache_dirty_cpu()
1689          * page->flags usage will work.
1690          *
1691          * When a page gets marked as dcache-dirty, we store the
1692          * cpu number starting at bit 32 in the page->flags.  Also,
1693          * functions like clear_dcache_dirty_cpu use the cpu mask
1694          * in 13-bit signed-immediate instruction fields.
1695          */
1696
1697         /*
1698          * Page flags must not reach into upper 32 bits that are used
1699          * for the cpu number
1700          */
1701         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1702
1703         /*
1704          * The bit fields placed in the high range must not reach below
1705          * the 32 bit boundary. Otherwise we cannot place the cpu field
1706          * at the 32 bit boundary.
1707          */
1708         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1709                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1710
1711         BUILD_BUG_ON(NR_CPUS > 4096);
1712
1713         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1714         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1715
1716         /* Invalidate both kernel TSBs.  */
1717         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1718 #ifndef CONFIG_DEBUG_PAGEALLOC
1719         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1720 #endif
1721
1722         if (tlb_type == hypervisor)
1723                 sun4v_pgprot_init();
1724         else
1725                 sun4u_pgprot_init();
1726
1727         if (tlb_type == cheetah_plus ||
1728             tlb_type == hypervisor)
1729                 tsb_phys_patch();
1730
1731         if (tlb_type == hypervisor) {
1732                 sun4v_patch_tlb_handlers();
1733                 sun4v_ktsb_init();
1734         }
1735
1736         lmb_init();
1737
1738         /* Find available physical memory...
1739          *
1740          * Read it twice in order to work around a bug in openfirmware.
1741          * The call to grab this table itself can cause openfirmware to
1742          * allocate memory, which in turn can take away some space from
1743          * the list of available memory.  Reading it twice makes sure
1744          * we really do get the final value.
1745          */
1746         read_obp_translations();
1747         read_obp_memory("reg", &pall[0], &pall_ents);
1748         read_obp_memory("available", &pavail[0], &pavail_ents);
1749         read_obp_memory("available", &pavail[0], &pavail_ents);
1750
1751         phys_base = 0xffffffffffffffffUL;
1752         for (i = 0; i < pavail_ents; i++) {
1753                 phys_base = min(phys_base, pavail[i].phys_addr);
1754                 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1755         }
1756
1757         lmb_reserve(kern_base, kern_size);
1758
1759         find_ramdisk(phys_base);
1760
1761         lmb_enforce_memory_limit(cmdline_memory_size);
1762
1763         lmb_analyze();
1764         lmb_dump_all();
1765
1766         set_bit(0, mmu_context_bmap);
1767
1768         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1769
1770         real_end = (unsigned long)_end;
1771         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1772         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1773                num_kernel_image_mappings);
1774
1775         /* Set kernel pgd to upper alias so physical page computations
1776          * work.
1777          */
1778         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1779         
1780         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1781
1782         /* Now can init the kernel/bad page tables. */
1783         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1784                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1785         
1786         inherit_prom_mappings();
1787         
1788         init_kpte_bitmap();
1789
1790         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1791         setup_tba();
1792
1793         __flush_tlb_all();
1794
1795         if (tlb_type == hypervisor)
1796                 sun4v_ktsb_register();
1797
1798         /* We must setup the per-cpu areas before we pull in the
1799          * PROM and the MDESC.  The code there fills in cpu and
1800          * other information into per-cpu data structures.
1801          */
1802         real_setup_per_cpu_areas();
1803
1804         prom_build_devicetree();
1805
1806         if (tlb_type == hypervisor)
1807                 sun4v_mdesc_init();
1808
1809         /* Once the OF device tree and MDESC have been setup, we know
1810          * the list of possible cpus.  Therefore we can allocate the
1811          * IRQ stacks.
1812          */
1813         for_each_possible_cpu(i) {
1814                 /* XXX Use node local allocations... XXX */
1815                 softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1816                 hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE));
1817         }
1818
1819         /* Setup bootmem... */
1820         last_valid_pfn = end_pfn = bootmem_init(phys_base);
1821
1822 #ifndef CONFIG_NEED_MULTIPLE_NODES
1823         max_mapnr = last_valid_pfn;
1824 #endif
1825         kernel_physical_mapping_init();
1826
1827         {
1828                 unsigned long max_zone_pfns[MAX_NR_ZONES];
1829
1830                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1831
1832                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1833
1834                 free_area_init_nodes(max_zone_pfns);
1835         }
1836
1837         printk("Booting Linux...\n");
1838 }
1839
1840 int __init page_in_phys_avail(unsigned long paddr)
1841 {
1842         int i;
1843
1844         paddr &= PAGE_MASK;
1845
1846         for (i = 0; i < pavail_ents; i++) {
1847                 unsigned long start, end;
1848
1849                 start = pavail[i].phys_addr;
1850                 end = start + pavail[i].reg_size;
1851
1852                 if (paddr >= start && paddr < end)
1853                         return 1;
1854         }
1855         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1856                 return 1;
1857 #ifdef CONFIG_BLK_DEV_INITRD
1858         if (paddr >= __pa(initrd_start) &&
1859             paddr < __pa(PAGE_ALIGN(initrd_end)))
1860                 return 1;
1861 #endif
1862
1863         return 0;
1864 }
1865
1866 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1867 static int pavail_rescan_ents __initdata;
1868
1869 /* Certain OBP calls, such as fetching "available" properties, can
1870  * claim physical memory.  So, along with initializing the valid
1871  * address bitmap, what we do here is refetch the physical available
1872  * memory list again, and make sure it provides at least as much
1873  * memory as 'pavail' does.
1874  */
1875 static void __init setup_valid_addr_bitmap_from_pavail(void)
1876 {
1877         int i;
1878
1879         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1880
1881         for (i = 0; i < pavail_ents; i++) {
1882                 unsigned long old_start, old_end;
1883
1884                 old_start = pavail[i].phys_addr;
1885                 old_end = old_start + pavail[i].reg_size;
1886                 while (old_start < old_end) {
1887                         int n;
1888
1889                         for (n = 0; n < pavail_rescan_ents; n++) {
1890                                 unsigned long new_start, new_end;
1891
1892                                 new_start = pavail_rescan[n].phys_addr;
1893                                 new_end = new_start +
1894                                         pavail_rescan[n].reg_size;
1895
1896                                 if (new_start <= old_start &&
1897                                     new_end >= (old_start + PAGE_SIZE)) {
1898                                         set_bit(old_start >> 22,
1899                                                 sparc64_valid_addr_bitmap);
1900                                         goto do_next_page;
1901                                 }
1902                         }
1903
1904                         prom_printf("mem_init: Lost memory in pavail\n");
1905                         prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1906                                     pavail[i].phys_addr,
1907                                     pavail[i].reg_size);
1908                         prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1909                                     pavail_rescan[i].phys_addr,
1910                                     pavail_rescan[i].reg_size);
1911                         prom_printf("mem_init: Cannot continue, aborting.\n");
1912                         prom_halt();
1913
1914                 do_next_page:
1915                         old_start += PAGE_SIZE;
1916                 }
1917         }
1918 }
1919
1920 void __init mem_init(void)
1921 {
1922         unsigned long codepages, datapages, initpages;
1923         unsigned long addr, last;
1924         int i;
1925
1926         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1927         i += 1;
1928         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1929         if (sparc64_valid_addr_bitmap == NULL) {
1930                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1931                 prom_halt();
1932         }
1933         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1934
1935         addr = PAGE_OFFSET + kern_base;
1936         last = PAGE_ALIGN(kern_size) + addr;
1937         while (addr < last) {
1938                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1939                 addr += PAGE_SIZE;
1940         }
1941
1942         setup_valid_addr_bitmap_from_pavail();
1943
1944         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1945
1946 #ifdef CONFIG_NEED_MULTIPLE_NODES
1947         for_each_online_node(i) {
1948                 if (NODE_DATA(i)->node_spanned_pages != 0) {
1949                         totalram_pages +=
1950                                 free_all_bootmem_node(NODE_DATA(i));
1951                 }
1952         }
1953 #else
1954         totalram_pages = free_all_bootmem();
1955 #endif
1956
1957         /* We subtract one to account for the mem_map_zero page
1958          * allocated below.
1959          */
1960         totalram_pages -= 1;
1961         num_physpages = totalram_pages;
1962
1963         /*
1964          * Set up the zero page, mark it reserved, so that page count
1965          * is not manipulated when freeing the page from user ptes.
1966          */
1967         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1968         if (mem_map_zero == NULL) {
1969                 prom_printf("paging_init: Cannot alloc zero page.\n");
1970                 prom_halt();
1971         }
1972         SetPageReserved(mem_map_zero);
1973
1974         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1975         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1976         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1977         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1978         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1979         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1980
1981         printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1982                nr_free_pages() << (PAGE_SHIFT-10),
1983                codepages << (PAGE_SHIFT-10),
1984                datapages << (PAGE_SHIFT-10), 
1985                initpages << (PAGE_SHIFT-10), 
1986                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1987
1988         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1989                 cheetah_ecache_flush_init();
1990 }
1991
1992 void free_initmem(void)
1993 {
1994         unsigned long addr, initend;
1995         int do_free = 1;
1996
1997         /* If the physical memory maps were trimmed by kernel command
1998          * line options, don't even try freeing this initmem stuff up.
1999          * The kernel image could have been in the trimmed out region
2000          * and if so the freeing below will free invalid page structs.
2001          */
2002         if (cmdline_memory_size)
2003                 do_free = 0;
2004
2005         /*
2006          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2007          */
2008         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2009         initend = (unsigned long)(__init_end) & PAGE_MASK;
2010         for (; addr < initend; addr += PAGE_SIZE) {
2011                 unsigned long page;
2012                 struct page *p;
2013
2014                 page = (addr +
2015                         ((unsigned long) __va(kern_base)) -
2016                         ((unsigned long) KERNBASE));
2017                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2018
2019                 if (do_free) {
2020                         p = virt_to_page(page);
2021
2022                         ClearPageReserved(p);
2023                         init_page_count(p);
2024                         __free_page(p);
2025                         num_physpages++;
2026                         totalram_pages++;
2027                 }
2028         }
2029 }
2030
2031 #ifdef CONFIG_BLK_DEV_INITRD
2032 void free_initrd_mem(unsigned long start, unsigned long end)
2033 {
2034         if (start < end)
2035                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2036         for (; start < end; start += PAGE_SIZE) {
2037                 struct page *p = virt_to_page(start);
2038
2039                 ClearPageReserved(p);
2040                 init_page_count(p);
2041                 __free_page(p);
2042                 num_physpages++;
2043                 totalram_pages++;
2044         }
2045 }
2046 #endif
2047
2048 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2049 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2050 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2051 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2052 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2053 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2054
2055 pgprot_t PAGE_KERNEL __read_mostly;
2056 EXPORT_SYMBOL(PAGE_KERNEL);
2057
2058 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2059 pgprot_t PAGE_COPY __read_mostly;
2060
2061 pgprot_t PAGE_SHARED __read_mostly;
2062 EXPORT_SYMBOL(PAGE_SHARED);
2063
2064 unsigned long pg_iobits __read_mostly;
2065
2066 unsigned long _PAGE_IE __read_mostly;
2067 EXPORT_SYMBOL(_PAGE_IE);
2068
2069 unsigned long _PAGE_E __read_mostly;
2070 EXPORT_SYMBOL(_PAGE_E);
2071
2072 unsigned long _PAGE_CACHE __read_mostly;
2073 EXPORT_SYMBOL(_PAGE_CACHE);
2074
2075 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2076 unsigned long vmemmap_table[VMEMMAP_SIZE];
2077
2078 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2079 {
2080         unsigned long vstart = (unsigned long) start;
2081         unsigned long vend = (unsigned long) (start + nr);
2082         unsigned long phys_start = (vstart - VMEMMAP_BASE);
2083         unsigned long phys_end = (vend - VMEMMAP_BASE);
2084         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2085         unsigned long end = VMEMMAP_ALIGN(phys_end);
2086         unsigned long pte_base;
2087
2088         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2089                     _PAGE_CP_4U | _PAGE_CV_4U |
2090                     _PAGE_P_4U | _PAGE_W_4U);
2091         if (tlb_type == hypervisor)
2092                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2093                             _PAGE_CP_4V | _PAGE_CV_4V |
2094                             _PAGE_P_4V | _PAGE_W_4V);
2095
2096         for (; addr < end; addr += VMEMMAP_CHUNK) {
2097                 unsigned long *vmem_pp =
2098                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2099                 void *block;
2100
2101                 if (!(*vmem_pp & _PAGE_VALID)) {
2102                         block = vmemmap_alloc_block(1UL << 22, node);
2103                         if (!block)
2104                                 return -ENOMEM;
2105
2106                         *vmem_pp = pte_base | __pa(block);
2107
2108                         printk(KERN_INFO "[%p-%p] page_structs=%lu "
2109                                "node=%d entry=%lu/%lu\n", start, block, nr,
2110                                node,
2111                                addr >> VMEMMAP_CHUNK_SHIFT,
2112                                VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2113                 }
2114         }
2115         return 0;
2116 }
2117 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2118
2119 static void prot_init_common(unsigned long page_none,
2120                              unsigned long page_shared,
2121                              unsigned long page_copy,
2122                              unsigned long page_readonly,
2123                              unsigned long page_exec_bit)
2124 {
2125         PAGE_COPY = __pgprot(page_copy);
2126         PAGE_SHARED = __pgprot(page_shared);
2127
2128         protection_map[0x0] = __pgprot(page_none);
2129         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2130         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2131         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2132         protection_map[0x4] = __pgprot(page_readonly);
2133         protection_map[0x5] = __pgprot(page_readonly);
2134         protection_map[0x6] = __pgprot(page_copy);
2135         protection_map[0x7] = __pgprot(page_copy);
2136         protection_map[0x8] = __pgprot(page_none);
2137         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2138         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2139         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2140         protection_map[0xc] = __pgprot(page_readonly);
2141         protection_map[0xd] = __pgprot(page_readonly);
2142         protection_map[0xe] = __pgprot(page_shared);
2143         protection_map[0xf] = __pgprot(page_shared);
2144 }
2145
2146 static void __init sun4u_pgprot_init(void)
2147 {
2148         unsigned long page_none, page_shared, page_copy, page_readonly;
2149         unsigned long page_exec_bit;
2150
2151         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2152                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2153                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2154                                 _PAGE_EXEC_4U);
2155         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2156                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2157                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2158                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2159
2160         _PAGE_IE = _PAGE_IE_4U;
2161         _PAGE_E = _PAGE_E_4U;
2162         _PAGE_CACHE = _PAGE_CACHE_4U;
2163
2164         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2165                      __ACCESS_BITS_4U | _PAGE_E_4U);
2166
2167 #ifdef CONFIG_DEBUG_PAGEALLOC
2168         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2169                 0xfffff80000000000UL;
2170 #else
2171         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2172                 0xfffff80000000000UL;
2173 #endif
2174         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2175                                    _PAGE_P_4U | _PAGE_W_4U);
2176
2177         /* XXX Should use 256MB on Panther. XXX */
2178         kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2179
2180         _PAGE_SZBITS = _PAGE_SZBITS_4U;
2181         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2182                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2183                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2184
2185
2186         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2187         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2188                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2189         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2190                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2191         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2192                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2193
2194         page_exec_bit = _PAGE_EXEC_4U;
2195
2196         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2197                          page_exec_bit);
2198 }
2199
2200 static void __init sun4v_pgprot_init(void)
2201 {
2202         unsigned long page_none, page_shared, page_copy, page_readonly;
2203         unsigned long page_exec_bit;
2204
2205         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2206                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2207                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2208                                 _PAGE_EXEC_4V);
2209         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2210
2211         _PAGE_IE = _PAGE_IE_4V;
2212         _PAGE_E = _PAGE_E_4V;
2213         _PAGE_CACHE = _PAGE_CACHE_4V;
2214
2215 #ifdef CONFIG_DEBUG_PAGEALLOC
2216         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2217                 0xfffff80000000000UL;
2218 #else
2219         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2220                 0xfffff80000000000UL;
2221 #endif
2222         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2223                                    _PAGE_P_4V | _PAGE_W_4V);
2224
2225 #ifdef CONFIG_DEBUG_PAGEALLOC
2226         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2227                 0xfffff80000000000UL;
2228 #else
2229         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2230                 0xfffff80000000000UL;
2231 #endif
2232         kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2233                                    _PAGE_P_4V | _PAGE_W_4V);
2234
2235         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2236                      __ACCESS_BITS_4V | _PAGE_E_4V);
2237
2238         _PAGE_SZBITS = _PAGE_SZBITS_4V;
2239         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2240                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2241                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2242                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2243
2244         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2245         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2246                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2247         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2248                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2249         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2250                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2251
2252         page_exec_bit = _PAGE_EXEC_4V;
2253
2254         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2255                          page_exec_bit);
2256 }
2257
2258 unsigned long pte_sz_bits(unsigned long sz)
2259 {
2260         if (tlb_type == hypervisor) {
2261                 switch (sz) {
2262                 case 8 * 1024:
2263                 default:
2264                         return _PAGE_SZ8K_4V;
2265                 case 64 * 1024:
2266                         return _PAGE_SZ64K_4V;
2267                 case 512 * 1024:
2268                         return _PAGE_SZ512K_4V;
2269                 case 4 * 1024 * 1024:
2270                         return _PAGE_SZ4MB_4V;
2271                 };
2272         } else {
2273                 switch (sz) {
2274                 case 8 * 1024:
2275                 default:
2276                         return _PAGE_SZ8K_4U;
2277                 case 64 * 1024:
2278                         return _PAGE_SZ64K_4U;
2279                 case 512 * 1024:
2280                         return _PAGE_SZ512K_4U;
2281                 case 4 * 1024 * 1024:
2282                         return _PAGE_SZ4MB_4U;
2283                 };
2284         }
2285 }
2286
2287 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2288 {
2289         pte_t pte;
2290
2291         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2292         pte_val(pte) |= (((unsigned long)space) << 32);
2293         pte_val(pte) |= pte_sz_bits(page_size);
2294
2295         return pte;
2296 }
2297
2298 static unsigned long kern_large_tte(unsigned long paddr)
2299 {
2300         unsigned long val;
2301
2302         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2303                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2304                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2305         if (tlb_type == hypervisor)
2306                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2307                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2308                        _PAGE_EXEC_4V | _PAGE_W_4V);
2309
2310         return val | paddr;
2311 }
2312
2313 /* If not locked, zap it. */
2314 void __flush_tlb_all(void)
2315 {
2316         unsigned long pstate;
2317         int i;
2318
2319         __asm__ __volatile__("flushw\n\t"
2320                              "rdpr      %%pstate, %0\n\t"
2321                              "wrpr      %0, %1, %%pstate"
2322                              : "=r" (pstate)
2323                              : "i" (PSTATE_IE));
2324         if (tlb_type == hypervisor) {
2325                 sun4v_mmu_demap_all();
2326         } else if (tlb_type == spitfire) {
2327                 for (i = 0; i < 64; i++) {
2328                         /* Spitfire Errata #32 workaround */
2329                         /* NOTE: Always runs on spitfire, so no
2330                          *       cheetah+ page size encodings.
2331                          */
2332                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2333                                              "flush     %%g6"
2334                                              : /* No outputs */
2335                                              : "r" (0),
2336                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2337
2338                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2339                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2340                                                      "membar #Sync"
2341                                                      : /* no outputs */
2342                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2343                                 spitfire_put_dtlb_data(i, 0x0UL);
2344                         }
2345
2346                         /* Spitfire Errata #32 workaround */
2347                         /* NOTE: Always runs on spitfire, so no
2348                          *       cheetah+ page size encodings.
2349                          */
2350                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2351                                              "flush     %%g6"
2352                                              : /* No outputs */
2353                                              : "r" (0),
2354                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2355
2356                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2357                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2358                                                      "membar #Sync"
2359                                                      : /* no outputs */
2360                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2361                                 spitfire_put_itlb_data(i, 0x0UL);
2362                         }
2363                 }
2364         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2365                 cheetah_flush_dtlb_all();
2366                 cheetah_flush_itlb_all();
2367         }
2368         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2369                              : : "r" (pstate));
2370 }