irq: update all arches for new irq_desc
[linux-2.6.git] / arch / sparc / kernel / irq_64.c
1 /* irq.c: UltraSparc IRQ handling/init/registry.
2  *
3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
6  */
7
8 #include <linux/module.h>
9 #include <linux/sched.h>
10 #include <linux/linkage.h>
11 #include <linux/ptrace.h>
12 #include <linux/errno.h>
13 #include <linux/kernel_stat.h>
14 #include <linux/signal.h>
15 #include <linux/mm.h>
16 #include <linux/interrupt.h>
17 #include <linux/slab.h>
18 #include <linux/random.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/proc_fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/bootmem.h>
24 #include <linux/irq.h>
25
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
30 #include <asm/irq.h>
31 #include <asm/io.h>
32 #include <asm/iommu.h>
33 #include <asm/upa.h>
34 #include <asm/oplib.h>
35 #include <asm/prom.h>
36 #include <asm/timer.h>
37 #include <asm/smp.h>
38 #include <asm/starfire.h>
39 #include <asm/uaccess.h>
40 #include <asm/cache.h>
41 #include <asm/cpudata.h>
42 #include <asm/auxio.h>
43 #include <asm/head.h>
44 #include <asm/hypervisor.h>
45 #include <asm/cacheflush.h>
46
47 #include "entry.h"
48
49 #define NUM_IVECS       (IMAP_INR + 1)
50
51 struct ino_bucket *ivector_table;
52 unsigned long ivector_table_pa;
53
54 /* On several sun4u processors, it is illegal to mix bypass and
55  * non-bypass accesses.  Therefore we access all INO buckets
56  * using bypass accesses only.
57  */
58 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
59 {
60         unsigned long ret;
61
62         __asm__ __volatile__("ldxa      [%1] %2, %0"
63                              : "=&r" (ret)
64                              : "r" (bucket_pa +
65                                     offsetof(struct ino_bucket,
66                                              __irq_chain_pa)),
67                                "i" (ASI_PHYS_USE_EC));
68
69         return ret;
70 }
71
72 static void bucket_clear_chain_pa(unsigned long bucket_pa)
73 {
74         __asm__ __volatile__("stxa      %%g0, [%0] %1"
75                              : /* no outputs */
76                              : "r" (bucket_pa +
77                                     offsetof(struct ino_bucket,
78                                              __irq_chain_pa)),
79                                "i" (ASI_PHYS_USE_EC));
80 }
81
82 static unsigned int bucket_get_virt_irq(unsigned long bucket_pa)
83 {
84         unsigned int ret;
85
86         __asm__ __volatile__("lduwa     [%1] %2, %0"
87                              : "=&r" (ret)
88                              : "r" (bucket_pa +
89                                     offsetof(struct ino_bucket,
90                                              __virt_irq)),
91                                "i" (ASI_PHYS_USE_EC));
92
93         return ret;
94 }
95
96 static void bucket_set_virt_irq(unsigned long bucket_pa,
97                                 unsigned int virt_irq)
98 {
99         __asm__ __volatile__("stwa      %0, [%1] %2"
100                              : /* no outputs */
101                              : "r" (virt_irq),
102                                "r" (bucket_pa +
103                                     offsetof(struct ino_bucket,
104                                              __virt_irq)),
105                                "i" (ASI_PHYS_USE_EC));
106 }
107
108 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
109
110 static struct {
111         unsigned int dev_handle;
112         unsigned int dev_ino;
113         unsigned int in_use;
114 } virt_irq_table[NR_IRQS];
115 static DEFINE_SPINLOCK(virt_irq_alloc_lock);
116
117 unsigned char virt_irq_alloc(unsigned int dev_handle,
118                              unsigned int dev_ino)
119 {
120         unsigned long flags;
121         unsigned char ent;
122
123         BUILD_BUG_ON(NR_IRQS >= 256);
124
125         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
126
127         for (ent = 1; ent < NR_IRQS; ent++) {
128                 if (!virt_irq_table[ent].in_use)
129                         break;
130         }
131         if (ent >= NR_IRQS) {
132                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
133                 ent = 0;
134         } else {
135                 virt_irq_table[ent].dev_handle = dev_handle;
136                 virt_irq_table[ent].dev_ino = dev_ino;
137                 virt_irq_table[ent].in_use = 1;
138         }
139
140         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
141
142         return ent;
143 }
144
145 #ifdef CONFIG_PCI_MSI
146 void virt_irq_free(unsigned int virt_irq)
147 {
148         unsigned long flags;
149
150         if (virt_irq >= NR_IRQS)
151                 return;
152
153         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
154
155         virt_irq_table[virt_irq].in_use = 0;
156
157         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
158 }
159 #endif
160
161 /*
162  * /proc/interrupts printing:
163  */
164
165 int show_interrupts(struct seq_file *p, void *v)
166 {
167         int i = *(loff_t *) v, j;
168         struct irqaction * action;
169         unsigned long flags;
170
171         if (i == 0) {
172                 seq_printf(p, "           ");
173                 for_each_online_cpu(j)
174                         seq_printf(p, "CPU%d       ",j);
175                 seq_putc(p, '\n');
176         }
177
178         if (i < NR_IRQS) {
179                 spin_lock_irqsave(&irq_desc[i].lock, flags);
180                 action = irq_desc[i].action;
181                 if (!action)
182                         goto skip;
183                 seq_printf(p, "%3d: ",i);
184 #ifndef CONFIG_SMP
185                 seq_printf(p, "%10u ", kstat_irqs(i));
186 #else
187                 for_each_online_cpu(j)
188                         seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
189 #endif
190                 seq_printf(p, " %9s", irq_desc[i].chip->typename);
191                 seq_printf(p, "  %s", action->name);
192
193                 for (action=action->next; action; action = action->next)
194                         seq_printf(p, ", %s", action->name);
195
196                 seq_putc(p, '\n');
197 skip:
198                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
199         }
200         return 0;
201 }
202
203 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
204 {
205         unsigned int tid;
206
207         if (this_is_starfire) {
208                 tid = starfire_translate(imap, cpuid);
209                 tid <<= IMAP_TID_SHIFT;
210                 tid &= IMAP_TID_UPA;
211         } else {
212                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
213                         unsigned long ver;
214
215                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
216                         if ((ver >> 32UL) == __JALAPENO_ID ||
217                             (ver >> 32UL) == __SERRANO_ID) {
218                                 tid = cpuid << IMAP_TID_SHIFT;
219                                 tid &= IMAP_TID_JBUS;
220                         } else {
221                                 unsigned int a = cpuid & 0x1f;
222                                 unsigned int n = (cpuid >> 5) & 0x1f;
223
224                                 tid = ((a << IMAP_AID_SHIFT) |
225                                        (n << IMAP_NID_SHIFT));
226                                 tid &= (IMAP_AID_SAFARI |
227                                         IMAP_NID_SAFARI);;
228                         }
229                 } else {
230                         tid = cpuid << IMAP_TID_SHIFT;
231                         tid &= IMAP_TID_UPA;
232                 }
233         }
234
235         return tid;
236 }
237
238 struct irq_handler_data {
239         unsigned long   iclr;
240         unsigned long   imap;
241
242         void            (*pre_handler)(unsigned int, void *, void *);
243         void            *arg1;
244         void            *arg2;
245 };
246
247 #ifdef CONFIG_SMP
248 static int irq_choose_cpu(unsigned int virt_irq)
249 {
250         cpumask_t mask;
251         int cpuid;
252
253         cpumask_copy(&mask, irq_desc[virt_irq].affinity);
254         if (cpus_equal(mask, CPU_MASK_ALL)) {
255                 static int irq_rover;
256                 static DEFINE_SPINLOCK(irq_rover_lock);
257                 unsigned long flags;
258
259                 /* Round-robin distribution... */
260         do_round_robin:
261                 spin_lock_irqsave(&irq_rover_lock, flags);
262
263                 while (!cpu_online(irq_rover)) {
264                         if (++irq_rover >= NR_CPUS)
265                                 irq_rover = 0;
266                 }
267                 cpuid = irq_rover;
268                 do {
269                         if (++irq_rover >= NR_CPUS)
270                                 irq_rover = 0;
271                 } while (!cpu_online(irq_rover));
272
273                 spin_unlock_irqrestore(&irq_rover_lock, flags);
274         } else {
275                 cpumask_t tmp;
276
277                 cpus_and(tmp, cpu_online_map, mask);
278
279                 if (cpus_empty(tmp))
280                         goto do_round_robin;
281
282                 cpuid = first_cpu(tmp);
283         }
284
285         return cpuid;
286 }
287 #else
288 static int irq_choose_cpu(unsigned int virt_irq)
289 {
290         return real_hard_smp_processor_id();
291 }
292 #endif
293
294 static void sun4u_irq_enable(unsigned int virt_irq)
295 {
296         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
297
298         if (likely(data)) {
299                 unsigned long cpuid, imap, val;
300                 unsigned int tid;
301
302                 cpuid = irq_choose_cpu(virt_irq);
303                 imap = data->imap;
304
305                 tid = sun4u_compute_tid(imap, cpuid);
306
307                 val = upa_readq(imap);
308                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
309                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
310                 val |= tid | IMAP_VALID;
311                 upa_writeq(val, imap);
312                 upa_writeq(ICLR_IDLE, data->iclr);
313         }
314 }
315
316 static void sun4u_set_affinity(unsigned int virt_irq,
317                                const struct cpumask *mask)
318 {
319         sun4u_irq_enable(virt_irq);
320 }
321
322 static void sun4u_irq_disable(unsigned int virt_irq)
323 {
324         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
325
326         if (likely(data)) {
327                 unsigned long imap = data->imap;
328                 unsigned long tmp = upa_readq(imap);
329
330                 tmp &= ~IMAP_VALID;
331                 upa_writeq(tmp, imap);
332         }
333 }
334
335 static void sun4u_irq_eoi(unsigned int virt_irq)
336 {
337         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
338         struct irq_desc *desc = irq_desc + virt_irq;
339
340         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
341                 return;
342
343         if (likely(data))
344                 upa_writeq(ICLR_IDLE, data->iclr);
345 }
346
347 static void sun4v_irq_enable(unsigned int virt_irq)
348 {
349         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
350         unsigned long cpuid = irq_choose_cpu(virt_irq);
351         int err;
352
353         err = sun4v_intr_settarget(ino, cpuid);
354         if (err != HV_EOK)
355                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
356                        "err(%d)\n", ino, cpuid, err);
357         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
358         if (err != HV_EOK)
359                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
360                        "err(%d)\n", ino, err);
361         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
362         if (err != HV_EOK)
363                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
364                        ino, err);
365 }
366
367 static void sun4v_set_affinity(unsigned int virt_irq,
368                                const struct cpumask *mask)
369 {
370         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
371         unsigned long cpuid = irq_choose_cpu(virt_irq);
372         int err;
373
374         err = sun4v_intr_settarget(ino, cpuid);
375         if (err != HV_EOK)
376                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
377                        "err(%d)\n", ino, cpuid, err);
378 }
379
380 static void sun4v_irq_disable(unsigned int virt_irq)
381 {
382         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
383         int err;
384
385         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
386         if (err != HV_EOK)
387                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
388                        "err(%d)\n", ino, err);
389 }
390
391 static void sun4v_irq_eoi(unsigned int virt_irq)
392 {
393         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
394         struct irq_desc *desc = irq_desc + virt_irq;
395         int err;
396
397         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
398                 return;
399
400         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
401         if (err != HV_EOK)
402                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
403                        "err(%d)\n", ino, err);
404 }
405
406 static void sun4v_virq_enable(unsigned int virt_irq)
407 {
408         unsigned long cpuid, dev_handle, dev_ino;
409         int err;
410
411         cpuid = irq_choose_cpu(virt_irq);
412
413         dev_handle = virt_irq_table[virt_irq].dev_handle;
414         dev_ino = virt_irq_table[virt_irq].dev_ino;
415
416         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
417         if (err != HV_EOK)
418                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
419                        "err(%d)\n",
420                        dev_handle, dev_ino, cpuid, err);
421         err = sun4v_vintr_set_state(dev_handle, dev_ino,
422                                     HV_INTR_STATE_IDLE);
423         if (err != HV_EOK)
424                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
425                        "HV_INTR_STATE_IDLE): err(%d)\n",
426                        dev_handle, dev_ino, err);
427         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
428                                     HV_INTR_ENABLED);
429         if (err != HV_EOK)
430                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
431                        "HV_INTR_ENABLED): err(%d)\n",
432                        dev_handle, dev_ino, err);
433 }
434
435 static void sun4v_virt_set_affinity(unsigned int virt_irq,
436                                     const struct cpumask *mask)
437 {
438         unsigned long cpuid, dev_handle, dev_ino;
439         int err;
440
441         cpuid = irq_choose_cpu(virt_irq);
442
443         dev_handle = virt_irq_table[virt_irq].dev_handle;
444         dev_ino = virt_irq_table[virt_irq].dev_ino;
445
446         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
447         if (err != HV_EOK)
448                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
449                        "err(%d)\n",
450                        dev_handle, dev_ino, cpuid, err);
451 }
452
453 static void sun4v_virq_disable(unsigned int virt_irq)
454 {
455         unsigned long dev_handle, dev_ino;
456         int err;
457
458         dev_handle = virt_irq_table[virt_irq].dev_handle;
459         dev_ino = virt_irq_table[virt_irq].dev_ino;
460
461         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
462                                     HV_INTR_DISABLED);
463         if (err != HV_EOK)
464                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
465                        "HV_INTR_DISABLED): err(%d)\n",
466                        dev_handle, dev_ino, err);
467 }
468
469 static void sun4v_virq_eoi(unsigned int virt_irq)
470 {
471         struct irq_desc *desc = irq_desc + virt_irq;
472         unsigned long dev_handle, dev_ino;
473         int err;
474
475         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
476                 return;
477
478         dev_handle = virt_irq_table[virt_irq].dev_handle;
479         dev_ino = virt_irq_table[virt_irq].dev_ino;
480
481         err = sun4v_vintr_set_state(dev_handle, dev_ino,
482                                     HV_INTR_STATE_IDLE);
483         if (err != HV_EOK)
484                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
485                        "HV_INTR_STATE_IDLE): err(%d)\n",
486                        dev_handle, dev_ino, err);
487 }
488
489 static struct irq_chip sun4u_irq = {
490         .typename       = "sun4u",
491         .enable         = sun4u_irq_enable,
492         .disable        = sun4u_irq_disable,
493         .eoi            = sun4u_irq_eoi,
494         .set_affinity   = sun4u_set_affinity,
495 };
496
497 static struct irq_chip sun4v_irq = {
498         .typename       = "sun4v",
499         .enable         = sun4v_irq_enable,
500         .disable        = sun4v_irq_disable,
501         .eoi            = sun4v_irq_eoi,
502         .set_affinity   = sun4v_set_affinity,
503 };
504
505 static struct irq_chip sun4v_virq = {
506         .typename       = "vsun4v",
507         .enable         = sun4v_virq_enable,
508         .disable        = sun4v_virq_disable,
509         .eoi            = sun4v_virq_eoi,
510         .set_affinity   = sun4v_virt_set_affinity,
511 };
512
513 static void pre_flow_handler(unsigned int virt_irq,
514                                       struct irq_desc *desc)
515 {
516         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
517         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
518
519         data->pre_handler(ino, data->arg1, data->arg2);
520
521         handle_fasteoi_irq(virt_irq, desc);
522 }
523
524 void irq_install_pre_handler(int virt_irq,
525                              void (*func)(unsigned int, void *, void *),
526                              void *arg1, void *arg2)
527 {
528         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
529         struct irq_desc *desc = irq_desc + virt_irq;
530
531         data->pre_handler = func;
532         data->arg1 = arg1;
533         data->arg2 = arg2;
534
535         desc->handle_irq = pre_flow_handler;
536 }
537
538 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
539 {
540         struct ino_bucket *bucket;
541         struct irq_handler_data *data;
542         unsigned int virt_irq;
543         int ino;
544
545         BUG_ON(tlb_type == hypervisor);
546
547         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
548         bucket = &ivector_table[ino];
549         virt_irq = bucket_get_virt_irq(__pa(bucket));
550         if (!virt_irq) {
551                 virt_irq = virt_irq_alloc(0, ino);
552                 bucket_set_virt_irq(__pa(bucket), virt_irq);
553                 set_irq_chip_and_handler_name(virt_irq,
554                                               &sun4u_irq,
555                                               handle_fasteoi_irq,
556                                               "IVEC");
557         }
558
559         data = get_irq_chip_data(virt_irq);
560         if (unlikely(data))
561                 goto out;
562
563         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
564         if (unlikely(!data)) {
565                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
566                 prom_halt();
567         }
568         set_irq_chip_data(virt_irq, data);
569
570         data->imap  = imap;
571         data->iclr  = iclr;
572
573 out:
574         return virt_irq;
575 }
576
577 static unsigned int sun4v_build_common(unsigned long sysino,
578                                        struct irq_chip *chip)
579 {
580         struct ino_bucket *bucket;
581         struct irq_handler_data *data;
582         unsigned int virt_irq;
583
584         BUG_ON(tlb_type != hypervisor);
585
586         bucket = &ivector_table[sysino];
587         virt_irq = bucket_get_virt_irq(__pa(bucket));
588         if (!virt_irq) {
589                 virt_irq = virt_irq_alloc(0, sysino);
590                 bucket_set_virt_irq(__pa(bucket), virt_irq);
591                 set_irq_chip_and_handler_name(virt_irq, chip,
592                                               handle_fasteoi_irq,
593                                               "IVEC");
594         }
595
596         data = get_irq_chip_data(virt_irq);
597         if (unlikely(data))
598                 goto out;
599
600         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
601         if (unlikely(!data)) {
602                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
603                 prom_halt();
604         }
605         set_irq_chip_data(virt_irq, data);
606
607         /* Catch accidental accesses to these things.  IMAP/ICLR handling
608          * is done by hypervisor calls on sun4v platforms, not by direct
609          * register accesses.
610          */
611         data->imap = ~0UL;
612         data->iclr = ~0UL;
613
614 out:
615         return virt_irq;
616 }
617
618 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
619 {
620         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
621
622         return sun4v_build_common(sysino, &sun4v_irq);
623 }
624
625 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
626 {
627         struct irq_handler_data *data;
628         unsigned long hv_err, cookie;
629         struct ino_bucket *bucket;
630         struct irq_desc *desc;
631         unsigned int virt_irq;
632
633         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
634         if (unlikely(!bucket))
635                 return 0;
636         __flush_dcache_range((unsigned long) bucket,
637                              ((unsigned long) bucket +
638                               sizeof(struct ino_bucket)));
639
640         virt_irq = virt_irq_alloc(devhandle, devino);
641         bucket_set_virt_irq(__pa(bucket), virt_irq);
642
643         set_irq_chip_and_handler_name(virt_irq, &sun4v_virq,
644                                       handle_fasteoi_irq,
645                                       "IVEC");
646
647         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
648         if (unlikely(!data))
649                 return 0;
650
651         /* In order to make the LDC channel startup sequence easier,
652          * especially wrt. locking, we do not let request_irq() enable
653          * the interrupt.
654          */
655         desc = irq_desc + virt_irq;
656         desc->status |= IRQ_NOAUTOEN;
657
658         set_irq_chip_data(virt_irq, data);
659
660         /* Catch accidental accesses to these things.  IMAP/ICLR handling
661          * is done by hypervisor calls on sun4v platforms, not by direct
662          * register accesses.
663          */
664         data->imap = ~0UL;
665         data->iclr = ~0UL;
666
667         cookie = ~__pa(bucket);
668         hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
669         if (hv_err) {
670                 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
671                             "err=%lu\n", devhandle, devino, hv_err);
672                 prom_halt();
673         }
674
675         return virt_irq;
676 }
677
678 void ack_bad_irq(unsigned int virt_irq)
679 {
680         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
681
682         if (!ino)
683                 ino = 0xdeadbeef;
684
685         printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
686                ino, virt_irq);
687 }
688
689 void *hardirq_stack[NR_CPUS];
690 void *softirq_stack[NR_CPUS];
691
692 static __attribute__((always_inline)) void *set_hardirq_stack(void)
693 {
694         void *orig_sp, *sp = hardirq_stack[smp_processor_id()];
695
696         __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp));
697         if (orig_sp < sp ||
698             orig_sp > (sp + THREAD_SIZE)) {
699                 sp += THREAD_SIZE - 192 - STACK_BIAS;
700                 __asm__ __volatile__("mov %0, %%sp" : : "r" (sp));
701         }
702
703         return orig_sp;
704 }
705 static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp)
706 {
707         __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp));
708 }
709
710 void handler_irq(int irq, struct pt_regs *regs)
711 {
712         unsigned long pstate, bucket_pa;
713         struct pt_regs *old_regs;
714         void *orig_sp;
715
716         clear_softint(1 << irq);
717
718         old_regs = set_irq_regs(regs);
719         irq_enter();
720
721         /* Grab an atomic snapshot of the pending IVECs.  */
722         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
723                              "wrpr      %0, %3, %%pstate\n\t"
724                              "ldx       [%2], %1\n\t"
725                              "stx       %%g0, [%2]\n\t"
726                              "wrpr      %0, 0x0, %%pstate\n\t"
727                              : "=&r" (pstate), "=&r" (bucket_pa)
728                              : "r" (irq_work_pa(smp_processor_id())),
729                                "i" (PSTATE_IE)
730                              : "memory");
731
732         orig_sp = set_hardirq_stack();
733
734         while (bucket_pa) {
735                 struct irq_desc *desc;
736                 unsigned long next_pa;
737                 unsigned int virt_irq;
738
739                 next_pa = bucket_get_chain_pa(bucket_pa);
740                 virt_irq = bucket_get_virt_irq(bucket_pa);
741                 bucket_clear_chain_pa(bucket_pa);
742
743                 desc = irq_desc + virt_irq;
744
745                 desc->handle_irq(virt_irq, desc);
746
747                 bucket_pa = next_pa;
748         }
749
750         restore_hardirq_stack(orig_sp);
751
752         irq_exit();
753         set_irq_regs(old_regs);
754 }
755
756 void do_softirq(void)
757 {
758         unsigned long flags;
759
760         if (in_interrupt())
761                 return;
762
763         local_irq_save(flags);
764
765         if (local_softirq_pending()) {
766                 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
767
768                 sp += THREAD_SIZE - 192 - STACK_BIAS;
769
770                 __asm__ __volatile__("mov %%sp, %0\n\t"
771                                      "mov %1, %%sp"
772                                      : "=&r" (orig_sp)
773                                      : "r" (sp));
774                 __do_softirq();
775                 __asm__ __volatile__("mov %0, %%sp"
776                                      : : "r" (orig_sp));
777         }
778
779         local_irq_restore(flags);
780 }
781
782 static void unhandled_perf_irq(struct pt_regs *regs)
783 {
784         unsigned long pcr, pic;
785
786         read_pcr(pcr);
787         read_pic(pic);
788
789         write_pcr(0);
790
791         printk(KERN_EMERG "CPU %d: Got unexpected perf counter IRQ.\n",
792                smp_processor_id());
793         printk(KERN_EMERG "CPU %d: PCR[%016lx] PIC[%016lx]\n",
794                smp_processor_id(), pcr, pic);
795 }
796
797 /* Almost a direct copy of the powerpc PMC code.  */
798 static DEFINE_SPINLOCK(perf_irq_lock);
799 static void *perf_irq_owner_caller; /* mostly for debugging */
800 static void (*perf_irq)(struct pt_regs *regs) = unhandled_perf_irq;
801
802 /* Invoked from level 15 PIL handler in trap table.  */
803 void perfctr_irq(int irq, struct pt_regs *regs)
804 {
805         clear_softint(1 << irq);
806         perf_irq(regs);
807 }
808
809 int register_perfctr_intr(void (*handler)(struct pt_regs *))
810 {
811         int ret;
812
813         if (!handler)
814                 return -EINVAL;
815
816         spin_lock(&perf_irq_lock);
817         if (perf_irq != unhandled_perf_irq) {
818                 printk(KERN_WARNING "register_perfctr_intr: "
819                        "perf IRQ busy (reserved by caller %p)\n",
820                        perf_irq_owner_caller);
821                 ret = -EBUSY;
822                 goto out;
823         }
824
825         perf_irq_owner_caller = __builtin_return_address(0);
826         perf_irq = handler;
827
828         ret = 0;
829 out:
830         spin_unlock(&perf_irq_lock);
831
832         return ret;
833 }
834 EXPORT_SYMBOL_GPL(register_perfctr_intr);
835
836 void release_perfctr_intr(void (*handler)(struct pt_regs *))
837 {
838         spin_lock(&perf_irq_lock);
839         perf_irq_owner_caller = NULL;
840         perf_irq = unhandled_perf_irq;
841         spin_unlock(&perf_irq_lock);
842 }
843 EXPORT_SYMBOL_GPL(release_perfctr_intr);
844
845 #ifdef CONFIG_HOTPLUG_CPU
846 void fixup_irqs(void)
847 {
848         unsigned int irq;
849
850         for (irq = 0; irq < NR_IRQS; irq++) {
851                 unsigned long flags;
852
853                 spin_lock_irqsave(&irq_desc[irq].lock, flags);
854                 if (irq_desc[irq].action &&
855                     !(irq_desc[irq].status & IRQ_PER_CPU)) {
856                         if (irq_desc[irq].chip->set_affinity)
857                                 irq_desc[irq].chip->set_affinity(irq,
858                                         irq_desc[irq].affinity);
859                 }
860                 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
861         }
862
863         tick_ops->disable_irq();
864 }
865 #endif
866
867 struct sun5_timer {
868         u64     count0;
869         u64     limit0;
870         u64     count1;
871         u64     limit1;
872 };
873
874 static struct sun5_timer *prom_timers;
875 static u64 prom_limit0, prom_limit1;
876
877 static void map_prom_timers(void)
878 {
879         struct device_node *dp;
880         const unsigned int *addr;
881
882         /* PROM timer node hangs out in the top level of device siblings... */
883         dp = of_find_node_by_path("/");
884         dp = dp->child;
885         while (dp) {
886                 if (!strcmp(dp->name, "counter-timer"))
887                         break;
888                 dp = dp->sibling;
889         }
890
891         /* Assume if node is not present, PROM uses different tick mechanism
892          * which we should not care about.
893          */
894         if (!dp) {
895                 prom_timers = (struct sun5_timer *) 0;
896                 return;
897         }
898
899         /* If PROM is really using this, it must be mapped by him. */
900         addr = of_get_property(dp, "address", NULL);
901         if (!addr) {
902                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
903                 prom_timers = (struct sun5_timer *) 0;
904                 return;
905         }
906         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
907 }
908
909 static void kill_prom_timer(void)
910 {
911         if (!prom_timers)
912                 return;
913
914         /* Save them away for later. */
915         prom_limit0 = prom_timers->limit0;
916         prom_limit1 = prom_timers->limit1;
917
918         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
919          * We turn both off here just to be paranoid.
920          */
921         prom_timers->limit0 = 0;
922         prom_timers->limit1 = 0;
923
924         /* Wheee, eat the interrupt packet too... */
925         __asm__ __volatile__(
926 "       mov     0x40, %%g2\n"
927 "       ldxa    [%%g0] %0, %%g1\n"
928 "       ldxa    [%%g2] %1, %%g1\n"
929 "       stxa    %%g0, [%%g0] %0\n"
930 "       membar  #Sync\n"
931         : /* no outputs */
932         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
933         : "g1", "g2");
934 }
935
936 void notrace init_irqwork_curcpu(void)
937 {
938         int cpu = hard_smp_processor_id();
939
940         trap_block[cpu].irq_worklist_pa = 0UL;
941 }
942
943 /* Please be very careful with register_one_mondo() and
944  * sun4v_register_mondo_queues().
945  *
946  * On SMP this gets invoked from the CPU trampoline before
947  * the cpu has fully taken over the trap table from OBP,
948  * and it's kernel stack + %g6 thread register state is
949  * not fully cooked yet.
950  *
951  * Therefore you cannot make any OBP calls, not even prom_printf,
952  * from these two routines.
953  */
954 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
955 {
956         unsigned long num_entries = (qmask + 1) / 64;
957         unsigned long status;
958
959         status = sun4v_cpu_qconf(type, paddr, num_entries);
960         if (status != HV_EOK) {
961                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
962                             "err %lu\n", type, paddr, num_entries, status);
963                 prom_halt();
964         }
965 }
966
967 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
968 {
969         struct trap_per_cpu *tb = &trap_block[this_cpu];
970
971         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
972                            tb->cpu_mondo_qmask);
973         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
974                            tb->dev_mondo_qmask);
975         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
976                            tb->resum_qmask);
977         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
978                            tb->nonresum_qmask);
979 }
980
981 static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask)
982 {
983         unsigned long size = PAGE_ALIGN(qmask + 1);
984         void *p = __alloc_bootmem(size, size, 0);
985         if (!p) {
986                 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
987                 prom_halt();
988         }
989
990         *pa_ptr = __pa(p);
991 }
992
993 static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask)
994 {
995         unsigned long size = PAGE_ALIGN(qmask + 1);
996         void *p = __alloc_bootmem(size, size, 0);
997
998         if (!p) {
999                 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
1000                 prom_halt();
1001         }
1002
1003         *pa_ptr = __pa(p);
1004 }
1005
1006 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
1007 {
1008 #ifdef CONFIG_SMP
1009         void *page;
1010
1011         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
1012
1013         page = alloc_bootmem_pages(PAGE_SIZE);
1014         if (!page) {
1015                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1016                 prom_halt();
1017         }
1018
1019         tb->cpu_mondo_block_pa = __pa(page);
1020         tb->cpu_list_pa = __pa(page + 64);
1021 #endif
1022 }
1023
1024 /* Allocate mondo and error queues for all possible cpus.  */
1025 static void __init sun4v_init_mondo_queues(void)
1026 {
1027         int cpu;
1028
1029         for_each_possible_cpu(cpu) {
1030                 struct trap_per_cpu *tb = &trap_block[cpu];
1031
1032                 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
1033                 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
1034                 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask);
1035                 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask);
1036                 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
1037                 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
1038                                tb->nonresum_qmask);
1039         }
1040 }
1041
1042 static void __init init_send_mondo_info(void)
1043 {
1044         int cpu;
1045
1046         for_each_possible_cpu(cpu) {
1047                 struct trap_per_cpu *tb = &trap_block[cpu];
1048
1049                 init_cpu_send_mondo_info(tb);
1050         }
1051 }
1052
1053 static struct irqaction timer_irq_action = {
1054         .name = "timer",
1055 };
1056
1057 /* Only invoked on boot processor. */
1058 void __init init_IRQ(void)
1059 {
1060         unsigned long size;
1061
1062         map_prom_timers();
1063         kill_prom_timer();
1064
1065         size = sizeof(struct ino_bucket) * NUM_IVECS;
1066         ivector_table = alloc_bootmem(size);
1067         if (!ivector_table) {
1068                 prom_printf("Fatal error, cannot allocate ivector_table\n");
1069                 prom_halt();
1070         }
1071         __flush_dcache_range((unsigned long) ivector_table,
1072                              ((unsigned long) ivector_table) + size);
1073
1074         ivector_table_pa = __pa(ivector_table);
1075
1076         if (tlb_type == hypervisor)
1077                 sun4v_init_mondo_queues();
1078
1079         init_send_mondo_info();
1080
1081         if (tlb_type == hypervisor) {
1082                 /* Load up the boot cpu's entries.  */
1083                 sun4v_register_mondo_queues(hard_smp_processor_id());
1084         }
1085
1086         /* We need to clear any IRQ's pending in the soft interrupt
1087          * registers, a spurious one could be left around from the
1088          * PROM timer which we just disabled.
1089          */
1090         clear_softint(get_softint());
1091
1092         /* Now that ivector table is initialized, it is safe
1093          * to receive IRQ vector traps.  We will normally take
1094          * one or two right now, in case some device PROM used
1095          * to boot us wants to speak to us.  We just ignore them.
1096          */
1097         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1098                              "or        %%g1, %0, %%g1\n\t"
1099                              "wrpr      %%g1, 0x0, %%pstate"
1100                              : /* No outputs */
1101                              : "i" (PSTATE_IE)
1102                              : "g1");
1103
1104         irq_desc[0].action = &timer_irq_action;
1105 }